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ad67ef68 PW |
1 | /* |
2 | * OMAP2/3 powerdomain control | |
3 | * | |
4 | * Copyright (C) 2007-8 Texas Instruments, Inc. | |
5 | * Copyright (C) 2007-8 Nokia Corporation | |
6 | * | |
7 | * Written by Paul Walmsley | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License version 2 as | |
11 | * published by the Free Software Foundation. | |
12 | */ | |
13 | ||
14 | #ifndef ASM_ARM_ARCH_OMAP_POWERDOMAIN | |
15 | #define ASM_ARM_ARCH_OMAP_POWERDOMAIN | |
16 | ||
17 | #include <linux/types.h> | |
18 | #include <linux/list.h> | |
19 | ||
20 | #include <asm/atomic.h> | |
21 | ||
ce491cf8 | 22 | #include <plat/cpu.h> |
ad67ef68 PW |
23 | |
24 | ||
25 | /* Powerdomain basic power states */ | |
26 | #define PWRDM_POWER_OFF 0x0 | |
27 | #define PWRDM_POWER_RET 0x1 | |
28 | #define PWRDM_POWER_INACTIVE 0x2 | |
29 | #define PWRDM_POWER_ON 0x3 | |
30 | ||
2354eb5a PW |
31 | #define PWRDM_MAX_PWRSTS 4 |
32 | ||
ad67ef68 PW |
33 | /* Powerdomain allowable state bitfields */ |
34 | #define PWRSTS_OFF_ON ((1 << PWRDM_POWER_OFF) | \ | |
35 | (1 << PWRDM_POWER_ON)) | |
36 | ||
37 | #define PWRSTS_OFF_RET ((1 << PWRDM_POWER_OFF) | \ | |
38 | (1 << PWRDM_POWER_RET)) | |
39 | ||
f37c6dfa AP |
40 | #define PWRSTS_RET_ON ((1 << PWRDM_POWER_RET) | \ |
41 | (1 << PWRDM_POWER_ON)) | |
42 | ||
ad67ef68 PW |
43 | #define PWRSTS_OFF_RET_ON (PWRSTS_OFF_RET | (1 << PWRDM_POWER_ON)) |
44 | ||
45 | ||
0b7cbfb5 PW |
46 | /* Powerdomain flags */ |
47 | #define PWRDM_HAS_HDWR_SAR (1 << 0) /* hardware save-and-restore support */ | |
3863c74b TG |
48 | #define PWRDM_HAS_MPU_QUIRK (1 << 1) /* MPU pwr domain has MEM bank 0 bits |
49 | * in MEM bank 1 position. This is | |
50 | * true for OMAP3430 | |
51 | */ | |
0b7cbfb5 | 52 | |
ad67ef68 PW |
53 | /* |
54 | * Number of memory banks that are power-controllable. On OMAP3430, the | |
55 | * maximum is 4. | |
56 | */ | |
57 | #define PWRDM_MAX_MEM_BANKS 4 | |
58 | ||
8420bb13 PW |
59 | /* |
60 | * Maximum number of clockdomains that can be associated with a powerdomain. | |
d37f1a13 | 61 | * CORE powerdomain on OMAP3 is the worst case |
8420bb13 | 62 | */ |
d37f1a13 | 63 | #define PWRDM_MAX_CLKDMS 4 |
8420bb13 | 64 | |
ad67ef68 PW |
65 | /* XXX A completely arbitrary number. What is reasonable here? */ |
66 | #define PWRDM_TRANSITION_BAILOUT 100000 | |
67 | ||
8420bb13 | 68 | struct clockdomain; |
ad67ef68 PW |
69 | struct powerdomain; |
70 | ||
71 | /* Encodes dependencies between powerdomains - statically defined */ | |
72 | struct pwrdm_dep { | |
73 | ||
74 | /* Powerdomain name */ | |
75 | const char *pwrdm_name; | |
76 | ||
77 | /* Powerdomain pointer - resolved by the powerdomain code */ | |
78 | struct powerdomain *pwrdm; | |
79 | ||
80 | /* Flags to mark OMAP chip restrictions, etc. */ | |
81 | const struct omap_chip_id omap_chip; | |
82 | ||
83 | }; | |
84 | ||
85 | struct powerdomain { | |
86 | ||
87 | /* Powerdomain name */ | |
88 | const char *name; | |
89 | ||
90 | /* the address offset from CM_BASE/PRM_BASE */ | |
91 | const s16 prcm_offs; | |
92 | ||
93 | /* Used to represent the OMAP chip types containing this pwrdm */ | |
94 | const struct omap_chip_id omap_chip; | |
95 | ||
ad67ef68 PW |
96 | /* Powerdomains that can be told to wake this powerdomain up */ |
97 | struct pwrdm_dep *wkdep_srcs; | |
98 | ||
99 | /* Powerdomains that can be told to keep this pwrdm from inactivity */ | |
100 | struct pwrdm_dep *sleepdep_srcs; | |
155a22ec PW |
101 | |
102 | /* Bit shift of this powerdomain's PM_WKDEP/CM_SLEEPDEP bit */ | |
103 | const u8 dep_bit; | |
ad67ef68 PW |
104 | |
105 | /* Possible powerdomain power states */ | |
106 | const u8 pwrsts; | |
107 | ||
108 | /* Possible logic power states when pwrdm in RETENTION */ | |
109 | const u8 pwrsts_logic_ret; | |
110 | ||
0b7cbfb5 PW |
111 | /* Powerdomain flags */ |
112 | const u8 flags; | |
113 | ||
ad67ef68 PW |
114 | /* Number of software-controllable memory banks in this powerdomain */ |
115 | const u8 banks; | |
116 | ||
117 | /* Possible memory bank pwrstates when pwrdm in RETENTION */ | |
118 | const u8 pwrsts_mem_ret[PWRDM_MAX_MEM_BANKS]; | |
119 | ||
120 | /* Possible memory bank pwrstates when pwrdm is ON */ | |
121 | const u8 pwrsts_mem_on[PWRDM_MAX_MEM_BANKS]; | |
122 | ||
8420bb13 PW |
123 | /* Clockdomains in this powerdomain */ |
124 | struct clockdomain *pwrdm_clkdms[PWRDM_MAX_CLKDMS]; | |
125 | ||
ad67ef68 PW |
126 | struct list_head node; |
127 | ||
ba20bb12 | 128 | int state; |
2354eb5a | 129 | unsigned state_counter[PWRDM_MAX_PWRSTS]; |
331b93f4 PDS |
130 | |
131 | #ifdef CONFIG_PM_DEBUG | |
132 | s64 timer; | |
2354eb5a | 133 | s64 state_timer[PWRDM_MAX_PWRSTS]; |
331b93f4 | 134 | #endif |
ad67ef68 PW |
135 | }; |
136 | ||
137 | ||
138 | void pwrdm_init(struct powerdomain **pwrdm_list); | |
139 | ||
140 | int pwrdm_register(struct powerdomain *pwrdm); | |
141 | int pwrdm_unregister(struct powerdomain *pwrdm); | |
142 | struct powerdomain *pwrdm_lookup(const char *name); | |
143 | ||
a23456e9 PDS |
144 | int pwrdm_for_each(int (*fn)(struct powerdomain *pwrdm, void *user), |
145 | void *user); | |
ee894b18 AB |
146 | int pwrdm_for_each_nolock(int (*fn)(struct powerdomain *pwrdm, void *user), |
147 | void *user); | |
ad67ef68 | 148 | |
8420bb13 PW |
149 | int pwrdm_add_clkdm(struct powerdomain *pwrdm, struct clockdomain *clkdm); |
150 | int pwrdm_del_clkdm(struct powerdomain *pwrdm, struct clockdomain *clkdm); | |
151 | int pwrdm_for_each_clkdm(struct powerdomain *pwrdm, | |
152 | int (*fn)(struct powerdomain *pwrdm, | |
153 | struct clockdomain *clkdm)); | |
154 | ||
ad67ef68 PW |
155 | int pwrdm_add_wkdep(struct powerdomain *pwrdm1, struct powerdomain *pwrdm2); |
156 | int pwrdm_del_wkdep(struct powerdomain *pwrdm1, struct powerdomain *pwrdm2); | |
157 | int pwrdm_read_wkdep(struct powerdomain *pwrdm1, struct powerdomain *pwrdm2); | |
158 | int pwrdm_add_sleepdep(struct powerdomain *pwrdm1, struct powerdomain *pwrdm2); | |
159 | int pwrdm_del_sleepdep(struct powerdomain *pwrdm1, struct powerdomain *pwrdm2); | |
160 | int pwrdm_read_sleepdep(struct powerdomain *pwrdm1, struct powerdomain *pwrdm2); | |
161 | ||
162 | int pwrdm_get_mem_bank_count(struct powerdomain *pwrdm); | |
163 | ||
164 | int pwrdm_set_next_pwrst(struct powerdomain *pwrdm, u8 pwrst); | |
165 | int pwrdm_read_next_pwrst(struct powerdomain *pwrdm); | |
fecb494b | 166 | int pwrdm_read_pwrst(struct powerdomain *pwrdm); |
ad67ef68 PW |
167 | int pwrdm_read_prev_pwrst(struct powerdomain *pwrdm); |
168 | int pwrdm_clear_all_prev_pwrst(struct powerdomain *pwrdm); | |
169 | ||
170 | int pwrdm_set_logic_retst(struct powerdomain *pwrdm, u8 pwrst); | |
171 | int pwrdm_set_mem_onst(struct powerdomain *pwrdm, u8 bank, u8 pwrst); | |
172 | int pwrdm_set_mem_retst(struct powerdomain *pwrdm, u8 bank, u8 pwrst); | |
173 | ||
174 | int pwrdm_read_logic_pwrst(struct powerdomain *pwrdm); | |
175 | int pwrdm_read_prev_logic_pwrst(struct powerdomain *pwrdm); | |
176 | int pwrdm_read_mem_pwrst(struct powerdomain *pwrdm, u8 bank); | |
177 | int pwrdm_read_prev_mem_pwrst(struct powerdomain *pwrdm, u8 bank); | |
178 | ||
0b7cbfb5 PW |
179 | int pwrdm_enable_hdwr_sar(struct powerdomain *pwrdm); |
180 | int pwrdm_disable_hdwr_sar(struct powerdomain *pwrdm); | |
181 | bool pwrdm_has_hdwr_sar(struct powerdomain *pwrdm); | |
182 | ||
ad67ef68 PW |
183 | int pwrdm_wait_transition(struct powerdomain *pwrdm); |
184 | ||
ba20bb12 PDS |
185 | int pwrdm_state_switch(struct powerdomain *pwrdm); |
186 | int pwrdm_clkdm_state_switch(struct clockdomain *clkdm); | |
187 | int pwrdm_pre_transition(void); | |
188 | int pwrdm_post_transition(void); | |
189 | ||
ad67ef68 | 190 | #endif |