Commit | Line | Data |
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1da177e4 | 1 | /* |
a09e64fb | 2 | * arch/arm/plat-omap/include/mach/io.h |
1da177e4 LT |
3 | * |
4 | * IO definitions for TI OMAP processors and boards | |
5 | * | |
a09e64fb | 6 | * Copied from arch/arm/mach-sa1100/include/mach/io.h |
1da177e4 LT |
7 | * Copyright (C) 1997-1999 Russell King |
8 | * | |
44169075 SS |
9 | * Copyright (C) 2009 Texas Instruments |
10 | * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com> | |
11 | * | |
1da177e4 LT |
12 | * This program is free software; you can redistribute it and/or modify it |
13 | * under the terms of the GNU General Public License as published by the | |
14 | * Free Software Foundation; either version 2 of the License, or (at your | |
15 | * option) any later version. | |
16 | * | |
17 | * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED | |
18 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF | |
19 | * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN | |
20 | * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, | |
21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT | |
22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF | |
23 | * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON | |
24 | * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT | |
25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF | |
26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | |
27 | * | |
28 | * You should have received a copy of the GNU General Public License along | |
29 | * with this program; if not, write to the Free Software Foundation, Inc., | |
30 | * 675 Mass Ave, Cambridge, MA 02139, USA. | |
31 | * | |
32 | * Modifications: | |
33 | * 06-12-1997 RMK Created. | |
34 | * 07-04-1999 RMK Major cleanup | |
35 | */ | |
36 | ||
37 | #ifndef __ASM_ARM_ARCH_IO_H | |
38 | #define __ASM_ARM_ARCH_IO_H | |
39 | ||
a09e64fb | 40 | #include <mach/hardware.h> |
7fca0aa4 | 41 | |
1da177e4 LT |
42 | #define IO_SPACE_LIMIT 0xffffffff |
43 | ||
44 | /* | |
45 | * We don't actually have real ISA nor PCI buses, but there is so many | |
46 | * drivers out there that might just work if we fake them... | |
47 | */ | |
0560cf5a RK |
48 | #define __io(a) __typesafe_io(a) |
49 | #define __mem_pci(a) (a) | |
1da177e4 LT |
50 | |
51 | /* | |
52 | * ---------------------------------------------------------------------------- | |
53 | * I/O mapping | |
54 | * ---------------------------------------------------------------------------- | |
55 | */ | |
1da177e4 | 56 | |
94113260 TL |
57 | #ifdef __ASSEMBLER__ |
58 | #define IOMEM(x) (x) | |
59 | #else | |
60 | #define IOMEM(x) ((void __force __iomem *)(x)) | |
61 | #endif | |
62 | ||
63 | #define OMAP1_IO_OFFSET 0x01000000 /* Virtual IO = 0xfefb0000 */ | |
64 | #define OMAP1_IO_ADDRESS(pa) IOMEM((pa) - OMAP1_IO_OFFSET) | |
65 | ||
233fd64e SS |
66 | #define OMAP2_L3_IO_OFFSET 0x90000000 |
67 | #define OMAP2_L3_IO_ADDRESS(pa) IOMEM((pa) + OMAP2_L3_IO_OFFSET) /* L3 */ | |
94113260 | 68 | |
f5d2d659 SS |
69 | |
70 | #define OMAP2_L4_IO_OFFSET 0xb2000000 | |
71 | #define OMAP2_L4_IO_ADDRESS(pa) IOMEM((pa) + OMAP2_L4_IO_OFFSET) /* L4 */ | |
72 | ||
10db25fe SS |
73 | #define OMAP4_L3_IO_OFFSET 0xb4000000 |
74 | #define OMAP4_L3_IO_ADDRESS(pa) IOMEM((pa) + OMAP4_L3_IO_OFFSET) /* L3 */ | |
75 | ||
f5d2d659 SS |
76 | #define OMAP4_L3_PER_IO_OFFSET 0xb1100000 |
77 | #define OMAP4_L3_PER_IO_ADDRESS(pa) IOMEM((pa) + OMAP4_L3_PER_IO_OFFSET) | |
78 | ||
10db25fe SS |
79 | #define OMAP4_GPMC_IO_OFFSET 0xa9000000 |
80 | #define OMAP4_GPMC_IO_ADDRESS(pa) IOMEM((pa) + OMAP4_GPMC_IO_OFFSET) | |
81 | ||
10db25fe SS |
82 | #define OMAP2_EMU_IO_OFFSET 0xaa800000 /* Emulation */ |
83 | #define OMAP2_EMU_IO_ADDRESS(pa) IOMEM((pa) + OMAP2_EMU_IO_OFFSET) | |
84 | ||
db326be1 TL |
85 | /* |
86 | * ---------------------------------------------------------------------------- | |
87 | * Omap1 specific IO mapping | |
88 | * ---------------------------------------------------------------------------- | |
89 | */ | |
9ad5897c | 90 | |
db326be1 TL |
91 | #define OMAP1_IO_PHYS 0xFFFB0000 |
92 | #define OMAP1_IO_SIZE 0x40000 | |
93 | #define OMAP1_IO_VIRT (OMAP1_IO_PHYS - OMAP1_IO_OFFSET) | |
1da177e4 | 94 | |
db326be1 TL |
95 | /* |
96 | * ---------------------------------------------------------------------------- | |
97 | * Omap2 specific IO mapping | |
98 | * ---------------------------------------------------------------------------- | |
99 | */ | |
9839c6b8 | 100 | |
9ad5897c | 101 | /* We map both L3 and L4 on OMAP2 */ |
10db25fe SS |
102 | #define L3_24XX_PHYS L3_24XX_BASE /* 0x68000000 --> 0xf8000000*/ |
103 | #define L3_24XX_VIRT (L3_24XX_PHYS + OMAP2_L3_IO_OFFSET) | |
9ad5897c | 104 | #define L3_24XX_SIZE SZ_1M /* 44kB of 128MB used, want 1MB sect */ |
10db25fe SS |
105 | #define L4_24XX_PHYS L4_24XX_BASE /* 0x48000000 --> 0xfa000000 */ |
106 | #define L4_24XX_VIRT (L4_24XX_PHYS + OMAP2_L4_IO_OFFSET) | |
9ad5897c | 107 | #define L4_24XX_SIZE SZ_1M /* 1MB of 128MB used, want 1MB sect */ |
72d0f1c3 | 108 | |
10db25fe SS |
109 | #define L4_WK_243X_PHYS L4_WK_243X_BASE /* 0x49000000 --> 0xfb000000 */ |
110 | #define L4_WK_243X_VIRT (L4_WK_243X_PHYS + OMAP2_L4_IO_OFFSET) | |
72d0f1c3 | 111 | #define L4_WK_243X_SIZE SZ_1M |
10db25fe SS |
112 | #define OMAP243X_GPMC_PHYS OMAP243X_GPMC_BASE |
113 | #define OMAP243X_GPMC_VIRT (OMAP243X_GPMC_PHYS + OMAP2_L3_IO_OFFSET) | |
114 | /* 0x6e000000 --> 0xfe000000 */ | |
72d0f1c3 | 115 | #define OMAP243X_GPMC_SIZE SZ_1M |
44595982 | 116 | #define OMAP243X_SDRC_PHYS OMAP243X_SDRC_BASE |
10db25fe SS |
117 | /* 0x6D000000 --> 0xfd000000 */ |
118 | #define OMAP243X_SDRC_VIRT (OMAP243X_SDRC_PHYS + OMAP2_L3_IO_OFFSET) | |
44595982 PW |
119 | #define OMAP243X_SDRC_SIZE SZ_1M |
120 | #define OMAP243X_SMS_PHYS OMAP243X_SMS_BASE | |
10db25fe SS |
121 | /* 0x6c000000 --> 0xfc000000 */ |
122 | #define OMAP243X_SMS_VIRT (OMAP243X_SMS_PHYS + OMAP2_L3_IO_OFFSET) | |
44595982 PW |
123 | #define OMAP243X_SMS_SIZE SZ_1M |
124 | ||
7adb9987 | 125 | /* 2420 IVA */ |
51e888d7 PW |
126 | #define DSP_MEM_2420_PHYS OMAP2420_DSP_MEM_BASE |
127 | /* 0x58000000 --> 0xfc100000 */ | |
128 | #define DSP_MEM_2420_VIRT 0xfc100000 | |
7adb9987 | 129 | #define DSP_MEM_2420_SIZE 0x28000 |
51e888d7 PW |
130 | #define DSP_IPI_2420_PHYS OMAP2420_DSP_IPI_BASE |
131 | /* 0x59000000 --> 0xfc128000 */ | |
132 | #define DSP_IPI_2420_VIRT 0xfc128000 | |
7adb9987 | 133 | #define DSP_IPI_2420_SIZE SZ_4K |
51e888d7 PW |
134 | #define DSP_MMU_2420_PHYS OMAP2420_DSP_MMU_BASE |
135 | /* 0x5a000000 --> 0xfc129000 */ | |
136 | #define DSP_MMU_2420_VIRT 0xfc129000 | |
7adb9987 PW |
137 | #define DSP_MMU_2420_SIZE SZ_4K |
138 | ||
139 | /* 2430 IVA2.1 - currently unmapped */ | |
f4e4c324 | 140 | |
db326be1 TL |
141 | /* |
142 | * ---------------------------------------------------------------------------- | |
143 | * Omap3 specific IO mapping | |
144 | * ---------------------------------------------------------------------------- | |
145 | */ | |
44595982 PW |
146 | |
147 | /* We map both L3 and L4 on OMAP3 */ | |
10db25fe SS |
148 | #define L3_34XX_PHYS L3_34XX_BASE /* 0x68000000 --> 0xf8000000 */ |
149 | #define L3_34XX_VIRT (L3_34XX_PHYS + OMAP2_L3_IO_OFFSET) | |
44595982 PW |
150 | #define L3_34XX_SIZE SZ_1M /* 44kB of 128MB used, want 1MB sect */ |
151 | ||
10db25fe SS |
152 | #define L4_34XX_PHYS L4_34XX_BASE /* 0x48000000 --> 0xfa000000 */ |
153 | #define L4_34XX_VIRT (L4_34XX_PHYS + OMAP2_L4_IO_OFFSET) | |
44595982 PW |
154 | #define L4_34XX_SIZE SZ_4M /* 1MB of 128MB used, want 1MB sect */ |
155 | ||
156 | /* | |
157 | * Need to look at the Size 4M for L4. | |
158 | * VPOM3430 was not working for Int controller | |
159 | */ | |
160 | ||
10db25fe SS |
161 | #define L4_PER_34XX_PHYS L4_PER_34XX_BASE |
162 | /* 0x49000000 --> 0xfb000000 */ | |
163 | #define L4_PER_34XX_VIRT (L4_PER_34XX_PHYS + OMAP2_L4_IO_OFFSET) | |
44595982 PW |
164 | #define L4_PER_34XX_SIZE SZ_1M |
165 | ||
10db25fe SS |
166 | #define L4_EMU_34XX_PHYS L4_EMU_34XX_BASE |
167 | /* 0x54000000 --> 0xfe800000 */ | |
168 | #define L4_EMU_34XX_VIRT (L4_EMU_34XX_PHYS + OMAP2_EMU_IO_OFFSET) | |
169 | #define L4_EMU_34XX_SIZE SZ_8M | |
44595982 | 170 | |
10db25fe SS |
171 | #define OMAP34XX_GPMC_PHYS OMAP34XX_GPMC_BASE |
172 | /* 0x6e000000 --> 0xfe000000 */ | |
173 | #define OMAP34XX_GPMC_VIRT (OMAP34XX_GPMC_PHYS + OMAP2_L3_IO_OFFSET) | |
44595982 PW |
174 | #define OMAP34XX_GPMC_SIZE SZ_1M |
175 | ||
10db25fe SS |
176 | #define OMAP343X_SMS_PHYS OMAP343X_SMS_BASE |
177 | /* 0x6c000000 --> 0xfc000000 */ | |
178 | #define OMAP343X_SMS_VIRT (OMAP343X_SMS_PHYS + OMAP2_L3_IO_OFFSET) | |
44595982 PW |
179 | #define OMAP343X_SMS_SIZE SZ_1M |
180 | ||
10db25fe SS |
181 | #define OMAP343X_SDRC_PHYS OMAP343X_SDRC_BASE |
182 | /* 0x6D000000 --> 0xfd000000 */ | |
183 | #define OMAP343X_SDRC_VIRT (OMAP343X_SDRC_PHYS + OMAP2_L3_IO_OFFSET) | |
44595982 PW |
184 | #define OMAP343X_SDRC_SIZE SZ_1M |
185 | ||
7adb9987 | 186 | /* 3430 IVA - currently unmapped */ |
44595982 | 187 | |
db326be1 TL |
188 | /* |
189 | * ---------------------------------------------------------------------------- | |
190 | * Omap4 specific IO mapping | |
191 | * ---------------------------------------------------------------------------- | |
192 | */ | |
44169075 | 193 | |
44169075 | 194 | /* We map both L3 and L4 on OMAP4 */ |
10db25fe SS |
195 | #define L3_44XX_PHYS L3_44XX_BASE /* 0x44000000 --> 0xf8000000 */ |
196 | #define L3_44XX_VIRT (L3_44XX_PHYS + OMAP4_L3_IO_OFFSET) | |
44169075 SS |
197 | #define L3_44XX_SIZE SZ_1M |
198 | ||
10db25fe SS |
199 | #define L4_44XX_PHYS L4_44XX_BASE /* 0x4a000000 --> 0xfc000000 */ |
200 | #define L4_44XX_VIRT (L4_44XX_PHYS + OMAP2_L4_IO_OFFSET) | |
44169075 SS |
201 | #define L4_44XX_SIZE SZ_4M |
202 | ||
44169075 | 203 | #define L4_PER_44XX_PHYS L4_PER_44XX_BASE |
10db25fe SS |
204 | /* 0x48000000 --> 0xfa000000 */ |
205 | #define L4_PER_44XX_VIRT (L4_PER_44XX_PHYS + OMAP2_L4_IO_OFFSET) | |
44169075 SS |
206 | #define L4_PER_44XX_SIZE SZ_4M |
207 | ||
f5d2d659 SS |
208 | #define L4_ABE_44XX_PHYS L4_ABE_44XX_BASE |
209 | /* 0x49000000 --> 0xfb000000 */ | |
210 | #define L4_ABE_44XX_VIRT (L4_ABE_44XX_PHYS + OMAP2_L4_IO_OFFSET) | |
211 | #define L4_ABE_44XX_SIZE SZ_1M | |
212 | ||
44169075 | 213 | #define L4_EMU_44XX_PHYS L4_EMU_44XX_BASE |
10db25fe SS |
214 | /* 0x54000000 --> 0xfe800000 */ |
215 | #define L4_EMU_44XX_VIRT (L4_EMU_44XX_PHYS + OMAP2_EMU_IO_OFFSET) | |
216 | #define L4_EMU_44XX_SIZE SZ_8M | |
44169075 SS |
217 | |
218 | #define OMAP44XX_GPMC_PHYS OMAP44XX_GPMC_BASE | |
10db25fe SS |
219 | /* 0x50000000 --> 0xf9000000 */ |
220 | #define OMAP44XX_GPMC_VIRT (OMAP44XX_GPMC_PHYS + OMAP4_GPMC_IO_OFFSET) | |
44169075 SS |
221 | #define OMAP44XX_GPMC_SIZE SZ_1M |
222 | ||
db326be1 | 223 | |
f5d2d659 SS |
224 | #define OMAP44XX_EMIF1_PHYS OMAP44XX_EMIF1_BASE |
225 | /* 0x4c000000 --> 0xfd100000 */ | |
226 | #define OMAP44XX_EMIF1_VIRT (OMAP44XX_EMIF1_PHYS + OMAP4_L3_PER_IO_OFFSET) | |
227 | #define OMAP44XX_EMIF1_SIZE SZ_1M | |
228 | ||
229 | #define OMAP44XX_EMIF2_PHYS OMAP44XX_EMIF2_BASE | |
230 | /* 0x4d000000 --> 0xfd200000 */ | |
f5d2d659 | 231 | #define OMAP44XX_EMIF2_SIZE SZ_1M |
cefcadea | 232 | #define OMAP44XX_EMIF2_VIRT (OMAP44XX_EMIF1_VIRT + OMAP44XX_EMIF1_SIZE) |
f5d2d659 SS |
233 | |
234 | #define OMAP44XX_DMM_PHYS OMAP44XX_DMM_BASE | |
235 | /* 0x4e000000 --> 0xfd300000 */ | |
f5d2d659 | 236 | #define OMAP44XX_DMM_SIZE SZ_1M |
cefcadea | 237 | #define OMAP44XX_DMM_VIRT (OMAP44XX_EMIF2_VIRT + OMAP44XX_EMIF2_SIZE) |
db326be1 TL |
238 | /* |
239 | * ---------------------------------------------------------------------------- | |
240 | * Omap specific register access | |
241 | * ---------------------------------------------------------------------------- | |
242 | */ | |
1da177e4 | 243 | |
94113260 | 244 | #ifndef __ASSEMBLER__ |
1da177e4 LT |
245 | |
246 | /* | |
94113260 | 247 | * NOTE: Please use ioremap + __raw_read/write where possible instead of these |
1da177e4 | 248 | */ |
1da177e4 | 249 | |
8aca3ab5 TL |
250 | void omap_ioremap_init(void); |
251 | ||
94113260 TL |
252 | extern u8 omap_readb(u32 pa); |
253 | extern u16 omap_readw(u32 pa); | |
254 | extern u32 omap_readl(u32 pa); | |
255 | extern void omap_writeb(u8 v, u32 pa); | |
256 | extern void omap_writew(u16 v, u32 pa); | |
257 | extern void omap_writel(u32 v, u32 pa); | |
1da177e4 | 258 | |
87246b75 | 259 | struct omap_sdrc_params; |
a4ca9dbe | 260 | extern void omap_sdrc_init(struct omap_sdrc_params *sdrc_cs0, |
4805734b | 261 | struct omap_sdrc_params *sdrc_cs1); |
9839c6b8 | 262 | |
a0b7bd08 RK |
263 | #define __arch_ioremap omap_ioremap |
264 | #define __arch_iounmap omap_iounmap | |
690b5a13 RK |
265 | |
266 | void __iomem *omap_ioremap(unsigned long phys, size_t size, unsigned int type); | |
267 | void omap_iounmap(volatile void __iomem *addr); | |
268 | ||
009426a0 JM |
269 | extern void __init omap_init_consistent_dma_size(void); |
270 | ||
1da177e4 LT |
271 | #endif |
272 | ||
273 | #endif |