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69d88a00 | 1 | /* |
a09e64fb | 2 | * arch/arm/plat-omap/include/mach/control.h |
69d88a00 | 3 | * |
44169075 | 4 | * OMAP2/3/4 System Control Module definitions |
69d88a00 | 5 | * |
44169075 | 6 | * Copyright (C) 2007-2009 Texas Instruments, Inc. |
646e3ed1 | 7 | * Copyright (C) 2007-2008 Nokia Corporation |
69d88a00 PW |
8 | * |
9 | * Written by Paul Walmsley | |
10 | * | |
11 | * This program is free software; you can redistribute it and/or modify | |
12 | * it under the terms of the GNU General Public License as published by | |
13 | * the Free Software Foundation. | |
14 | */ | |
15 | ||
646e3ed1 TL |
16 | #ifndef __ASM_ARCH_CONTROL_H |
17 | #define __ASM_ARCH_CONTROL_H | |
18 | ||
a09e64fb | 19 | #include <mach/io.h> |
69d88a00 | 20 | |
646e3ed1 | 21 | #ifndef __ASSEMBLY__ |
69d88a00 | 22 | #define OMAP242X_CTRL_REGADDR(reg) \ |
233fd64e | 23 | OMAP2_L4_IO_ADDRESS(OMAP242X_CTRL_BASE + (reg)) |
69d88a00 | 24 | #define OMAP243X_CTRL_REGADDR(reg) \ |
233fd64e | 25 | OMAP2_L4_IO_ADDRESS(OMAP243X_CTRL_BASE + (reg)) |
69d88a00 | 26 | #define OMAP343X_CTRL_REGADDR(reg) \ |
233fd64e | 27 | OMAP2_L4_IO_ADDRESS(OMAP343X_CTRL_BASE + (reg)) |
646e3ed1 | 28 | #else |
233fd64e SS |
29 | #define OMAP242X_CTRL_REGADDR(reg) \ |
30 | OMAP2_L4_IO_ADDRESS(OMAP242X_CTRL_BASE + (reg)) | |
31 | #define OMAP243X_CTRL_REGADDR(reg) \ | |
32 | OMAP2_L4_IO_ADDRESS(OMAP243X_CTRL_BASE + (reg)) | |
33 | #define OMAP343X_CTRL_REGADDR(reg) \ | |
34 | OMAP2_L4_IO_ADDRESS(OMAP343X_CTRL_BASE + (reg)) | |
646e3ed1 | 35 | #endif /* __ASSEMBLY__ */ |
69d88a00 PW |
36 | |
37 | /* | |
38 | * As elsewhere, the "OMAP2_" prefix indicates that the macro is valid for | |
39 | * OMAP24XX and OMAP34XX. | |
40 | */ | |
41 | ||
42 | /* Control submodule offsets */ | |
43 | ||
44 | #define OMAP2_CONTROL_INTERFACE 0x000 | |
45 | #define OMAP2_CONTROL_PADCONFS 0x030 | |
46 | #define OMAP2_CONTROL_GENERAL 0x270 | |
47 | #define OMAP343X_CONTROL_MEM_WKUP 0x600 | |
48 | #define OMAP343X_CONTROL_PADCONFS_WKUP 0xa00 | |
49 | #define OMAP343X_CONTROL_GENERAL_WKUP 0xa60 | |
50 | ||
51 | /* Control register offsets - read/write with omap_ctrl_{read,write}{bwl}() */ | |
52 | ||
53 | #define OMAP2_CONTROL_SYSCONFIG (OMAP2_CONTROL_INTERFACE + 0x10) | |
54 | ||
55 | /* CONTROL_GENERAL register offsets common to OMAP2 & 3 */ | |
56 | #define OMAP2_CONTROL_DEVCONF0 (OMAP2_CONTROL_GENERAL + 0x0004) | |
57 | #define OMAP2_CONTROL_MSUSPENDMUX_0 (OMAP2_CONTROL_GENERAL + 0x0020) | |
58 | #define OMAP2_CONTROL_MSUSPENDMUX_1 (OMAP2_CONTROL_GENERAL + 0x0024) | |
59 | #define OMAP2_CONTROL_MSUSPENDMUX_2 (OMAP2_CONTROL_GENERAL + 0x0028) | |
60 | #define OMAP2_CONTROL_MSUSPENDMUX_3 (OMAP2_CONTROL_GENERAL + 0x002c) | |
61 | #define OMAP2_CONTROL_MSUSPENDMUX_4 (OMAP2_CONTROL_GENERAL + 0x0030) | |
62 | #define OMAP2_CONTROL_MSUSPENDMUX_5 (OMAP2_CONTROL_GENERAL + 0x0034) | |
63 | #define OMAP2_CONTROL_SEC_CTRL (OMAP2_CONTROL_GENERAL + 0x0040) | |
64 | #define OMAP2_CONTROL_RPUB_KEY_H_0 (OMAP2_CONTROL_GENERAL + 0x0090) | |
65 | #define OMAP2_CONTROL_RPUB_KEY_H_1 (OMAP2_CONTROL_GENERAL + 0x0094) | |
66 | #define OMAP2_CONTROL_RPUB_KEY_H_2 (OMAP2_CONTROL_GENERAL + 0x0098) | |
67 | #define OMAP2_CONTROL_RPUB_KEY_H_3 (OMAP2_CONTROL_GENERAL + 0x009c) | |
68 | ||
69 | /* 242x-only CONTROL_GENERAL register offsets */ | |
70 | #define OMAP242X_CONTROL_DEVCONF OMAP2_CONTROL_DEVCONF0 /* match TRM */ | |
71 | #define OMAP242X_CONTROL_OCM_RAM_PERM (OMAP2_CONTROL_GENERAL + 0x0068) | |
72 | ||
73 | /* 243x-only CONTROL_GENERAL register offsets */ | |
74 | /* CONTROL_IVA2_BOOT{ADDR,MOD} are at the same place on 343x - noted below */ | |
75 | #define OMAP243X_CONTROL_DEVCONF1 (OMAP2_CONTROL_GENERAL + 0x0078) | |
76 | #define OMAP243X_CONTROL_CSIRXFE (OMAP2_CONTROL_GENERAL + 0x007c) | |
77 | #define OMAP243X_CONTROL_IVA2_BOOTADDR (OMAP2_CONTROL_GENERAL + 0x0190) | |
78 | #define OMAP243X_CONTROL_IVA2_BOOTMOD (OMAP2_CONTROL_GENERAL + 0x0194) | |
79 | #define OMAP243X_CONTROL_IVA2_GEMCFG (OMAP2_CONTROL_GENERAL + 0x0198) | |
90c62bf0 | 80 | #define OMAP243X_CONTROL_PBIAS_LITE (OMAP2_CONTROL_GENERAL + 0x0230) |
69d88a00 PW |
81 | |
82 | /* 24xx-only CONTROL_GENERAL register offsets */ | |
83 | #define OMAP24XX_CONTROL_DEBOBS (OMAP2_CONTROL_GENERAL + 0x0000) | |
84 | #define OMAP24XX_CONTROL_EMU_SUPPORT (OMAP2_CONTROL_GENERAL + 0x0008) | |
85 | #define OMAP24XX_CONTROL_SEC_TEST (OMAP2_CONTROL_GENERAL + 0x0044) | |
86 | #define OMAP24XX_CONTROL_PSA_CTRL (OMAP2_CONTROL_GENERAL + 0x0048) | |
87 | #define OMAP24XX_CONTROL_PSA_CMD (OMAP2_CONTROL_GENERAL + 0x004c) | |
88 | #define OMAP24XX_CONTROL_PSA_VALUE (OMAP2_CONTROL_GENERAL + 0x0050) | |
89 | #define OMAP24XX_CONTROL_SEC_EMU (OMAP2_CONTROL_GENERAL + 0x0060) | |
90 | #define OMAP24XX_CONTROL_SEC_TAP (OMAP2_CONTROL_GENERAL + 0x0064) | |
91 | #define OMAP24XX_CONTROL_OCM_PUB_RAM_ADD (OMAP2_CONTROL_GENERAL + 0x006c) | |
92 | #define OMAP24XX_CONTROL_EXT_SEC_RAM_START_ADD (OMAP2_CONTROL_GENERAL + 0x0070) | |
1df5a8d0 | 93 | #define OMAP24XX_CONTROL_EXT_SEC_RAM_STOP_ADD (OMAP2_CONTROL_GENERAL + 0x0074) |
69d88a00 PW |
94 | #define OMAP24XX_CONTROL_SEC_STATUS (OMAP2_CONTROL_GENERAL + 0x0080) |
95 | #define OMAP24XX_CONTROL_SEC_ERR_STATUS (OMAP2_CONTROL_GENERAL + 0x0084) | |
96 | #define OMAP24XX_CONTROL_STATUS (OMAP2_CONTROL_GENERAL + 0x0088) | |
97 | #define OMAP24XX_CONTROL_GENERAL_PURPOSE_STATUS (OMAP2_CONTROL_GENERAL + 0x008c) | |
98 | #define OMAP24XX_CONTROL_RAND_KEY_0 (OMAP2_CONTROL_GENERAL + 0x00a0) | |
99 | #define OMAP24XX_CONTROL_RAND_KEY_1 (OMAP2_CONTROL_GENERAL + 0x00a4) | |
100 | #define OMAP24XX_CONTROL_RAND_KEY_2 (OMAP2_CONTROL_GENERAL + 0x00a8) | |
101 | #define OMAP24XX_CONTROL_RAND_KEY_3 (OMAP2_CONTROL_GENERAL + 0x00ac) | |
102 | #define OMAP24XX_CONTROL_CUST_KEY_0 (OMAP2_CONTROL_GENERAL + 0x00b0) | |
103 | #define OMAP24XX_CONTROL_CUST_KEY_1 (OMAP2_CONTROL_GENERAL + 0x00b4) | |
104 | #define OMAP24XX_CONTROL_TEST_KEY_0 (OMAP2_CONTROL_GENERAL + 0x00c0) | |
105 | #define OMAP24XX_CONTROL_TEST_KEY_1 (OMAP2_CONTROL_GENERAL + 0x00c4) | |
106 | #define OMAP24XX_CONTROL_TEST_KEY_2 (OMAP2_CONTROL_GENERAL + 0x00c8) | |
107 | #define OMAP24XX_CONTROL_TEST_KEY_3 (OMAP2_CONTROL_GENERAL + 0x00cc) | |
108 | #define OMAP24XX_CONTROL_TEST_KEY_4 (OMAP2_CONTROL_GENERAL + 0x00d0) | |
109 | #define OMAP24XX_CONTROL_TEST_KEY_5 (OMAP2_CONTROL_GENERAL + 0x00d4) | |
110 | #define OMAP24XX_CONTROL_TEST_KEY_6 (OMAP2_CONTROL_GENERAL + 0x00d8) | |
111 | #define OMAP24XX_CONTROL_TEST_KEY_7 (OMAP2_CONTROL_GENERAL + 0x00dc) | |
112 | #define OMAP24XX_CONTROL_TEST_KEY_8 (OMAP2_CONTROL_GENERAL + 0x00e0) | |
113 | #define OMAP24XX_CONTROL_TEST_KEY_9 (OMAP2_CONTROL_GENERAL + 0x00e4) | |
114 | ||
c171a258 RN |
115 | #define OMAP343X_CONTROL_PADCONF_SYSNIRQ (OMAP2_CONTROL_INTERFACE + 0x01b0) |
116 | ||
69d88a00 PW |
117 | /* 34xx-only CONTROL_GENERAL register offsets */ |
118 | #define OMAP343X_CONTROL_PADCONF_OFF (OMAP2_CONTROL_GENERAL + 0x0000) | |
119 | #define OMAP343X_CONTROL_MEM_DFTRW0 (OMAP2_CONTROL_GENERAL + 0x0008) | |
120 | #define OMAP343X_CONTROL_MEM_DFTRW1 (OMAP2_CONTROL_GENERAL + 0x000c) | |
121 | #define OMAP343X_CONTROL_DEVCONF1 (OMAP2_CONTROL_GENERAL + 0x0068) | |
122 | #define OMAP343X_CONTROL_CSIRXFE (OMAP2_CONTROL_GENERAL + 0x006c) | |
123 | #define OMAP343X_CONTROL_SEC_STATUS (OMAP2_CONTROL_GENERAL + 0x0070) | |
124 | #define OMAP343X_CONTROL_SEC_ERR_STATUS (OMAP2_CONTROL_GENERAL + 0x0074) | |
125 | #define OMAP343X_CONTROL_SEC_ERR_STATUS_DEBUG (OMAP2_CONTROL_GENERAL + 0x0078) | |
126 | #define OMAP343X_CONTROL_STATUS (OMAP2_CONTROL_GENERAL + 0x0080) | |
127 | #define OMAP343X_CONTROL_GENERAL_PURPOSE_STATUS (OMAP2_CONTROL_GENERAL + 0x0084) | |
128 | #define OMAP343X_CONTROL_RPUB_KEY_H_4 (OMAP2_CONTROL_GENERAL + 0x00a0) | |
129 | #define OMAP343X_CONTROL_RAND_KEY_0 (OMAP2_CONTROL_GENERAL + 0x00a8) | |
130 | #define OMAP343X_CONTROL_RAND_KEY_1 (OMAP2_CONTROL_GENERAL + 0x00ac) | |
131 | #define OMAP343X_CONTROL_RAND_KEY_2 (OMAP2_CONTROL_GENERAL + 0x00b0) | |
132 | #define OMAP343X_CONTROL_RAND_KEY_3 (OMAP2_CONTROL_GENERAL + 0x00b4) | |
133 | #define OMAP343X_CONTROL_TEST_KEY_0 (OMAP2_CONTROL_GENERAL + 0x00c8) | |
134 | #define OMAP343X_CONTROL_TEST_KEY_1 (OMAP2_CONTROL_GENERAL + 0x00cc) | |
135 | #define OMAP343X_CONTROL_TEST_KEY_2 (OMAP2_CONTROL_GENERAL + 0x00d0) | |
136 | #define OMAP343X_CONTROL_TEST_KEY_3 (OMAP2_CONTROL_GENERAL + 0x00d4) | |
137 | #define OMAP343X_CONTROL_TEST_KEY_4 (OMAP2_CONTROL_GENERAL + 0x00d8) | |
138 | #define OMAP343X_CONTROL_TEST_KEY_5 (OMAP2_CONTROL_GENERAL + 0x00dc) | |
139 | #define OMAP343X_CONTROL_TEST_KEY_6 (OMAP2_CONTROL_GENERAL + 0x00e0) | |
140 | #define OMAP343X_CONTROL_TEST_KEY_7 (OMAP2_CONTROL_GENERAL + 0x00e4) | |
141 | #define OMAP343X_CONTROL_TEST_KEY_8 (OMAP2_CONTROL_GENERAL + 0x00e8) | |
142 | #define OMAP343X_CONTROL_TEST_KEY_9 (OMAP2_CONTROL_GENERAL + 0x00ec) | |
143 | #define OMAP343X_CONTROL_TEST_KEY_10 (OMAP2_CONTROL_GENERAL + 0x00f0) | |
144 | #define OMAP343X_CONTROL_TEST_KEY_11 (OMAP2_CONTROL_GENERAL + 0x00f4) | |
145 | #define OMAP343X_CONTROL_TEST_KEY_12 (OMAP2_CONTROL_GENERAL + 0x00f8) | |
146 | #define OMAP343X_CONTROL_TEST_KEY_13 (OMAP2_CONTROL_GENERAL + 0x00fc) | |
147 | #define OMAP343X_CONTROL_IVA2_BOOTADDR (OMAP2_CONTROL_GENERAL + 0x0190) | |
148 | #define OMAP343X_CONTROL_IVA2_BOOTMOD (OMAP2_CONTROL_GENERAL + 0x0194) | |
c96631e1 RN |
149 | #define OMAP343X_CONTROL_DEBOBS(i) (OMAP2_CONTROL_GENERAL + 0x01B0 \ |
150 | + ((i) >> 1) * 4 + (!(i) & 1) * 2) | |
151 | #define OMAP343X_CONTROL_PROG_IO0 (OMAP2_CONTROL_GENERAL + 0x01D4) | |
152 | #define OMAP343X_CONTROL_PROG_IO1 (OMAP2_CONTROL_GENERAL + 0x01D8) | |
153 | #define OMAP343X_CONTROL_DSS_DPLL_SPREADING (OMAP2_CONTROL_GENERAL + 0x01E0) | |
154 | #define OMAP343X_CONTROL_CORE_DPLL_SPREADING (OMAP2_CONTROL_GENERAL + 0x01E4) | |
155 | #define OMAP343X_CONTROL_PER_DPLL_SPREADING (OMAP2_CONTROL_GENERAL + 0x01E8) | |
156 | #define OMAP343X_CONTROL_USBHOST_DPLL_SPREADING (OMAP2_CONTROL_GENERAL + 0x01EC) | |
157 | #define OMAP343X_CONTROL_PBIAS_LITE (OMAP2_CONTROL_GENERAL + 0x02B0) | |
158 | #define OMAP343X_CONTROL_TEMP_SENSOR (OMAP2_CONTROL_GENERAL + 0x02B4) | |
159 | #define OMAP343X_CONTROL_SRAMLDO4 (OMAP2_CONTROL_GENERAL + 0x02B8) | |
160 | #define OMAP343X_CONTROL_SRAMLDO5 (OMAP2_CONTROL_GENERAL + 0x02C0) | |
161 | #define OMAP343X_CONTROL_CSI (OMAP2_CONTROL_GENERAL + 0x02C4) | |
162 | ||
163 | ||
164 | /* 34xx PADCONF register offsets */ | |
165 | #define OMAP343X_PADCONF_ETK(i) (OMAP2_CONTROL_PADCONFS + 0x5a8 + \ | |
166 | (i)*2) | |
167 | #define OMAP343X_PADCONF_ETK_CLK OMAP343X_PADCONF_ETK(0) | |
168 | #define OMAP343X_PADCONF_ETK_CTL OMAP343X_PADCONF_ETK(1) | |
169 | #define OMAP343X_PADCONF_ETK_D0 OMAP343X_PADCONF_ETK(2) | |
170 | #define OMAP343X_PADCONF_ETK_D1 OMAP343X_PADCONF_ETK(3) | |
171 | #define OMAP343X_PADCONF_ETK_D2 OMAP343X_PADCONF_ETK(4) | |
172 | #define OMAP343X_PADCONF_ETK_D3 OMAP343X_PADCONF_ETK(5) | |
173 | #define OMAP343X_PADCONF_ETK_D4 OMAP343X_PADCONF_ETK(6) | |
174 | #define OMAP343X_PADCONF_ETK_D5 OMAP343X_PADCONF_ETK(7) | |
175 | #define OMAP343X_PADCONF_ETK_D6 OMAP343X_PADCONF_ETK(8) | |
176 | #define OMAP343X_PADCONF_ETK_D7 OMAP343X_PADCONF_ETK(9) | |
177 | #define OMAP343X_PADCONF_ETK_D8 OMAP343X_PADCONF_ETK(10) | |
178 | #define OMAP343X_PADCONF_ETK_D9 OMAP343X_PADCONF_ETK(11) | |
179 | #define OMAP343X_PADCONF_ETK_D10 OMAP343X_PADCONF_ETK(12) | |
180 | #define OMAP343X_PADCONF_ETK_D11 OMAP343X_PADCONF_ETK(13) | |
181 | #define OMAP343X_PADCONF_ETK_D12 OMAP343X_PADCONF_ETK(14) | |
182 | #define OMAP343X_PADCONF_ETK_D13 OMAP343X_PADCONF_ETK(15) | |
183 | #define OMAP343X_PADCONF_ETK_D14 OMAP343X_PADCONF_ETK(16) | |
184 | #define OMAP343X_PADCONF_ETK_D15 OMAP343X_PADCONF_ETK(17) | |
185 | ||
186 | /* 34xx GENERAL_WKUP regist offsets */ | |
187 | #define OMAP343X_CONTROL_WKUP_DEBOBSMUX(i) (OMAP343X_CONTROL_GENERAL_WKUP + \ | |
188 | 0x008 + (i)) | |
189 | #define OMAP343X_CONTROL_WKUP_DEBOBS0 (OMAP343X_CONTROL_GENERAL_WKUP + 0x008) | |
190 | #define OMAP343X_CONTROL_WKUP_DEBOBS1 (OMAP343X_CONTROL_GENERAL_WKUP + 0x00C) | |
191 | #define OMAP343X_CONTROL_WKUP_DEBOBS2 (OMAP343X_CONTROL_GENERAL_WKUP + 0x010) | |
192 | #define OMAP343X_CONTROL_WKUP_DEBOBS3 (OMAP343X_CONTROL_GENERAL_WKUP + 0x014) | |
193 | #define OMAP343X_CONTROL_WKUP_DEBOBS4 (OMAP343X_CONTROL_GENERAL_WKUP + 0x018) | |
69d88a00 | 194 | |
8111b221 KH |
195 | /* 34xx D2D idle-related pins, handled by PM core */ |
196 | #define OMAP3_PADCONF_SAD2D_MSTANDBY 0x250 | |
197 | #define OMAP3_PADCONF_SAD2D_IDLEACK 0x254 | |
198 | ||
69d88a00 PW |
199 | /* |
200 | * REVISIT: This list of registers is not comprehensive - there are more | |
201 | * that should be added. | |
202 | */ | |
203 | ||
204 | /* | |
205 | * Control module register bit defines - these should eventually go into | |
206 | * their own regbits file. Some of these will be complicated, depending | |
207 | * on the device type (general-purpose, emulator, test, secure, bad, other) | |
208 | * and the security mode (secure, non-secure, don't care) | |
209 | */ | |
210 | /* CONTROL_DEVCONF0 bits */ | |
90c62bf0 | 211 | #define OMAP2_MMCSDIO1ADPCLKISEL (1 << 24) /* MMC1 loop back clock */ |
69d88a00 PW |
212 | #define OMAP24XX_USBSTANDBYCTRL (1 << 15) |
213 | #define OMAP2_MCBSP2_CLKS_MASK (1 << 6) | |
214 | #define OMAP2_MCBSP1_CLKS_MASK (1 << 2) | |
215 | ||
216 | /* CONTROL_DEVCONF1 bits */ | |
90c62bf0 TL |
217 | #define OMAP243X_MMC1_ACTIVE_OVERWRITE (1 << 31) |
218 | #define OMAP2_MMCSDIO2ADPCLKISEL (1 << 6) /* MMC2 loop back clock */ | |
69d88a00 PW |
219 | #define OMAP2_MCBSP5_CLKS_MASK (1 << 4) /* > 242x */ |
220 | #define OMAP2_MCBSP4_CLKS_MASK (1 << 2) /* > 242x */ | |
221 | #define OMAP2_MCBSP3_CLKS_MASK (1 << 0) /* > 242x */ | |
222 | ||
223 | /* CONTROL_STATUS bits */ | |
224 | #define OMAP2_DEVICETYPE_MASK (0x7 << 8) | |
225 | #define OMAP2_SYSBOOT_5_MASK (1 << 5) | |
226 | #define OMAP2_SYSBOOT_4_MASK (1 << 4) | |
227 | #define OMAP2_SYSBOOT_3_MASK (1 << 3) | |
228 | #define OMAP2_SYSBOOT_2_MASK (1 << 2) | |
229 | #define OMAP2_SYSBOOT_1_MASK (1 << 1) | |
230 | #define OMAP2_SYSBOOT_0_MASK (1 << 0) | |
231 | ||
90c62bf0 TL |
232 | /* CONTROL_PBIAS_LITE bits */ |
233 | #define OMAP343X_PBIASLITESUPPLY_HIGH1 (1 << 15) | |
234 | #define OMAP343X_PBIASLITEVMODEERROR1 (1 << 11) | |
235 | #define OMAP343X_PBIASSPEEDCTRL1 (1 << 10) | |
236 | #define OMAP343X_PBIASLITEPWRDNZ1 (1 << 9) | |
237 | #define OMAP343X_PBIASLITEVMODE1 (1 << 8) | |
238 | #define OMAP343X_PBIASLITESUPPLY_HIGH0 (1 << 7) | |
239 | #define OMAP343X_PBIASLITEVMODEERROR0 (1 << 3) | |
240 | #define OMAP2_PBIASSPEEDCTRL0 (1 << 2) | |
241 | #define OMAP2_PBIASLITEPWRDNZ0 (1 << 1) | |
242 | #define OMAP2_PBIASLITEVMODE0 (1 << 0) | |
243 | ||
1155e426 KH |
244 | /* CONTROL_IVA2_BOOTMOD bits */ |
245 | #define OMAP3_IVA2_BOOTMOD_SHIFT 0 | |
246 | #define OMAP3_IVA2_BOOTMOD_MASK (0xf << 0) | |
247 | #define OMAP3_IVA2_BOOTMOD_IDLE (0x1 << 0) | |
248 | ||
5a1a5abd KH |
249 | /* CONTROL_PADCONF_X bits */ |
250 | #define OMAP3_PADCONF_WAKEUPEVENT0 (1 << 15) | |
251 | #define OMAP3_PADCONF_WAKEUPENABLE0 (1 << 14) | |
252 | ||
80140786 RN |
253 | #define OMAP343X_SCRATCHPAD_ROM (OMAP343X_CTRL_BASE + 0x860) |
254 | #define OMAP343X_SCRATCHPAD (OMAP343X_CTRL_BASE + 0x910) | |
255 | #define OMAP343X_SCRATCHPAD_ROM_OFFSET 0x19C | |
256 | ||
69d88a00 | 257 | #ifndef __ASSEMBLY__ |
44169075 SS |
258 | #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) || \ |
259 | defined(CONFIG_ARCH_OMAP4) | |
a58caad1 | 260 | extern void __iomem *omap_ctrl_base_get(void); |
69d88a00 PW |
261 | extern u8 omap_ctrl_readb(u16 offset); |
262 | extern u16 omap_ctrl_readw(u16 offset); | |
263 | extern u32 omap_ctrl_readl(u16 offset); | |
264 | extern void omap_ctrl_writeb(u8 val, u16 offset); | |
265 | extern void omap_ctrl_writew(u16 val, u16 offset); | |
266 | extern void omap_ctrl_writel(u32 val, u16 offset); | |
80140786 RN |
267 | |
268 | extern void omap3_save_scratchpad_contents(void); | |
269 | extern void omap3_clear_scratchpad_contents(void); | |
270 | extern u32 *get_restore_pointer(void); | |
0795a75a | 271 | extern u32 *get_es3_restore_pointer(void); |
80140786 | 272 | extern u32 omap3_arm_context[128]; |
c96631e1 RN |
273 | extern void omap3_control_save_context(void); |
274 | extern void omap3_control_restore_context(void); | |
80140786 | 275 | |
69d88a00 | 276 | #else |
69d88a00 PW |
277 | #define omap_ctrl_base_get() 0 |
278 | #define omap_ctrl_readb(x) 0 | |
279 | #define omap_ctrl_readw(x) 0 | |
280 | #define omap_ctrl_readl(x) 0 | |
281 | #define omap_ctrl_writeb(x, y) WARN_ON(1) | |
282 | #define omap_ctrl_writew(x, y) WARN_ON(1) | |
283 | #define omap_ctrl_writel(x, y) WARN_ON(1) | |
284 | #endif | |
285 | #endif /* __ASSEMBLY__ */ | |
286 | ||
287 | #endif /* __ASM_ARCH_CONTROL_H */ | |
288 |