Commit | Line | Data |
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9ad5897c | 1 | /* |
93340a22 | 2 | * OMAP clock: data structure definitions, function prototypes, shared macros |
9ad5897c | 3 | * |
93340a22 PW |
4 | * Copyright (C) 2004-2005, 2008-2010 Nokia Corporation |
5 | * Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com> | |
6 | * Based on clocks.h by Tony Lindgren, Gordon McNutt and RidgeRun, Inc | |
9ad5897c TL |
7 | * |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License version 2 as | |
10 | * published by the Free Software Foundation. | |
11 | */ | |
12 | ||
13 | #ifndef __ARCH_ARM_OMAP_CLOCK_H | |
14 | #define __ARCH_ARM_OMAP_CLOCK_H | |
15 | ||
d8a94458 PW |
16 | #include <linux/list.h> |
17 | ||
9ad5897c | 18 | struct module; |
6b8858a9 | 19 | struct clk; |
d1b03f61 | 20 | struct clockdomain; |
6b8858a9 | 21 | |
b3c1cff6 PW |
22 | /** |
23 | * struct clkops - some clock function pointers | |
24 | * @enable: fn ptr that enables the current clock in hardware | |
25 | * @disable: fn ptr that enables the current clock in hardware | |
26 | * @find_idlest: function returning the IDLEST register for the clock's IP blk | |
27 | * @find_companion: function returning the "companion" clk reg for the clock | |
58e846fe RN |
28 | * @allow_idle: fn ptr that enables autoidle for the current clock in hardware |
29 | * @deny_idle: fn ptr that disables autoidle for the current clock in hardware | |
b3c1cff6 PW |
30 | * |
31 | * A "companion" clk is an accompanying clock to the one being queried | |
32 | * that must be enabled for the IP module connected to the clock to | |
33 | * become accessible by the hardware. Neither @find_idlest nor | |
34 | * @find_companion should be needed; that information is IP | |
35 | * block-specific; the hwmod code has been created to handle this, but | |
36 | * until hwmod data is ready and drivers have been converted to use PM | |
37 | * runtime calls in place of clk_enable()/clk_disable(), @find_idlest and | |
38 | * @find_companion must, unfortunately, remain. | |
39 | */ | |
548d8495 RK |
40 | struct clkops { |
41 | int (*enable)(struct clk *); | |
42 | void (*disable)(struct clk *); | |
419cc97d RL |
43 | void (*find_idlest)(struct clk *, void __iomem **, |
44 | u8 *, u8 *); | |
45 | void (*find_companion)(struct clk *, void __iomem **, | |
46 | u8 *); | |
58e846fe RN |
47 | void (*allow_idle)(struct clk *); |
48 | void (*deny_idle)(struct clk *); | |
548d8495 RK |
49 | }; |
50 | ||
140455fa | 51 | #ifdef CONFIG_ARCH_OMAP2PLUS |
6b8858a9 | 52 | |
b3c1cff6 PW |
53 | /* struct clksel_rate.flags possibilities */ |
54 | #define RATE_IN_242X (1 << 0) | |
55 | #define RATE_IN_243X (1 << 1) | |
553d239a PW |
56 | #define RATE_IN_3430ES1 (1 << 2) /* 3430ES1 rates only */ |
57 | #define RATE_IN_3430ES2PLUS (1 << 3) /* 3430 ES >= 2 rates only */ | |
b3c1cff6 PW |
58 | #define RATE_IN_36XX (1 << 4) |
59 | #define RATE_IN_4430 (1 << 5) | |
4bd7be22 | 60 | #define RATE_IN_TI816X (1 << 6) |
b3c1cff6 PW |
61 | |
62 | #define RATE_IN_24XX (RATE_IN_242X | RATE_IN_243X) | |
553d239a PW |
63 | #define RATE_IN_34XX (RATE_IN_3430ES1 | RATE_IN_3430ES2PLUS) |
64 | #define RATE_IN_3XXX (RATE_IN_34XX | RATE_IN_36XX) | |
65 | ||
66 | /* RATE_IN_3430ES2PLUS_36XX includes 34xx/35xx with ES >=2, and all 36xx/37xx */ | |
67 | #define RATE_IN_3430ES2PLUS_36XX (RATE_IN_3430ES2PLUS | RATE_IN_36XX) | |
68 | ||
b3c1cff6 PW |
69 | |
70 | /** | |
71 | * struct clksel_rate - register bitfield values corresponding to clk divisors | |
72 | * @val: register bitfield value (shifted to bit 0) | |
73 | * @div: clock divisor corresponding to @val | |
74 | * @flags: (see "struct clksel_rate.flags possibilities" above) | |
75 | * | |
76 | * @val should match the value of a read from struct clk.clksel_reg | |
77 | * AND'ed with struct clk.clksel_mask, shifted right to bit 0. | |
78 | * | |
79 | * @div is the divisor that should be applied to the parent clock's rate | |
80 | * to produce the current clock's rate. | |
81 | * | |
82 | * XXX @flags probably should be replaced with an struct omap_chip. | |
83 | */ | |
6b8858a9 | 84 | struct clksel_rate { |
6b8858a9 | 85 | u32 val; |
ebb8dca2 | 86 | u8 div; |
6b8858a9 PW |
87 | u8 flags; |
88 | }; | |
89 | ||
b3c1cff6 PW |
90 | /** |
91 | * struct clksel - available parent clocks, and a pointer to their divisors | |
92 | * @parent: struct clk * to a possible parent clock | |
93 | * @rates: available divisors for this parent clock | |
94 | * | |
95 | * A struct clksel is always associated with one or more struct clks | |
96 | * and one or more struct clksel_rates. | |
97 | */ | |
6b8858a9 PW |
98 | struct clksel { |
99 | struct clk *parent; | |
100 | const struct clksel_rate *rates; | |
101 | }; | |
102 | ||
93340a22 PW |
103 | /** |
104 | * struct dpll_data - DPLL registers and integration data | |
105 | * @mult_div1_reg: register containing the DPLL M and N bitfields | |
106 | * @mult_mask: mask of the DPLL M bitfield in @mult_div1_reg | |
107 | * @div1_mask: mask of the DPLL N bitfield in @mult_div1_reg | |
108 | * @clk_bypass: struct clk pointer to the clock's bypass clock input | |
109 | * @clk_ref: struct clk pointer to the clock's reference clock input | |
110 | * @control_reg: register containing the DPLL mode bitfield | |
111 | * @enable_mask: mask of the DPLL mode bitfield in @control_reg | |
93340a22 PW |
112 | * @last_rounded_rate: cache of the last rate result of omap2_dpll_round_rate() |
113 | * @last_rounded_m: cache of the last M result of omap2_dpll_round_rate() | |
114 | * @max_multiplier: maximum valid non-bypass multiplier value (actual) | |
115 | * @last_rounded_n: cache of the last N result of omap2_dpll_round_rate() | |
116 | * @min_divider: minimum valid non-bypass divider value (actual) | |
117 | * @max_divider: maximum valid non-bypass divider value (actual) | |
118 | * @modes: possible values of @enable_mask | |
119 | * @autoidle_reg: register containing the DPLL autoidle mode bitfield | |
120 | * @idlest_reg: register containing the DPLL idle status bitfield | |
121 | * @autoidle_mask: mask of the DPLL autoidle mode bitfield in @autoidle_reg | |
122 | * @freqsel_mask: mask of the DPLL jitter correction bitfield in @control_reg | |
123 | * @idlest_mask: mask of the DPLL idle status bitfield in @idlest_reg | |
124 | * @auto_recal_bit: bitshift of the driftguard enable bit in @control_reg | |
125 | * @recal_en_bit: bitshift of the PRM_IRQENABLE_* bit for recalibration IRQs | |
126 | * @recal_st_bit: bitshift of the PRM_IRQSTATUS_* bit for recalibration IRQs | |
127 | * @flags: DPLL type/features (see below) | |
128 | * | |
129 | * Possible values for @flags: | |
130 | * DPLL_J_TYPE: "J-type DPLL" (only some 36xx, 4xxx DPLLs) | |
a36795c1 | 131 | * |
93340a22 PW |
132 | * @freqsel_mask is only used on the OMAP34xx family and AM35xx. |
133 | * | |
134 | * XXX Some DPLLs have multiple bypass inputs, so it's not technically | |
135 | * correct to only have one @clk_bypass pointer. | |
136 | * | |
93340a22 PW |
137 | * XXX The runtime-variable fields (@last_rounded_rate, @last_rounded_m, |
138 | * @last_rounded_n) should be separated from the runtime-fixed fields | |
241d3a8d | 139 | * and placed into a different structure, so that the runtime-fixed data |
93340a22 | 140 | * can be placed into read-only space. |
358965d7 | 141 | */ |
6b8858a9 PW |
142 | struct dpll_data { |
143 | void __iomem *mult_div1_reg; | |
144 | u32 mult_mask; | |
145 | u32 div1_mask; | |
c0bf3132 RK |
146 | struct clk *clk_bypass; |
147 | struct clk *clk_ref; | |
148 | void __iomem *control_reg; | |
149 | u32 enable_mask; | |
ebb8dca2 | 150 | unsigned long last_rounded_rate; |
88b8ba90 | 151 | u16 last_rounded_m; |
93340a22 | 152 | u16 max_multiplier; |
88b8ba90 | 153 | u8 last_rounded_n; |
95f538ac | 154 | u8 min_divider; |
88b8ba90 | 155 | u8 max_divider; |
542313cc | 156 | u8 modes; |
93340a22 | 157 | #if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4) |
ebb8dca2 RK |
158 | void __iomem *autoidle_reg; |
159 | void __iomem *idlest_reg; | |
ebb8dca2 | 160 | u32 autoidle_mask; |
16c90f02 | 161 | u32 freqsel_mask; |
c1bd7aaf | 162 | u32 idlest_mask; |
a36795c1 JH |
163 | u32 dco_mask; |
164 | u32 sddiv_mask; | |
b045d080 PW |
165 | u8 auto_recal_bit; |
166 | u8 recal_en_bit; | |
167 | u8 recal_st_bit; | |
358965d7 | 168 | u8 flags; |
b045d080 | 169 | # endif |
6b8858a9 PW |
170 | }; |
171 | ||
172 | #endif | |
9ad5897c | 173 | |
97f67898 RN |
174 | /* |
175 | * struct clk.flags possibilities | |
176 | * | |
177 | * XXX document the rest of the clock flags here | |
178 | * | |
179 | * CLOCK_CLKOUTX2: (OMAP4 only) DPLL CLKOUT and CLKOUTX2 GATE_CTRL | |
180 | * bits share the same register. This flag allows the | |
181 | * omap4_dpllmx*() code to determine which GATE_CTRL bit field | |
182 | * should be used. This is a temporary solution - a better approach | |
183 | * would be to associate clock type-specific data with the clock, | |
184 | * similar to the struct dpll_data approach. | |
185 | */ | |
b3c1cff6 PW |
186 | #define ENABLE_REG_32BIT (1 << 0) /* Use 32-bit access */ |
187 | #define CLOCK_IDLE_CONTROL (1 << 1) | |
188 | #define CLOCK_NO_IDLE_PARENT (1 << 2) | |
189 | #define ENABLE_ON_INIT (1 << 3) /* Enable upon framework init */ | |
190 | #define INVERT_ENABLE (1 << 4) /* 0 enables, 1 disables */ | |
97f67898 | 191 | #define CLOCK_CLKOUTX2 (1 << 5) |
b3c1cff6 PW |
192 | |
193 | /** | |
194 | * struct clk - OMAP struct clk | |
195 | * @node: list_head connecting this clock into the full clock list | |
196 | * @ops: struct clkops * for this clock | |
197 | * @name: the name of the clock in the hardware (used in hwmod data and debug) | |
198 | * @parent: pointer to this clock's parent struct clk | |
199 | * @children: list_head connecting to the child clks' @sibling list_heads | |
200 | * @sibling: list_head connecting this clk to its parent clk's @children | |
201 | * @rate: current clock rate | |
202 | * @enable_reg: register to write to enable the clock (see @enable_bit) | |
203 | * @recalc: fn ptr that returns the clock's current rate | |
204 | * @set_rate: fn ptr that can change the clock's current rate | |
205 | * @round_rate: fn ptr that can round the clock's current rate | |
206 | * @init: fn ptr to do clock-specific initialization | |
207 | * @enable_bit: bitshift to write to enable/disable the clock (see @enable_reg) | |
208 | * @usecount: number of users that have requested this clock to be enabled | |
209 | * @fixed_div: when > 0, this clock's rate is its parent's rate / @fixed_div | |
210 | * @flags: see "struct clk.flags possibilities" above | |
211 | * @clksel_reg: for clksel clks, register va containing src/divisor select | |
212 | * @clksel_mask: bitmask in @clksel_reg for the src/divisor selector | |
213 | * @clksel: for clksel clks, pointer to struct clksel for this clock | |
214 | * @dpll_data: for DPLLs, pointer to struct dpll_data for this clock | |
215 | * @clkdm_name: clockdomain name that this clock is contained in | |
216 | * @clkdm: pointer to struct clockdomain, resolved from @clkdm_name at runtime | |
217 | * @rate_offset: bitshift for rate selection bitfield (OMAP1 only) | |
218 | * @src_offset: bitshift for source selection bitfield (OMAP1 only) | |
219 | * | |
220 | * XXX @rate_offset, @src_offset should probably be removed and OMAP1 | |
221 | * clock code converted to use clksel. | |
222 | * | |
223 | * XXX @usecount is poorly named. It should be "enable_count" or | |
224 | * something similar. "users" in the description refers to kernel | |
225 | * code (core code or drivers) that have called clk_enable() and not | |
226 | * yet called clk_disable(); the usecount of parent clocks is also | |
227 | * incremented by the clock code when clk_enable() is called on child | |
228 | * clocks and decremented by the clock code when clk_disable() is | |
229 | * called on child clocks. | |
230 | * | |
231 | * XXX @clkdm, @usecount, @children, @sibling should be marked for | |
232 | * internal use only. | |
233 | * | |
234 | * @children and @sibling are used to optimize parent-to-child clock | |
235 | * tree traversals. (child-to-parent traversals use @parent.) | |
236 | * | |
237 | * XXX The notion of the clock's current rate probably needs to be | |
238 | * separated from the clock's target rate. | |
239 | */ | |
9ad5897c TL |
240 | struct clk { |
241 | struct list_head node; | |
548d8495 | 242 | const struct clkops *ops; |
9ad5897c TL |
243 | const char *name; |
244 | struct clk *parent; | |
3f0a820c RK |
245 | struct list_head children; |
246 | struct list_head sibling; /* node for children */ | |
9ad5897c | 247 | unsigned long rate; |
9ad5897c | 248 | void __iomem *enable_reg; |
8b9dbc16 | 249 | unsigned long (*recalc)(struct clk *); |
9ad5897c TL |
250 | int (*set_rate)(struct clk *, unsigned long); |
251 | long (*round_rate)(struct clk *, unsigned long); | |
252 | void (*init)(struct clk *); | |
b3c1cff6 PW |
253 | u8 enable_bit; |
254 | s8 usecount; | |
e9b98f60 | 255 | u8 fixed_div; |
f71eddb1 | 256 | u8 flags; |
140455fa | 257 | #ifdef CONFIG_ARCH_OMAP2PLUS |
6b8858a9 PW |
258 | void __iomem *clksel_reg; |
259 | u32 clksel_mask; | |
260 | const struct clksel *clksel; | |
88b8ba90 | 261 | struct dpll_data *dpll_data; |
d1b03f61 PW |
262 | const char *clkdm_name; |
263 | struct clockdomain *clkdm; | |
6b8858a9 | 264 | #else |
b3c1cff6 PW |
265 | u8 rate_offset; |
266 | u8 src_offset; | |
6b8858a9 | 267 | #endif |
137b3ee2 HD |
268 | #if defined(CONFIG_PM_DEBUG) && defined(CONFIG_DEBUG_FS) |
269 | struct dentry *dent; /* For visible tree hierarchy */ | |
270 | #endif | |
9ad5897c TL |
271 | }; |
272 | ||
b851cb28 RK |
273 | struct cpufreq_frequency_table; |
274 | ||
9ad5897c TL |
275 | struct clk_functions { |
276 | int (*clk_enable)(struct clk *clk); | |
277 | void (*clk_disable)(struct clk *clk); | |
9ad5897c TL |
278 | long (*clk_round_rate)(struct clk *clk, unsigned long rate); |
279 | int (*clk_set_rate)(struct clk *clk, unsigned long rate); | |
280 | int (*clk_set_parent)(struct clk *clk, struct clk *parent); | |
9ad5897c TL |
281 | void (*clk_allow_idle)(struct clk *clk); |
282 | void (*clk_deny_idle)(struct clk *clk); | |
90afd5cb | 283 | void (*clk_disable_unused)(struct clk *clk); |
b851cb28 RK |
284 | #ifdef CONFIG_CPU_FREQ |
285 | void (*clk_init_cpufreq_table)(struct cpufreq_frequency_table **); | |
4e37c10d | 286 | void (*clk_exit_cpufreq_table)(struct cpufreq_frequency_table **); |
b851cb28 | 287 | #endif |
9ad5897c TL |
288 | }; |
289 | ||
d3730192 | 290 | extern int mpurate; |
9ad5897c | 291 | |
fecb494b | 292 | extern int clk_init(struct clk_functions *custom_clocks); |
79716870 | 293 | extern void clk_preinit(struct clk *clk); |
9ad5897c | 294 | extern int clk_register(struct clk *clk); |
3f0a820c | 295 | extern void clk_reparent(struct clk *child, struct clk *parent); |
9ad5897c TL |
296 | extern void clk_unregister(struct clk *clk); |
297 | extern void propagate_rate(struct clk *clk); | |
6b8858a9 | 298 | extern void recalculate_root_clocks(void); |
8b9dbc16 | 299 | extern unsigned long followparent_recalc(struct clk *clk); |
6b8858a9 | 300 | extern void clk_enable_init_clocks(void); |
e9b98f60 | 301 | unsigned long omap_fixed_divisor_recalc(struct clk *clk); |
aeec2990 KH |
302 | #ifdef CONFIG_CPU_FREQ |
303 | extern void clk_init_cpufreq_table(struct cpufreq_frequency_table **table); | |
4e37c10d | 304 | extern void clk_exit_cpufreq_table(struct cpufreq_frequency_table **table); |
aeec2990 | 305 | #endif |
74be8427 | 306 | extern struct clk *omap_clk_get_by_name(const char *name); |
58e846fe RN |
307 | extern int omap_clk_enable_autoidle_all(void); |
308 | extern int omap_clk_disable_autoidle_all(void); | |
9ad5897c | 309 | |
897dcded RK |
310 | extern const struct clkops clkops_null; |
311 | ||
7c43d547 SS |
312 | extern struct clk dummy_ck; |
313 | ||
9ad5897c | 314 | #endif |