projects / linux-block.git / blame
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1 | #ifndef ____ASM_ARCH_SDRC_H |
| 2 | #define ____ASM_ARCH_SDRC_H | |
| 3 | ||
| 4 | /* | |
| 5 | * OMAP2/3 SDRC/SMS register definitions | |
| 6 | * | |
| 7 | * Copyright (C) 2007 Texas Instruments, Inc. | |
| 8 | * Copyright (C) 2007 Nokia Corporation | |
| 9 | * | |
| 10 | * Written by Paul Walmsley | |
| 11 | * | |
| 12 | * This program is free software; you can redistribute it and/or modify | |
| 13 | * it under the terms of the GNU General Public License version 2 as | |
| 14 | * published by the Free Software Foundation. | |
| 15 | */ | |
| 16 | ||
| a09e64fb | 17 | #include <mach/io.h> |
| 69d88a00 PW |
18 | |
| 19 | /* SDRC register offsets - read/write with sdrc_{read,write}_reg() */ | |
| 20 | ||
| 21 | #define SDRC_SYSCONFIG 0x010 | |
| 22 | #define SDRC_DLLA_CTRL 0x060 | |
| 23 | #define SDRC_DLLA_STATUS 0x064 | |
| 24 | #define SDRC_DLLB_CTRL 0x068 | |
| 25 | #define SDRC_DLLB_STATUS 0x06C | |
| 26 | #define SDRC_POWER 0x070 | |
| 27 | #define SDRC_MR_0 0x084 | |
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28 | #define SDRC_ACTIM_CTRL_A_0 0x09c |
| 29 | #define SDRC_ACTIM_CTRL_B_0 0x0a0 | |
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30 | #define SDRC_RFR_CTRL_0 0x0a4 |
| 31 | ||
| 32 | /* | |
| 33 | * These values represent the number of memory clock cycles between | |
| 34 | * autorefresh initiation. They assume 1 refresh per 64 ms (JEDEC), 8192 | |
| 35 | * rows per device, and include a subtraction of a 50 cycle window in the | |
| 36 | * event that the autorefresh command is delayed due to other SDRC activity. | |
| 37 | * The '| 1' sets the ARE field to send one autorefresh when the autorefresh | |
| 38 | * counter reaches 0. | |
| 39 | * | |
| 40 | * These represent optimal values for common parts, it won't work for all. | |
| 41 | * As long as you scale down, most parameters are still work, they just | |
| 42 | * become sub-optimal. The RFR value goes in the opposite direction. If you | |
| 43 | * don't adjust it down as your clock period increases the refresh interval | |
| 44 | * will not be met. Setting all parameters for complete worst case may work, | |
| 45 | * but may cut memory performance by 2x. Due to errata the DLLs need to be | |
| 46 | * unlocked and their value needs run time calibration. A dynamic call is | |
| 47 | * need for that as no single right value exists acorss production samples. | |
| 48 | * | |
| 49 | * Only the FULL speed values are given. Current code is such that rate | |
| 50 | * changes must be made at DPLLoutx2. The actual value adjustment for low | |
| 51 | * frequency operation will be handled by omap_set_performance() | |
| 52 | * | |
| 53 | * By having the boot loader boot up in the fastest L4 speed available likely | |
| 54 | * will result in something which you can switch between. | |
| 55 | */ | |
| 56 | #define SDRC_RFR_CTRL_165MHz (0x00044c00 | 1) | |
| 57 | #define SDRC_RFR_CTRL_133MHz (0x0003de00 | 1) | |
| 58 | #define SDRC_RFR_CTRL_100MHz (0x0002da01 | 1) | |
| 59 | #define SDRC_RFR_CTRL_110MHz (0x0002da01 | 1) /* Need to calc */ | |
| 60 | #define SDRC_RFR_CTRL_BYPASS (0x00005000 | 1) /* Need to calc */ | |
| 61 | ||
| 62 | ||
| 63 | /* | |
| 64 | * SMS register access | |
| 65 | */ | |
| 66 | ||
| 67 | ||
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68 | #define OMAP242X_SMS_REGADDR(reg) IO_ADDRESS(OMAP2420_SMS_BASE + reg) |
| 69 | #define OMAP243X_SMS_REGADDR(reg) IO_ADDRESS(OMAP243X_SMS_BASE + reg) | |
| 70 | #define OMAP343X_SMS_REGADDR(reg) IO_ADDRESS(OMAP343X_SMS_BASE + reg) | |
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71 | |
| 72 | /* SMS register offsets - read/write with sms_{read,write}_reg() */ | |
| 73 | ||
| 74 | #define SMS_SYSCONFIG 0x010 | |
| 75 | /* REVISIT: fill in other SMS registers here */ | |
| 76 | ||
| 77 | #endif |