[linux-2.6-block.git] / arch / arm / plat-omap / include / mach / pm.h

/*
 * arch/arm/plat-omap/include/mach/pm.h
 *
 * Header file for OMAP Power Management Routines
 *
 * Author: MontaVista Software, Inc.
 *	   support@mvista.com
 *
 * Copyright 2002 MontaVista Software Inc.
 *
 * Cleanup 2004 for Linux 2.6 by Dirk Behme <dirk.behme@de.bosch.com>
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms of the GNU General Public License as published by the
 * Free Software Foundation; either version 2 of the License, or (at your
 * option) any later version.
 *
 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
 * You should have received a copy of the GNU General Public License along
 * with this program; if not, write to the Free Software Foundation, Inc.,
 * 675 Mass Ave, Cambridge, MA 02139, USA.
 */

#ifndef __ASM_ARCH_OMAP_PM_H
#define __ASM_ARCH_OMAP_PM_H

/*
 * ----------------------------------------------------------------------------
 * Register and offset definitions to be used in PM assembler code
 * ----------------------------------------------------------------------------
 */
#define CLKGEN_REG_ASM_BASE		IO_ADDRESS(0xfffece00)
#define ARM_IDLECT1_ASM_OFFSET		0x04
#define ARM_IDLECT2_ASM_OFFSET		0x08

#define TCMIF_ASM_BASE			IO_ADDRESS(0xfffecc00)
#define EMIFS_CONFIG_ASM_OFFSET		0x0c
#define EMIFF_SDRAM_CONFIG_ASM_OFFSET	0x20

/*
 * ----------------------------------------------------------------------------
 * Power management bitmasks
 * ----------------------------------------------------------------------------
 */
#define IDLE_WAIT_CYCLES		0x00000fff
#define PERIPHERAL_ENABLE		0x2

#define SELF_REFRESH_MODE		0x0c000001
#define IDLE_EMIFS_REQUEST		0xc
#define MODEM_32K_EN			0x1
#define PER_EN				0x1

#define CPU_SUSPEND_SIZE		200
#define ULPD_LOW_PWR_EN			0x0001
#define ULPD_DEEP_SLEEP_TRANSITION_EN	0x0010
#define ULPD_SETUP_ANALOG_CELL_3_VAL	0
#define ULPD_POWER_CTRL_REG_VAL		0x0219

#define DSP_IDLE_DELAY			10
#define DSP_IDLE			0x0040
#define DSP_RST				0x0004
#define DSP_ENABLE			0x0002
#define SUFFICIENT_DSP_RESET_TIME	1000
#define DEFAULT_MPUI_CONFIG		0x05cf
#define ENABLE_XORCLK			0x2
#define DSP_CLOCK_ENABLE		0x2000
#define DSP_IDLE_MODE			0x2
#define TC_IDLE_REQUEST			(0x0000000c)

#define IRQ_LEVEL2			(1<<0)
#define IRQ_KEYBOARD			(1<<1)
#define IRQ_UART2			(1<<15)

#define PDE_BIT				0x08
#define PWD_EN_BIT			0x04
#define EN_PERCK_BIT			0x04

#define OMAP1510_DEEP_SLEEP_REQUEST	0x0ec7
#define OMAP1510_BIG_SLEEP_REQUEST	0x0cc5
#define OMAP1510_IDLE_LOOP_REQUEST	0x0c00
#define OMAP1510_IDLE_CLOCK_DOMAINS	0x2

/* Both big sleep and deep sleep use same values. Difference is in ULPD. */
#define OMAP1610_IDLECT1_SLEEP_VAL	0x13c7
#define OMAP1610_IDLECT2_SLEEP_VAL	0x09c7
#define OMAP1610_IDLECT3_VAL		0x3f
#define OMAP1610_IDLECT3_SLEEP_ORMASK	0x2c
#define OMAP1610_IDLECT3		0xfffece24
#define OMAP1610_IDLE_LOOP_REQUEST	0x0400

#define OMAP730_IDLECT1_SLEEP_VAL	0x16c7
#define OMAP730_IDLECT2_SLEEP_VAL	0x09c7
#define OMAP730_IDLECT3_VAL		0x3f
#define OMAP730_IDLECT3		0xfffece24
#define OMAP730_IDLE_LOOP_REQUEST	0x0C00

#if     !defined(CONFIG_ARCH_OMAP730) && \
	!defined(CONFIG_ARCH_OMAP15XX) && \
	!defined(CONFIG_ARCH_OMAP16XX) && \
	!defined(CONFIG_ARCH_OMAP24XX)
#error "Power management for this processor not implemented yet"
#endif

#ifndef __ASSEMBLER__

#include <linux/clk.h>

extern void prevent_idle_sleep(void);
extern void allow_idle_sleep(void);

extern void omap_pm_idle(void);
extern void omap_pm_suspend(void);
extern void omap730_cpu_suspend(unsigned short, unsigned short);
extern void omap1510_cpu_suspend(unsigned short, unsigned short);
extern void omap1610_cpu_suspend(unsigned short, unsigned short);
extern void omap24xx_cpu_suspend(u32 dll_ctrl, void __iomem *sdrc_dlla_ctrl,
					void __iomem *sdrc_power);
extern void omap730_idle_loop_suspend(void);
extern void omap1510_idle_loop_suspend(void);
extern void omap1610_idle_loop_suspend(void);
extern void omap24xx_idle_loop_suspend(void);

extern unsigned int omap730_cpu_suspend_sz;
extern unsigned int omap1510_cpu_suspend_sz;
extern unsigned int omap1610_cpu_suspend_sz;
extern unsigned int omap24xx_cpu_suspend_sz;
extern unsigned int omap730_idle_loop_suspend_sz;
extern unsigned int omap1510_idle_loop_suspend_sz;
extern unsigned int omap1610_idle_loop_suspend_sz;
extern unsigned int omap24xx_idle_loop_suspend_sz;

#ifdef CONFIG_OMAP_SERIAL_WAKE
extern void omap_serial_wake_trigger(int enable);
#else
#define omap_serial_wakeup_init()	{}
#define omap_serial_wake_trigger(x)	{}
#endif	/* CONFIG_OMAP_SERIAL_WAKE */

#define ARM_SAVE(x) arm_sleep_save[ARM_SLEEP_SAVE_##x] = omap_readl(x)
#define ARM_RESTORE(x) omap_writel((arm_sleep_save[ARM_SLEEP_SAVE_##x]), (x))
#define ARM_SHOW(x) arm_sleep_save[ARM_SLEEP_SAVE_##x]

#define DSP_SAVE(x) dsp_sleep_save[DSP_SLEEP_SAVE_##x] = __raw_readw(x)
#define DSP_RESTORE(x) __raw_writew((dsp_sleep_save[DSP_SLEEP_SAVE_##x]), (x))
#define DSP_SHOW(x) dsp_sleep_save[DSP_SLEEP_SAVE_##x]

#define ULPD_SAVE(x) ulpd_sleep_save[ULPD_SLEEP_SAVE_##x] = omap_readw(x)
#define ULPD_RESTORE(x) omap_writew((ulpd_sleep_save[ULPD_SLEEP_SAVE_##x]), (x))
#define ULPD_SHOW(x) ulpd_sleep_save[ULPD_SLEEP_SAVE_##x]

#define MPUI730_SAVE(x) mpui730_sleep_save[MPUI730_SLEEP_SAVE_##x] = omap_readl(x)
#define MPUI730_RESTORE(x) omap_writel((mpui730_sleep_save[MPUI730_SLEEP_SAVE_##x]), (x))
#define MPUI730_SHOW(x) mpui730_sleep_save[MPUI730_SLEEP_SAVE_##x]

#define MPUI1510_SAVE(x) mpui1510_sleep_save[MPUI1510_SLEEP_SAVE_##x] = omap_readl(x)
#define MPUI1510_RESTORE(x) omap_writel((mpui1510_sleep_save[MPUI1510_SLEEP_SAVE_##x]), (x))
#define MPUI1510_SHOW(x) mpui1510_sleep_save[MPUI1510_SLEEP_SAVE_##x]

#define MPUI1610_SAVE(x) mpui1610_sleep_save[MPUI1610_SLEEP_SAVE_##x] = omap_readl(x)
#define MPUI1610_RESTORE(x) omap_writel((mpui1610_sleep_save[MPUI1610_SLEEP_SAVE_##x]), (x))
#define MPUI1610_SHOW(x) mpui1610_sleep_save[MPUI1610_SLEEP_SAVE_##x]

#define OMAP24XX_SAVE(x) omap24xx_sleep_save[OMAP24XX_SLEEP_SAVE_##x] = x
#define OMAP24XX_RESTORE(x) x = omap24xx_sleep_save[OMAP24XX_SLEEP_SAVE_##x]
#define OMAP24XX_SHOW(x) omap24xx_sleep_save[OMAP24XX_SLEEP_SAVE_##x]

/*
 * List of global OMAP registers to preserve.
 * More ones like CP and general purpose register values are preserved
 * with the stack pointer in sleep.S.
 */

enum arm_save_state {
	ARM_SLEEP_SAVE_START = 0,
	/*
	 * MPU control registers 32 bits
	 */
	ARM_SLEEP_SAVE_ARM_CKCTL,
	ARM_SLEEP_SAVE_ARM_IDLECT1,
	ARM_SLEEP_SAVE_ARM_IDLECT2,
	ARM_SLEEP_SAVE_ARM_IDLECT3,
	ARM_SLEEP_SAVE_ARM_EWUPCT,
	ARM_SLEEP_SAVE_ARM_RSTCT1,
	ARM_SLEEP_SAVE_ARM_RSTCT2,
	ARM_SLEEP_SAVE_ARM_SYSST,
	ARM_SLEEP_SAVE_SIZE
};

enum dsp_save_state {
	DSP_SLEEP_SAVE_START = 0,
	/*
	 * DSP registers 16 bits
	 */
	DSP_SLEEP_SAVE_DSP_IDLECT2,
	DSP_SLEEP_SAVE_SIZE
};

enum ulpd_save_state {
	ULPD_SLEEP_SAVE_START = 0,
	/*
	 * ULPD registers 16 bits
	 */
	ULPD_SLEEP_SAVE_ULPD_IT_STATUS,
	ULPD_SLEEP_SAVE_ULPD_CLOCK_CTRL,
	ULPD_SLEEP_SAVE_ULPD_SOFT_REQ,
	ULPD_SLEEP_SAVE_ULPD_STATUS_REQ,
	ULPD_SLEEP_SAVE_ULPD_DPLL_CTRL,
	ULPD_SLEEP_SAVE_ULPD_POWER_CTRL,
	ULPD_SLEEP_SAVE_SIZE
};

enum mpui1510_save_state {
	MPUI1510_SLEEP_SAVE_START = 0,
	/*
	 * MPUI registers 32 bits
	 */
	MPUI1510_SLEEP_SAVE_MPUI_CTRL,
	MPUI1510_SLEEP_SAVE_MPUI_DSP_BOOT_CONFIG,
	MPUI1510_SLEEP_SAVE_MPUI_DSP_API_CONFIG,
	MPUI1510_SLEEP_SAVE_MPUI_DSP_STATUS,
	MPUI1510_SLEEP_SAVE_EMIFF_SDRAM_CONFIG,
	MPUI1510_SLEEP_SAVE_EMIFS_CONFIG,
	MPUI1510_SLEEP_SAVE_OMAP_IH1_MIR,
	MPUI1510_SLEEP_SAVE_OMAP_IH2_MIR,
#if defined(CONFIG_ARCH_OMAP15XX)
	MPUI1510_SLEEP_SAVE_SIZE
#else
	MPUI1510_SLEEP_SAVE_SIZE = 0
#endif
};

enum mpui730_save_state {
	MPUI730_SLEEP_SAVE_START = 0,
	/*
	 * MPUI registers 32 bits
	 */
	MPUI730_SLEEP_SAVE_MPUI_CTRL,
	MPUI730_SLEEP_SAVE_MPUI_DSP_BOOT_CONFIG,
	MPUI730_SLEEP_SAVE_MPUI_DSP_API_CONFIG,
	MPUI730_SLEEP_SAVE_MPUI_DSP_STATUS,
	MPUI730_SLEEP_SAVE_EMIFF_SDRAM_CONFIG,
	MPUI730_SLEEP_SAVE_EMIFS_CONFIG,
	MPUI730_SLEEP_SAVE_OMAP_IH1_MIR,
	MPUI730_SLEEP_SAVE_OMAP_IH2_0_MIR,
	MPUI730_SLEEP_SAVE_OMAP_IH2_1_MIR,
#if defined(CONFIG_ARCH_OMAP730)
	MPUI730_SLEEP_SAVE_SIZE
#else
	MPUI730_SLEEP_SAVE_SIZE = 0
#endif
};

enum mpui1610_save_state {
	MPUI1610_SLEEP_SAVE_START = 0,
	/*
	 * MPUI registers 32 bits
	 */
	MPUI1610_SLEEP_SAVE_MPUI_CTRL,
	MPUI1610_SLEEP_SAVE_MPUI_DSP_BOOT_CONFIG,
	MPUI1610_SLEEP_SAVE_MPUI_DSP_API_CONFIG,
	MPUI1610_SLEEP_SAVE_MPUI_DSP_STATUS,
	MPUI1610_SLEEP_SAVE_EMIFF_SDRAM_CONFIG,
	MPUI1610_SLEEP_SAVE_EMIFS_CONFIG,
	MPUI1610_SLEEP_SAVE_OMAP_IH1_MIR,
	MPUI1610_SLEEP_SAVE_OMAP_IH2_0_MIR,
	MPUI1610_SLEEP_SAVE_OMAP_IH2_1_MIR,
	MPUI1610_SLEEP_SAVE_OMAP_IH2_2_MIR,
	MPUI1610_SLEEP_SAVE_OMAP_IH2_3_MIR,
#if defined(CONFIG_ARCH_OMAP16XX)
	MPUI1610_SLEEP_SAVE_SIZE
#else
	MPUI1610_SLEEP_SAVE_SIZE = 0
#endif
};

enum omap24xx_save_state {
	OMAP24XX_SLEEP_SAVE_START = 0,
	OMAP24XX_SLEEP_SAVE_INTC_MIR0,
	OMAP24XX_SLEEP_SAVE_INTC_MIR1,
	OMAP24XX_SLEEP_SAVE_INTC_MIR2,

	OMAP24XX_SLEEP_SAVE_CM_CLKSTCTRL_MPU,
	OMAP24XX_SLEEP_SAVE_CM_CLKSTCTRL_CORE,
	OMAP24XX_SLEEP_SAVE_CM_CLKSTCTRL_GFX,
	OMAP24XX_SLEEP_SAVE_CM_CLKSTCTRL_DSP,
	OMAP24XX_SLEEP_SAVE_CM_CLKSTCTRL_MDM,

	OMAP24XX_SLEEP_SAVE_PM_PWSTCTRL_MPU,
	OMAP24XX_SLEEP_SAVE_PM_PWSTCTRL_CORE,
	OMAP24XX_SLEEP_SAVE_PM_PWSTCTRL_GFX,
	OMAP24XX_SLEEP_SAVE_PM_PWSTCTRL_DSP,
	OMAP24XX_SLEEP_SAVE_PM_PWSTCTRL_MDM,

	OMAP24XX_SLEEP_SAVE_CM_IDLEST1_CORE,
	OMAP24XX_SLEEP_SAVE_CM_IDLEST2_CORE,
	OMAP24XX_SLEEP_SAVE_CM_IDLEST3_CORE,
	OMAP24XX_SLEEP_SAVE_CM_IDLEST4_CORE,
	OMAP24XX_SLEEP_SAVE_CM_IDLEST_GFX,
	OMAP24XX_SLEEP_SAVE_CM_IDLEST_WKUP,
	OMAP24XX_SLEEP_SAVE_CM_IDLEST_CKGEN,
	OMAP24XX_SLEEP_SAVE_CM_IDLEST_DSP,
	OMAP24XX_SLEEP_SAVE_CM_IDLEST_MDM,

	OMAP24XX_SLEEP_SAVE_CM_AUTOIDLE1_CORE,
	OMAP24XX_SLEEP_SAVE_CM_AUTOIDLE2_CORE,
	OMAP24XX_SLEEP_SAVE_CM_AUTOIDLE3_CORE,
	OMAP24XX_SLEEP_SAVE_CM_AUTOIDLE4_CORE,
	OMAP24XX_SLEEP_SAVE_CM_AUTOIDLE_WKUP,
	OMAP24XX_SLEEP_SAVE_CM_AUTOIDLE_PLL,
	OMAP24XX_SLEEP_SAVE_CM_AUTOIDLE_DSP,
	OMAP24XX_SLEEP_SAVE_CM_AUTOIDLE_MDM,

	OMAP24XX_SLEEP_SAVE_CM_FCLKEN1_CORE,
	OMAP24XX_SLEEP_SAVE_CM_FCLKEN2_CORE,
	OMAP24XX_SLEEP_SAVE_CM_ICLKEN1_CORE,
	OMAP24XX_SLEEP_SAVE_CM_ICLKEN2_CORE,
	OMAP24XX_SLEEP_SAVE_CM_ICLKEN3_CORE,
	OMAP24XX_SLEEP_SAVE_CM_ICLKEN4_CORE,
	OMAP24XX_SLEEP_SAVE_GPIO1_IRQENABLE1,
	OMAP24XX_SLEEP_SAVE_GPIO2_IRQENABLE1,
	OMAP24XX_SLEEP_SAVE_GPIO3_IRQENABLE1,
	OMAP24XX_SLEEP_SAVE_GPIO4_IRQENABLE1,
	OMAP24XX_SLEEP_SAVE_GPIO3_OE,
	OMAP24XX_SLEEP_SAVE_GPIO4_OE,
	OMAP24XX_SLEEP_SAVE_GPIO3_RISINGDETECT,
	OMAP24XX_SLEEP_SAVE_GPIO3_FALLINGDETECT,
	OMAP24XX_SLEEP_SAVE_CONTROL_PADCONF_SPI1_NCS2,
	OMAP24XX_SLEEP_SAVE_CONTROL_PADCONF_MCBSP1_DX,
	OMAP24XX_SLEEP_SAVE_CONTROL_PADCONF_SSI1_FLAG_TX,
	OMAP24XX_SLEEP_SAVE_CONTROL_PADCONF_SYS_NIRQW0,
	OMAP24XX_SLEEP_SAVE_SIZE
};

#endif /* ASSEMBLER */
#endif /* __ASM_ARCH_OMAP_PM_H */
Commit	Line	Data
1da177e4	1	/*
a09e64fb	2	* arch/arm/plat-omap/include/mach/pm.h
1da177e4 LT	3	*
	4	* Header file for OMAP Power Management Routines
	5	*
	6	* Author: MontaVista Software, Inc.
	7	* support@mvista.com
	8	*
	9	* Copyright 2002 MontaVista Software Inc.
	10	*
	11	* Cleanup 2004 for Linux 2.6 by Dirk Behme <dirk.behme@de.bosch.com>
	12	*
	13	* This program is free software; you can redistribute it and/or modify it
	14	* under the terms of the GNU General Public License as published by the
	15	* Free Software Foundation; either version 2 of the License, or (at your
	16	* option) any later version.
	17	*
	18	* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
	19	* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
	20	* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
	21	* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
	22	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
	23	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
	24	* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
	25	* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
	26	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
	27	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
	28	*
	29	* You should have received a copy of the GNU General Public License along
	30	* with this program; if not, write to the Free Software Foundation, Inc.,
	31	* 675 Mass Ave, Cambridge, MA 02139, USA.
	32	*/
	33
	34	#ifndef __ASM_ARCH_OMAP_PM_H
	35	#define __ASM_ARCH_OMAP_PM_H
	36
	37	/*
	38	* ----------------------------------------------------------------------------
	39	* Register and offset definitions to be used in PM assembler code
	40	* ----------------------------------------------------------------------------
	41	*/
e8a91c95	42	#define CLKGEN_REG_ASM_BASE IO_ADDRESS(0xfffece00)
1da177e4 LT	43	#define ARM_IDLECT1_ASM_OFFSET 0x04
	44	#define ARM_IDLECT2_ASM_OFFSET 0x08
	45
e8a91c95	46	#define TCMIF_ASM_BASE IO_ADDRESS(0xfffecc00)
1da177e4 LT	47	#define EMIFS_CONFIG_ASM_OFFSET 0x0c
	48	#define EMIFF_SDRAM_CONFIG_ASM_OFFSET 0x20
	49
	50	/*
	51	* ----------------------------------------------------------------------------
670c104a	52	* Power management bitmasks
1da177e4 LT	53	* ----------------------------------------------------------------------------
	54	*/
	55	#define IDLE_WAIT_CYCLES 0x00000fff
	56	#define PERIPHERAL_ENABLE 0x2
	57
	58	#define SELF_REFRESH_MODE 0x0c000001
	59	#define IDLE_EMIFS_REQUEST 0xc
	60	#define MODEM_32K_EN 0x1
	61	#define PER_EN 0x1
	62
	63	#define CPU_SUSPEND_SIZE 200
9839c6b8 TL	64	#define ULPD_LOW_PWR_EN 0x0001
	65	#define ULPD_DEEP_SLEEP_TRANSITION_EN 0x0010
	66	#define ULPD_SETUP_ANALOG_CELL_3_VAL 0
	67	#define ULPD_POWER_CTRL_REG_VAL 0x0219
1da177e4 LT	68
	69	#define DSP_IDLE_DELAY 10
	70	#define DSP_IDLE 0x0040
	71	#define DSP_RST 0x0004
	72	#define DSP_ENABLE 0x0002
	73	#define SUFFICIENT_DSP_RESET_TIME 1000
	74	#define DEFAULT_MPUI_CONFIG 0x05cf
	75	#define ENABLE_XORCLK 0x2
	76	#define DSP_CLOCK_ENABLE 0x2000
	77	#define DSP_IDLE_MODE 0x2
	78	#define TC_IDLE_REQUEST (0x0000000c)
	79
	80	#define IRQ_LEVEL2 (1<<0)
	81	#define IRQ_KEYBOARD (1<<1)
	82	#define IRQ_UART2 (1<<15)
	83
	84	#define PDE_BIT 0x08
	85	#define PWD_EN_BIT 0x04
	86	#define EN_PERCK_BIT 0x04
	87
	88	#define OMAP1510_DEEP_SLEEP_REQUEST 0x0ec7
	89	#define OMAP1510_BIG_SLEEP_REQUEST 0x0cc5
	90	#define OMAP1510_IDLE_LOOP_REQUEST 0x0c00
	91	#define OMAP1510_IDLE_CLOCK_DOMAINS 0x2
1da177e4	92
9839c6b8 TL	93	/* Both big sleep and deep sleep use same values. Difference is in ULPD. */
	94	#define OMAP1610_IDLECT1_SLEEP_VAL 0x13c7
	95	#define OMAP1610_IDLECT2_SLEEP_VAL 0x09c7
	96	#define OMAP1610_IDLECT3_VAL 0x3f
	97	#define OMAP1610_IDLECT3_SLEEP_ORMASK 0x2c
	98	#define OMAP1610_IDLECT3 0xfffece24
1da177e4	99	#define OMAP1610_IDLE_LOOP_REQUEST 0x0400
1da177e4	100
9ad5897c TL	101	#define OMAP730_IDLECT1_SLEEP_VAL 0x16c7
	102	#define OMAP730_IDLECT2_SLEEP_VAL 0x09c7
	103	#define OMAP730_IDLECT3_VAL 0x3f
	104	#define OMAP730_IDLECT3 0xfffece24
	105	#define OMAP730_IDLE_LOOP_REQUEST 0x0C00
	106
	107	#if !defined(CONFIG_ARCH_OMAP730) && \
	108	!defined(CONFIG_ARCH_OMAP15XX) && \
9839c6b8 TL	109	!defined(CONFIG_ARCH_OMAP16XX) && \
9839c6b8 TL	110	!defined(CONFIG_ARCH_OMAP24XX)
1da177e4 LT	111	#error "Power management for this processor not implemented yet"
	112	#endif
	113
	114	#ifndef __ASSEMBLER__
670c104a TL	115
	116	#include <linux/clk.h>
	117
	118	extern void prevent_idle_sleep(void);
	119	extern void allow_idle_sleep(void);
	120
1da177e4 LT	121	extern void omap_pm_idle(void);
1da177e4 LT	122	extern void omap_pm_suspend(void);
9ad5897c	123	extern void omap730_cpu_suspend(unsigned short, unsigned short);
9839c6b8 TL	124	extern void omap1510_cpu_suspend(unsigned short, unsigned short);
9839c6b8 TL	125	extern void omap1610_cpu_suspend(unsigned short, unsigned short);
1835f1d7 TL	126	extern void omap24xx_cpu_suspend(u32 dll_ctrl, void __iomem *sdrc_dlla_ctrl,
1835f1d7 TL	127	void __iomem *sdrc_power);
9ad5897c	128	extern void omap730_idle_loop_suspend(void);
9839c6b8 TL	129	extern void omap1510_idle_loop_suspend(void);
9839c6b8 TL	130	extern void omap1610_idle_loop_suspend(void);
670c104a TL	131	extern void omap24xx_idle_loop_suspend(void);
	132
	133	extern unsigned int omap730_cpu_suspend_sz;
	134	extern unsigned int omap1510_cpu_suspend_sz;
	135	extern unsigned int omap1610_cpu_suspend_sz;
	136	extern unsigned int omap24xx_cpu_suspend_sz;
	137	extern unsigned int omap730_idle_loop_suspend_sz;
	138	extern unsigned int omap1510_idle_loop_suspend_sz;
	139	extern unsigned int omap1610_idle_loop_suspend_sz;
	140	extern unsigned int omap24xx_idle_loop_suspend_sz;
9839c6b8 TL	141
	142	#ifdef CONFIG_OMAP_SERIAL_WAKE
	143	extern void omap_serial_wake_trigger(int enable);
	144	#else
670c104a	145	#define omap_serial_wakeup_init() {}
9839c6b8 TL	146	#define omap_serial_wake_trigger(x) {}
	147	#endif /* CONFIG_OMAP_SERIAL_WAKE */
	148
1da177e4 LT	149	#define ARM_SAVE(x) arm_sleep_save[ARM_SLEEP_SAVE_##x] = omap_readl(x)
	150	#define ARM_RESTORE(x) omap_writel((arm_sleep_save[ARM_SLEEP_SAVE_##x]), (x))
	151	#define ARM_SHOW(x) arm_sleep_save[ARM_SLEEP_SAVE_##x]
	152
670c104a TL	153	#define DSP_SAVE(x) dsp_sleep_save[DSP_SLEEP_SAVE_##x] = __raw_readw(x)
	154	#define DSP_RESTORE(x) __raw_writew((dsp_sleep_save[DSP_SLEEP_SAVE_##x]), (x))
	155	#define DSP_SHOW(x) dsp_sleep_save[DSP_SLEEP_SAVE_##x]
	156
1da177e4 LT	157	#define ULPD_SAVE(x) ulpd_sleep_save[ULPD_SLEEP_SAVE_##x] = omap_readw(x)
	158	#define ULPD_RESTORE(x) omap_writew((ulpd_sleep_save[ULPD_SLEEP_SAVE_##x]), (x))
	159	#define ULPD_SHOW(x) ulpd_sleep_save[ULPD_SLEEP_SAVE_##x]
	160
9ad5897c TL	161	#define MPUI730_SAVE(x) mpui730_sleep_save[MPUI730_SLEEP_SAVE_##x] = omap_readl(x)
	162	#define MPUI730_RESTORE(x) omap_writel((mpui730_sleep_save[MPUI730_SLEEP_SAVE_##x]), (x))
	163	#define MPUI730_SHOW(x) mpui730_sleep_save[MPUI730_SLEEP_SAVE_##x]
	164
1da177e4 LT	165	#define MPUI1510_SAVE(x) mpui1510_sleep_save[MPUI1510_SLEEP_SAVE_##x] = omap_readl(x)
	166	#define MPUI1510_RESTORE(x) omap_writel((mpui1510_sleep_save[MPUI1510_SLEEP_SAVE_##x]), (x))
	167	#define MPUI1510_SHOW(x) mpui1510_sleep_save[MPUI1510_SLEEP_SAVE_##x]
	168
	169	#define MPUI1610_SAVE(x) mpui1610_sleep_save[MPUI1610_SLEEP_SAVE_##x] = omap_readl(x)
	170	#define MPUI1610_RESTORE(x) omap_writel((mpui1610_sleep_save[MPUI1610_SLEEP_SAVE_##x]), (x))
	171	#define MPUI1610_SHOW(x) mpui1610_sleep_save[MPUI1610_SLEEP_SAVE_##x]
	172
670c104a TL	173	#define OMAP24XX_SAVE(x) omap24xx_sleep_save[OMAP24XX_SLEEP_SAVE_##x] = x
	174	#define OMAP24XX_RESTORE(x) x = omap24xx_sleep_save[OMAP24XX_SLEEP_SAVE_##x]
	175	#define OMAP24XX_SHOW(x) omap24xx_sleep_save[OMAP24XX_SLEEP_SAVE_##x]
	176
1da177e4 LT	177	/*
	178	* List of global OMAP registers to preserve.
	179	* More ones like CP and general purpose register values are preserved
	180	* with the stack pointer in sleep.S.
	181	*/
	182
	183	enum arm_save_state {
	184	ARM_SLEEP_SAVE_START = 0,
	185	/*
	186	* MPU control registers 32 bits
	187	*/
	188	ARM_SLEEP_SAVE_ARM_CKCTL,
	189	ARM_SLEEP_SAVE_ARM_IDLECT1,
	190	ARM_SLEEP_SAVE_ARM_IDLECT2,
9839c6b8	191	ARM_SLEEP_SAVE_ARM_IDLECT3,
1da177e4 LT	192	ARM_SLEEP_SAVE_ARM_EWUPCT,
	193	ARM_SLEEP_SAVE_ARM_RSTCT1,
	194	ARM_SLEEP_SAVE_ARM_RSTCT2,
	195	ARM_SLEEP_SAVE_ARM_SYSST,
	196	ARM_SLEEP_SAVE_SIZE
	197	};
	198
670c104a TL	199	enum dsp_save_state {
	200	DSP_SLEEP_SAVE_START = 0,
	201	/*
	202	* DSP registers 16 bits
	203	*/
	204	DSP_SLEEP_SAVE_DSP_IDLECT2,
	205	DSP_SLEEP_SAVE_SIZE
	206	};
	207
1da177e4 LT	208	enum ulpd_save_state {
	209	ULPD_SLEEP_SAVE_START = 0,
	210	/*
	211	* ULPD registers 16 bits
	212	*/
	213	ULPD_SLEEP_SAVE_ULPD_IT_STATUS,
	214	ULPD_SLEEP_SAVE_ULPD_CLOCK_CTRL,
	215	ULPD_SLEEP_SAVE_ULPD_SOFT_REQ,
	216	ULPD_SLEEP_SAVE_ULPD_STATUS_REQ,
	217	ULPD_SLEEP_SAVE_ULPD_DPLL_CTRL,
	218	ULPD_SLEEP_SAVE_ULPD_POWER_CTRL,
	219	ULPD_SLEEP_SAVE_SIZE
	220	};
	221
	222	enum mpui1510_save_state {
	223	MPUI1510_SLEEP_SAVE_START = 0,
	224	/*
	225	* MPUI registers 32 bits
	226	*/
	227	MPUI1510_SLEEP_SAVE_MPUI_CTRL,
	228	MPUI1510_SLEEP_SAVE_MPUI_DSP_BOOT_CONFIG,
	229	MPUI1510_SLEEP_SAVE_MPUI_DSP_API_CONFIG,
	230	MPUI1510_SLEEP_SAVE_MPUI_DSP_STATUS,
	231	MPUI1510_SLEEP_SAVE_EMIFF_SDRAM_CONFIG,
	232	MPUI1510_SLEEP_SAVE_EMIFS_CONFIG,
	233	MPUI1510_SLEEP_SAVE_OMAP_IH1_MIR,
	234	MPUI1510_SLEEP_SAVE_OMAP_IH2_MIR,
9ad5897c	235	#if defined(CONFIG_ARCH_OMAP15XX)
1da177e4 LT	236	MPUI1510_SLEEP_SAVE_SIZE
	237	#else
	238	MPUI1510_SLEEP_SAVE_SIZE = 0
	239	#endif
	240	};
	241
9ad5897c TL	242	enum mpui730_save_state {
	243	MPUI730_SLEEP_SAVE_START = 0,
	244	/*
	245	* MPUI registers 32 bits
	246	*/
	247	MPUI730_SLEEP_SAVE_MPUI_CTRL,
	248	MPUI730_SLEEP_SAVE_MPUI_DSP_BOOT_CONFIG,
	249	MPUI730_SLEEP_SAVE_MPUI_DSP_API_CONFIG,
	250	MPUI730_SLEEP_SAVE_MPUI_DSP_STATUS,
	251	MPUI730_SLEEP_SAVE_EMIFF_SDRAM_CONFIG,
	252	MPUI730_SLEEP_SAVE_EMIFS_CONFIG,
	253	MPUI730_SLEEP_SAVE_OMAP_IH1_MIR,
	254	MPUI730_SLEEP_SAVE_OMAP_IH2_0_MIR,
	255	MPUI730_SLEEP_SAVE_OMAP_IH2_1_MIR,
	256	#if defined(CONFIG_ARCH_OMAP730)
	257	MPUI730_SLEEP_SAVE_SIZE
	258	#else
	259	MPUI730_SLEEP_SAVE_SIZE = 0
	260	#endif
	261	};
	262
1da177e4 LT	263	enum mpui1610_save_state {
	264	MPUI1610_SLEEP_SAVE_START = 0,
	265	/*
	266	* MPUI registers 32 bits
	267	*/
	268	MPUI1610_SLEEP_SAVE_MPUI_CTRL,
	269	MPUI1610_SLEEP_SAVE_MPUI_DSP_BOOT_CONFIG,
	270	MPUI1610_SLEEP_SAVE_MPUI_DSP_API_CONFIG,
	271	MPUI1610_SLEEP_SAVE_MPUI_DSP_STATUS,
	272	MPUI1610_SLEEP_SAVE_EMIFF_SDRAM_CONFIG,
	273	MPUI1610_SLEEP_SAVE_EMIFS_CONFIG,
	274	MPUI1610_SLEEP_SAVE_OMAP_IH1_MIR,
	275	MPUI1610_SLEEP_SAVE_OMAP_IH2_0_MIR,
	276	MPUI1610_SLEEP_SAVE_OMAP_IH2_1_MIR,
	277	MPUI1610_SLEEP_SAVE_OMAP_IH2_2_MIR,
	278	MPUI1610_SLEEP_SAVE_OMAP_IH2_3_MIR,
	279	#if defined(CONFIG_ARCH_OMAP16XX)
	280	MPUI1610_SLEEP_SAVE_SIZE
	281	#else
	282	MPUI1610_SLEEP_SAVE_SIZE = 0
	283	#endif
	284	};
	285
670c104a TL	286	enum omap24xx_save_state {
	287	OMAP24XX_SLEEP_SAVE_START = 0,
	288	OMAP24XX_SLEEP_SAVE_INTC_MIR0,
	289	OMAP24XX_SLEEP_SAVE_INTC_MIR1,
	290	OMAP24XX_SLEEP_SAVE_INTC_MIR2,
22a16f39 TL	291
	292	OMAP24XX_SLEEP_SAVE_CM_CLKSTCTRL_MPU,
	293	OMAP24XX_SLEEP_SAVE_CM_CLKSTCTRL_CORE,
	294	OMAP24XX_SLEEP_SAVE_CM_CLKSTCTRL_GFX,
	295	OMAP24XX_SLEEP_SAVE_CM_CLKSTCTRL_DSP,
	296	OMAP24XX_SLEEP_SAVE_CM_CLKSTCTRL_MDM,
	297
	298	OMAP24XX_SLEEP_SAVE_PM_PWSTCTRL_MPU,
	299	OMAP24XX_SLEEP_SAVE_PM_PWSTCTRL_CORE,
	300	OMAP24XX_SLEEP_SAVE_PM_PWSTCTRL_GFX,
	301	OMAP24XX_SLEEP_SAVE_PM_PWSTCTRL_DSP,
	302	OMAP24XX_SLEEP_SAVE_PM_PWSTCTRL_MDM,
	303
	304	OMAP24XX_SLEEP_SAVE_CM_IDLEST1_CORE,
	305	OMAP24XX_SLEEP_SAVE_CM_IDLEST2_CORE,
	306	OMAP24XX_SLEEP_SAVE_CM_IDLEST3_CORE,
	307	OMAP24XX_SLEEP_SAVE_CM_IDLEST4_CORE,
	308	OMAP24XX_SLEEP_SAVE_CM_IDLEST_GFX,
	309	OMAP24XX_SLEEP_SAVE_CM_IDLEST_WKUP,
	310	OMAP24XX_SLEEP_SAVE_CM_IDLEST_CKGEN,
	311	OMAP24XX_SLEEP_SAVE_CM_IDLEST_DSP,
	312	OMAP24XX_SLEEP_SAVE_CM_IDLEST_MDM,
	313
	314	OMAP24XX_SLEEP_SAVE_CM_AUTOIDLE1_CORE,
	315	OMAP24XX_SLEEP_SAVE_CM_AUTOIDLE2_CORE,
	316	OMAP24XX_SLEEP_SAVE_CM_AUTOIDLE3_CORE,
	317	OMAP24XX_SLEEP_SAVE_CM_AUTOIDLE4_CORE,
	318	OMAP24XX_SLEEP_SAVE_CM_AUTOIDLE_WKUP,
	319	OMAP24XX_SLEEP_SAVE_CM_AUTOIDLE_PLL,
	320	OMAP24XX_SLEEP_SAVE_CM_AUTOIDLE_DSP,
	321	OMAP24XX_SLEEP_SAVE_CM_AUTOIDLE_MDM,
	322
670c104a TL	323	OMAP24XX_SLEEP_SAVE_CM_FCLKEN1_CORE,
	324	OMAP24XX_SLEEP_SAVE_CM_FCLKEN2_CORE,
	325	OMAP24XX_SLEEP_SAVE_CM_ICLKEN1_CORE,
	326	OMAP24XX_SLEEP_SAVE_CM_ICLKEN2_CORE,
22a16f39	327	OMAP24XX_SLEEP_SAVE_CM_ICLKEN3_CORE,
670c104a TL	328	OMAP24XX_SLEEP_SAVE_CM_ICLKEN4_CORE,
	329	OMAP24XX_SLEEP_SAVE_GPIO1_IRQENABLE1,
	330	OMAP24XX_SLEEP_SAVE_GPIO2_IRQENABLE1,
	331	OMAP24XX_SLEEP_SAVE_GPIO3_IRQENABLE1,
	332	OMAP24XX_SLEEP_SAVE_GPIO4_IRQENABLE1,
	333	OMAP24XX_SLEEP_SAVE_GPIO3_OE,
	334	OMAP24XX_SLEEP_SAVE_GPIO4_OE,
	335	OMAP24XX_SLEEP_SAVE_GPIO3_RISINGDETECT,
	336	OMAP24XX_SLEEP_SAVE_GPIO3_FALLINGDETECT,
	337	OMAP24XX_SLEEP_SAVE_CONTROL_PADCONF_SPI1_NCS2,
	338	OMAP24XX_SLEEP_SAVE_CONTROL_PADCONF_MCBSP1_DX,
	339	OMAP24XX_SLEEP_SAVE_CONTROL_PADCONF_SSI1_FLAG_TX,
	340	OMAP24XX_SLEEP_SAVE_CONTROL_PADCONF_SYS_NIRQW0,
	341	OMAP24XX_SLEEP_SAVE_SIZE
	342	};
	343
1da177e4 LT	344	#endif /* ASSEMBLER */
1da177e4 LT	345	#endif /* __ASM_ARCH_OMAP_PM_H */