[linux-2.6-block.git] / arch / arm / plat-omap / include / mach / mcbsp.h

/*
 * arch/arm/plat-omap/include/mach/mcbsp.h
 *
 * Defines for Multi-Channel Buffered Serial Port
 *
 * Copyright (C) 2002 RidgeRun, Inc.
 * Author: Steve Johnson
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
 *
 */
#ifndef __ASM_ARCH_OMAP_MCBSP_H
#define __ASM_ARCH_OMAP_MCBSP_H

#include <linux/completion.h>
#include <linux/spinlock.h>

#include <mach/hardware.h>
#include <mach/clock.h>

#define OMAP730_MCBSP1_BASE	0xfffb1000
#define OMAP730_MCBSP2_BASE	0xfffb1800

#define OMAP1510_MCBSP1_BASE	0xe1011800
#define OMAP1510_MCBSP2_BASE	0xfffb1000
#define OMAP1510_MCBSP3_BASE	0xe1017000

#define OMAP1610_MCBSP1_BASE	0xe1011800
#define OMAP1610_MCBSP2_BASE	0xfffb1000
#define OMAP1610_MCBSP3_BASE	0xe1017000

#define OMAP24XX_MCBSP1_BASE	0x48074000
#define OMAP24XX_MCBSP2_BASE	0x48076000
#define OMAP2430_MCBSP3_BASE	0x4808c000
#define OMAP2430_MCBSP4_BASE	0x4808e000
#define OMAP2430_MCBSP5_BASE	0x48096000

#define OMAP34XX_MCBSP1_BASE	0x48074000
#define OMAP34XX_MCBSP2_BASE	0x49022000
#define OMAP34XX_MCBSP3_BASE	0x49024000
#define OMAP34XX_MCBSP4_BASE	0x49026000
#define OMAP34XX_MCBSP5_BASE	0x48096000

#if defined(CONFIG_ARCH_OMAP15XX) || defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP730)

#define OMAP_MCBSP_REG_DRR2	0x00
#define OMAP_MCBSP_REG_DRR1	0x02
#define OMAP_MCBSP_REG_DXR2	0x04
#define OMAP_MCBSP_REG_DXR1	0x06
#define OMAP_MCBSP_REG_SPCR2	0x08
#define OMAP_MCBSP_REG_SPCR1	0x0a
#define OMAP_MCBSP_REG_RCR2	0x0c
#define OMAP_MCBSP_REG_RCR1	0x0e
#define OMAP_MCBSP_REG_XCR2	0x10
#define OMAP_MCBSP_REG_XCR1	0x12
#define OMAP_MCBSP_REG_SRGR2	0x14
#define OMAP_MCBSP_REG_SRGR1	0x16
#define OMAP_MCBSP_REG_MCR2	0x18
#define OMAP_MCBSP_REG_MCR1	0x1a
#define OMAP_MCBSP_REG_RCERA	0x1c
#define OMAP_MCBSP_REG_RCERB	0x1e
#define OMAP_MCBSP_REG_XCERA	0x20
#define OMAP_MCBSP_REG_XCERB	0x22
#define OMAP_MCBSP_REG_PCR0	0x24
#define OMAP_MCBSP_REG_RCERC	0x26
#define OMAP_MCBSP_REG_RCERD	0x28
#define OMAP_MCBSP_REG_XCERC	0x2A
#define OMAP_MCBSP_REG_XCERD	0x2C
#define OMAP_MCBSP_REG_RCERE	0x2E
#define OMAP_MCBSP_REG_RCERF	0x30
#define OMAP_MCBSP_REG_XCERE	0x32
#define OMAP_MCBSP_REG_XCERF	0x34
#define OMAP_MCBSP_REG_RCERG	0x36
#define OMAP_MCBSP_REG_RCERH	0x38
#define OMAP_MCBSP_REG_XCERG	0x3A
#define OMAP_MCBSP_REG_XCERH	0x3C

/* Dummy defines, these are not available on omap1 */
#define OMAP_MCBSP_REG_XCCR	0x00
#define OMAP_MCBSP_REG_RCCR	0x00

#define AUDIO_MCBSP_DATAWRITE	(OMAP1510_MCBSP1_BASE + OMAP_MCBSP_REG_DXR1)
#define AUDIO_MCBSP_DATAREAD	(OMAP1510_MCBSP1_BASE + OMAP_MCBSP_REG_DRR1)

#define AUDIO_MCBSP		OMAP_MCBSP1
#define AUDIO_DMA_TX		OMAP_DMA_MCBSP1_TX
#define AUDIO_DMA_RX		OMAP_DMA_MCBSP1_RX

#elif defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)

#define OMAP_MCBSP_REG_DRR2	0x00
#define OMAP_MCBSP_REG_DRR1	0x04
#define OMAP_MCBSP_REG_DXR2	0x08
#define OMAP_MCBSP_REG_DXR1	0x0C
#define OMAP_MCBSP_REG_DRR	0x00
#define OMAP_MCBSP_REG_DXR	0x08
#define OMAP_MCBSP_REG_SPCR2	0x10
#define OMAP_MCBSP_REG_SPCR1	0x14
#define OMAP_MCBSP_REG_RCR2	0x18
#define OMAP_MCBSP_REG_RCR1	0x1C
#define OMAP_MCBSP_REG_XCR2	0x20
#define OMAP_MCBSP_REG_XCR1	0x24
#define OMAP_MCBSP_REG_SRGR2	0x28
#define OMAP_MCBSP_REG_SRGR1	0x2C
#define OMAP_MCBSP_REG_MCR2	0x30
#define OMAP_MCBSP_REG_MCR1	0x34
#define OMAP_MCBSP_REG_RCERA	0x38
#define OMAP_MCBSP_REG_RCERB	0x3C
#define OMAP_MCBSP_REG_XCERA	0x40
#define OMAP_MCBSP_REG_XCERB	0x44
#define OMAP_MCBSP_REG_PCR0	0x48
#define OMAP_MCBSP_REG_RCERC	0x4C
#define OMAP_MCBSP_REG_RCERD	0x50
#define OMAP_MCBSP_REG_XCERC	0x54
#define OMAP_MCBSP_REG_XCERD	0x58
#define OMAP_MCBSP_REG_RCERE	0x5C
#define OMAP_MCBSP_REG_RCERF	0x60
#define OMAP_MCBSP_REG_XCERE	0x64
#define OMAP_MCBSP_REG_XCERF	0x68
#define OMAP_MCBSP_REG_RCERG	0x6C
#define OMAP_MCBSP_REG_RCERH	0x70
#define OMAP_MCBSP_REG_XCERG	0x74
#define OMAP_MCBSP_REG_XCERH	0x78
#define OMAP_MCBSP_REG_SYSCON	0x8C
#define OMAP_MCBSP_REG_THRSH2	0x90
#define OMAP_MCBSP_REG_THRSH1	0x94
#define OMAP_MCBSP_REG_IRQST	0xA0
#define OMAP_MCBSP_REG_IRQEN	0xA4
#define OMAP_MCBSP_REG_WAKEUPEN	0xA8
#define OMAP_MCBSP_REG_XCCR	0xAC
#define OMAP_MCBSP_REG_RCCR	0xB0

#define AUDIO_MCBSP_DATAWRITE	(OMAP24XX_MCBSP2_BASE + OMAP_MCBSP_REG_DXR1)
#define AUDIO_MCBSP_DATAREAD	(OMAP24XX_MCBSP2_BASE + OMAP_MCBSP_REG_DRR1)

#define AUDIO_MCBSP		OMAP_MCBSP2
#define AUDIO_DMA_TX		OMAP24XX_DMA_MCBSP2_TX
#define AUDIO_DMA_RX		OMAP24XX_DMA_MCBSP2_RX

#endif

/************************** McBSP SPCR1 bit definitions ***********************/
#define RRST			0x0001
#define RRDY			0x0002
#define RFULL			0x0004
#define RSYNC_ERR		0x0008
#define RINTM(value)		((value)<<4)	/* bits 4:5 */
#define ABIS			0x0040
#define DXENA			0x0080
#define CLKSTP(value)		((value)<<11)	/* bits 11:12 */
#define RJUST(value)		((value)<<13)	/* bits 13:14 */
#define ALB			0x8000
#define DLB			0x8000

/************************** McBSP SPCR2 bit definitions ***********************/
#define XRST		0x0001
#define XRDY		0x0002
#define XEMPTY		0x0004
#define XSYNC_ERR	0x0008
#define XINTM(value)	((value)<<4)		/* bits 4:5 */
#define GRST		0x0040
#define FRST		0x0080
#define SOFT		0x0100
#define FREE		0x0200

/************************** McBSP PCR bit definitions *************************/
#define CLKRP		0x0001
#define CLKXP		0x0002
#define FSRP		0x0004
#define FSXP		0x0008
#define DR_STAT		0x0010
#define DX_STAT		0x0020
#define CLKS_STAT	0x0040
#define SCLKME		0x0080
#define CLKRM		0x0100
#define CLKXM		0x0200
#define FSRM		0x0400
#define FSXM		0x0800
#define RIOEN		0x1000
#define XIOEN		0x2000
#define IDLE_EN		0x4000

/************************** McBSP RCR1 bit definitions ************************/
#define RWDLEN1(value)		((value)<<5)	/* Bits 5:7 */
#define RFRLEN1(value)		((value)<<8)	/* Bits 8:14 */

/************************** McBSP XCR1 bit definitions ************************/
#define XWDLEN1(value)		((value)<<5)	/* Bits 5:7 */
#define XFRLEN1(value)		((value)<<8)	/* Bits 8:14 */

/*************************** McBSP RCR2 bit definitions ***********************/
#define RDATDLY(value)		(value)		/* Bits 0:1 */
#define RFIG			0x0004
#define RCOMPAND(value)		((value)<<3)	/* Bits 3:4 */
#define RWDLEN2(value)		((value)<<5)	/* Bits 5:7 */
#define RFRLEN2(value)		((value)<<8)	/* Bits 8:14 */
#define RPHASE			0x8000

/*************************** McBSP XCR2 bit definitions ***********************/
#define XDATDLY(value)		(value)		/* Bits 0:1 */
#define XFIG			0x0004
#define XCOMPAND(value)		((value)<<3)	/* Bits 3:4 */
#define XWDLEN2(value)		((value)<<5)	/* Bits 5:7 */
#define XFRLEN2(value)		((value)<<8)	/* Bits 8:14 */
#define XPHASE			0x8000

/************************* McBSP SRGR1 bit definitions ************************/
#define CLKGDV(value)		(value)		/* Bits 0:7 */
#define FWID(value)		((value)<<8)	/* Bits 8:15 */

/************************* McBSP SRGR2 bit definitions ************************/
#define FPER(value)		(value)		/* Bits 0:11 */
#define FSGM			0x1000
#define CLKSM			0x2000
#define CLKSP			0x4000
#define GSYNC			0x8000

/************************* McBSP MCR1 bit definitions *************************/
#define RMCM			0x0001
#define RCBLK(value)		((value)<<2)	/* Bits 2:4 */
#define RPABLK(value)		((value)<<5)	/* Bits 5:6 */
#define RPBBLK(value)		((value)<<7)	/* Bits 7:8 */

/************************* McBSP MCR2 bit definitions *************************/
#define XMCM(value)		(value)		/* Bits 0:1 */
#define XCBLK(value)		((value)<<2)	/* Bits 2:4 */
#define XPABLK(value)		((value)<<5)	/* Bits 5:6 */
#define XPBBLK(value)		((value)<<7)	/* Bits 7:8 */

/*********************** McBSP XCCR bit definitions *************************/
#define EXTCLKGATE		0x8000
#define PPCONNECT		0x4000
#define DXENDLY(value)		((value)<<12)	/* Bits 12:13 */
#define XFULL_CYCLE		0x0800
#define DILB			0x0020
#define XDMAEN			0x0008
#define XDISABLE		0x0001

/********************** McBSP RCCR bit definitions *************************/
#define RFULL_CYCLE		0x0800
#define RDMAEN			0x0008
#define RDISABLE		0x0001

/********************** McBSP SYSCONFIG bit definitions ********************/
#define CLOCKACTIVITY(value)	((value)<<8)
#define SIDLEMODE(value)	((value)<<3)
#define ENAWAKEUP		0x0004
#define SOFTRST			0x0002

/********************** McBSP DMA operating modes **************************/
#define MCBSP_DMA_MODE_ELEMENT		0
#define MCBSP_DMA_MODE_THRESHOLD	1
#define MCBSP_DMA_MODE_FRAME		2

/********************** McBSP WAKEUPEN bit definitions *********************/
#define XEMPTYEOFEN		0x4000
#define XRDYEN			0x0400
#define XEOFEN			0x0200
#define XFSXEN			0x0100
#define XSYNCERREN		0x0080
#define RRDYEN			0x0008
#define REOFEN			0x0004
#define RFSREN			0x0002
#define RSYNCERREN		0x0001

/* we don't do multichannel for now */
struct omap_mcbsp_reg_cfg {
	u16 spcr2;
	u16 spcr1;
	u16 rcr2;
	u16 rcr1;
	u16 xcr2;
	u16 xcr1;
	u16 srgr2;
	u16 srgr1;
	u16 mcr2;
	u16 mcr1;
	u16 pcr0;
	u16 rcerc;
	u16 rcerd;
	u16 xcerc;
	u16 xcerd;
	u16 rcere;
	u16 rcerf;
	u16 xcere;
	u16 xcerf;
	u16 rcerg;
	u16 rcerh;
	u16 xcerg;
	u16 xcerh;
	u16 xccr;
	u16 rccr;
};

typedef enum {
	OMAP_MCBSP1 = 0,
	OMAP_MCBSP2,
	OMAP_MCBSP3,
	OMAP_MCBSP4,
	OMAP_MCBSP5
} omap_mcbsp_id;

typedef int __bitwise omap_mcbsp_io_type_t;
#define OMAP_MCBSP_IRQ_IO ((__force omap_mcbsp_io_type_t) 1)
#define OMAP_MCBSP_POLL_IO ((__force omap_mcbsp_io_type_t) 2)

typedef enum {
	OMAP_MCBSP_WORD_8 = 0,
	OMAP_MCBSP_WORD_12,
	OMAP_MCBSP_WORD_16,
	OMAP_MCBSP_WORD_20,
	OMAP_MCBSP_WORD_24,
	OMAP_MCBSP_WORD_32,
} omap_mcbsp_word_length;

typedef enum {
	OMAP_MCBSP_CLK_RISING = 0,
	OMAP_MCBSP_CLK_FALLING,
} omap_mcbsp_clk_polarity;

typedef enum {
	OMAP_MCBSP_FS_ACTIVE_HIGH = 0,
	OMAP_MCBSP_FS_ACTIVE_LOW,
} omap_mcbsp_fs_polarity;

typedef enum {
	OMAP_MCBSP_CLK_STP_MODE_NO_DELAY = 0,
	OMAP_MCBSP_CLK_STP_MODE_DELAY,
} omap_mcbsp_clk_stp_mode;


/******* SPI specific mode **********/
typedef enum {
	OMAP_MCBSP_SPI_MASTER = 0,
	OMAP_MCBSP_SPI_SLAVE,
} omap_mcbsp_spi_mode;

struct omap_mcbsp_spi_cfg {
	omap_mcbsp_spi_mode		spi_mode;
	omap_mcbsp_clk_polarity		rx_clock_polarity;
	omap_mcbsp_clk_polarity		tx_clock_polarity;
	omap_mcbsp_fs_polarity		fsx_polarity;
	u8				clk_div;
	omap_mcbsp_clk_stp_mode		clk_stp_mode;
	omap_mcbsp_word_length		word_length;
};

/* Platform specific configuration */
struct omap_mcbsp_ops {
	void (*request)(unsigned int);
	void (*free)(unsigned int);
};

struct omap_mcbsp_platform_data {
	unsigned long phys_base;
	u8 dma_rx_sync, dma_tx_sync;
	u16 rx_irq, tx_irq;
	struct omap_mcbsp_ops *ops;
#ifdef CONFIG_ARCH_OMAP34XX
	u16 buffer_size;
#endif
};

struct omap_mcbsp {
	struct device *dev;
	unsigned long phys_base;
	void __iomem *io_base;
	u8 id;
	u8 free;
	omap_mcbsp_word_length rx_word_length;
	omap_mcbsp_word_length tx_word_length;

	omap_mcbsp_io_type_t io_type; /* IRQ or poll */
	/* IRQ based TX/RX */
	int rx_irq;
	int tx_irq;

	/* DMA stuff */
	u8 dma_rx_sync;
	short dma_rx_lch;
	u8 dma_tx_sync;
	short dma_tx_lch;

	/* Completion queues */
	struct completion tx_irq_completion;
	struct completion rx_irq_completion;
	struct completion tx_dma_completion;
	struct completion rx_dma_completion;

	/* Protect the field .free, while checking if the mcbsp is in use */
	spinlock_t lock;
	struct omap_mcbsp_platform_data *pdata;
	struct clk *iclk;
	struct clk *fclk;
#ifdef CONFIG_ARCH_OMAP34XX
	int dma_op_mode;
	u16 max_tx_thres;
	u16 max_rx_thres;
#endif
};
extern struct omap_mcbsp **mcbsp_ptr;
extern int omap_mcbsp_count;

int omap_mcbsp_init(void);
void omap_mcbsp_register_board_cfg(struct omap_mcbsp_platform_data *config,
					int size);
void omap_mcbsp_config(unsigned int id, const struct omap_mcbsp_reg_cfg * config);
#ifdef CONFIG_ARCH_OMAP34XX
void omap_mcbsp_set_tx_threshold(unsigned int id, u16 threshold);
void omap_mcbsp_set_rx_threshold(unsigned int id, u16 threshold);
u16 omap_mcbsp_get_max_tx_threshold(unsigned int id);
u16 omap_mcbsp_get_max_rx_threshold(unsigned int id);
int omap_mcbsp_get_dma_op_mode(unsigned int id);
#else
static inline void omap_mcbsp_set_tx_threshold(unsigned int id, u16 threshold)
{ }
static inline void omap_mcbsp_set_rx_threshold(unsigned int id, u16 threshold)
{ }
static inline u16 omap_mcbsp_get_max_tx_threshold(unsigned int id) { return 0; }
static inline u16 omap_mcbsp_get_max_rx_threshold(unsigned int id) { return 0; }
static inline int omap_mcbsp_get_dma_op_mode(unsigned int id) { return 0; }
#endif
int omap_mcbsp_request(unsigned int id);
void omap_mcbsp_free(unsigned int id);
void omap_mcbsp_start(unsigned int id, int tx, int rx);
void omap_mcbsp_stop(unsigned int id, int tx, int rx);
void omap_mcbsp_xmit_word(unsigned int id, u32 word);
u32 omap_mcbsp_recv_word(unsigned int id);

int omap_mcbsp_xmit_buffer(unsigned int id, dma_addr_t buffer, unsigned int length);
int omap_mcbsp_recv_buffer(unsigned int id, dma_addr_t buffer, unsigned int length);
int omap_mcbsp_spi_master_xmit_word_poll(unsigned int id, u32 word);
int omap_mcbsp_spi_master_recv_word_poll(unsigned int id, u32 * word);


/* SPI specific API */
void omap_mcbsp_set_spi_mode(unsigned int id, const struct omap_mcbsp_spi_cfg * spi_cfg);

/* Polled read/write functions */
int omap_mcbsp_pollread(unsigned int id, u16 * buf);
int omap_mcbsp_pollwrite(unsigned int id, u16 buf);
int omap_mcbsp_set_io_type(unsigned int id, omap_mcbsp_io_type_t io_type);

#endif
Commit	Line	Data
1da177e4	1	/*
a09e64fb	2	* arch/arm/plat-omap/include/mach/mcbsp.h
1da177e4 LT	3	*
	4	* Defines for Multi-Channel Buffered Serial Port
	5	*
	6	* Copyright (C) 2002 RidgeRun, Inc.
	7	* Author: Steve Johnson
	8	*
	9	* This program is free software; you can redistribute it and/or modify
	10	* it under the terms of the GNU General Public License as published by
	11	* the Free Software Foundation; either version 2 of the License, or
	12	* (at your option) any later version.
	13	*
	14	* This program is distributed in the hope that it will be useful,
	15	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	16	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	17	* GNU General Public License for more details.
	18	*
	19	* You should have received a copy of the GNU General Public License
	20	* along with this program; if not, write to the Free Software
	21	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	22	*
	23	*/
	24	#ifndef __ASM_ARCH_OMAP_MCBSP_H
	25	#define __ASM_ARCH_OMAP_MCBSP_H
	26
bc5d0c89 EV	27	#include <linux/completion.h>
	28	#include <linux/spinlock.h>
	29
a09e64fb RK	30	#include <mach/hardware.h>
a09e64fb RK	31	#include <mach/clock.h>
1da177e4 LT	32
	33	#define OMAP730_MCBSP1_BASE 0xfffb1000
	34	#define OMAP730_MCBSP2_BASE 0xfffb1800
	35
	36	#define OMAP1510_MCBSP1_BASE 0xe1011800
	37	#define OMAP1510_MCBSP2_BASE 0xfffb1000
	38	#define OMAP1510_MCBSP3_BASE 0xe1017000
	39
	40	#define OMAP1610_MCBSP1_BASE 0xe1011800
	41	#define OMAP1610_MCBSP2_BASE 0xfffb1000
	42	#define OMAP1610_MCBSP3_BASE 0xe1017000
	43
120db2cb TL	44	#define OMAP24XX_MCBSP1_BASE 0x48074000
120db2cb TL	45	#define OMAP24XX_MCBSP2_BASE 0x48076000
05228c35 JN	46	#define OMAP2430_MCBSP3_BASE 0x4808c000
	47	#define OMAP2430_MCBSP4_BASE 0x4808e000
	48	#define OMAP2430_MCBSP5_BASE 0x48096000
120db2cb	49
bc5d0c89 EV	50	#define OMAP34XX_MCBSP1_BASE 0x48074000
bc5d0c89 EV	51	#define OMAP34XX_MCBSP2_BASE 0x49022000
9c8e3a0f CS	52	#define OMAP34XX_MCBSP3_BASE 0x49024000
	53	#define OMAP34XX_MCBSP4_BASE 0x49026000
	54	#define OMAP34XX_MCBSP5_BASE 0x48096000
bc5d0c89	55
120db2cb TL	56	#if defined(CONFIG_ARCH_OMAP15XX) \|\| defined(CONFIG_ARCH_OMAP16XX) \|\| defined(CONFIG_ARCH_OMAP730)
120db2cb TL	57
1da177e4 LT	58	#define OMAP_MCBSP_REG_DRR2 0x00
	59	#define OMAP_MCBSP_REG_DRR1 0x02
	60	#define OMAP_MCBSP_REG_DXR2 0x04
	61	#define OMAP_MCBSP_REG_DXR1 0x06
	62	#define OMAP_MCBSP_REG_SPCR2 0x08
	63	#define OMAP_MCBSP_REG_SPCR1 0x0a
	64	#define OMAP_MCBSP_REG_RCR2 0x0c
	65	#define OMAP_MCBSP_REG_RCR1 0x0e
	66	#define OMAP_MCBSP_REG_XCR2 0x10
	67	#define OMAP_MCBSP_REG_XCR1 0x12
	68	#define OMAP_MCBSP_REG_SRGR2 0x14
	69	#define OMAP_MCBSP_REG_SRGR1 0x16
	70	#define OMAP_MCBSP_REG_MCR2 0x18
	71	#define OMAP_MCBSP_REG_MCR1 0x1a
	72	#define OMAP_MCBSP_REG_RCERA 0x1c
	73	#define OMAP_MCBSP_REG_RCERB 0x1e
	74	#define OMAP_MCBSP_REG_XCERA 0x20
	75	#define OMAP_MCBSP_REG_XCERB 0x22
	76	#define OMAP_MCBSP_REG_PCR0 0x24
	77	#define OMAP_MCBSP_REG_RCERC 0x26
	78	#define OMAP_MCBSP_REG_RCERD 0x28
	79	#define OMAP_MCBSP_REG_XCERC 0x2A
	80	#define OMAP_MCBSP_REG_XCERD 0x2C
	81	#define OMAP_MCBSP_REG_RCERE 0x2E
	82	#define OMAP_MCBSP_REG_RCERF 0x30
	83	#define OMAP_MCBSP_REG_XCERE 0x32
	84	#define OMAP_MCBSP_REG_XCERF 0x34
	85	#define OMAP_MCBSP_REG_RCERG 0x36
	86	#define OMAP_MCBSP_REG_RCERH 0x38
	87	#define OMAP_MCBSP_REG_XCERG 0x3A
	88	#define OMAP_MCBSP_REG_XCERH 0x3C
	89
3127f8f8 TL	90	/* Dummy defines, these are not available on omap1 */
	91	#define OMAP_MCBSP_REG_XCCR 0x00
	92	#define OMAP_MCBSP_REG_RCCR 0x00
	93
120db2cb TL	94	#define AUDIO_MCBSP_DATAWRITE (OMAP1510_MCBSP1_BASE + OMAP_MCBSP_REG_DXR1)
	95	#define AUDIO_MCBSP_DATAREAD (OMAP1510_MCBSP1_BASE + OMAP_MCBSP_REG_DRR1)
	96
	97	#define AUDIO_MCBSP OMAP_MCBSP1
	98	#define AUDIO_DMA_TX OMAP_DMA_MCBSP1_TX
	99	#define AUDIO_DMA_RX OMAP_DMA_MCBSP1_RX
	100
b4b58f58	101	#elif defined(CONFIG_ARCH_OMAP24XX) \|\| defined(CONFIG_ARCH_OMAP34XX)
120db2cb TL	102
	103	#define OMAP_MCBSP_REG_DRR2 0x00
	104	#define OMAP_MCBSP_REG_DRR1 0x04
	105	#define OMAP_MCBSP_REG_DXR2 0x08
	106	#define OMAP_MCBSP_REG_DXR1 0x0C
b4b58f58 CS	107	#define OMAP_MCBSP_REG_DRR 0x00
b4b58f58 CS	108	#define OMAP_MCBSP_REG_DXR 0x08
120db2cb TL	109	#define OMAP_MCBSP_REG_SPCR2 0x10
	110	#define OMAP_MCBSP_REG_SPCR1 0x14
	111	#define OMAP_MCBSP_REG_RCR2 0x18
	112	#define OMAP_MCBSP_REG_RCR1 0x1C
	113	#define OMAP_MCBSP_REG_XCR2 0x20
	114	#define OMAP_MCBSP_REG_XCR1 0x24
	115	#define OMAP_MCBSP_REG_SRGR2 0x28
	116	#define OMAP_MCBSP_REG_SRGR1 0x2C
	117	#define OMAP_MCBSP_REG_MCR2 0x30
	118	#define OMAP_MCBSP_REG_MCR1 0x34
	119	#define OMAP_MCBSP_REG_RCERA 0x38
	120	#define OMAP_MCBSP_REG_RCERB 0x3C
	121	#define OMAP_MCBSP_REG_XCERA 0x40
	122	#define OMAP_MCBSP_REG_XCERB 0x44
	123	#define OMAP_MCBSP_REG_PCR0 0x48
	124	#define OMAP_MCBSP_REG_RCERC 0x4C
	125	#define OMAP_MCBSP_REG_RCERD 0x50
	126	#define OMAP_MCBSP_REG_XCERC 0x54
	127	#define OMAP_MCBSP_REG_XCERD 0x58
	128	#define OMAP_MCBSP_REG_RCERE 0x5C
	129	#define OMAP_MCBSP_REG_RCERF 0x60
	130	#define OMAP_MCBSP_REG_XCERE 0x64
	131	#define OMAP_MCBSP_REG_XCERF 0x68
	132	#define OMAP_MCBSP_REG_RCERG 0x6C
	133	#define OMAP_MCBSP_REG_RCERH 0x70
	134	#define OMAP_MCBSP_REG_XCERG 0x74
	135	#define OMAP_MCBSP_REG_XCERH 0x78
b4b58f58	136	#define OMAP_MCBSP_REG_SYSCON 0x8C
946a49a9 EV	137	#define OMAP_MCBSP_REG_THRSH2 0x90
	138	#define OMAP_MCBSP_REG_THRSH1 0x94
	139	#define OMAP_MCBSP_REG_IRQST 0xA0
	140	#define OMAP_MCBSP_REG_IRQEN 0xA4
2122fdc6	141	#define OMAP_MCBSP_REG_WAKEUPEN 0xA8
b4b58f58 CS	142	#define OMAP_MCBSP_REG_XCCR 0xAC
b4b58f58 CS	143	#define OMAP_MCBSP_REG_RCCR 0xB0
120db2cb TL	144
	145	#define AUDIO_MCBSP_DATAWRITE (OMAP24XX_MCBSP2_BASE + OMAP_MCBSP_REG_DXR1)
	146	#define AUDIO_MCBSP_DATAREAD (OMAP24XX_MCBSP2_BASE + OMAP_MCBSP_REG_DRR1)
	147
	148	#define AUDIO_MCBSP OMAP_MCBSP2
	149	#define AUDIO_DMA_TX OMAP24XX_DMA_MCBSP2_TX
	150	#define AUDIO_DMA_RX OMAP24XX_DMA_MCBSP2_RX
	151
	152	#endif
	153
1da177e4 LT	154	/************************ McBSP SPCR1 bit definitions *********************/
	155	#define RRST 0x0001
	156	#define RRDY 0x0002
	157	#define RFULL 0x0004
	158	#define RSYNC_ERR 0x0008
	159	#define RINTM(value) ((value)<<4) /* bits 4:5 */
	160	#define ABIS 0x0040
	161	#define DXENA 0x0080
	162	#define CLKSTP(value) ((value)<<11) /* bits 11:12 */
	163	#define RJUST(value) ((value)<<13) /* bits 13:14 */
b4b58f58	164	#define ALB 0x8000
1da177e4 LT	165	#define DLB 0x8000
	166
	167	/************************ McBSP SPCR2 bit definitions *********************/
	168	#define XRST 0x0001
	169	#define XRDY 0x0002
	170	#define XEMPTY 0x0004
	171	#define XSYNC_ERR 0x0008
	172	#define XINTM(value) ((value)<<4) /* bits 4:5 */
	173	#define GRST 0x0040
	174	#define FRST 0x0080
	175	#define SOFT 0x0100
	176	#define FREE 0x0200
	177
	178	/************************ McBSP PCR bit definitions ***********************/
	179	#define CLKRP 0x0001
	180	#define CLKXP 0x0002
	181	#define FSRP 0x0004
	182	#define FSXP 0x0008
	183	#define DR_STAT 0x0010
	184	#define DX_STAT 0x0020
	185	#define CLKS_STAT 0x0040
	186	#define SCLKME 0x0080
	187	#define CLKRM 0x0100
	188	#define CLKXM 0x0200
	189	#define FSRM 0x0400
	190	#define FSXM 0x0800
	191	#define RIOEN 0x1000
	192	#define XIOEN 0x2000
	193	#define IDLE_EN 0x4000
	194
	195	/************************ McBSP RCR1 bit definitions **********************/
	196	#define RWDLEN1(value) ((value)<<5) /* Bits 5:7 */
	197	#define RFRLEN1(value) ((value)<<8) /* Bits 8:14 */
	198
	199	/************************ McBSP XCR1 bit definitions **********************/
	200	#define XWDLEN1(value) ((value)<<5) /* Bits 5:7 */
	201	#define XFRLEN1(value) ((value)<<8) /* Bits 8:14 */
	202
	203	/************************* McBSP RCR2 bit definitions *********************/
	204	#define RDATDLY(value) (value) /* Bits 0:1 */
	205	#define RFIG 0x0004
	206	#define RCOMPAND(value) ((value)<<3) /* Bits 3:4 */
	207	#define RWDLEN2(value) ((value)<<5) /* Bits 5:7 */
	208	#define RFRLEN2(value) ((value)<<8) /* Bits 8:14 */
	209	#define RPHASE 0x8000
	210
	211	/************************* McBSP XCR2 bit definitions *********************/
	212	#define XDATDLY(value) (value) /* Bits 0:1 */
	213	#define XFIG 0x0004
	214	#define XCOMPAND(value) ((value)<<3) /* Bits 3:4 */
	215	#define XWDLEN2(value) ((value)<<5) /* Bits 5:7 */
	216	#define XFRLEN2(value) ((value)<<8) /* Bits 8:14 */
	217	#define XPHASE 0x8000
	218
	219	/*********************** McBSP SRGR1 bit definitions **********************/
	220	#define CLKGDV(value) (value) /* Bits 0:7 */
	221	#define FWID(value) ((value)<<8) /* Bits 8:15 */
	222
	223	/*********************** McBSP SRGR2 bit definitions **********************/
	224	#define FPER(value) (value) /* Bits 0:11 */
	225	#define FSGM 0x1000
	226	#define CLKSM 0x2000
	227	#define CLKSP 0x4000
	228	#define GSYNC 0x8000
229
230	/*********************** McBSP MCR1 bit definitions ***********************/
231	#define RMCM 0x0001
232	#define RCBLK(value) ((value)<<2) /* Bits 2:4 */
233	#define RPABLK(value) ((value)<<5) /* Bits 5:6 */
234	#define RPBBLK(value) ((value)<<7) /* Bits 7:8 */
235
236	/*********************** McBSP MCR2 bit definitions ***********************/
237	#define XMCM(value) (value) /* Bits 0:1 */
238	#define XCBLK(value) ((value)<<2) /* Bits 2:4 */
239	#define XPABLK(value) ((value)<<5) /* Bits 5:6 */
240	#define XPBBLK(value) ((value)<<7) /* Bits 7:8 */
241
b4b58f58	242	/********************* McBSP XCCR bit definitions ***********************/
3127f8f8 TL	243	#define EXTCLKGATE 0x8000
	244	#define PPCONNECT 0x4000
	245	#define DXENDLY(value) ((value)<<12) /* Bits 12:13 */
	246	#define XFULL_CYCLE 0x0800
b4b58f58 CS	247	#define DILB 0x0020
	248	#define XDMAEN 0x0008
	249	#define XDISABLE 0x0001
	250
	251	/******************** McBSP RCCR bit definitions ***********************/
3127f8f8	252	#define RFULL_CYCLE 0x0800
b4b58f58 CS	253	#define RDMAEN 0x0008
	254	#define RDISABLE 0x0001
	255
	256	/******************** McBSP SYSCONFIG bit definitions ******************/
2ba93f8f	257	#define CLOCKACTIVITY(value) ((value)<<8)
2122fdc6 EN	258	#define SIDLEMODE(value) ((value)<<3)
2122fdc6 EN	259	#define ENAWAKEUP 0x0004
b4b58f58	260	#define SOFTRST 0x0002
1da177e4	261
98cb20e8 PU	262	/******************** McBSP DMA operating modes ************************/
	263	#define MCBSP_DMA_MODE_ELEMENT 0
	264	#define MCBSP_DMA_MODE_THRESHOLD 1
	265	#define MCBSP_DMA_MODE_FRAME 2
	266
2122fdc6 EN	267	/******************** McBSP WAKEUPEN bit definitions *******************/
	268	#define XEMPTYEOFEN 0x4000
	269	#define XRDYEN 0x0400
	270	#define XEOFEN 0x0200
	271	#define XFSXEN 0x0100
	272	#define XSYNCERREN 0x0080
	273	#define RRDYEN 0x0008
	274	#define REOFEN 0x0004
	275	#define RFSREN 0x0002
	276	#define RSYNCERREN 0x0001
2122fdc6	277
1da177e4 LT	278	/* we don't do multichannel for now */
	279	struct omap_mcbsp_reg_cfg {
	280	u16 spcr2;
	281	u16 spcr1;
	282	u16 rcr2;
	283	u16 rcr1;
	284	u16 xcr2;
	285	u16 xcr1;
	286	u16 srgr2;
	287	u16 srgr1;
	288	u16 mcr2;
	289	u16 mcr1;
	290	u16 pcr0;
	291	u16 rcerc;
	292	u16 rcerd;
	293	u16 xcerc;
	294	u16 xcerd;
	295	u16 rcere;
	296	u16 rcerf;
	297	u16 xcere;
	298	u16 xcerf;
	299	u16 rcerg;
	300	u16 rcerh;
	301	u16 xcerg;
	302	u16 xcerh;
3127f8f8 TL	303	u16 xccr;
3127f8f8 TL	304	u16 rccr;
1da177e4 LT	305	};
	306
	307	typedef enum {
	308	OMAP_MCBSP1 = 0,
	309	OMAP_MCBSP2,
	310	OMAP_MCBSP3,
9c8e3a0f CS	311	OMAP_MCBSP4,
9c8e3a0f CS	312	OMAP_MCBSP5
1da177e4 LT	313	} omap_mcbsp_id;
1da177e4 LT	314
120db2cb TL	315	typedef int __bitwise omap_mcbsp_io_type_t;
	316	#define OMAP_MCBSP_IRQ_IO ((__force omap_mcbsp_io_type_t) 1)
	317	#define OMAP_MCBSP_POLL_IO ((__force omap_mcbsp_io_type_t) 2)
	318
1da177e4 LT	319	typedef enum {
	320	OMAP_MCBSP_WORD_8 = 0,
	321	OMAP_MCBSP_WORD_12,
	322	OMAP_MCBSP_WORD_16,
	323	OMAP_MCBSP_WORD_20,
	324	OMAP_MCBSP_WORD_24,
	325	OMAP_MCBSP_WORD_32,
	326	} omap_mcbsp_word_length;
	327
	328	typedef enum {
	329	OMAP_MCBSP_CLK_RISING = 0,
	330	OMAP_MCBSP_CLK_FALLING,
	331	} omap_mcbsp_clk_polarity;
	332
	333	typedef enum {
	334	OMAP_MCBSP_FS_ACTIVE_HIGH = 0,
	335	OMAP_MCBSP_FS_ACTIVE_LOW,
	336	} omap_mcbsp_fs_polarity;
	337
	338	typedef enum {
	339	OMAP_MCBSP_CLK_STP_MODE_NO_DELAY = 0,
	340	OMAP_MCBSP_CLK_STP_MODE_DELAY,
	341	} omap_mcbsp_clk_stp_mode;
	342
	343
	344	/***** SPI specific mode ********/
	345	typedef enum {
	346	OMAP_MCBSP_SPI_MASTER = 0,
	347	OMAP_MCBSP_SPI_SLAVE,
	348	} omap_mcbsp_spi_mode;
	349
	350	struct omap_mcbsp_spi_cfg {
	351	omap_mcbsp_spi_mode spi_mode;
	352	omap_mcbsp_clk_polarity rx_clock_polarity;
	353	omap_mcbsp_clk_polarity tx_clock_polarity;
	354	omap_mcbsp_fs_polarity fsx_polarity;
	355	u8 clk_div;
	356	omap_mcbsp_clk_stp_mode clk_stp_mode;
	357	omap_mcbsp_word_length word_length;
	358	};
	359
bc5d0c89 EV	360	/* Platform specific configuration */
	361	struct omap_mcbsp_ops {
	362	void (*request)(unsigned int);
	363	void (*free)(unsigned int);
bc5d0c89 EV	364	};
	365
	366	struct omap_mcbsp_platform_data {
65846909	367	unsigned long phys_base;
bc5d0c89 EV	368	u8 dma_rx_sync, dma_tx_sync;
	369	u16 rx_irq, tx_irq;
	370	struct omap_mcbsp_ops *ops;
a1a56f5f EV	371	#ifdef CONFIG_ARCH_OMAP34XX
	372	u16 buffer_size;
	373	#endif
bc5d0c89 EV	374	};
	375
	376	struct omap_mcbsp {
	377	struct device *dev;
65846909	378	unsigned long phys_base;
d592dd1a	379	void __iomem *io_base;
bc5d0c89 EV	380	u8 id;
	381	u8 free;
	382	omap_mcbsp_word_length rx_word_length;
	383	omap_mcbsp_word_length tx_word_length;
	384
	385	omap_mcbsp_io_type_t io_type; /* IRQ or poll */
	386	/* IRQ based TX/RX */
	387	int rx_irq;
	388	int tx_irq;
	389
	390	/* DMA stuff */
	391	u8 dma_rx_sync;
	392	short dma_rx_lch;
	393	u8 dma_tx_sync;
	394	short dma_tx_lch;
	395
	396	/* Completion queues */
	397	struct completion tx_irq_completion;
	398	struct completion rx_irq_completion;
	399	struct completion tx_dma_completion;
	400	struct completion rx_dma_completion;
	401
	402	/* Protect the field .free, while checking if the mcbsp is in use */
	403	spinlock_t lock;
	404	struct omap_mcbsp_platform_data *pdata;
b820ce4e RK	405	struct clk *iclk;
b820ce4e RK	406	struct clk *fclk;
a1a56f5f	407	#ifdef CONFIG_ARCH_OMAP34XX
98cb20e8	408	int dma_op_mode;
a1a56f5f EV	409	u16 max_tx_thres;
	410	u16 max_rx_thres;
	411	#endif
bc5d0c89	412	};
b4b58f58 CS	413	extern struct omap_mcbsp **mcbsp_ptr;
b4b58f58 CS	414	extern int omap_mcbsp_count;
bc5d0c89 EV	415
	416	int omap_mcbsp_init(void);
	417	void omap_mcbsp_register_board_cfg(struct omap_mcbsp_platform_data *config,
	418	int size);
1da177e4	419	void omap_mcbsp_config(unsigned int id, const struct omap_mcbsp_reg_cfg * config);
7aa9ff56 EV	420	#ifdef CONFIG_ARCH_OMAP34XX
	421	void omap_mcbsp_set_tx_threshold(unsigned int id, u16 threshold);
	422	void omap_mcbsp_set_rx_threshold(unsigned int id, u16 threshold);
a1a56f5f EV	423	u16 omap_mcbsp_get_max_tx_threshold(unsigned int id);
a1a56f5f EV	424	u16 omap_mcbsp_get_max_rx_threshold(unsigned int id);
98cb20e8	425	int omap_mcbsp_get_dma_op_mode(unsigned int id);
7aa9ff56 EV	426	#else
	427	static inline void omap_mcbsp_set_tx_threshold(unsigned int id, u16 threshold)
	428	{ }
	429	static inline void omap_mcbsp_set_rx_threshold(unsigned int id, u16 threshold)
	430	{ }
a1a56f5f EV	431	static inline u16 omap_mcbsp_get_max_tx_threshold(unsigned int id) { return 0; }
a1a56f5f EV	432	static inline u16 omap_mcbsp_get_max_rx_threshold(unsigned int id) { return 0; }
98cb20e8	433	static inline int omap_mcbsp_get_dma_op_mode(unsigned int id) { return 0; }
7aa9ff56	434	#endif
1da177e4 LT	435	int omap_mcbsp_request(unsigned int id);
1da177e4 LT	436	void omap_mcbsp_free(unsigned int id);
c12abc01 JN	437	void omap_mcbsp_start(unsigned int id, int tx, int rx);
c12abc01 JN	438	void omap_mcbsp_stop(unsigned int id, int tx, int rx);
1da177e4 LT	439	void omap_mcbsp_xmit_word(unsigned int id, u32 word);
	440	u32 omap_mcbsp_recv_word(unsigned int id);
	441
	442	int omap_mcbsp_xmit_buffer(unsigned int id, dma_addr_t buffer, unsigned int length);
	443	int omap_mcbsp_recv_buffer(unsigned int id, dma_addr_t buffer, unsigned int length);
120db2cb TL	444	int omap_mcbsp_spi_master_xmit_word_poll(unsigned int id, u32 word);
	445	int omap_mcbsp_spi_master_recv_word_poll(unsigned int id, u32 * word);
	446
1da177e4 LT	447
	448	/* SPI specific API */
	449	void omap_mcbsp_set_spi_mode(unsigned int id, const struct omap_mcbsp_spi_cfg * spi_cfg);
	450
	451	/* Polled read/write functions */
	452	int omap_mcbsp_pollread(unsigned int id, u16 * buf);
	453	int omap_mcbsp_pollwrite(unsigned int id, u16 buf);
b4b58f58	454	int omap_mcbsp_set_io_type(unsigned int id, omap_mcbsp_io_type_t io_type);
1da177e4 LT	455
1da177e4 LT	456	#endif