[linux-2.6-block.git] / arch / arm / plat-omap / include / mach / entry-macro.S

/*
 * arch/arm/plat-omap/include/mach/entry-macro.S
 *
 * Low-level IRQ helper macros for OMAP-based platforms
 *
 * Copyright (C) 2009 Texas Instruments
 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
 *
 * This file is licensed under  the terms of the GNU General Public
 * License version 2. This program is licensed "as is" without any
 * warranty of any kind, whether express or implied.
 */
#include <mach/hardware.h>
#include <mach/io.h>
#include <mach/irqs.h>
#include <asm/hardware/gic.h>

#if defined(CONFIG_ARCH_OMAP1)

#if defined(CONFIG_ARCH_OMAP730) && \
	(defined(CONFIG_ARCH_OMAP15XX) || defined(CONFIG_ARCH_OMAP16XX))
#error "FIXME: OMAP730 doesn't support multiple-OMAP"
#elif defined(CONFIG_ARCH_OMAP730)
#define INT_IH2_IRQ		INT_730_IH2_IRQ
#elif defined(CONFIG_ARCH_OMAP15XX)
#define INT_IH2_IRQ		INT_1510_IH2_IRQ
#elif defined(CONFIG_ARCH_OMAP16XX)
#define INT_IH2_IRQ		INT_1610_IH2_IRQ
#else
#warning "IH2 IRQ defaulted"
#define INT_IH2_IRQ		INT_1510_IH2_IRQ
#endif

 		.macro	disable_fiq
		.endm

		.macro  get_irqnr_preamble, base, tmp
		.endm

		.macro  arch_ret_to_user, tmp1, tmp2
		.endm

		.macro	get_irqnr_and_base, irqnr, irqstat, base, tmp
		ldr	\base, =OMAP1_IO_ADDRESS(OMAP_IH1_BASE)
		ldr	\irqnr, [\base, #IRQ_ITR_REG_OFFSET]
		ldr	\tmp, [\base, #IRQ_MIR_REG_OFFSET]
		mov	\irqstat, #0xffffffff
		bic	\tmp, \irqstat, \tmp
		tst	\irqnr, \tmp
		beq	1510f

		ldr	\irqnr, [\base, #IRQ_SIR_FIQ_REG_OFFSET]
		cmp	\irqnr, #0
		ldreq	\irqnr, [\base, #IRQ_SIR_IRQ_REG_OFFSET]
		cmpeq	\irqnr, #INT_IH2_IRQ
		ldreq	\base, =OMAP1_IO_ADDRESS(OMAP_IH2_BASE)
		ldreq	\irqnr, [\base, #IRQ_SIR_IRQ_REG_OFFSET]
		addeqs	\irqnr, \irqnr, #32
1510:
		.endm

#endif
#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \
			defined(CONFIG_ARCH_OMAP4)

#include <mach/omap24xx.h>
#include <mach/omap34xx.h>

/* REVISIT: This should be set dynamically if CONFIG_MULTI_OMAP2 is selected */
#if defined(CONFIG_ARCH_OMAP2420) || defined(CONFIG_ARCH_OMAP2430)
#define OMAP2_VA_IC_BASE		OMAP2_IO_ADDRESS(OMAP24XX_IC_BASE)
#elif defined(CONFIG_ARCH_OMAP34XX)
#define OMAP2_VA_IC_BASE		OMAP2_IO_ADDRESS(OMAP34XX_IC_BASE)
#endif
#if defined(CONFIG_ARCH_OMAP4)
#include <mach/omap44xx.h>
#endif
#define INTCPS_SIR_IRQ_OFFSET	0x0040		/* Active interrupt offset */
#define	ACTIVEIRQ_MASK		0x7f		/* Active interrupt bits */

		.macro	disable_fiq
		.endm

		.macro  get_irqnr_preamble, base, tmp
		.endm

		.macro  arch_ret_to_user, tmp1, tmp2
		.endm

#ifndef CONFIG_ARCH_OMAP4
		.macro	get_irqnr_and_base, irqnr, irqstat, base, tmp
		ldr	\base, =OMAP2_VA_IC_BASE
		ldr	\irqnr, [\base, #0x98] /* IRQ pending reg 1 */
		cmp	\irqnr, #0x0
		bne	2222f
		ldr	\irqnr, [\base, #0xb8] /* IRQ pending reg 2 */
		cmp	\irqnr, #0x0
		bne	2222f
		ldr	\irqnr, [\base, #0xd8] /* IRQ pending reg 3 */
		cmp	\irqnr, #0x0
2222:
		ldrne	\irqnr, [\base, #INTCPS_SIR_IRQ_OFFSET]
		and	\irqnr, \irqnr, #ACTIVEIRQ_MASK /* Clear spurious bits */

		.endm
#else
		/*
		 * The interrupt numbering scheme is defined in the
		 * interrupt controller spec.  To wit:
		 *
		 * Interrupts 0-15 are IPI
		 * 16-28 are reserved
		 * 29-31 are local.  We allow 30 to be used for the watchdog.
		 * 32-1020 are global
		 * 1021-1022 are reserved
		 * 1023 is "spurious" (no interrupt)
		 *
		 * For now, we ignore all local interrupts so only return an
		 * interrupt if it's between 30 and 1020.  The test_for_ipi
		 * routine below will pick up on IPIs.
		 * A simple read from the controller will tell us the number
		 * of the highest priority enabled interrupt.
		 * We then just need to check whether it is in the
		 * valid range for an IRQ (30-1020 inclusive).
		 */
		.macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
		ldr     \base, =OMAP44XX_VA_GIC_CPU_BASE
		ldr     \irqstat, [\base, #GIC_CPU_INTACK]

		ldr     \tmp, =1021

		bic     \irqnr, \irqstat, #0x1c00

		cmp     \irqnr, #29
		cmpcc   \irqnr, \irqnr
		cmpne   \irqnr, \tmp
		cmpcs   \irqnr, \irqnr
		.endm

		/* We assume that irqstat (the raw value of the IRQ acknowledge
		 * register) is preserved from the macro above.
		 * If there is an IPI, we immediately signal end of interrupt
		 * on the controller, since this requires the original irqstat
		 * value which we won't easily be able to recreate later.
		 */

		.macro test_for_ipi, irqnr, irqstat, base, tmp
		bic	\irqnr, \irqstat, #0x1c00
		cmp	\irqnr, #16
		it	cc
		strcc	\irqstat, [\base, #GIC_CPU_EOI]
		it	cs
		cmpcs	\irqnr, \irqnr
		.endm

		/* As above, this assumes that irqstat and base are preserved */

		.macro test_for_ltirq, irqnr, irqstat, base, tmp
		bic	\irqnr, \irqstat, #0x1c00
		mov 	\tmp, #0
		cmp	\irqnr, #29
		itt	eq
		moveq	\tmp, #1
		streq	\irqstat, [\base, #GIC_CPU_EOI]
		cmp	\tmp, #0
		.endm
#endif

		.macro	irq_prio_table
		.endm

#endif
Commit	Line	Data
1da177e4	1	/*
a09e64fb	2	* arch/arm/plat-omap/include/mach/entry-macro.S
1da177e4 LT	3	*
	4	* Low-level IRQ helper macros for OMAP-based platforms
	5	*
44169075 SS	6	* Copyright (C) 2009 Texas Instruments
	7	* Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
	8	*
1da177e4 LT	9	* This file is licensed under the terms of the GNU General Public
	10	* License version 2. This program is licensed "as is" without any
	11	* warranty of any kind, whether express or implied.
	12	*/
a09e64fb RK	13	#include <mach/hardware.h>
	14	#include <mach/io.h>
	15	#include <mach/irqs.h>
44169075	16	#include <asm/hardware/gic.h>
1da177e4	17
9839c6b8 TL	18	#if defined(CONFIG_ARCH_OMAP1)
9839c6b8 TL	19
9ad5897c TL	20	#if defined(CONFIG_ARCH_OMAP730) && \
	21	(defined(CONFIG_ARCH_OMAP15XX) \|\| defined(CONFIG_ARCH_OMAP16XX))
	22	#error "FIXME: OMAP730 doesn't support multiple-OMAP"
	23	#elif defined(CONFIG_ARCH_OMAP730)
	24	#define INT_IH2_IRQ INT_730_IH2_IRQ
	25	#elif defined(CONFIG_ARCH_OMAP15XX)
	26	#define INT_IH2_IRQ INT_1510_IH2_IRQ
	27	#elif defined(CONFIG_ARCH_OMAP16XX)
	28	#define INT_IH2_IRQ INT_1610_IH2_IRQ
	29	#else
	30	#warning "IH2 IRQ defaulted"
	31	#define INT_IH2_IRQ INT_1510_IH2_IRQ
	32	#endif
	33
1da177e4 LT	34	.macro disable_fiq
	35	.endm
	36
f80dff9d DW	37	.macro get_irqnr_preamble, base, tmp
	38	.endm
	39
	40	.macro arch_ret_to_user, tmp1, tmp2
	41	.endm
	42
1da177e4	43	.macro get_irqnr_and_base, irqnr, irqstat, base, tmp
94113260	44	ldr \base, =OMAP1_IO_ADDRESS(OMAP_IH1_BASE)
1da177e4 LT	45	ldr \irqnr, [\base, #IRQ_ITR_REG_OFFSET]
	46	ldr \tmp, [\base, #IRQ_MIR_REG_OFFSET]
	47	mov \irqstat, #0xffffffff
	48	bic \tmp, \irqstat, \tmp
	49	tst \irqnr, \tmp
	50	beq 1510f
	51
	52	ldr \irqnr, [\base, #IRQ_SIR_FIQ_REG_OFFSET]
	53	cmp \irqnr, #0
	54	ldreq \irqnr, [\base, #IRQ_SIR_IRQ_REG_OFFSET]
	55	cmpeq \irqnr, #INT_IH2_IRQ
94113260	56	ldreq \base, =OMAP1_IO_ADDRESS(OMAP_IH2_BASE)
1da177e4 LT	57	ldreq \irqnr, [\base, #IRQ_SIR_IRQ_REG_OFFSET]
	58	addeqs \irqnr, \irqnr, #32
	59	1510:
	60	.endm
	61
cc26b3b0	62	#endif
44169075 SS	63	#if defined(CONFIG_ARCH_OMAP24XX) \|\| defined(CONFIG_ARCH_OMAP34XX) \|\| \
44169075 SS	64	defined(CONFIG_ARCH_OMAP4)
9839c6b8	65
a09e64fb	66	#include <mach/omap24xx.h>
cc26b3b0	67	#include <mach/omap34xx.h>
8a424bb3 TL	68
	69	/* REVISIT: This should be set dynamically if CONFIG_MULTI_OMAP2 is selected */
	70	#if defined(CONFIG_ARCH_OMAP2420) \|\| defined(CONFIG_ARCH_OMAP2430)
94113260	71	#define OMAP2_VA_IC_BASE OMAP2_IO_ADDRESS(OMAP24XX_IC_BASE)
8a424bb3	72	#elif defined(CONFIG_ARCH_OMAP34XX)
94113260	73	#define OMAP2_VA_IC_BASE OMAP2_IO_ADDRESS(OMAP34XX_IC_BASE)
cc26b3b0	74	#endif
44169075 SS	75	#if defined(CONFIG_ARCH_OMAP4)
	76	#include <mach/omap44xx.h>
	77	#endif
52414739 TL	78	#define INTCPS_SIR_IRQ_OFFSET 0x0040 /* Active interrupt offset */
52414739 TL	79	#define ACTIVEIRQ_MASK 0x7f /* Active interrupt bits */
9839c6b8 TL	80
	81	.macro disable_fiq
	82	.endm
	83
1f4d1774 TL	84	.macro get_irqnr_preamble, base, tmp
	85	.endm
	86
	87	.macro arch_ret_to_user, tmp1, tmp2
	88	.endm
	89
44169075	90	#ifndef CONFIG_ARCH_OMAP4
9839c6b8	91	.macro get_irqnr_and_base, irqnr, irqstat, base, tmp
44595982	92	ldr \base, =OMAP2_VA_IC_BASE
9839c6b8 TL	93	ldr \irqnr, [\base, #0x98] /* IRQ pending reg 1 */
	94	cmp \irqnr, #0x0
	95	bne 2222f
	96	ldr \irqnr, [\base, #0xb8] /* IRQ pending reg 2 */
	97	cmp \irqnr, #0x0
	98	bne 2222f
	99	ldr \irqnr, [\base, #0xd8] /* IRQ pending reg 3 */
	100	cmp \irqnr, #0x0
	101	2222:
cc26b3b0	102	ldrne \irqnr, [\base, #INTCPS_SIR_IRQ_OFFSET]
52414739	103	and \irqnr, \irqnr, #ACTIVEIRQ_MASK /* Clear spurious bits */
9839c6b8 TL	104
9839c6b8 TL	105	.endm
44169075 SS	106	#else
	107	/*
	108	* The interrupt numbering scheme is defined in the
	109	* interrupt controller spec. To wit:
	110	*
	111	* Interrupts 0-15 are IPI
	112	* 16-28 are reserved
	113	* 29-31 are local. We allow 30 to be used for the watchdog.
	114	* 32-1020 are global
	115	* 1021-1022 are reserved
	116	* 1023 is "spurious" (no interrupt)
	117	*
	118	* For now, we ignore all local interrupts so only return an
	119	* interrupt if it's between 30 and 1020. The test_for_ipi
	120	* routine below will pick up on IPIs.
	121	* A simple read from the controller will tell us the number
	122	* of the highest priority enabled interrupt.
	123	* We then just need to check whether it is in the
	124	* valid range for an IRQ (30-1020 inclusive).
	125	*/
	126	.macro get_irqnr_and_base, irqnr, irqstat, base, tmp
	127	ldr \base, =OMAP44XX_VA_GIC_CPU_BASE
	128	ldr \irqstat, [\base, #GIC_CPU_INTACK]
	129
	130	ldr \tmp, =1021
	131
	132	bic \irqnr, \irqstat, #0x1c00
	133
	134	cmp \irqnr, #29
	135	cmpcc \irqnr, \irqnr
	136	cmpne \irqnr, \tmp
	137	cmpcs \irqnr, \irqnr
	138	.endm
39e1d4c1 SS	139
	140	/* We assume that irqstat (the raw value of the IRQ acknowledge
	141	* register) is preserved from the macro above.
	142	* If there is an IPI, we immediately signal end of interrupt
	143	* on the controller, since this requires the original irqstat
	144	* value which we won't easily be able to recreate later.
	145	*/
	146
	147	.macro test_for_ipi, irqnr, irqstat, base, tmp
	148	bic \irqnr, \irqstat, #0x1c00
	149	cmp \irqnr, #16
	150	it cc
	151	strcc \irqstat, [\base, #GIC_CPU_EOI]
	152	it cs
	153	cmpcs \irqnr, \irqnr
	154	.endm
	155
	156	/* As above, this assumes that irqstat and base are preserved */
	157
	158	.macro test_for_ltirq, irqnr, irqstat, base, tmp
	159	bic \irqnr, \irqstat, #0x1c00
	160	mov \tmp, #0
	161	cmp \irqnr, #29
	162	itt eq
	163	moveq \tmp, #1
	164	streq \irqstat, [\base, #GIC_CPU_EOI]
	165	cmp \tmp, #0
	166	.endm
44169075	167	#endif
9839c6b8 TL	168
	169	.macro irq_prio_table
	170	.endm
	171
	172	#endif