[linux-block.git] / arch / arm / plat-omap / include / mach / clock.h

/*
 *  arch/arm/plat-omap/include/mach/clock.h
 *
 *  Copyright (C) 2004 - 2005 Nokia corporation
 *  Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com>
 *  Based on clocks.h by Tony Lindgren, Gordon McNutt and RidgeRun, Inc
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#ifndef __ARCH_ARM_OMAP_CLOCK_H
#define __ARCH_ARM_OMAP_CLOCK_H

struct module;
struct clk;
struct clockdomain;

struct clkops {
	int			(*enable)(struct clk *);
	void			(*disable)(struct clk *);
};

#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)

struct clksel_rate {
	u32			val;
	u8			div;
	u8			flags;
};

struct clksel {
	struct clk		 *parent;
	const struct clksel_rate *rates;
};

struct dpll_data {
	void __iomem		*mult_div1_reg;
	u32			mult_mask;
	u32			div1_mask;
	unsigned int		rate_tolerance;
	unsigned long		last_rounded_rate;
	u16			last_rounded_m;
	u8			last_rounded_n;
	u8			min_divider;
	u8			max_divider;
	u32			max_tolerance;
	u16			max_multiplier;
#  if defined(CONFIG_ARCH_OMAP3)
	u8			modes;
	void __iomem		*control_reg;
	void __iomem		*autoidle_reg;
	void __iomem		*idlest_reg;
	u32			enable_mask;
	u32			autoidle_mask;
	u32			freqsel_mask;
	u32			idlest_mask;
	u8			auto_recal_bit;
	u8			recal_en_bit;
	u8			recal_st_bit;
#  endif
};

#endif

struct clk {
	struct list_head	node;
	const struct clkops	*ops;
	const char		*name;
	int			id;
	struct clk		*parent;
	struct list_head	children;
	struct list_head	sibling;	/* node for children */
	unsigned long		rate;
	__u32			flags;
	void __iomem		*enable_reg;
	void			(*recalc)(struct clk *);
	int			(*set_rate)(struct clk *, unsigned long);
	long			(*round_rate)(struct clk *, unsigned long);
	void			(*init)(struct clk *);
	__u8			enable_bit;
	__s8			usecount;
#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
	u8			fixed_div;
	void __iomem		*clksel_reg;
	u32			clksel_mask;
	const struct clksel	*clksel;
	struct dpll_data	*dpll_data;
	const char		*clkdm_name;
	struct clockdomain	*clkdm;
#else
	__u8			rate_offset;
	__u8			src_offset;
#endif
#if defined(CONFIG_PM_DEBUG) && defined(CONFIG_DEBUG_FS)
	struct dentry		*dent;	/* For visible tree hierarchy */
#endif
};

struct cpufreq_frequency_table;

struct clk_functions {
	int		(*clk_enable)(struct clk *clk);
	void		(*clk_disable)(struct clk *clk);
	long		(*clk_round_rate)(struct clk *clk, unsigned long rate);
	int		(*clk_set_rate)(struct clk *clk, unsigned long rate);
	int		(*clk_set_parent)(struct clk *clk, struct clk *parent);
	void		(*clk_allow_idle)(struct clk *clk);
	void		(*clk_deny_idle)(struct clk *clk);
	void		(*clk_disable_unused)(struct clk *clk);
#ifdef CONFIG_CPU_FREQ
	void		(*clk_init_cpufreq_table)(struct cpufreq_frequency_table **);
#endif
};

extern unsigned int mpurate;

extern int clk_init(struct clk_functions *custom_clocks);
extern void clk_init_one(struct clk *clk);
extern int clk_register(struct clk *clk);
extern void clk_reparent(struct clk *child, struct clk *parent);
extern void clk_unregister(struct clk *clk);
extern void propagate_rate(struct clk *clk);
extern void recalculate_root_clocks(void);
extern void followparent_recalc(struct clk *clk);
extern void clk_enable_init_clocks(void);
#ifdef CONFIG_CPU_FREQ
extern void clk_init_cpufreq_table(struct cpufreq_frequency_table **table);
#endif

extern const struct clkops clkops_null;

/* Clock flags */
/* bit 0 is free */
#define RATE_FIXED		(1 << 1)	/* Fixed clock rate */
/* bits 2-4 are free */
#define ENABLE_REG_32BIT	(1 << 5)	/* Use 32-bit access */
#define CLOCK_IDLE_CONTROL	(1 << 7)
#define CLOCK_NO_IDLE_PARENT	(1 << 8)
#define DELAYED_APP		(1 << 9)	/* Delay application of clock */
#define CONFIG_PARTICIPANT	(1 << 10)	/* Fundamental clock */
#define ENABLE_ON_INIT		(1 << 11)	/* Enable upon framework init */
#define INVERT_ENABLE           (1 << 12)       /* 0 enables, 1 disables */
/* bits 13-31 are currently free */

/* Clksel_rate flags */
#define DEFAULT_RATE		(1 << 0)
#define RATE_IN_242X		(1 << 1)
#define RATE_IN_243X		(1 << 2)
#define RATE_IN_343X		(1 << 3)	/* rates common to all 343X */
#define RATE_IN_3430ES2		(1 << 4)	/* 3430ES2 rates only */

#define RATE_IN_24XX		(RATE_IN_242X | RATE_IN_243X)


/* CM_CLKSEL2_PLL.CORE_CLK_SRC options (24XX) */
#define CORE_CLK_SRC_32K		0
#define CORE_CLK_SRC_DPLL		1
#define CORE_CLK_SRC_DPLL_X2		2

#endif
Commit	Line	Data
9ad5897c	1	/*
a09e64fb	2	* arch/arm/plat-omap/include/mach/clock.h
9ad5897c TL	3	*
	4	* Copyright (C) 2004 - 2005 Nokia corporation
	5	* Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com>
	6	* Based on clocks.h by Tony Lindgren, Gordon McNutt and RidgeRun, Inc
	7	*
	8	* This program is free software; you can redistribute it and/or modify
	9	* it under the terms of the GNU General Public License version 2 as
	10	* published by the Free Software Foundation.
	11	*/
	12
	13	#ifndef __ARCH_ARM_OMAP_CLOCK_H
	14	#define __ARCH_ARM_OMAP_CLOCK_H
	15
	16	struct module;
6b8858a9	17	struct clk;
d1b03f61	18	struct clockdomain;
6b8858a9	19
548d8495 RK	20	struct clkops {
	21	int (enable)(struct clk );
	22	void (disable)(struct clk );
	23	};
	24
b045d080	25	#if defined(CONFIG_ARCH_OMAP2) \|\| defined(CONFIG_ARCH_OMAP3)
6b8858a9 PW	26
6b8858a9 PW	27	struct clksel_rate {
6b8858a9	28	u32 val;
ebb8dca2	29	u8 div;
6b8858a9 PW	30	u8 flags;
	31	};
	32
	33	struct clksel {
	34	struct clk *parent;
	35	const struct clksel_rate *rates;
	36	};
	37
	38	struct dpll_data {
	39	void __iomem *mult_div1_reg;
	40	u32 mult_mask;
	41	u32 div1_mask;
ebb8dca2 RK	42	unsigned int rate_tolerance;
ebb8dca2 RK	43	unsigned long last_rounded_rate;
88b8ba90 PW	44	u16 last_rounded_m;
88b8ba90 PW	45	u8 last_rounded_n;
95f538ac	46	u8 min_divider;
88b8ba90 PW	47	u8 max_divider;
88b8ba90 PW	48	u32 max_tolerance;
ebb8dca2	49	u16 max_multiplier;
b045d080	50	# if defined(CONFIG_ARCH_OMAP3)
542313cc	51	u8 modes;
b045d080	52	void __iomem *control_reg;
ebb8dca2 RK	53	void __iomem *autoidle_reg;
ebb8dca2 RK	54	void __iomem *idlest_reg;
b045d080	55	u32 enable_mask;
ebb8dca2	56	u32 autoidle_mask;
16c90f02	57	u32 freqsel_mask;
c1bd7aaf	58	u32 idlest_mask;
b045d080 PW	59	u8 auto_recal_bit;
	60	u8 recal_en_bit;
	61	u8 recal_st_bit;
	62	# endif
6b8858a9 PW	63	};
	64
	65	#endif
9ad5897c TL	66
	67	struct clk {
	68	struct list_head node;
548d8495	69	const struct clkops *ops;
9ad5897c	70	const char *name;
b824efae	71	int id;
9ad5897c	72	struct clk *parent;
3f0a820c RK	73	struct list_head children;
3f0a820c RK	74	struct list_head sibling; /* node for children */
9ad5897c TL	75	unsigned long rate;
	76	__u32 flags;
	77	void __iomem *enable_reg;
9ad5897c TL	78	void (recalc)(struct clk );
	79	int (set_rate)(struct clk , unsigned long);
	80	long (round_rate)(struct clk , unsigned long);
	81	void (init)(struct clk );
ebb8dca2 RK	82	__u8 enable_bit;
ebb8dca2 RK	83	__s8 usecount;
b045d080	84	#if defined(CONFIG_ARCH_OMAP2) \|\| defined(CONFIG_ARCH_OMAP3)
6b8858a9 PW	85	u8 fixed_div;
	86	void __iomem *clksel_reg;
	87	u32 clksel_mask;
	88	const struct clksel *clksel;
88b8ba90	89	struct dpll_data *dpll_data;
d1b03f61 PW	90	const char *clkdm_name;
d1b03f61 PW	91	struct clockdomain *clkdm;
6b8858a9 PW	92	#else
	93	__u8 rate_offset;
	94	__u8 src_offset;
	95	#endif
137b3ee2 HD	96	#if defined(CONFIG_PM_DEBUG) && defined(CONFIG_DEBUG_FS)
	97	struct dentry dent; / For visible tree hierarchy */
	98	#endif
9ad5897c TL	99	};
9ad5897c TL	100
b851cb28 RK	101	struct cpufreq_frequency_table;
b851cb28 RK	102
9ad5897c TL	103	struct clk_functions {
	104	int (clk_enable)(struct clk clk);
	105	void (clk_disable)(struct clk clk);
9ad5897c TL	106	long (clk_round_rate)(struct clk clk, unsigned long rate);
	107	int (clk_set_rate)(struct clk clk, unsigned long rate);
	108	int (clk_set_parent)(struct clk clk, struct clk *parent);
9ad5897c TL	109	void (clk_allow_idle)(struct clk clk);
9ad5897c TL	110	void (clk_deny_idle)(struct clk clk);
90afd5cb	111	void (clk_disable_unused)(struct clk clk);
b851cb28 RK	112	#ifdef CONFIG_CPU_FREQ
	113	void (clk_init_cpufreq_table)(struct cpufreq_frequency_table *);
	114	#endif
9ad5897c TL	115	};
	116
	117	extern unsigned int mpurate;
9ad5897c	118
fecb494b	119	extern int clk_init(struct clk_functions *custom_clocks);
3f0a820c	120	extern void clk_init_one(struct clk *clk);
9ad5897c	121	extern int clk_register(struct clk *clk);
3f0a820c	122	extern void clk_reparent(struct clk child, struct clk parent);
9ad5897c TL	123	extern void clk_unregister(struct clk *clk);
9ad5897c TL	124	extern void propagate_rate(struct clk *clk);
6b8858a9	125	extern void recalculate_root_clocks(void);
fecb494b	126	extern void followparent_recalc(struct clk *clk);
6b8858a9	127	extern void clk_enable_init_clocks(void);
aeec2990 KH	128	#ifdef CONFIG_CPU_FREQ
	129	extern void clk_init_cpufreq_table(struct cpufreq_frequency_table **table);
	130	#endif
9ad5897c	131
897dcded RK	132	extern const struct clkops clkops_null;
897dcded RK	133
9ad5897c	134	/* Clock flags */
d5e6072b	135	/* bit 0 is free */
9ad5897c	136	#define RATE_FIXED (1 << 1) /* Fixed clock rate */
3f0a820c	137	/* bits 2-4 are free */
9ad5897c	138	#define ENABLE_REG_32BIT (1 << 5) /* Use 32-bit access */
9ad5897c TL	139	#define CLOCK_IDLE_CONTROL (1 << 7)
	140	#define CLOCK_NO_IDLE_PARENT (1 << 8)
	141	#define DELAYED_APP (1 << 9) /* Delay application of clock */
	142	#define CONFIG_PARTICIPANT (1 << 10) /* Fundamental clock */
6b8858a9 PW	143	#define ENABLE_ON_INIT (1 << 11) /* Enable upon framework init */
6b8858a9 PW	144	#define INVERT_ENABLE (1 << 12) /* 0 enables, 1 disables */
44dc9d02	145	/* bits 13-31 are currently free */
6b8858a9 PW	146
	147	/* Clksel_rate flags */
	148	#define DEFAULT_RATE (1 << 0)
	149	#define RATE_IN_242X (1 << 1)
	150	#define RATE_IN_243X (1 << 2)
	151	#define RATE_IN_343X (1 << 3) /* rates common to all 343X */
	152	#define RATE_IN_3430ES2 (1 << 4) /* 3430ES2 rates only */
	153
	154	#define RATE_IN_24XX (RATE_IN_242X \| RATE_IN_243X)
	155
9ad5897c	156
44595982 PW	157	/* CM_CLKSEL2_PLL.CORE_CLK_SRC options (24XX) */
	158	#define CORE_CLK_SRC_32K 0
	159	#define CORE_CLK_SRC_DPLL 1
	160	#define CORE_CLK_SRC_DPLL_X2 2
	161
9ad5897c	162	#endif