Commit | Line | Data |
---|---|---|
9ad5897c | 1 | /* |
a09e64fb | 2 | * arch/arm/plat-omap/include/mach/clock.h |
9ad5897c TL |
3 | * |
4 | * Copyright (C) 2004 - 2005 Nokia corporation | |
5 | * Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com> | |
6 | * Based on clocks.h by Tony Lindgren, Gordon McNutt and RidgeRun, Inc | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License version 2 as | |
10 | * published by the Free Software Foundation. | |
11 | */ | |
12 | ||
13 | #ifndef __ARCH_ARM_OMAP_CLOCK_H | |
14 | #define __ARCH_ARM_OMAP_CLOCK_H | |
15 | ||
16 | struct module; | |
6b8858a9 PW |
17 | struct clk; |
18 | ||
b045d080 | 19 | #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) |
6b8858a9 PW |
20 | |
21 | struct clksel_rate { | |
22 | u8 div; | |
23 | u32 val; | |
24 | u8 flags; | |
25 | }; | |
26 | ||
27 | struct clksel { | |
28 | struct clk *parent; | |
29 | const struct clksel_rate *rates; | |
30 | }; | |
31 | ||
32 | struct dpll_data { | |
33 | void __iomem *mult_div1_reg; | |
34 | u32 mult_mask; | |
35 | u32 div1_mask; | |
88b8ba90 PW |
36 | u16 last_rounded_m; |
37 | u8 last_rounded_n; | |
38 | unsigned long last_rounded_rate; | |
39 | unsigned int rate_tolerance; | |
40 | u16 max_multiplier; | |
41 | u8 max_divider; | |
42 | u32 max_tolerance; | |
b045d080 | 43 | # if defined(CONFIG_ARCH_OMAP3) |
542313cc | 44 | u8 modes; |
b045d080 PW |
45 | void __iomem *control_reg; |
46 | u32 enable_mask; | |
47 | u8 auto_recal_bit; | |
48 | u8 recal_en_bit; | |
49 | u8 recal_st_bit; | |
542313cc PW |
50 | void __iomem *autoidle_reg; |
51 | u32 autoidle_mask; | |
52 | void __iomem *idlest_reg; | |
53 | u8 idlest_bit; | |
b045d080 | 54 | # endif |
6b8858a9 PW |
55 | }; |
56 | ||
57 | #endif | |
9ad5897c TL |
58 | |
59 | struct clk { | |
60 | struct list_head node; | |
61 | struct module *owner; | |
62 | const char *name; | |
b824efae | 63 | int id; |
9ad5897c TL |
64 | struct clk *parent; |
65 | unsigned long rate; | |
66 | __u32 flags; | |
67 | void __iomem *enable_reg; | |
68 | __u8 enable_bit; | |
9ad5897c TL |
69 | __s8 usecount; |
70 | void (*recalc)(struct clk *); | |
71 | int (*set_rate)(struct clk *, unsigned long); | |
72 | long (*round_rate)(struct clk *, unsigned long); | |
73 | void (*init)(struct clk *); | |
74 | int (*enable)(struct clk *); | |
75 | void (*disable)(struct clk *); | |
b045d080 | 76 | #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) |
6b8858a9 PW |
77 | u8 fixed_div; |
78 | void __iomem *clksel_reg; | |
79 | u32 clksel_mask; | |
80 | const struct clksel *clksel; | |
88b8ba90 | 81 | struct dpll_data *dpll_data; |
6b8858a9 PW |
82 | #else |
83 | __u8 rate_offset; | |
84 | __u8 src_offset; | |
85 | #endif | |
137b3ee2 HD |
86 | #if defined(CONFIG_PM_DEBUG) && defined(CONFIG_DEBUG_FS) |
87 | struct dentry *dent; /* For visible tree hierarchy */ | |
88 | #endif | |
9ad5897c TL |
89 | }; |
90 | ||
b851cb28 RK |
91 | struct cpufreq_frequency_table; |
92 | ||
9ad5897c TL |
93 | struct clk_functions { |
94 | int (*clk_enable)(struct clk *clk); | |
95 | void (*clk_disable)(struct clk *clk); | |
9ad5897c TL |
96 | long (*clk_round_rate)(struct clk *clk, unsigned long rate); |
97 | int (*clk_set_rate)(struct clk *clk, unsigned long rate); | |
98 | int (*clk_set_parent)(struct clk *clk, struct clk *parent); | |
99 | struct clk * (*clk_get_parent)(struct clk *clk); | |
100 | void (*clk_allow_idle)(struct clk *clk); | |
101 | void (*clk_deny_idle)(struct clk *clk); | |
90afd5cb | 102 | void (*clk_disable_unused)(struct clk *clk); |
b851cb28 RK |
103 | #ifdef CONFIG_CPU_FREQ |
104 | void (*clk_init_cpufreq_table)(struct cpufreq_frequency_table **); | |
105 | #endif | |
9ad5897c TL |
106 | }; |
107 | ||
108 | extern unsigned int mpurate; | |
9ad5897c TL |
109 | |
110 | extern int clk_init(struct clk_functions * custom_clocks); | |
111 | extern int clk_register(struct clk *clk); | |
112 | extern void clk_unregister(struct clk *clk); | |
113 | extern void propagate_rate(struct clk *clk); | |
6b8858a9 | 114 | extern void recalculate_root_clocks(void); |
9ad5897c TL |
115 | extern void followparent_recalc(struct clk * clk); |
116 | extern void clk_allow_idle(struct clk *clk); | |
117 | extern void clk_deny_idle(struct clk *clk); | |
b824efae | 118 | extern int clk_get_usecount(struct clk *clk); |
6b8858a9 | 119 | extern void clk_enable_init_clocks(void); |
9ad5897c TL |
120 | |
121 | /* Clock flags */ | |
122 | #define RATE_CKCTL (1 << 0) /* Main fixed ratio clocks */ | |
123 | #define RATE_FIXED (1 << 1) /* Fixed clock rate */ | |
124 | #define RATE_PROPAGATES (1 << 2) /* Program children too */ | |
125 | #define VIRTUAL_CLOCK (1 << 3) /* Composite clock from table */ | |
126 | #define ALWAYS_ENABLED (1 << 4) /* Clock cannot be disabled */ | |
127 | #define ENABLE_REG_32BIT (1 << 5) /* Use 32-bit access */ | |
128 | #define VIRTUAL_IO_ADDRESS (1 << 6) /* Clock in virtual address */ | |
129 | #define CLOCK_IDLE_CONTROL (1 << 7) | |
130 | #define CLOCK_NO_IDLE_PARENT (1 << 8) | |
131 | #define DELAYED_APP (1 << 9) /* Delay application of clock */ | |
132 | #define CONFIG_PARTICIPANT (1 << 10) /* Fundamental clock */ | |
6b8858a9 PW |
133 | #define ENABLE_ON_INIT (1 << 11) /* Enable upon framework init */ |
134 | #define INVERT_ENABLE (1 << 12) /* 0 enables, 1 disables */ | |
135 | /* bits 13-20 are currently free */ | |
b824efae TL |
136 | #define CLOCK_IN_OMAP310 (1 << 21) |
137 | #define CLOCK_IN_OMAP730 (1 << 22) | |
138 | #define CLOCK_IN_OMAP1510 (1 << 23) | |
139 | #define CLOCK_IN_OMAP16XX (1 << 24) | |
140 | #define CLOCK_IN_OMAP242X (1 << 25) | |
141 | #define CLOCK_IN_OMAP243X (1 << 26) | |
6b8858a9 PW |
142 | #define CLOCK_IN_OMAP343X (1 << 27) /* clocks common to all 343X */ |
143 | #define PARENT_CONTROLS_CLOCK (1 << 28) | |
144 | #define CLOCK_IN_OMAP3430ES1 (1 << 29) /* 3430ES1 clocks only */ | |
145 | #define CLOCK_IN_OMAP3430ES2 (1 << 30) /* 3430ES2 clocks only */ | |
146 | ||
147 | /* Clksel_rate flags */ | |
148 | #define DEFAULT_RATE (1 << 0) | |
149 | #define RATE_IN_242X (1 << 1) | |
150 | #define RATE_IN_243X (1 << 2) | |
151 | #define RATE_IN_343X (1 << 3) /* rates common to all 343X */ | |
152 | #define RATE_IN_3430ES2 (1 << 4) /* 3430ES2 rates only */ | |
153 | ||
154 | #define RATE_IN_24XX (RATE_IN_242X | RATE_IN_243X) | |
155 | ||
9ad5897c | 156 | |
44595982 PW |
157 | /* CM_CLKSEL2_PLL.CORE_CLK_SRC options (24XX) */ |
158 | #define CORE_CLK_SRC_32K 0 | |
159 | #define CORE_CLK_SRC_DPLL 1 | |
160 | #define CORE_CLK_SRC_DPLL_X2 2 | |
161 | ||
9ad5897c | 162 | #endif |