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9ad5897c | 1 | /* |
a09e64fb | 2 | * arch/arm/plat-omap/include/mach/clock.h |
9ad5897c TL |
3 | * |
4 | * Copyright (C) 2004 - 2005 Nokia corporation | |
5 | * Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com> | |
6 | * Based on clocks.h by Tony Lindgren, Gordon McNutt and RidgeRun, Inc | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License version 2 as | |
10 | * published by the Free Software Foundation. | |
11 | */ | |
12 | ||
13 | #ifndef __ARCH_ARM_OMAP_CLOCK_H | |
14 | #define __ARCH_ARM_OMAP_CLOCK_H | |
15 | ||
16 | struct module; | |
6b8858a9 | 17 | struct clk; |
d1b03f61 | 18 | struct clockdomain; |
6b8858a9 | 19 | |
548d8495 RK |
20 | struct clkops { |
21 | int (*enable)(struct clk *); | |
22 | void (*disable)(struct clk *); | |
23 | }; | |
24 | ||
b045d080 | 25 | #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) |
6b8858a9 PW |
26 | |
27 | struct clksel_rate { | |
6b8858a9 | 28 | u32 val; |
ebb8dca2 | 29 | u8 div; |
6b8858a9 PW |
30 | u8 flags; |
31 | }; | |
32 | ||
33 | struct clksel { | |
34 | struct clk *parent; | |
35 | const struct clksel_rate *rates; | |
36 | }; | |
37 | ||
38 | struct dpll_data { | |
39 | void __iomem *mult_div1_reg; | |
40 | u32 mult_mask; | |
41 | u32 div1_mask; | |
ebb8dca2 RK |
42 | unsigned int rate_tolerance; |
43 | unsigned long last_rounded_rate; | |
88b8ba90 PW |
44 | u16 last_rounded_m; |
45 | u8 last_rounded_n; | |
88b8ba90 PW |
46 | u8 max_divider; |
47 | u32 max_tolerance; | |
ebb8dca2 | 48 | u16 max_multiplier; |
b045d080 | 49 | # if defined(CONFIG_ARCH_OMAP3) |
542313cc | 50 | u8 modes; |
b045d080 | 51 | void __iomem *control_reg; |
ebb8dca2 RK |
52 | void __iomem *autoidle_reg; |
53 | void __iomem *idlest_reg; | |
b045d080 | 54 | u32 enable_mask; |
ebb8dca2 | 55 | u32 autoidle_mask; |
16c90f02 | 56 | u32 freqsel_mask; |
b045d080 PW |
57 | u8 auto_recal_bit; |
58 | u8 recal_en_bit; | |
59 | u8 recal_st_bit; | |
542313cc | 60 | u8 idlest_bit; |
b045d080 | 61 | # endif |
6b8858a9 PW |
62 | }; |
63 | ||
64 | #endif | |
9ad5897c TL |
65 | |
66 | struct clk { | |
67 | struct list_head node; | |
548d8495 | 68 | const struct clkops *ops; |
9ad5897c | 69 | const char *name; |
b824efae | 70 | int id; |
9ad5897c TL |
71 | struct clk *parent; |
72 | unsigned long rate; | |
73 | __u32 flags; | |
74 | void __iomem *enable_reg; | |
9ad5897c TL |
75 | void (*recalc)(struct clk *); |
76 | int (*set_rate)(struct clk *, unsigned long); | |
77 | long (*round_rate)(struct clk *, unsigned long); | |
78 | void (*init)(struct clk *); | |
ebb8dca2 RK |
79 | __u8 enable_bit; |
80 | __s8 usecount; | |
b045d080 | 81 | #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) |
6b8858a9 PW |
82 | u8 fixed_div; |
83 | void __iomem *clksel_reg; | |
84 | u32 clksel_mask; | |
85 | const struct clksel *clksel; | |
88b8ba90 | 86 | struct dpll_data *dpll_data; |
d1b03f61 PW |
87 | const char *clkdm_name; |
88 | struct clockdomain *clkdm; | |
6b8858a9 PW |
89 | #else |
90 | __u8 rate_offset; | |
91 | __u8 src_offset; | |
92 | #endif | |
137b3ee2 HD |
93 | #if defined(CONFIG_PM_DEBUG) && defined(CONFIG_DEBUG_FS) |
94 | struct dentry *dent; /* For visible tree hierarchy */ | |
95 | #endif | |
9ad5897c TL |
96 | }; |
97 | ||
b851cb28 RK |
98 | struct cpufreq_frequency_table; |
99 | ||
9ad5897c TL |
100 | struct clk_functions { |
101 | int (*clk_enable)(struct clk *clk); | |
102 | void (*clk_disable)(struct clk *clk); | |
9ad5897c TL |
103 | long (*clk_round_rate)(struct clk *clk, unsigned long rate); |
104 | int (*clk_set_rate)(struct clk *clk, unsigned long rate); | |
105 | int (*clk_set_parent)(struct clk *clk, struct clk *parent); | |
9ad5897c TL |
106 | void (*clk_allow_idle)(struct clk *clk); |
107 | void (*clk_deny_idle)(struct clk *clk); | |
90afd5cb | 108 | void (*clk_disable_unused)(struct clk *clk); |
b851cb28 RK |
109 | #ifdef CONFIG_CPU_FREQ |
110 | void (*clk_init_cpufreq_table)(struct cpufreq_frequency_table **); | |
111 | #endif | |
9ad5897c TL |
112 | }; |
113 | ||
114 | extern unsigned int mpurate; | |
9ad5897c TL |
115 | |
116 | extern int clk_init(struct clk_functions * custom_clocks); | |
117 | extern int clk_register(struct clk *clk); | |
118 | extern void clk_unregister(struct clk *clk); | |
119 | extern void propagate_rate(struct clk *clk); | |
6b8858a9 | 120 | extern void recalculate_root_clocks(void); |
9ad5897c | 121 | extern void followparent_recalc(struct clk * clk); |
b824efae | 122 | extern int clk_get_usecount(struct clk *clk); |
6b8858a9 | 123 | extern void clk_enable_init_clocks(void); |
9ad5897c | 124 | |
897dcded RK |
125 | extern const struct clkops clkops_null; |
126 | ||
9ad5897c | 127 | /* Clock flags */ |
d5e6072b | 128 | /* bit 0 is free */ |
9ad5897c TL |
129 | #define RATE_FIXED (1 << 1) /* Fixed clock rate */ |
130 | #define RATE_PROPAGATES (1 << 2) /* Program children too */ | |
897dcded | 131 | /* bits 3-4 are free */ |
9ad5897c TL |
132 | #define ENABLE_REG_32BIT (1 << 5) /* Use 32-bit access */ |
133 | #define VIRTUAL_IO_ADDRESS (1 << 6) /* Clock in virtual address */ | |
134 | #define CLOCK_IDLE_CONTROL (1 << 7) | |
135 | #define CLOCK_NO_IDLE_PARENT (1 << 8) | |
136 | #define DELAYED_APP (1 << 9) /* Delay application of clock */ | |
137 | #define CONFIG_PARTICIPANT (1 << 10) /* Fundamental clock */ | |
6b8858a9 PW |
138 | #define ENABLE_ON_INIT (1 << 11) /* Enable upon framework init */ |
139 | #define INVERT_ENABLE (1 << 12) /* 0 enables, 1 disables */ | |
44dc9d02 | 140 | /* bits 13-31 are currently free */ |
6b8858a9 PW |
141 | |
142 | /* Clksel_rate flags */ | |
143 | #define DEFAULT_RATE (1 << 0) | |
144 | #define RATE_IN_242X (1 << 1) | |
145 | #define RATE_IN_243X (1 << 2) | |
146 | #define RATE_IN_343X (1 << 3) /* rates common to all 343X */ | |
147 | #define RATE_IN_3430ES2 (1 << 4) /* 3430ES2 rates only */ | |
148 | ||
149 | #define RATE_IN_24XX (RATE_IN_242X | RATE_IN_243X) | |
150 | ||
9ad5897c | 151 | |
44595982 PW |
152 | /* CM_CLKSEL2_PLL.CORE_CLK_SRC options (24XX) */ |
153 | #define CORE_CLK_SRC_32K 0 | |
154 | #define CORE_CLK_SRC_DPLL 1 | |
155 | #define CORE_CLK_SRC_DPLL_X2 2 | |
156 | ||
9ad5897c | 157 | #endif |