[linux-2.6-block.git] / arch / arm / plat-omap / i2c.c

/*
 * linux/arch/arm/plat-omap/i2c.c
 *
 * Helper module for board specific I2C bus registration
 *
 * Copyright (C) 2007 Nokia Corporation.
 *
 * Contact: Jarkko Nikula <jhnikula@gmail.com>
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * version 2 as published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful, but
 * WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
 * 02110-1301 USA
 *
 */

#include <linux/kernel.h>
#include <linux/platform_device.h>
#include <linux/i2c.h>
#include <linux/i2c-omap.h>

#include <mach/irqs.h>
#include <plat/mux.h>
#include <plat/i2c.h>
#include <plat/omap-pm.h>

#define OMAP_I2C_SIZE		0x3f
#define OMAP1_I2C_BASE		0xfffb3800
#define OMAP2_I2C_BASE1		0x48070000
#define OMAP2_I2C_BASE2		0x48072000
#define OMAP2_I2C_BASE3		0x48060000
#define OMAP4_I2C_BASE4		0x48350000

static const char name[] = "i2c_omap";

#define I2C_RESOURCE_BUILDER(base, irq)			\
	{						\
		.start	= (base),			\
		.end	= (base) + OMAP_I2C_SIZE,	\
		.flags	= IORESOURCE_MEM,		\
	},						\
	{						\
		.start	= (irq),			\
		.flags	= IORESOURCE_IRQ,		\
	},

static struct resource i2c_resources[][2] = {
	{ I2C_RESOURCE_BUILDER(0, 0) },
#if	defined(CONFIG_ARCH_OMAP2PLUS)
	{ I2C_RESOURCE_BUILDER(OMAP2_I2C_BASE2, 0) },
#endif
#if	defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)
	{ I2C_RESOURCE_BUILDER(OMAP2_I2C_BASE3, 0) },
#endif
#if	defined(CONFIG_ARCH_OMAP4)
	{ I2C_RESOURCE_BUILDER(OMAP4_I2C_BASE4, 0) },
#endif
};

#define I2C_DEV_BUILDER(bus_id, res, data)		\
	{						\
		.id	= (bus_id),			\
		.name	= name,				\
		.num_resources	= ARRAY_SIZE(res),	\
		.resource	= (res),		\
		.dev		= {			\
			.platform_data	= (data),	\
		},					\
	}

static struct omap_i2c_bus_platform_data i2c_pdata[ARRAY_SIZE(i2c_resources)];
static struct platform_device omap_i2c_devices[] = {
	I2C_DEV_BUILDER(1, i2c_resources[0], &i2c_pdata[0]),
#if	defined(CONFIG_ARCH_OMAP2PLUS)
	I2C_DEV_BUILDER(2, i2c_resources[1], &i2c_pdata[1]),
#endif
#if	defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)
	I2C_DEV_BUILDER(3, i2c_resources[2], &i2c_pdata[2]),
#endif
#if	defined(CONFIG_ARCH_OMAP4)
	I2C_DEV_BUILDER(4, i2c_resources[3], &i2c_pdata[3]),
#endif
};

#define OMAP_I2C_CMDLINE_SETUP	(BIT(31))

static int __init omap_i2c_nr_ports(void)
{
	int ports = 0;

	if (cpu_class_is_omap1())
		ports = 1;
	else if (cpu_is_omap24xx())
		ports = 2;
	else if (cpu_is_omap34xx())
		ports = 3;
	else if (cpu_is_omap44xx())
		ports = 4;

	return ports;
}

/* Shared between omap2 and 3 */
static resource_size_t omap2_i2c_irq[3] __initdata = {
	INT_24XX_I2C1_IRQ,
	INT_24XX_I2C2_IRQ,
	INT_34XX_I2C3_IRQ,
};

static resource_size_t omap4_i2c_irq[4] __initdata = {
	OMAP44XX_IRQ_I2C1,
	OMAP44XX_IRQ_I2C2,
	OMAP44XX_IRQ_I2C3,
	OMAP44XX_IRQ_I2C4,
};

static inline int omap1_i2c_add_bus(struct platform_device *pdev, int bus_id)
{
	struct omap_i2c_bus_platform_data *pd;
	struct resource *res;

	pd = pdev->dev.platform_data;
	res = pdev->resource;
	res[0].start = OMAP1_I2C_BASE;
	res[0].end = res[0].start + OMAP_I2C_SIZE;
	res[1].start = INT_I2C;
	omap1_i2c_mux_pins(bus_id);

	return platform_device_register(pdev);
}

/*
 * XXX This function is a temporary compatibility wrapper - only
 * needed until the I2C driver can be converted to call
 * omap_pm_set_max_dev_wakeup_lat() and handle a return code.
 */
static void omap_pm_set_max_mpu_wakeup_lat_compat(struct device *dev, long t)
{
	omap_pm_set_max_mpu_wakeup_lat(dev, t);
}

static inline int omap2_i2c_add_bus(struct platform_device *pdev, int bus_id)
{
	struct resource *res;
	resource_size_t *irq;

	res = pdev->resource;

	if (!cpu_is_omap44xx())
		irq = omap2_i2c_irq;
	else
		irq = omap4_i2c_irq;

	if (bus_id == 1) {
		res[0].start = OMAP2_I2C_BASE1;
		res[0].end = res[0].start + OMAP_I2C_SIZE;
	}

	res[1].start = irq[bus_id - 1];
	omap2_i2c_mux_pins(bus_id);

	/*
	 * When waiting for completion of a i2c transfer, we need to
	 * set a wake up latency constraint for the MPU. This is to
	 * ensure quick enough wakeup from idle, when transfer
	 * completes.
	 */
	if (cpu_is_omap34xx()) {
		struct omap_i2c_bus_platform_data *pd;

		pd = pdev->dev.platform_data;
		pd->set_mpu_wkup_lat = omap_pm_set_max_mpu_wakeup_lat_compat;
	}

	return platform_device_register(pdev);
}

static int __init omap_i2c_add_bus(int bus_id)
{
	struct platform_device *pdev;

	pdev = &omap_i2c_devices[bus_id - 1];

	if (cpu_class_is_omap1())
		return omap1_i2c_add_bus(pdev, bus_id);
	else
		return omap2_i2c_add_bus(pdev, bus_id);
}

/**
 * omap_i2c_bus_setup - Process command line options for the I2C bus speed
 * @str: String of options
 *
 * This function allow to override the default I2C bus speed for given I2C
 * bus with a command line option.
 *
 * Format: i2c_bus=bus_id,clkrate (in kHz)
 *
 * Returns 1 on success, 0 otherwise.
 */
static int __init omap_i2c_bus_setup(char *str)
{
	int ports;
	int ints[3];

	ports = omap_i2c_nr_ports();
	get_options(str, 3, ints);
	if (ints[0] < 2 || ints[1] < 1 || ints[1] > ports)
		return 0;
	i2c_pdata[ints[1] - 1].clkrate = ints[2];
	i2c_pdata[ints[1] - 1].clkrate |= OMAP_I2C_CMDLINE_SETUP;

	return 1;
}
__setup("i2c_bus=", omap_i2c_bus_setup);

/*
 * Register busses defined in command line but that are not registered with
 * omap_register_i2c_bus from board initialization code.
 */
static int __init omap_register_i2c_bus_cmdline(void)
{
	int i, err = 0;

	for (i = 0; i < ARRAY_SIZE(i2c_pdata); i++)
		if (i2c_pdata[i].clkrate & OMAP_I2C_CMDLINE_SETUP) {
			i2c_pdata[i].clkrate &= ~OMAP_I2C_CMDLINE_SETUP;
			err = omap_i2c_add_bus(i + 1);
			if (err)
				goto out;
		}

out:
	return err;
}
subsys_initcall(omap_register_i2c_bus_cmdline);

/**
 * omap_register_i2c_bus - register I2C bus with device descriptors
 * @bus_id: bus id counting from number 1
 * @clkrate: clock rate of the bus in kHz
 * @info: pointer into I2C device descriptor table or NULL
 * @len: number of descriptors in the table
 *
 * Returns 0 on success or an error code.
 */
int __init omap_register_i2c_bus(int bus_id, u32 clkrate,
			  struct i2c_board_info const *info,
			  unsigned len)
{
	int err;

	BUG_ON(bus_id < 1 || bus_id > omap_i2c_nr_ports());

	if (info) {
		err = i2c_register_board_info(bus_id, info, len);
		if (err)
			return err;
	}

	if (!i2c_pdata[bus_id - 1].clkrate)
		i2c_pdata[bus_id - 1].clkrate = clkrate;

	i2c_pdata[bus_id - 1].clkrate &= ~OMAP_I2C_CMDLINE_SETUP;

	return omap_i2c_add_bus(bus_id);
}
Commit	Line	Data
85d05fb3 JN	1	/*
	2	* linux/arch/arm/plat-omap/i2c.c
	3	*
	4	* Helper module for board specific I2C bus registration
	5	*
	6	* Copyright (C) 2007 Nokia Corporation.
	7	*
ddf25dfe	8	* Contact: Jarkko Nikula <jhnikula@gmail.com>
85d05fb3 JN	9	*
	10	* This program is free software; you can redistribute it and/or
	11	* modify it under the terms of the GNU General Public License
	12	* version 2 as published by the Free Software Foundation.
	13	*
	14	* This program is distributed in the hope that it will be useful, but
	15	* WITHOUT ANY WARRANTY; without even the implied warranty of
	16	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	17	* General Public License for more details.
	18	*
	19	* You should have received a copy of the GNU General Public License
	20	* along with this program; if not, write to the Free Software
	21	* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
	22	* 02110-1301 USA
	23	*
	24	*/
	25
	26	#include <linux/kernel.h>
	27	#include <linux/platform_device.h>
	28	#include <linux/i2c.h>
20c9d2c4 KJ	29	#include <linux/i2c-omap.h>
20c9d2c4 KJ	30
80b02c17	31	#include <mach/irqs.h>
ce491cf8	32	#include <plat/mux.h>
9833eff3	33	#include <plat/i2c.h>
20c9d2c4	34	#include <plat/omap-pm.h>
85d05fb3 JN	35
	36	#define OMAP_I2C_SIZE 0x3f
	37	#define OMAP1_I2C_BASE 0xfffb3800
	38	#define OMAP2_I2C_BASE1 0x48070000
	39	#define OMAP2_I2C_BASE2 0x48072000
	40	#define OMAP2_I2C_BASE3 0x48060000
6daa642d	41	#define OMAP4_I2C_BASE4 0x48350000
85d05fb3 JN	42
	43	static const char name[] = "i2c_omap";
	44
	45	#define I2C_RESOURCE_BUILDER(base, irq) \
	46	{ \
	47	.start = (base), \
	48	.end = (base) + OMAP_I2C_SIZE, \
	49	.flags = IORESOURCE_MEM, \
	50	}, \
	51	{ \
	52	.start = (irq), \
	53	.flags = IORESOURCE_IRQ, \
	54	},
	55
	56	static struct resource i2c_resources[][2] = {
	57	{ I2C_RESOURCE_BUILDER(0, 0) },
6daa642d TL	58	#if defined(CONFIG_ARCH_OMAP2PLUS)
6daa642d TL	59	{ I2C_RESOURCE_BUILDER(OMAP2_I2C_BASE2, 0) },
85d05fb3	60	#endif
6daa642d TL	61	#if defined(CONFIG_ARCH_OMAP3) \|\| defined(CONFIG_ARCH_OMAP4)
	62	{ I2C_RESOURCE_BUILDER(OMAP2_I2C_BASE3, 0) },
	63	#endif
	64	#if defined(CONFIG_ARCH_OMAP4)
	65	{ I2C_RESOURCE_BUILDER(OMAP4_I2C_BASE4, 0) },
85d05fb3 JN	66	#endif
	67	};
	68
	69	#define I2C_DEV_BUILDER(bus_id, res, data) \
	70	{ \
	71	.id = (bus_id), \
	72	.name = name, \
	73	.num_resources = ARRAY_SIZE(res), \
	74	.resource = (res), \
	75	.dev = { \
	76	.platform_data = (data), \
	77	}, \
	78	}
	79
20c9d2c4	80	static struct omap_i2c_bus_platform_data i2c_pdata[ARRAY_SIZE(i2c_resources)];
85d05fb3	81	static struct platform_device omap_i2c_devices[] = {
20c9d2c4	82	I2C_DEV_BUILDER(1, i2c_resources[0], &i2c_pdata[0]),
6daa642d	83	#if defined(CONFIG_ARCH_OMAP2PLUS)
20c9d2c4	84	I2C_DEV_BUILDER(2, i2c_resources[1], &i2c_pdata[1]),
85d05fb3	85	#endif
6daa642d	86	#if defined(CONFIG_ARCH_OMAP3) \|\| defined(CONFIG_ARCH_OMAP4)
20c9d2c4	87	I2C_DEV_BUILDER(3, i2c_resources[2], &i2c_pdata[2]),
85d05fb3	88	#endif
6daa642d TL	89	#if defined(CONFIG_ARCH_OMAP4)
	90	I2C_DEV_BUILDER(4, i2c_resources[3], &i2c_pdata[3]),
	91	#endif
85d05fb3 JN	92	};
85d05fb3 JN	93
7954763b JN	94	#define OMAP_I2C_CMDLINE_SETUP (BIT(31))
7954763b JN	95
3a853fb9 JN	96	static int __init omap_i2c_nr_ports(void)
	97	{
	98	int ports = 0;
	99
	100	if (cpu_class_is_omap1())
	101	ports = 1;
	102	else if (cpu_is_omap24xx())
	103	ports = 2;
	104	else if (cpu_is_omap34xx())
	105	ports = 3;
6daa642d TL	106	else if (cpu_is_omap44xx())
6daa642d TL	107	ports = 4;
3a853fb9 JN	108
	109	return ports;
	110	}
	111
b32dd41e TL	112	/* Shared between omap2 and 3 */
	113	static resource_size_t omap2_i2c_irq[3] __initdata = {
	114	INT_24XX_I2C1_IRQ,
	115	INT_24XX_I2C2_IRQ,
	116	INT_34XX_I2C3_IRQ,
	117	};
	118
6daa642d TL	119	static resource_size_t omap4_i2c_irq[4] __initdata = {
	120	OMAP44XX_IRQ_I2C1,
	121	OMAP44XX_IRQ_I2C2,
	122	OMAP44XX_IRQ_I2C3,
	123	OMAP44XX_IRQ_I2C4,
	124	};
	125
b32dd41e	126	static inline int omap1_i2c_add_bus(struct platform_device *pdev, int bus_id)
7954763b	127	{
20c9d2c4	128	struct omap_i2c_bus_platform_data *pd;
7954763b	129	struct resource *res;
7954763b	130
20c9d2c4	131	pd = pdev->dev.platform_data;
b32dd41e TL	132	res = pdev->resource;
	133	res[0].start = OMAP1_I2C_BASE;
	134	res[0].end = res[0].start + OMAP_I2C_SIZE;
	135	res[1].start = INT_I2C;
	136	omap1_i2c_mux_pins(bus_id);
	137
	138	return platform_device_register(pdev);
	139	}
	140
564889c1 PW	141	/*
	142	* XXX This function is a temporary compatibility wrapper - only
	143	* needed until the I2C driver can be converted to call
	144	* omap_pm_set_max_dev_wakeup_lat() and handle a return code.
	145	*/
	146	static void omap_pm_set_max_mpu_wakeup_lat_compat(struct device *dev, long t)
	147	{
	148	omap_pm_set_max_mpu_wakeup_lat(dev, t);
	149	}
	150
b32dd41e TL	151	static inline int omap2_i2c_add_bus(struct platform_device *pdev, int bus_id)
	152	{
	153	struct resource *res;
	154	resource_size_t *irq;
	155
	156	res = pdev->resource;
	157
6daa642d TL	158	if (!cpu_is_omap44xx())
	159	irq = omap2_i2c_irq;
	160	else
	161	irq = omap4_i2c_irq;
b32dd41e	162
7954763b	163	if (bus_id == 1) {
b32dd41e TL	164	res[0].start = OMAP2_I2C_BASE1;
b32dd41e TL	165	res[0].end = res[0].start + OMAP_I2C_SIZE;
7954763b JN	166	}
7954763b JN	167
b32dd41e TL	168	res[1].start = irq[bus_id - 1];
b32dd41e TL	169	omap2_i2c_mux_pins(bus_id);
9833eff3	170
20c9d2c4 KJ	171	/*
	172	* When waiting for completion of a i2c transfer, we need to
	173	* set a wake up latency constraint for the MPU. This is to
	174	* ensure quick enough wakeup from idle, when transfer
	175	* completes.
	176	*/
b32dd41e TL	177	if (cpu_is_omap34xx()) {
	178	struct omap_i2c_bus_platform_data *pd;
	179
	180	pd = pdev->dev.platform_data;
564889c1	181	pd->set_mpu_wkup_lat = omap_pm_set_max_mpu_wakeup_lat_compat;
b32dd41e	182	}
20c9d2c4	183
7954763b JN	184	return platform_device_register(pdev);
	185	}
	186
b32dd41e TL	187	static int __init omap_i2c_add_bus(int bus_id)
	188	{
	189	struct platform_device *pdev;
	190
	191	pdev = &omap_i2c_devices[bus_id - 1];
	192
	193	if (cpu_class_is_omap1())
	194	return omap1_i2c_add_bus(pdev, bus_id);
	195	else
	196	return omap2_i2c_add_bus(pdev, bus_id);
	197	}
	198
3a853fb9 JN	199	/**
	200	* omap_i2c_bus_setup - Process command line options for the I2C bus speed
	201	* @str: String of options
	202	*
	203	* This function allow to override the default I2C bus speed for given I2C
	204	* bus with a command line option.
	205	*
	206	* Format: i2c_bus=bus_id,clkrate (in kHz)
	207	*
	208	* Returns 1 on success, 0 otherwise.
	209	*/
	210	static int __init omap_i2c_bus_setup(char *str)
	211	{
	212	int ports;
	213	int ints[3];
	214
	215	ports = omap_i2c_nr_ports();
	216	get_options(str, 3, ints);
	217	if (ints[0] < 2 \|\| ints[1] < 1 \|\| ints[1] > ports)
	218	return 0;
20c9d2c4 KJ	219	i2c_pdata[ints[1] - 1].clkrate = ints[2];
20c9d2c4 KJ	220	i2c_pdata[ints[1] - 1].clkrate \|= OMAP_I2C_CMDLINE_SETUP;
3a853fb9 JN	221
	222	return 1;
	223	}
	224	__setup("i2c_bus=", omap_i2c_bus_setup);
	225
7954763b JN	226	/*
	227	* Register busses defined in command line but that are not registered with
	228	* omap_register_i2c_bus from board initialization code.
	229	*/
	230	static int __init omap_register_i2c_bus_cmdline(void)
	231	{
	232	int i, err = 0;
	233
20c9d2c4 KJ	234	for (i = 0; i < ARRAY_SIZE(i2c_pdata); i++)
	235	if (i2c_pdata[i].clkrate & OMAP_I2C_CMDLINE_SETUP) {
	236	i2c_pdata[i].clkrate &= ~OMAP_I2C_CMDLINE_SETUP;
7954763b JN	237	err = omap_i2c_add_bus(i + 1);
	238	if (err)
	239	goto out;
	240	}
	241
	242	out:
	243	return err;
	244	}
	245	subsys_initcall(omap_register_i2c_bus_cmdline);
	246
d4c58bf4	247	/**
9833eff3	248	* omap_register_i2c_bus - register I2C bus with device descriptors
d4c58bf4 JN	249	* @bus_id: bus id counting from number 1
	250	* @clkrate: clock rate of the bus in kHz
	251	* @info: pointer into I2C device descriptor table or NULL
	252	* @len: number of descriptors in the table
	253	*
	254	* Returns 0 on success or an error code.
	255	*/
9833eff3	256	int __init omap_register_i2c_bus(int bus_id, u32 clkrate,
85d05fb3 JN	257	struct i2c_board_info const *info,
	258	unsigned len)
	259	{
3a853fb9	260	int err;
85d05fb3	261
3a853fb9	262	BUG_ON(bus_id < 1 \|\| bus_id > omap_i2c_nr_ports());
85d05fb3 JN	263
	264	if (info) {
	265	err = i2c_register_board_info(bus_id, info, len);
	266	if (err)
	267	return err;
	268	}
	269
20c9d2c4 KJ	270	if (!i2c_pdata[bus_id - 1].clkrate)
	271	i2c_pdata[bus_id - 1].clkrate = clkrate;
	272
	273	i2c_pdata[bus_id - 1].clkrate &= ~OMAP_I2C_CMDLINE_SETUP;
85d05fb3	274
7954763b	275	return omap_i2c_add_bus(bus_id);
85d05fb3	276	}