projects / linux-block.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
gpiolib: introduce set_debounce method
[linux-block.git] / arch / arm / plat-omap / gpio.c
CommitLineData
5e1c5ff4
TL		 1/*
2 * linux/arch/arm/plat-omap/gpio.c
3 *
4 * Support functions for OMAP GPIO
5 *
92105bb7 6 * Copyright (C) 2003-2005 Nokia Corporation
96de0e25 7 * Written by Juha Yrjölä <juha.yrjola@nokia.com>
5e1c5ff4 8 *
44169075
SS		 9 * Copyright (C) 2009 Texas Instruments
10 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
11 *
5e1c5ff4
TL		 12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License version 2 as
14 * published by the Free Software Foundation.
15 */
16
5e1c5ff4
TL		 17#include <linux/init.h>
18#include <linux/module.h>
5e1c5ff4 19#include <linux/interrupt.h>
92105bb7
TL		 20#include <linux/sysdev.h>
21#include <linux/err.h>
f8ce2547 22#include <linux/clk.h>
fced80c7 23#include <linux/io.h>
5e1c5ff4 24
a09e64fb 25#include <mach/hardware.h>
5e1c5ff4 26#include <asm/irq.h>
a09e64fb
RK		 27#include <mach/irqs.h>
28#include <mach/gpio.h>
5e1c5ff4 29#include <asm/mach/irq.h>
43ffcd9a 30#include <plat/powerdomain.h>
5e1c5ff4 31
5e1c5ff4
TL		 32/*
33 * OMAP1510 GPIO registers
34 */
9f7065da 35#define OMAP1510_GPIO_BASE 0xfffce000
5e1c5ff4
TL		 36#define OMAP1510_GPIO_DATA_INPUT 0x00
37#define OMAP1510_GPIO_DATA_OUTPUT 0x04
38#define OMAP1510_GPIO_DIR_CONTROL 0x08
39#define OMAP1510_GPIO_INT_CONTROL 0x0c
40#define OMAP1510_GPIO_INT_MASK 0x10
41#define OMAP1510_GPIO_INT_STATUS 0x14
42#define OMAP1510_GPIO_PIN_CONTROL 0x18
43
44#define OMAP1510_IH_GPIO_BASE 64
45
46/*
47 * OMAP1610 specific GPIO registers
48 */
9f7065da
TL		 49#define OMAP1610_GPIO1_BASE 0xfffbe400
50#define OMAP1610_GPIO2_BASE 0xfffbec00
51#define OMAP1610_GPIO3_BASE 0xfffbb400
52#define OMAP1610_GPIO4_BASE 0xfffbbc00
5e1c5ff4
TL		 53#define OMAP1610_GPIO_REVISION 0x0000
54#define OMAP1610_GPIO_SYSCONFIG 0x0010
55#define OMAP1610_GPIO_SYSSTATUS 0x0014
56#define OMAP1610_GPIO_IRQSTATUS1 0x0018
57#define OMAP1610_GPIO_IRQENABLE1 0x001c
92105bb7 58#define OMAP1610_GPIO_WAKEUPENABLE 0x0028
5e1c5ff4
TL		 59#define OMAP1610_GPIO_DATAIN 0x002c
60#define OMAP1610_GPIO_DATAOUT 0x0030
61#define OMAP1610_GPIO_DIRECTION 0x0034
62#define OMAP1610_GPIO_EDGE_CTRL1 0x0038
63#define OMAP1610_GPIO_EDGE_CTRL2 0x003c
64#define OMAP1610_GPIO_CLEAR_IRQENABLE1 0x009c
92105bb7 65#define OMAP1610_GPIO_CLEAR_WAKEUPENA 0x00a8
5e1c5ff4
TL		 66#define OMAP1610_GPIO_CLEAR_DATAOUT 0x00b0
67#define OMAP1610_GPIO_SET_IRQENABLE1 0x00dc
92105bb7 68#define OMAP1610_GPIO_SET_WAKEUPENA 0x00e8
5e1c5ff4
TL		 69#define OMAP1610_GPIO_SET_DATAOUT 0x00f0
70
71/*
7c006926 72 * OMAP7XX specific GPIO registers
5e1c5ff4 73 */
9f7065da
TL		 74#define OMAP7XX_GPIO1_BASE 0xfffbc000
75#define OMAP7XX_GPIO2_BASE 0xfffbc800
76#define OMAP7XX_GPIO3_BASE 0xfffbd000
77#define OMAP7XX_GPIO4_BASE 0xfffbd800
78#define OMAP7XX_GPIO5_BASE 0xfffbe000
79#define OMAP7XX_GPIO6_BASE 0xfffbe800
7c006926
AB		 80#define OMAP7XX_GPIO_DATA_INPUT 0x00
81#define OMAP7XX_GPIO_DATA_OUTPUT 0x04
82#define OMAP7XX_GPIO_DIR_CONTROL 0x08
83#define OMAP7XX_GPIO_INT_CONTROL 0x0c
84#define OMAP7XX_GPIO_INT_MASK 0x10
85#define OMAP7XX_GPIO_INT_STATUS 0x14
5e1c5ff4 86
9f7065da 87#define OMAP1_MPUIO_VBASE OMAP1_MPUIO_BASE
94113260 88
92105bb7
TL		 89/*
90 * omap24xx specific GPIO registers
91 */
9f7065da
TL		 92#define OMAP242X_GPIO1_BASE 0x48018000
93#define OMAP242X_GPIO2_BASE 0x4801a000
94#define OMAP242X_GPIO3_BASE 0x4801c000
95#define OMAP242X_GPIO4_BASE 0x4801e000
56a25641 96
9f7065da
TL		 97#define OMAP243X_GPIO1_BASE 0x4900C000
98#define OMAP243X_GPIO2_BASE 0x4900E000
99#define OMAP243X_GPIO3_BASE 0x49010000
100#define OMAP243X_GPIO4_BASE 0x49012000
101#define OMAP243X_GPIO5_BASE 0x480B6000
56a25641 102
92105bb7
TL		 103#define OMAP24XX_GPIO_REVISION 0x0000
104#define OMAP24XX_GPIO_SYSCONFIG 0x0010
105#define OMAP24XX_GPIO_SYSSTATUS 0x0014
106#define OMAP24XX_GPIO_IRQSTATUS1 0x0018
bee7930f
HD		 107#define OMAP24XX_GPIO_IRQSTATUS2 0x0028
108#define OMAP24XX_GPIO_IRQENABLE2 0x002c
92105bb7 109#define OMAP24XX_GPIO_IRQENABLE1 0x001c
723fdb78 110#define OMAP24XX_GPIO_WAKE_EN 0x0020
92105bb7
TL		 111#define OMAP24XX_GPIO_CTRL 0x0030
112#define OMAP24XX_GPIO_OE 0x0034
113#define OMAP24XX_GPIO_DATAIN 0x0038
114#define OMAP24XX_GPIO_DATAOUT 0x003c
115#define OMAP24XX_GPIO_LEVELDETECT0 0x0040
116#define OMAP24XX_GPIO_LEVELDETECT1 0x0044
117#define OMAP24XX_GPIO_RISINGDETECT 0x0048
118#define OMAP24XX_GPIO_FALLINGDETECT 0x004c
5eb3bb9c
KH		 119#define OMAP24XX_GPIO_DEBOUNCE_EN 0x0050
120#define OMAP24XX_GPIO_DEBOUNCE_VAL 0x0054
92105bb7
TL		 121#define OMAP24XX_GPIO_CLEARIRQENABLE1 0x0060
122#define OMAP24XX_GPIO_SETIRQENABLE1 0x0064
123#define OMAP24XX_GPIO_CLEARWKUENA 0x0080
124#define OMAP24XX_GPIO_SETWKUENA 0x0084
125#define OMAP24XX_GPIO_CLEARDATAOUT 0x0090
126#define OMAP24XX_GPIO_SETDATAOUT 0x0094
127
78a1a6d3
SR		 128#define OMAP4_GPIO_REVISION 0x0000
129#define OMAP4_GPIO_SYSCONFIG 0x0010
130#define OMAP4_GPIO_EOI 0x0020
131#define OMAP4_GPIO_IRQSTATUSRAW0 0x0024
132#define OMAP4_GPIO_IRQSTATUSRAW1 0x0028
133#define OMAP4_GPIO_IRQSTATUS0 0x002c
134#define OMAP4_GPIO_IRQSTATUS1 0x0030
135#define OMAP4_GPIO_IRQSTATUSSET0 0x0034
136#define OMAP4_GPIO_IRQSTATUSSET1 0x0038
137#define OMAP4_GPIO_IRQSTATUSCLR0 0x003c
138#define OMAP4_GPIO_IRQSTATUSCLR1 0x0040
139#define OMAP4_GPIO_IRQWAKEN0 0x0044
140#define OMAP4_GPIO_IRQWAKEN1 0x0048
9f096868
C		 141#define OMAP4_GPIO_SYSSTATUS 0x0114
142#define OMAP4_GPIO_IRQENABLE1 0x011c
143#define OMAP4_GPIO_WAKE_EN 0x0120
144#define OMAP4_GPIO_IRQSTATUS2 0x0128
145#define OMAP4_GPIO_IRQENABLE2 0x012c
78a1a6d3
SR		 146#define OMAP4_GPIO_CTRL 0x0130
147#define OMAP4_GPIO_OE 0x0134
148#define OMAP4_GPIO_DATAIN 0x0138
149#define OMAP4_GPIO_DATAOUT 0x013c
150#define OMAP4_GPIO_LEVELDETECT0 0x0140
151#define OMAP4_GPIO_LEVELDETECT1 0x0144
152#define OMAP4_GPIO_RISINGDETECT 0x0148
153#define OMAP4_GPIO_FALLINGDETECT 0x014c
154#define OMAP4_GPIO_DEBOUNCENABLE 0x0150
155#define OMAP4_GPIO_DEBOUNCINGTIME 0x0154
9f096868
C		 156#define OMAP4_GPIO_CLEARIRQENABLE1 0x0160
157#define OMAP4_GPIO_SETIRQENABLE1 0x0164
158#define OMAP4_GPIO_CLEARWKUENA 0x0180
159#define OMAP4_GPIO_SETWKUENA 0x0184
78a1a6d3
SR		 160#define OMAP4_GPIO_CLEARDATAOUT 0x0190
161#define OMAP4_GPIO_SETDATAOUT 0x0194
5492fb1a
SMK		 162/*
163 * omap34xx specific GPIO registers
164 */
165
9f7065da
TL		 166#define OMAP34XX_GPIO1_BASE 0x48310000
167#define OMAP34XX_GPIO2_BASE 0x49050000
168#define OMAP34XX_GPIO3_BASE 0x49052000
169#define OMAP34XX_GPIO4_BASE 0x49054000
170#define OMAP34XX_GPIO5_BASE 0x49056000
171#define OMAP34XX_GPIO6_BASE 0x49058000
5492fb1a 172
44169075
SS		 173/*
174 * OMAP44XX specific GPIO registers
175 */
9f7065da
TL		 176#define OMAP44XX_GPIO1_BASE 0x4a310000
177#define OMAP44XX_GPIO2_BASE 0x48055000
178#define OMAP44XX_GPIO3_BASE 0x48057000
179#define OMAP44XX_GPIO4_BASE 0x48059000
180#define OMAP44XX_GPIO5_BASE 0x4805B000
181#define OMAP44XX_GPIO6_BASE 0x4805D000
5492fb1a 182
5e1c5ff4 183struct gpio_bank {
9f7065da 184 unsigned long pbase;
92105bb7 185 void __iomem *base;
5e1c5ff4
TL		 186 u16 irq;
187 u16 virtual_irq_start;
92105bb7 188 int method;
140455fa 189#if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP2PLUS)
92105bb7
TL		 190 u32 suspend_wakeup;
191 u32 saved_wakeup;
3ac4fa99 192#endif
140455fa 193#ifdef CONFIG_ARCH_OMAP2PLUS
3ac4fa99
JY		 194 u32 non_wakeup_gpios;
195 u32 enabled_non_wakeup_gpios;
196
197 u32 saved_datain;
198 u32 saved_fallingdetect;
199 u32 saved_risingdetect;
200#endif
b144ff6f 201 u32 level_mask;
4318f36b 202 u32 toggle_mask;
5e1c5ff4 203 spinlock_t lock;
52e31344 204 struct gpio_chip chip;
89db9482 205 struct clk *dbck;
058af1ea 206 u32 mod_usage;
8865b9b6 207 u32 dbck_enable_mask;
5e1c5ff4
TL		 208};
209
210#define METHOD_MPUIO 0
211#define METHOD_GPIO_1510 1
212#define METHOD_GPIO_1610 2
7c006926 213#define METHOD_GPIO_7XX 3
56739a69 214#define METHOD_GPIO_24XX 5
3f1686a9 215#define METHOD_GPIO_44XX 6
5e1c5ff4 216
92105bb7 217#ifdef CONFIG_ARCH_OMAP16XX
5e1c5ff4 218static struct gpio_bank gpio_bank_1610[5] = {
9f7065da
TL		 219 { OMAP1_MPUIO_VBASE, NULL, INT_MPUIO, IH_MPUIO_BASE,
220 METHOD_MPUIO },
221 { OMAP1610_GPIO1_BASE, NULL, INT_GPIO_BANK1, IH_GPIO_BASE,
222 METHOD_GPIO_1610 },
223 { OMAP1610_GPIO2_BASE, NULL, INT_1610_GPIO_BANK2, IH_GPIO_BASE + 16,
224 METHOD_GPIO_1610 },
225 { OMAP1610_GPIO3_BASE, NULL, INT_1610_GPIO_BANK3, IH_GPIO_BASE + 32,
226 METHOD_GPIO_1610 },
227 { OMAP1610_GPIO4_BASE, NULL, INT_1610_GPIO_BANK4, IH_GPIO_BASE + 48,
228 METHOD_GPIO_1610 },
5e1c5ff4
TL		 229};
230#endif
231
1a8bfa1e 232#ifdef CONFIG_ARCH_OMAP15XX
5e1c5ff4 233static struct gpio_bank gpio_bank_1510[2] = {
9f7065da
TL		 234 { OMAP1_MPUIO_VBASE, NULL, INT_MPUIO, IH_MPUIO_BASE,
235 METHOD_MPUIO },
236 { OMAP1510_GPIO_BASE, NULL, INT_GPIO_BANK1, IH_GPIO_BASE,
237 METHOD_GPIO_1510 }
5e1c5ff4
TL		 238};
239#endif
240
b718aa81 241#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
7c006926 242static struct gpio_bank gpio_bank_7xx[7] = {
9f7065da
TL		 243 { OMAP1_MPUIO_VBASE, NULL, INT_7XX_MPUIO, IH_MPUIO_BASE,
244 METHOD_MPUIO },
245 { OMAP7XX_GPIO1_BASE, NULL, INT_7XX_GPIO_BANK1, IH_GPIO_BASE,
246 METHOD_GPIO_7XX },
247 { OMAP7XX_GPIO2_BASE, NULL, INT_7XX_GPIO_BANK2, IH_GPIO_BASE + 32,
248 METHOD_GPIO_7XX },
249 { OMAP7XX_GPIO3_BASE, NULL, INT_7XX_GPIO_BANK3, IH_GPIO_BASE + 64,
250 METHOD_GPIO_7XX },
251 { OMAP7XX_GPIO4_BASE, NULL, INT_7XX_GPIO_BANK4, IH_GPIO_BASE + 96,
252 METHOD_GPIO_7XX },
253 { OMAP7XX_GPIO5_BASE, NULL, INT_7XX_GPIO_BANK5, IH_GPIO_BASE + 128,
254 METHOD_GPIO_7XX },
255 { OMAP7XX_GPIO6_BASE, NULL, INT_7XX_GPIO_BANK6, IH_GPIO_BASE + 160,
256 METHOD_GPIO_7XX },
5e1c5ff4
TL		 257};
258#endif
259
088ef950 260#ifdef CONFIG_ARCH_OMAP2
56a25641
SMK		 261
262static struct gpio_bank gpio_bank_242x[4] = {
9f7065da
TL		 263 { OMAP242X_GPIO1_BASE, NULL, INT_24XX_GPIO_BANK1, IH_GPIO_BASE,
264 METHOD_GPIO_24XX },
265 { OMAP242X_GPIO2_BASE, NULL, INT_24XX_GPIO_BANK2, IH_GPIO_BASE + 32,
266 METHOD_GPIO_24XX },
267 { OMAP242X_GPIO3_BASE, NULL, INT_24XX_GPIO_BANK3, IH_GPIO_BASE + 64,
268 METHOD_GPIO_24XX },
269 { OMAP242X_GPIO4_BASE, NULL, INT_24XX_GPIO_BANK4, IH_GPIO_BASE + 96,
270 METHOD_GPIO_24XX },
92105bb7 271};
56a25641
SMK		 272
273static struct gpio_bank gpio_bank_243x[5] = {
9f7065da
TL		 274 { OMAP243X_GPIO1_BASE, NULL, INT_24XX_GPIO_BANK1, IH_GPIO_BASE,
275 METHOD_GPIO_24XX },
276 { OMAP243X_GPIO2_BASE, NULL, INT_24XX_GPIO_BANK2, IH_GPIO_BASE + 32,
277 METHOD_GPIO_24XX },
278 { OMAP243X_GPIO3_BASE, NULL, INT_24XX_GPIO_BANK3, IH_GPIO_BASE + 64,
279 METHOD_GPIO_24XX },
280 { OMAP243X_GPIO4_BASE, NULL, INT_24XX_GPIO_BANK4, IH_GPIO_BASE + 96,
281 METHOD_GPIO_24XX },
282 { OMAP243X_GPIO5_BASE, NULL, INT_24XX_GPIO_BANK5, IH_GPIO_BASE + 128,
283 METHOD_GPIO_24XX },
56a25641
SMK		 284};
285
92105bb7
TL		 286#endif
287
a8eb7ca0 288#ifdef CONFIG_ARCH_OMAP3
5492fb1a 289static struct gpio_bank gpio_bank_34xx[6] = {
9f7065da
TL		 290 { OMAP34XX_GPIO1_BASE, NULL, INT_34XX_GPIO_BANK1, IH_GPIO_BASE,
291 METHOD_GPIO_24XX },
292 { OMAP34XX_GPIO2_BASE, NULL, INT_34XX_GPIO_BANK2, IH_GPIO_BASE + 32,
293 METHOD_GPIO_24XX },
294 { OMAP34XX_GPIO3_BASE, NULL, INT_34XX_GPIO_BANK3, IH_GPIO_BASE + 64,
295 METHOD_GPIO_24XX },
296 { OMAP34XX_GPIO4_BASE, NULL, INT_34XX_GPIO_BANK4, IH_GPIO_BASE + 96,
297 METHOD_GPIO_24XX },
298 { OMAP34XX_GPIO5_BASE, NULL, INT_34XX_GPIO_BANK5, IH_GPIO_BASE + 128,
299 METHOD_GPIO_24XX },
300 { OMAP34XX_GPIO6_BASE, NULL, INT_34XX_GPIO_BANK6, IH_GPIO_BASE + 160,
301 METHOD_GPIO_24XX },
5492fb1a
SMK		 302};
303
40c670f0
RN		 304struct omap3_gpio_regs {
305 u32 sysconfig;
306 u32 irqenable1;
307 u32 irqenable2;
308 u32 wake_en;
309 u32 ctrl;
310 u32 oe;
311 u32 leveldetect0;
312 u32 leveldetect1;
313 u32 risingdetect;
314 u32 fallingdetect;
315 u32 dataout;
5492fb1a
SMK		 316};
317
40c670f0 318static struct omap3_gpio_regs gpio_context[OMAP34XX_NR_GPIOS];
5492fb1a
SMK		 319#endif
320
44169075
SS		 321#ifdef CONFIG_ARCH_OMAP4
322static struct gpio_bank gpio_bank_44xx[6] = {
5772ca7d 323 { OMAP44XX_GPIO1_BASE, NULL, OMAP44XX_IRQ_GPIO1, IH_GPIO_BASE,
3f1686a9 324 METHOD_GPIO_44XX },
5772ca7d 325 { OMAP44XX_GPIO2_BASE, NULL, OMAP44XX_IRQ_GPIO2, IH_GPIO_BASE + 32,
3f1686a9 326 METHOD_GPIO_44XX },
5772ca7d 327 { OMAP44XX_GPIO3_BASE, NULL, OMAP44XX_IRQ_GPIO3, IH_GPIO_BASE + 64,
3f1686a9 328 METHOD_GPIO_44XX },
5772ca7d 329 { OMAP44XX_GPIO4_BASE, NULL, OMAP44XX_IRQ_GPIO4, IH_GPIO_BASE + 96,
3f1686a9 330 METHOD_GPIO_44XX },
5772ca7d 331 { OMAP44XX_GPIO5_BASE, NULL, OMAP44XX_IRQ_GPIO5, IH_GPIO_BASE + 128,
3f1686a9 332 METHOD_GPIO_44XX },
5772ca7d 333 { OMAP44XX_GPIO6_BASE, NULL, OMAP44XX_IRQ_GPIO6, IH_GPIO_BASE + 160,
3f1686a9 334 METHOD_GPIO_44XX },
44169075
SS		 335};
336
337#endif
338
5e1c5ff4
TL		 339static struct gpio_bank *gpio_bank;
340static int gpio_bank_count;
341
342static inline struct gpio_bank *get_gpio_bank(int gpio)
343{
6e60e79a 344 if (cpu_is_omap15xx()) {
5e1c5ff4
TL		 345 if (OMAP_GPIO_IS_MPUIO(gpio))
346 return &gpio_bank[0];
347 return &gpio_bank[1];
348 }
5e1c5ff4
TL		 349 if (cpu_is_omap16xx()) {
350 if (OMAP_GPIO_IS_MPUIO(gpio))
351 return &gpio_bank[0];
352 return &gpio_bank[1 + (gpio >> 4)];
353 }
56739a69 354 if (cpu_is_omap7xx()) {
5e1c5ff4
TL		 355 if (OMAP_GPIO_IS_MPUIO(gpio))
356 return &gpio_bank[0];
357 return &gpio_bank[1 + (gpio >> 5)];
358 }
92105bb7
TL		 359 if (cpu_is_omap24xx())
360 return &gpio_bank[gpio >> 5];
44169075 361 if (cpu_is_omap34xx() || cpu_is_omap44xx())
5492fb1a 362 return &gpio_bank[gpio >> 5];
e031ab23
DB		 363 BUG();
364 return NULL;
5e1c5ff4
TL		 365}
366
367static inline int get_gpio_index(int gpio)
368{
56739a69 369 if (cpu_is_omap7xx())
5e1c5ff4 370 return gpio & 0x1f;
92105bb7
TL		 371 if (cpu_is_omap24xx())
372 return gpio & 0x1f;
44169075 373 if (cpu_is_omap34xx() || cpu_is_omap44xx())
5492fb1a 374 return gpio & 0x1f;
92105bb7 375 return gpio & 0x0f;
5e1c5ff4
TL		 376}
377
378static inline int gpio_valid(int gpio)
379{
380 if (gpio < 0)
381 return -1;
d11ac979 382 if (cpu_class_is_omap1() && OMAP_GPIO_IS_MPUIO(gpio)) {
193e68be 383 if (gpio >= OMAP_MAX_GPIO_LINES + 16)
5e1c5ff4
TL		 384 return -1;
385 return 0;
386 }
6e60e79a 387 if (cpu_is_omap15xx() && gpio < 16)
5e1c5ff4 388 return 0;
5e1c5ff4
TL		 389 if ((cpu_is_omap16xx()) && gpio < 64)
390 return 0;
56739a69 391 if (cpu_is_omap7xx() && gpio < 192)
5e1c5ff4 392 return 0;
92105bb7
TL		 393 if (cpu_is_omap24xx() && gpio < 128)
394 return 0;
44169075 395 if ((cpu_is_omap34xx() || cpu_is_omap44xx()) && gpio < 192)
5492fb1a 396 return 0;
5e1c5ff4
TL		 397 return -1;
398}
399
400static int check_gpio(int gpio)
401{
d32b20fc 402 if (unlikely(gpio_valid(gpio) < 0)) {
5e1c5ff4
TL		 403 printk(KERN_ERR "omap-gpio: invalid GPIO %d\n", gpio);
404 dump_stack();
405 return -1;
406 }
407 return 0;
408}
409
410static void _set_gpio_direction(struct gpio_bank *bank, int gpio, int is_input)
411{
92105bb7 412 void __iomem *reg = bank->base;
5e1c5ff4
TL		 413 u32 l;
414
415 switch (bank->method) {
e5c56ed3 416#ifdef CONFIG_ARCH_OMAP1
5e1c5ff4
TL		 417 case METHOD_MPUIO:
418 reg += OMAP_MPUIO_IO_CNTL;
419 break;
e5c56ed3
DB		 420#endif
421#ifdef CONFIG_ARCH_OMAP15XX
5e1c5ff4
TL		 422 case METHOD_GPIO_1510:
423 reg += OMAP1510_GPIO_DIR_CONTROL;
424 break;
e5c56ed3
DB		 425#endif
426#ifdef CONFIG_ARCH_OMAP16XX
5e1c5ff4
TL		 427 case METHOD_GPIO_1610:
428 reg += OMAP1610_GPIO_DIRECTION;
429 break;
e5c56ed3 430#endif
b718aa81 431#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
7c006926
AB		 432 case METHOD_GPIO_7XX:
433 reg += OMAP7XX_GPIO_DIR_CONTROL;
56739a69
ZM		 434 break;
435#endif
a8eb7ca0 436#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
92105bb7
TL		 437 case METHOD_GPIO_24XX:
438 reg += OMAP24XX_GPIO_OE;
439 break;
78a1a6d3
SR		 440#endif
441#if defined(CONFIG_ARCH_OMAP4)
3f1686a9 442 case METHOD_GPIO_44XX:
78a1a6d3
SR		 443 reg += OMAP4_GPIO_OE;
444 break;
e5c56ed3
DB		 445#endif
446 default:
447 WARN_ON(1);
448 return;
5e1c5ff4
TL		 449 }
450 l = __raw_readl(reg);
451 if (is_input)
452 l |= 1 << gpio;
453 else
454 l &= ~(1 << gpio);
455 __raw_writel(l, reg);
456}
457
5e1c5ff4
TL		 458static void _set_gpio_dataout(struct gpio_bank *bank, int gpio, int enable)
459{
92105bb7 460 void __iomem *reg = bank->base;
5e1c5ff4
TL		 461 u32 l = 0;
462
463 switch (bank->method) {
e5c56ed3 464#ifdef CONFIG_ARCH_OMAP1
5e1c5ff4
TL		 465 case METHOD_MPUIO:
466 reg += OMAP_MPUIO_OUTPUT;
467 l = __raw_readl(reg);
468 if (enable)
469 l |= 1 << gpio;
470 else
471 l &= ~(1 << gpio);
472 break;
e5c56ed3
DB		 473#endif
474#ifdef CONFIG_ARCH_OMAP15XX
5e1c5ff4
TL		 475 case METHOD_GPIO_1510:
476 reg += OMAP1510_GPIO_DATA_OUTPUT;
477 l = __raw_readl(reg);
478 if (enable)
479 l |= 1 << gpio;
480 else
481 l &= ~(1 << gpio);
482 break;
e5c56ed3
DB		 483#endif
484#ifdef CONFIG_ARCH_OMAP16XX
5e1c5ff4
TL		 485 case METHOD_GPIO_1610:
486 if (enable)
487 reg += OMAP1610_GPIO_SET_DATAOUT;
488 else
489 reg += OMAP1610_GPIO_CLEAR_DATAOUT;
490 l = 1 << gpio;
491 break;
e5c56ed3 492#endif
b718aa81 493#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
7c006926
AB		 494 case METHOD_GPIO_7XX:
495 reg += OMAP7XX_GPIO_DATA_OUTPUT;
56739a69
ZM		 496 l = __raw_readl(reg);
497 if (enable)
498 l |= 1 << gpio;
499 else
500 l &= ~(1 << gpio);
501 break;
502#endif
a8eb7ca0 503#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
92105bb7
TL		 504 case METHOD_GPIO_24XX:
505 if (enable)
506 reg += OMAP24XX_GPIO_SETDATAOUT;
507 else
508 reg += OMAP24XX_GPIO_CLEARDATAOUT;
509 l = 1 << gpio;
510 break;
78a1a6d3
SR		 511#endif
512#ifdef CONFIG_ARCH_OMAP4
3f1686a9 513 case METHOD_GPIO_44XX:
78a1a6d3
SR		 514 if (enable)
515 reg += OMAP4_GPIO_SETDATAOUT;
516 else
517 reg += OMAP4_GPIO_CLEARDATAOUT;
518 l = 1 << gpio;
519 break;
e5c56ed3 520#endif
5e1c5ff4 521 default:
e5c56ed3 522 WARN_ON(1);
5e1c5ff4
TL		 523 return;
524 }
525 __raw_writel(l, reg);
526}
527
b37c45b8 528static int _get_gpio_datain(struct gpio_bank *bank, int gpio)
5e1c5ff4 529{
92105bb7 530 void __iomem *reg;
5e1c5ff4
TL		 531
532 if (check_gpio(gpio) < 0)
e5c56ed3 533 return -EINVAL;
5e1c5ff4
TL		 534 reg = bank->base;
535 switch (bank->method) {
e5c56ed3 536#ifdef CONFIG_ARCH_OMAP1
5e1c5ff4
TL		 537 case METHOD_MPUIO:
538 reg += OMAP_MPUIO_INPUT_LATCH;
539 break;
e5c56ed3
DB		 540#endif
541#ifdef CONFIG_ARCH_OMAP15XX
5e1c5ff4
TL		 542 case METHOD_GPIO_1510:
543 reg += OMAP1510_GPIO_DATA_INPUT;
544 break;
e5c56ed3
DB		 545#endif
546#ifdef CONFIG_ARCH_OMAP16XX
5e1c5ff4
TL		 547 case METHOD_GPIO_1610:
548 reg += OMAP1610_GPIO_DATAIN;
549 break;
e5c56ed3 550#endif
b718aa81 551#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
7c006926
AB		 552 case METHOD_GPIO_7XX:
553 reg += OMAP7XX_GPIO_DATA_INPUT;
56739a69
ZM		 554 break;
555#endif
a8eb7ca0 556#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
92105bb7
TL		 557 case METHOD_GPIO_24XX:
558 reg += OMAP24XX_GPIO_DATAIN;
559 break;
78a1a6d3
SR		 560#endif
561#ifdef CONFIG_ARCH_OMAP4
3f1686a9 562 case METHOD_GPIO_44XX:
78a1a6d3
SR		 563 reg += OMAP4_GPIO_DATAIN;
564 break;
e5c56ed3 565#endif
5e1c5ff4 566 default:
e5c56ed3 567 return -EINVAL;
5e1c5ff4 568 }
92105bb7
TL		 569 return (__raw_readl(reg)
570 & (1 << get_gpio_index(gpio))) != 0;
5e1c5ff4
TL		 571}
572
b37c45b8
RQ		 573static int _get_gpio_dataout(struct gpio_bank *bank, int gpio)
574{
575 void __iomem *reg;
576
577 if (check_gpio(gpio) < 0)
578 return -EINVAL;
579 reg = bank->base;
580
581 switch (bank->method) {
582#ifdef CONFIG_ARCH_OMAP1
583 case METHOD_MPUIO:
584 reg += OMAP_MPUIO_OUTPUT;
585 break;
586#endif
587#ifdef CONFIG_ARCH_OMAP15XX
588 case METHOD_GPIO_1510:
589 reg += OMAP1510_GPIO_DATA_OUTPUT;
590 break;
591#endif
592#ifdef CONFIG_ARCH_OMAP16XX
593 case METHOD_GPIO_1610:
594 reg += OMAP1610_GPIO_DATAOUT;
595 break;
596#endif
b718aa81 597#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
7c006926
AB		 598 case METHOD_GPIO_7XX:
599 reg += OMAP7XX_GPIO_DATA_OUTPUT;
b37c45b8
RQ		 600 break;
601#endif
9f096868 602#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
b37c45b8
RQ		 603 case METHOD_GPIO_24XX:
604 reg += OMAP24XX_GPIO_DATAOUT;
605 break;
9f096868
C		 606#endif
607#ifdef CONFIG_ARCH_OMAP4
608 case METHOD_GPIO_44XX:
609 reg += OMAP4_GPIO_DATAOUT;
610 break;
b37c45b8
RQ		 611#endif
612 default:
613 return -EINVAL;
614 }
615
616 return (__raw_readl(reg) & (1 << get_gpio_index(gpio))) != 0;
617}
618
92105bb7
TL		 619#define MOD_REG_BIT(reg, bit_mask, set) \
620do { \
621 int l = __raw_readl(base + reg); \
622 if (set) l |= bit_mask; \
623 else l &= ~bit_mask; \
624 __raw_writel(l, base + reg); \
625} while(0)
626
5eb3bb9c
KH		 627void omap_set_gpio_debounce(int gpio, int enable)
628{
629 struct gpio_bank *bank;
630 void __iomem *reg;
e031ab23 631 unsigned long flags;
5eb3bb9c
KH		 632 u32 val, l = 1 << get_gpio_index(gpio);
633
634 if (cpu_class_is_omap1())
635 return;
636
637 bank = get_gpio_bank(gpio);
638 reg = bank->base;
3f1686a9
TL		 639
640 if (cpu_is_omap44xx())
641 reg += OMAP4_GPIO_DEBOUNCENABLE;
642 else
643 reg += OMAP24XX_GPIO_DEBOUNCE_EN;
644
058af1ea
C		 645 if (!(bank->mod_usage & l)) {
646 printk(KERN_ERR "GPIO %d not requested\n", gpio);
647 return;
648 }
e031ab23
DB		 649
650 spin_lock_irqsave(&bank->lock, flags);
5eb3bb9c
KH		 651 val = __raw_readl(reg);
652
89db9482 653 if (enable && !(val & l))
5eb3bb9c 654 val |= l;
e031ab23 655 else if (!enable && (val & l))
5eb3bb9c 656 val &= ~l;
89db9482 657 else
e031ab23 658 goto done;
89db9482 659
44169075 660 if (cpu_is_omap34xx() || cpu_is_omap44xx()) {
8865b9b6 661 bank->dbck_enable_mask = val;
e031ab23
DB		 662 if (enable)
663 clk_enable(bank->dbck);
664 else
665 clk_disable(bank->dbck);
666 }
5eb3bb9c
KH		 667
668 __raw_writel(val, reg);
e031ab23
DB		 669done:
670 spin_unlock_irqrestore(&bank->lock, flags);
5eb3bb9c
KH		 671}
672EXPORT_SYMBOL(omap_set_gpio_debounce);
673
674void omap_set_gpio_debounce_time(int gpio, int enc_time)
675{
676 struct gpio_bank *bank;
677 void __iomem *reg;
678
679 if (cpu_class_is_omap1())
680 return;
681
682 bank = get_gpio_bank(gpio);
683 reg = bank->base;
684
058af1ea
C		 685 if (!bank->mod_usage) {
686 printk(KERN_ERR "GPIO not requested\n");
687 return;
688 }
689
5eb3bb9c 690 enc_time &= 0xff;
3f1686a9
TL		 691
692 if (cpu_is_omap44xx())
693 reg += OMAP4_GPIO_DEBOUNCINGTIME;
694 else
695 reg += OMAP24XX_GPIO_DEBOUNCE_VAL;
696
5eb3bb9c
KH		 697 __raw_writel(enc_time, reg);
698}
699EXPORT_SYMBOL(omap_set_gpio_debounce_time);
700
140455fa 701#ifdef CONFIG_ARCH_OMAP2PLUS
5eb3bb9c
KH		 702static inline void set_24xx_gpio_triggering(struct gpio_bank *bank, int gpio,
703 int trigger)
5e1c5ff4 704{
3ac4fa99 705 void __iomem *base = bank->base;
92105bb7 706 u32 gpio_bit = 1 << gpio;
78a1a6d3 707 u32 val;
92105bb7 708
78a1a6d3
SR		 709 if (cpu_is_omap44xx()) {
710 MOD_REG_BIT(OMAP4_GPIO_LEVELDETECT0, gpio_bit,
711 trigger & IRQ_TYPE_LEVEL_LOW);
712 MOD_REG_BIT(OMAP4_GPIO_LEVELDETECT1, gpio_bit,
713 trigger & IRQ_TYPE_LEVEL_HIGH);
714 MOD_REG_BIT(OMAP4_GPIO_RISINGDETECT, gpio_bit,
715 trigger & IRQ_TYPE_EDGE_RISING);
716 MOD_REG_BIT(OMAP4_GPIO_FALLINGDETECT, gpio_bit,
717 trigger & IRQ_TYPE_EDGE_FALLING);
718 } else {
719 MOD_REG_BIT(OMAP24XX_GPIO_LEVELDETECT0, gpio_bit,
720 trigger & IRQ_TYPE_LEVEL_LOW);
721 MOD_REG_BIT(OMAP24XX_GPIO_LEVELDETECT1, gpio_bit,
722 trigger & IRQ_TYPE_LEVEL_HIGH);
723 MOD_REG_BIT(OMAP24XX_GPIO_RISINGDETECT, gpio_bit,
724 trigger & IRQ_TYPE_EDGE_RISING);
725 MOD_REG_BIT(OMAP24XX_GPIO_FALLINGDETECT, gpio_bit,
726 trigger & IRQ_TYPE_EDGE_FALLING);
727 }
3ac4fa99 728 if (likely(!(bank->non_wakeup_gpios & gpio_bit))) {
78a1a6d3
SR		 729 if (cpu_is_omap44xx()) {
730 if (trigger != 0)
731 __raw_writel(1 << gpio, bank->base+
732 OMAP4_GPIO_IRQWAKEN0);
733 else {
734 val = __raw_readl(bank->base +
735 OMAP4_GPIO_IRQWAKEN0);
736 __raw_writel(val & (~(1 << gpio)), bank->base +
737 OMAP4_GPIO_IRQWAKEN0);
738 }
739 } else {
699117a6
CW		 740 /*
741 * GPIO wakeup request can only be generated on edge
742 * transitions
743 */
744 if (trigger & IRQ_TYPE_EDGE_BOTH)
78a1a6d3 745 __raw_writel(1 << gpio, bank->base
5eb3bb9c 746 + OMAP24XX_GPIO_SETWKUENA);
78a1a6d3
SR		 747 else
748 __raw_writel(1 << gpio, bank->base
5eb3bb9c 749 + OMAP24XX_GPIO_CLEARWKUENA);
78a1a6d3 750 }
a118b5f3
TK		 751 }
752 /* This part needs to be executed always for OMAP34xx */
753 if (cpu_is_omap34xx() || (bank->non_wakeup_gpios & gpio_bit)) {
699117a6
CW		 754 /*
755 * Log the edge gpio and manually trigger the IRQ
756 * after resume if the input level changes
757 * to avoid irq lost during PER RET/OFF mode
758 * Applies for omap2 non-wakeup gpio and all omap3 gpios
759 */
760 if (trigger & IRQ_TYPE_EDGE_BOTH)
3ac4fa99
JY		 761 bank->enabled_non_wakeup_gpios |= gpio_bit;
762 else
763 bank->enabled_non_wakeup_gpios &= ~gpio_bit;
764 }
5eb3bb9c 765
78a1a6d3
SR		 766 if (cpu_is_omap44xx()) {
767 bank->level_mask =
768 __raw_readl(bank->base + OMAP4_GPIO_LEVELDETECT0) |
769 __raw_readl(bank->base + OMAP4_GPIO_LEVELDETECT1);
770 } else {
771 bank->level_mask =
772 __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT0) |
773 __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT1);
774 }
92105bb7 775}
3ac4fa99 776#endif
92105bb7 777
9198bcd3 778#ifdef CONFIG_ARCH_OMAP1
4318f36b
CM		 779/*
780 * This only applies to chips that can't do both rising and falling edge
781 * detection at once. For all other chips, this function is a noop.
782 */
783static void _toggle_gpio_edge_triggering(struct gpio_bank *bank, int gpio)
784{
785 void __iomem *reg = bank->base;
786 u32 l = 0;
787
788 switch (bank->method) {
4318f36b
CM		 789 case METHOD_MPUIO:
790 reg += OMAP_MPUIO_GPIO_INT_EDGE;
791 break;
4318f36b
CM		 792#ifdef CONFIG_ARCH_OMAP15XX
793 case METHOD_GPIO_1510:
794 reg += OMAP1510_GPIO_INT_CONTROL;
795 break;
796#endif
797#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
798 case METHOD_GPIO_7XX:
799 reg += OMAP7XX_GPIO_INT_CONTROL;
800 break;
801#endif
802 default:
803 return;
804 }
805
806 l = __raw_readl(reg);
807 if ((l >> gpio) & 1)
808 l &= ~(1 << gpio);
809 else
810 l |= 1 << gpio;
811
812 __raw_writel(l, reg);
813}
9198bcd3 814#endif
4318f36b 815
92105bb7
TL		 816static int _set_gpio_triggering(struct gpio_bank *bank, int gpio, int trigger)
817{
818 void __iomem *reg = bank->base;
819 u32 l = 0;
5e1c5ff4
TL		 820
821 switch (bank->method) {
e5c56ed3 822#ifdef CONFIG_ARCH_OMAP1
5e1c5ff4
TL		 823 case METHOD_MPUIO:
824 reg += OMAP_MPUIO_GPIO_INT_EDGE;
825 l = __raw_readl(reg);
29501577 826 if ((trigger & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH)
4318f36b 827 bank->toggle_mask |= 1 << gpio;
6cab4860 828 if (trigger & IRQ_TYPE_EDGE_RISING)
5e1c5ff4 829 l |= 1 << gpio;
6cab4860 830 else if (trigger & IRQ_TYPE_EDGE_FALLING)
5e1c5ff4 831 l &= ~(1 << gpio);
92105bb7
TL		 832 else
833 goto bad;
5e1c5ff4 834 break;
e5c56ed3
DB		 835#endif
836#ifdef CONFIG_ARCH_OMAP15XX
5e1c5ff4
TL		 837 case METHOD_GPIO_1510:
838 reg += OMAP1510_GPIO_INT_CONTROL;
839 l = __raw_readl(reg);
29501577 840 if ((trigger & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH)
4318f36b 841 bank->toggle_mask |= 1 << gpio;
6cab4860 842 if (trigger & IRQ_TYPE_EDGE_RISING)
5e1c5ff4 843 l |= 1 << gpio;
6cab4860 844 else if (trigger & IRQ_TYPE_EDGE_FALLING)
5e1c5ff4 845 l &= ~(1 << gpio);
92105bb7
TL		 846 else
847 goto bad;
5e1c5ff4 848 break;
e5c56ed3 849#endif
3ac4fa99 850#ifdef CONFIG_ARCH_OMAP16XX
5e1c5ff4 851 case METHOD_GPIO_1610:
5e1c5ff4
TL		 852 if (gpio & 0x08)
853 reg += OMAP1610_GPIO_EDGE_CTRL2;
854 else
855 reg += OMAP1610_GPIO_EDGE_CTRL1;
856 gpio &= 0x07;
857 l = __raw_readl(reg);
858 l &= ~(3 << (gpio << 1));
6cab4860 859 if (trigger & IRQ_TYPE_EDGE_RISING)
6e60e79a 860 l |= 2 << (gpio << 1);
6cab4860 861 if (trigger & IRQ_TYPE_EDGE_FALLING)
6e60e79a 862 l |= 1 << (gpio << 1);
3ac4fa99
JY		 863 if (trigger)
864 /* Enable wake-up during idle for dynamic tick */
865 __raw_writel(1 << gpio, bank->base + OMAP1610_GPIO_SET_WAKEUPENA);
866 else
867 __raw_writel(1 << gpio, bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA);
5e1c5ff4 868 break;
3ac4fa99 869#endif
b718aa81 870#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
7c006926
AB		 871 case METHOD_GPIO_7XX:
872 reg += OMAP7XX_GPIO_INT_CONTROL;
56739a69 873 l = __raw_readl(reg);
29501577 874 if ((trigger & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH)
4318f36b 875 bank->toggle_mask |= 1 << gpio;
56739a69
ZM		 876 if (trigger & IRQ_TYPE_EDGE_RISING)
877 l |= 1 << gpio;
878 else if (trigger & IRQ_TYPE_EDGE_FALLING)
879 l &= ~(1 << gpio);
880 else
881 goto bad;
882 break;
883#endif
140455fa 884#ifdef CONFIG_ARCH_OMAP2PLUS
92105bb7 885 case METHOD_GPIO_24XX:
3f1686a9 886 case METHOD_GPIO_44XX:
3ac4fa99 887 set_24xx_gpio_triggering(bank, gpio, trigger);
5e1c5ff4 888 break;
3ac4fa99 889#endif
5e1c5ff4 890 default:
92105bb7 891 goto bad;
5e1c5ff4 892 }
92105bb7
TL		 893 __raw_writel(l, reg);
894 return 0;
895bad:
896 return -EINVAL;
5e1c5ff4
TL		 897}
898
92105bb7 899static int gpio_irq_type(unsigned irq, unsigned type)
5e1c5ff4
TL		 900{
901 struct gpio_bank *bank;
92105bb7
TL		 902 unsigned gpio;
903 int retval;
a6472533 904 unsigned long flags;
92105bb7 905
5492fb1a 906 if (!cpu_class_is_omap2() && irq > IH_MPUIO_BASE)
92105bb7
TL		 907 gpio = OMAP_MPUIO(irq - IH_MPUIO_BASE);
908 else
909 gpio = irq - IH_GPIO_BASE;
5e1c5ff4
TL		 910
911 if (check_gpio(gpio) < 0)
92105bb7
TL		 912 return -EINVAL;
913
e5c56ed3 914 if (type & ~IRQ_TYPE_SENSE_MASK)
6e60e79a 915 return -EINVAL;
e5c56ed3
DB		 916
917 /* OMAP1 allows only only edge triggering */
5492fb1a 918 if (!cpu_class_is_omap2()
e5c56ed3 919 && (type & (IRQ_TYPE_LEVEL_LOW|IRQ_TYPE_LEVEL_HIGH)))
92105bb7
TL		 920 return -EINVAL;
921
58781016 922 bank = get_irq_chip_data(irq);
a6472533 923 spin_lock_irqsave(&bank->lock, flags);
92105bb7 924 retval = _set_gpio_triggering(bank, get_gpio_index(gpio), type);
b9772a22
DB		 925 if (retval == 0) {
926 irq_desc[irq].status &= ~IRQ_TYPE_SENSE_MASK;
927 irq_desc[irq].status |= type;
928 }
a6472533 929 spin_unlock_irqrestore(&bank->lock, flags);
672e302e
KH		 930
931 if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
932 __set_irq_handler_unlocked(irq, handle_level_irq);
933 else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
934 __set_irq_handler_unlocked(irq, handle_edge_irq);
935
92105bb7 936 return retval;
5e1c5ff4
TL		 937}
938
939static void _clear_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
940{
92105bb7 941 void __iomem *reg = bank->base;
5e1c5ff4
TL		 942
943 switch (bank->method) {
e5c56ed3 944#ifdef CONFIG_ARCH_OMAP1
5e1c5ff4
TL		 945 case METHOD_MPUIO:
946 /* MPUIO irqstatus is reset by reading the status register,
947 * so do nothing here */
948 return;
e5c56ed3
DB		 949#endif
950#ifdef CONFIG_ARCH_OMAP15XX
5e1c5ff4
TL		 951 case METHOD_GPIO_1510:
952 reg += OMAP1510_GPIO_INT_STATUS;
953 break;
e5c56ed3
DB		 954#endif
955#ifdef CONFIG_ARCH_OMAP16XX
5e1c5ff4
TL		 956 case METHOD_GPIO_1610:
957 reg += OMAP1610_GPIO_IRQSTATUS1;
958 break;
e5c56ed3 959#endif
b718aa81 960#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
7c006926
AB		 961 case METHOD_GPIO_7XX:
962 reg += OMAP7XX_GPIO_INT_STATUS;
56739a69
ZM		 963 break;
964#endif
a8eb7ca0 965#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
92105bb7
TL		 966 case METHOD_GPIO_24XX:
967 reg += OMAP24XX_GPIO_IRQSTATUS1;
968 break;
78a1a6d3
SR		 969#endif
970#if defined(CONFIG_ARCH_OMAP4)
3f1686a9 971 case METHOD_GPIO_44XX:
78a1a6d3
SR		 972 reg += OMAP4_GPIO_IRQSTATUS0;
973 break;
e5c56ed3 974#endif
5e1c5ff4 975 default:
e5c56ed3 976 WARN_ON(1);
5e1c5ff4
TL		 977 return;
978 }
979 __raw_writel(gpio_mask, reg);
bee7930f
HD		 980
981 /* Workaround for clearing DSP GPIO interrupts to allow retention */
3f1686a9
TL		 982 if (cpu_is_omap24xx() || cpu_is_omap34xx())
983 reg = bank->base + OMAP24XX_GPIO_IRQSTATUS2;
984 else if (cpu_is_omap44xx())
985 reg = bank->base + OMAP4_GPIO_IRQSTATUS1;
986
78a1a6d3 987 if (cpu_is_omap24xx() || cpu_is_omap34xx() || cpu_is_omap44xx()) {
bedfd154
RQ		 988 __raw_writel(gpio_mask, reg);
989
990 /* Flush posted write for the irq status to avoid spurious interrupts */
991 __raw_readl(reg);
78a1a6d3 992 }
5e1c5ff4
TL		 993}
994
995static inline void _clear_gpio_irqstatus(struct gpio_bank *bank, int gpio)
996{
997 _clear_gpio_irqbank(bank, 1 << get_gpio_index(gpio));
998}
999
ea6dedd7
ID		 1000static u32 _get_gpio_irqbank_mask(struct gpio_bank *bank)
1001{
1002 void __iomem *reg = bank->base;
99c47707
ID		 1003 int inv = 0;
1004 u32 l;
1005 u32 mask;
ea6dedd7
ID		 1006
1007 switch (bank->method) {
e5c56ed3 1008#ifdef CONFIG_ARCH_OMAP1
ea6dedd7
ID		 1009 case METHOD_MPUIO:
1010 reg += OMAP_MPUIO_GPIO_MASKIT;
99c47707
ID		 1011 mask = 0xffff;
1012 inv = 1;
ea6dedd7 1013 break;
e5c56ed3
DB		 1014#endif
1015#ifdef CONFIG_ARCH_OMAP15XX
ea6dedd7
ID		 1016 case METHOD_GPIO_1510:
1017 reg += OMAP1510_GPIO_INT_MASK;
99c47707
ID		 1018 mask = 0xffff;
1019 inv = 1;
ea6dedd7 1020 break;
e5c56ed3
DB		 1021#endif
1022#ifdef CONFIG_ARCH_OMAP16XX
ea6dedd7
ID		 1023 case METHOD_GPIO_1610:
1024 reg += OMAP1610_GPIO_IRQENABLE1;
99c47707 1025 mask = 0xffff;
ea6dedd7 1026 break;
e5c56ed3 1027#endif
b718aa81 1028#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
7c006926
AB		 1029 case METHOD_GPIO_7XX:
1030 reg += OMAP7XX_GPIO_INT_MASK;
56739a69
ZM		 1031 mask = 0xffffffff;
1032 inv = 1;
1033 break;
1034#endif
a8eb7ca0 1035#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
ea6dedd7
ID		 1036 case METHOD_GPIO_24XX:
1037 reg += OMAP24XX_GPIO_IRQENABLE1;
99c47707 1038 mask = 0xffffffff;
ea6dedd7 1039 break;
78a1a6d3
SR		 1040#endif
1041#if defined(CONFIG_ARCH_OMAP4)
3f1686a9 1042 case METHOD_GPIO_44XX:
78a1a6d3
SR		 1043 reg += OMAP4_GPIO_IRQSTATUSSET0;
1044 mask = 0xffffffff;
1045 break;
e5c56ed3 1046#endif
ea6dedd7 1047 default:
e5c56ed3 1048 WARN_ON(1);
ea6dedd7
ID		 1049 return 0;
1050 }
1051
99c47707
ID		 1052 l = __raw_readl(reg);
1053 if (inv)
1054 l = ~l;
1055 l &= mask;
1056 return l;
ea6dedd7
ID		 1057}
1058
5e1c5ff4
TL		 1059static void _enable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask, int enable)
1060{
92105bb7 1061 void __iomem *reg = bank->base;
5e1c5ff4
TL		 1062 u32 l;
1063
1064 switch (bank->method) {
e5c56ed3 1065#ifdef CONFIG_ARCH_OMAP1
5e1c5ff4
TL		 1066 case METHOD_MPUIO:
1067 reg += OMAP_MPUIO_GPIO_MASKIT;
1068 l = __raw_readl(reg);
1069 if (enable)
1070 l &= ~(gpio_mask);
1071 else
1072 l |= gpio_mask;
1073 break;
e5c56ed3
DB		 1074#endif
1075#ifdef CONFIG_ARCH_OMAP15XX
5e1c5ff4
TL		 1076 case METHOD_GPIO_1510:
1077 reg += OMAP1510_GPIO_INT_MASK;
1078 l = __raw_readl(reg);
1079 if (enable)
1080 l &= ~(gpio_mask);
1081 else
1082 l |= gpio_mask;
1083 break;
e5c56ed3
DB		 1084#endif
1085#ifdef CONFIG_ARCH_OMAP16XX
5e1c5ff4
TL		 1086 case METHOD_GPIO_1610:
1087 if (enable)
1088 reg += OMAP1610_GPIO_SET_IRQENABLE1;
1089 else
1090 reg += OMAP1610_GPIO_CLEAR_IRQENABLE1;
1091 l = gpio_mask;
1092 break;
e5c56ed3 1093#endif
b718aa81 1094#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
7c006926
AB		 1095 case METHOD_GPIO_7XX:
1096 reg += OMAP7XX_GPIO_INT_MASK;
56739a69
ZM		 1097 l = __raw_readl(reg);
1098 if (enable)
1099 l &= ~(gpio_mask);
1100 else
1101 l |= gpio_mask;
1102 break;
1103#endif
a8eb7ca0 1104#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
92105bb7
TL		 1105 case METHOD_GPIO_24XX:
1106 if (enable)
1107 reg += OMAP24XX_GPIO_SETIRQENABLE1;
1108 else
1109 reg += OMAP24XX_GPIO_CLEARIRQENABLE1;
1110 l = gpio_mask;
1111 break;
78a1a6d3
SR		 1112#endif
1113#ifdef CONFIG_ARCH_OMAP4
3f1686a9 1114 case METHOD_GPIO_44XX:
78a1a6d3
SR		 1115 if (enable)
1116 reg += OMAP4_GPIO_IRQSTATUSSET0;
1117 else
1118 reg += OMAP4_GPIO_IRQSTATUSCLR0;
1119 l = gpio_mask;
1120 break;
e5c56ed3 1121#endif
5e1c5ff4 1122 default:
e5c56ed3 1123 WARN_ON(1);
5e1c5ff4
TL		 1124 return;
1125 }
1126 __raw_writel(l, reg);
1127}
1128
1129static inline void _set_gpio_irqenable(struct gpio_bank *bank, int gpio, int enable)
1130{
1131 _enable_gpio_irqbank(bank, 1 << get_gpio_index(gpio), enable);
1132}
1133
92105bb7
TL		 1134/*
1135 * Note that ENAWAKEUP needs to be enabled in GPIO_SYSCONFIG register.
1136 * 1510 does not seem to have a wake-up register. If JTAG is connected
1137 * to the target, system will wake up always on GPIO events. While
1138 * system is running all registered GPIO interrupts need to have wake-up
1139 * enabled. When system is suspended, only selected GPIO interrupts need
1140 * to have wake-up enabled.
1141 */
1142static int _set_gpio_wakeup(struct gpio_bank *bank, int gpio, int enable)
1143{
4cc6420c 1144 unsigned long uninitialized_var(flags);
a6472533 1145
92105bb7 1146 switch (bank->method) {
3ac4fa99 1147#ifdef CONFIG_ARCH_OMAP16XX
11a78b79 1148 case METHOD_MPUIO:
92105bb7 1149 case METHOD_GPIO_1610:
a6472533 1150 spin_lock_irqsave(&bank->lock, flags);
b3bb4f68 1151 if (enable)
92105bb7 1152 bank->suspend_wakeup |= (1 << gpio);
b3bb4f68 1153 else
92105bb7 1154 bank->suspend_wakeup &= ~(1 << gpio);
a6472533 1155 spin_unlock_irqrestore(&bank->lock, flags);
92105bb7 1156 return 0;
3ac4fa99 1157#endif
140455fa 1158#ifdef CONFIG_ARCH_OMAP2PLUS
3ac4fa99 1159 case METHOD_GPIO_24XX:
3f1686a9 1160 case METHOD_GPIO_44XX:
11a78b79
DB		 1161 if (bank->non_wakeup_gpios & (1 << gpio)) {
1162 printk(KERN_ERR "Unable to modify wakeup on "
1163 "non-wakeup GPIO%d\n",
1164 (bank - gpio_bank) * 32 + gpio);
1165 return -EINVAL;
1166 }
a6472533 1167 spin_lock_irqsave(&bank->lock, flags);
b3bb4f68 1168 if (enable)
3ac4fa99 1169 bank->suspend_wakeup |= (1 << gpio);
b3bb4f68 1170 else
3ac4fa99 1171 bank->suspend_wakeup &= ~(1 << gpio);
a6472533 1172 spin_unlock_irqrestore(&bank->lock, flags);
3ac4fa99
JY		 1173 return 0;
1174#endif
92105bb7
TL		 1175 default:
1176 printk(KERN_ERR "Can't enable GPIO wakeup for method %i\n",
1177 bank->method);
1178 return -EINVAL;
1179 }
1180}
1181
4196dd6b
TL		 1182static void _reset_gpio(struct gpio_bank *bank, int gpio)
1183{
1184 _set_gpio_direction(bank, get_gpio_index(gpio), 1);
1185 _set_gpio_irqenable(bank, gpio, 0);
1186 _clear_gpio_irqstatus(bank, gpio);
6cab4860 1187 _set_gpio_triggering(bank, get_gpio_index(gpio), IRQ_TYPE_NONE);
4196dd6b
TL		 1188}
1189
92105bb7
TL		 1190/* Use disable_irq_wake() and enable_irq_wake() functions from drivers */
1191static int gpio_wake_enable(unsigned int irq, unsigned int enable)
1192{
1193 unsigned int gpio = irq - IH_GPIO_BASE;
1194 struct gpio_bank *bank;
1195 int retval;
1196
1197 if (check_gpio(gpio) < 0)
1198 return -ENODEV;
58781016 1199 bank = get_irq_chip_data(irq);
92105bb7 1200 retval = _set_gpio_wakeup(bank, get_gpio_index(gpio), enable);
92105bb7
TL		 1201
1202 return retval;
1203}
1204
3ff164e1 1205static int omap_gpio_request(struct gpio_chip *chip, unsigned offset)
5e1c5ff4 1206{
3ff164e1 1207 struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip);
a6472533 1208 unsigned long flags;
52e31344 1209
a6472533 1210 spin_lock_irqsave(&bank->lock, flags);
92105bb7 1211
4196dd6b
TL		 1212 /* Set trigger to none. You need to enable the desired trigger with
1213 * request_irq() or set_irq_type().
1214 */
3ff164e1 1215 _set_gpio_triggering(bank, offset, IRQ_TYPE_NONE);
92105bb7 1216
1a8bfa1e 1217#ifdef CONFIG_ARCH_OMAP15XX
5e1c5ff4 1218 if (bank->method == METHOD_GPIO_1510) {
92105bb7 1219 void __iomem *reg;
5e1c5ff4 1220
92105bb7 1221 /* Claim the pin for MPU */
5e1c5ff4 1222 reg = bank->base + OMAP1510_GPIO_PIN_CONTROL;
3ff164e1 1223 __raw_writel(__raw_readl(reg) | (1 << offset), reg);
5e1c5ff4
TL		 1224 }
1225#endif
058af1ea
C		 1226 if (!cpu_class_is_omap1()) {
1227 if (!bank->mod_usage) {
9f096868 1228 void __iomem *reg = bank->base;
058af1ea 1229 u32 ctrl;
9f096868
C		 1230
1231 if (cpu_is_omap24xx() || cpu_is_omap34xx())
1232 reg += OMAP24XX_GPIO_CTRL;
1233 else if (cpu_is_omap44xx())
1234 reg += OMAP4_GPIO_CTRL;
1235 ctrl = __raw_readl(reg);
058af1ea 1236 /* Module is enabled, clocks are not gated */
9f096868
C		 1237 ctrl &= 0xFFFFFFFE;
1238 __raw_writel(ctrl, reg);
058af1ea
C		 1239 }
1240 bank->mod_usage |= 1 << offset;
1241 }
a6472533 1242 spin_unlock_irqrestore(&bank->lock, flags);
5e1c5ff4
TL		 1243
1244 return 0;
1245}
1246
3ff164e1 1247static void omap_gpio_free(struct gpio_chip *chip, unsigned offset)
5e1c5ff4 1248{
3ff164e1 1249 struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip);
a6472533 1250 unsigned long flags;
5e1c5ff4 1251
a6472533 1252 spin_lock_irqsave(&bank->lock, flags);
92105bb7
TL		 1253#ifdef CONFIG_ARCH_OMAP16XX
1254 if (bank->method == METHOD_GPIO_1610) {
1255 /* Disable wake-up during idle for dynamic tick */
1256 void __iomem *reg = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
3ff164e1 1257 __raw_writel(1 << offset, reg);
92105bb7
TL		 1258 }
1259#endif
9f096868
C		 1260#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
1261 if (bank->method == METHOD_GPIO_24XX) {
92105bb7
TL		 1262 /* Disable wake-up during idle for dynamic tick */
1263 void __iomem *reg = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
3ff164e1 1264 __raw_writel(1 << offset, reg);
92105bb7 1265 }
9f096868
C		 1266#endif
1267#ifdef CONFIG_ARCH_OMAP4
1268 if (bank->method == METHOD_GPIO_44XX) {
1269 /* Disable wake-up during idle for dynamic tick */
1270 void __iomem *reg = bank->base + OMAP4_GPIO_IRQWAKEN0;
1271 __raw_writel(1 << offset, reg);
1272 }
92105bb7 1273#endif
058af1ea
C		 1274 if (!cpu_class_is_omap1()) {
1275 bank->mod_usage &= ~(1 << offset);
1276 if (!bank->mod_usage) {
9f096868 1277 void __iomem *reg = bank->base;
058af1ea 1278 u32 ctrl;
9f096868
C		 1279
1280 if (cpu_is_omap24xx() || cpu_is_omap34xx())
1281 reg += OMAP24XX_GPIO_CTRL;
1282 else if (cpu_is_omap44xx())
1283 reg += OMAP4_GPIO_CTRL;
1284 ctrl = __raw_readl(reg);
058af1ea
C		 1285 /* Module is disabled, clocks are gated */
1286 ctrl |= 1;
9f096868 1287 __raw_writel(ctrl, reg);
058af1ea
C		 1288 }
1289 }
3ff164e1 1290 _reset_gpio(bank, bank->chip.base + offset);
a6472533 1291 spin_unlock_irqrestore(&bank->lock, flags);
5e1c5ff4
TL		 1292}
1293
1294/*
1295 * We need to unmask the GPIO bank interrupt as soon as possible to
1296 * avoid missing GPIO interrupts for other lines in the bank.
1297 * Then we need to mask-read-clear-unmask the triggered GPIO lines
1298 * in the bank to avoid missing nested interrupts for a GPIO line.
1299 * If we wait to unmask individual GPIO lines in the bank after the
1300 * line's interrupt handler has been run, we may miss some nested
1301 * interrupts.
1302 */
10dd5ce2 1303static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
5e1c5ff4 1304{
92105bb7 1305 void __iomem *isr_reg = NULL;
5e1c5ff4 1306 u32 isr;
4318f36b 1307 unsigned int gpio_irq, gpio_index;
5e1c5ff4 1308 struct gpio_bank *bank;
ea6dedd7
ID		 1309 u32 retrigger = 0;
1310 int unmasked = 0;
5e1c5ff4
TL		 1311
1312 desc->chip->ack(irq);
1313
418ca1f0 1314 bank = get_irq_data(irq);
e5c56ed3 1315#ifdef CONFIG_ARCH_OMAP1
5e1c5ff4
TL		 1316 if (bank->method == METHOD_MPUIO)
1317 isr_reg = bank->base + OMAP_MPUIO_GPIO_INT;
e5c56ed3 1318#endif
1a8bfa1e 1319#ifdef CONFIG_ARCH_OMAP15XX
5e1c5ff4
TL		 1320 if (bank->method == METHOD_GPIO_1510)
1321 isr_reg = bank->base + OMAP1510_GPIO_INT_STATUS;
1322#endif
1323#if defined(CONFIG_ARCH_OMAP16XX)
1324 if (bank->method == METHOD_GPIO_1610)
1325 isr_reg = bank->base + OMAP1610_GPIO_IRQSTATUS1;
1326#endif
b718aa81 1327#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
7c006926
AB		 1328 if (bank->method == METHOD_GPIO_7XX)
1329 isr_reg = bank->base + OMAP7XX_GPIO_INT_STATUS;
56739a69 1330#endif
a8eb7ca0 1331#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
92105bb7
TL		 1332 if (bank->method == METHOD_GPIO_24XX)
1333 isr_reg = bank->base + OMAP24XX_GPIO_IRQSTATUS1;
78a1a6d3
SR		 1334#endif
1335#if defined(CONFIG_ARCH_OMAP4)
3f1686a9 1336 if (bank->method == METHOD_GPIO_44XX)
78a1a6d3 1337 isr_reg = bank->base + OMAP4_GPIO_IRQSTATUS0;
92105bb7 1338#endif
92105bb7 1339 while(1) {
6e60e79a 1340 u32 isr_saved, level_mask = 0;
ea6dedd7 1341 u32 enabled;
6e60e79a 1342
ea6dedd7
ID		 1343 enabled = _get_gpio_irqbank_mask(bank);
1344 isr_saved = isr = __raw_readl(isr_reg) & enabled;
6e60e79a
TL		 1345
1346 if (cpu_is_omap15xx() && (bank->method == METHOD_MPUIO))
1347 isr &= 0x0000ffff;
1348
5492fb1a 1349 if (cpu_class_is_omap2()) {
b144ff6f 1350 level_mask = bank->level_mask & enabled;
ea6dedd7 1351 }
6e60e79a
TL		 1352
1353 /* clear edge sensitive interrupts before handler(s) are
1354 called so that we don't miss any interrupt occurred while
1355 executing them */
1356 _enable_gpio_irqbank(bank, isr_saved & ~level_mask, 0);
1357 _clear_gpio_irqbank(bank, isr_saved & ~level_mask);
1358 _enable_gpio_irqbank(bank, isr_saved & ~level_mask, 1);
1359
1360 /* if there is only edge sensitive GPIO pin interrupts
1361 configured, we could unmask GPIO bank interrupt immediately */
ea6dedd7
ID		 1362 if (!level_mask && !unmasked) {
1363 unmasked = 1;
6e60e79a 1364 desc->chip->unmask(irq);
ea6dedd7 1365 }
92105bb7 1366
ea6dedd7
ID		 1367 isr |= retrigger;
1368 retrigger = 0;
92105bb7
TL		 1369 if (!isr)
1370 break;
1371
1372 gpio_irq = bank->virtual_irq_start;
1373 for (; isr != 0; isr >>= 1, gpio_irq++) {
4318f36b
CM		 1374 gpio_index = get_gpio_index(irq_to_gpio(gpio_irq));
1375
92105bb7
TL		 1376 if (!(isr & 1))
1377 continue;
29454dde 1378
4318f36b
CM		 1379#ifdef CONFIG_ARCH_OMAP1
1380 /*
1381 * Some chips can't respond to both rising and falling
1382 * at the same time. If this irq was requested with
1383 * both flags, we need to flip the ICR data for the IRQ
1384 * to respond to the IRQ for the opposite direction.
1385 * This will be indicated in the bank toggle_mask.
1386 */
1387 if (bank->toggle_mask & (1 << gpio_index))
1388 _toggle_gpio_edge_triggering(bank, gpio_index);
1389#endif
1390
d8aa0251 1391 generic_handle_irq(gpio_irq);
92105bb7 1392 }
1a8bfa1e 1393 }
ea6dedd7
ID		 1394 /* if bank has any level sensitive GPIO pin interrupt
1395 configured, we must unmask the bank interrupt only after
1396 handler(s) are executed in order to avoid spurious bank
1397 interrupt */
1398 if (!unmasked)
1399 desc->chip->unmask(irq);
1400
5e1c5ff4
TL		 1401}
1402
4196dd6b
TL		 1403static void gpio_irq_shutdown(unsigned int irq)
1404{
1405 unsigned int gpio = irq - IH_GPIO_BASE;
58781016 1406 struct gpio_bank *bank = get_irq_chip_data(irq);
4196dd6b
TL		 1407
1408 _reset_gpio(bank, gpio);
1409}
1410
5e1c5ff4
TL		 1411static void gpio_ack_irq(unsigned int irq)
1412{
1413 unsigned int gpio = irq - IH_GPIO_BASE;
58781016 1414 struct gpio_bank *bank = get_irq_chip_data(irq);
5e1c5ff4
TL		 1415
1416 _clear_gpio_irqstatus(bank, gpio);
1417}
1418
1419static void gpio_mask_irq(unsigned int irq)
1420{
1421 unsigned int gpio = irq - IH_GPIO_BASE;
58781016 1422 struct gpio_bank *bank = get_irq_chip_data(irq);
5e1c5ff4
TL		 1423
1424 _set_gpio_irqenable(bank, gpio, 0);
55b6019a 1425 _set_gpio_triggering(bank, get_gpio_index(gpio), IRQ_TYPE_NONE);
5e1c5ff4
TL		 1426}
1427
1428static void gpio_unmask_irq(unsigned int irq)
1429{
1430 unsigned int gpio = irq - IH_GPIO_BASE;
58781016 1431 struct gpio_bank *bank = get_irq_chip_data(irq);
b144ff6f 1432 unsigned int irq_mask = 1 << get_gpio_index(gpio);
55b6019a
KH		 1433 struct irq_desc *desc = irq_to_desc(irq);
1434 u32 trigger = desc->status & IRQ_TYPE_SENSE_MASK;
1435
1436 if (trigger)
1437 _set_gpio_triggering(bank, get_gpio_index(gpio), trigger);
b144ff6f
KH		 1438
1439 /* For level-triggered GPIOs, the clearing must be done after
1440 * the HW source is cleared, thus after the handler has run */
1441 if (bank->level_mask & irq_mask) {
1442 _set_gpio_irqenable(bank, gpio, 0);
1443 _clear_gpio_irqstatus(bank, gpio);
1444 }
5e1c5ff4 1445
4de8c75b 1446 _set_gpio_irqenable(bank, gpio, 1);
5e1c5ff4
TL		 1447}
1448
e5c56ed3
DB		 1449static struct irq_chip gpio_irq_chip = {
1450 .name = "GPIO",
1451 .shutdown = gpio_irq_shutdown,
1452 .ack = gpio_ack_irq,
1453 .mask = gpio_mask_irq,
1454 .unmask = gpio_unmask_irq,
1455 .set_type = gpio_irq_type,
1456 .set_wake = gpio_wake_enable,
1457};
1458
1459/*---------------------------------------------------------------------*/
1460
1461#ifdef CONFIG_ARCH_OMAP1
1462
1463/* MPUIO uses the always-on 32k clock */
1464
5e1c5ff4
TL		 1465static void mpuio_ack_irq(unsigned int irq)
1466{
1467 /* The ISR is reset automatically, so do nothing here. */
1468}
1469
1470static void mpuio_mask_irq(unsigned int irq)
1471{
1472 unsigned int gpio = OMAP_MPUIO(irq - IH_MPUIO_BASE);
58781016 1473 struct gpio_bank *bank = get_irq_chip_data(irq);
5e1c5ff4
TL		 1474
1475 _set_gpio_irqenable(bank, gpio, 0);
1476}
1477
1478static void mpuio_unmask_irq(unsigned int irq)
1479{
1480 unsigned int gpio = OMAP_MPUIO(irq - IH_MPUIO_BASE);
58781016 1481 struct gpio_bank *bank = get_irq_chip_data(irq);
5e1c5ff4
TL		 1482
1483 _set_gpio_irqenable(bank, gpio, 1);
1484}
1485
e5c56ed3
DB		 1486static struct irq_chip mpuio_irq_chip = {
1487 .name = "MPUIO",
1488 .ack = mpuio_ack_irq,
1489 .mask = mpuio_mask_irq,
1490 .unmask = mpuio_unmask_irq,
92105bb7 1491 .set_type = gpio_irq_type,
11a78b79
DB		 1492#ifdef CONFIG_ARCH_OMAP16XX
1493 /* REVISIT: assuming only 16xx supports MPUIO wake events */
1494 .set_wake = gpio_wake_enable,
1495#endif
5e1c5ff4
TL		 1496};
1497
e5c56ed3
DB		 1498
1499#define bank_is_mpuio(bank) ((bank)->method == METHOD_MPUIO)
1500
11a78b79
DB		 1501
1502#ifdef CONFIG_ARCH_OMAP16XX
1503
1504#include <linux/platform_device.h>
1505
79ee031f 1506static int omap_mpuio_suspend_noirq(struct device *dev)
11a78b79 1507{
79ee031f 1508 struct platform_device *pdev = to_platform_device(dev);
11a78b79
DB		 1509 struct gpio_bank *bank = platform_get_drvdata(pdev);
1510 void __iomem *mask_reg = bank->base + OMAP_MPUIO_GPIO_MASKIT;
a6472533 1511 unsigned long flags;
11a78b79 1512
a6472533 1513 spin_lock_irqsave(&bank->lock, flags);
11a78b79
DB		 1514 bank->saved_wakeup = __raw_readl(mask_reg);
1515 __raw_writel(0xffff & ~bank->suspend_wakeup, mask_reg);
a6472533 1516 spin_unlock_irqrestore(&bank->lock, flags);
11a78b79
DB		 1517
1518 return 0;
1519}
1520
79ee031f 1521static int omap_mpuio_resume_noirq(struct device *dev)
11a78b79 1522{
79ee031f 1523 struct platform_device *pdev = to_platform_device(dev);
11a78b79
DB		 1524 struct gpio_bank *bank = platform_get_drvdata(pdev);
1525 void __iomem *mask_reg = bank->base + OMAP_MPUIO_GPIO_MASKIT;
a6472533 1526 unsigned long flags;
11a78b79 1527
a6472533 1528 spin_lock_irqsave(&bank->lock, flags);
11a78b79 1529 __raw_writel(bank->saved_wakeup, mask_reg);
a6472533 1530 spin_unlock_irqrestore(&bank->lock, flags);
11a78b79
DB		 1531
1532 return 0;
1533}
1534
47145210 1535static const struct dev_pm_ops omap_mpuio_dev_pm_ops = {
79ee031f
MD		 1536 .suspend_noirq = omap_mpuio_suspend_noirq,
1537 .resume_noirq = omap_mpuio_resume_noirq,
1538};
1539
11a78b79
DB		 1540/* use platform_driver for this, now that there's no longer any
1541 * point to sys_device (other than not disturbing old code).
1542 */
1543static struct platform_driver omap_mpuio_driver = {
11a78b79
DB		 1544 .driver = {
1545 .name = "mpuio",
79ee031f 1546 .pm = &omap_mpuio_dev_pm_ops,
11a78b79
DB		 1547 },
1548};
1549
1550static struct platform_device omap_mpuio_device = {
1551 .name = "mpuio",
1552 .id = -1,
1553 .dev = {
1554 .driver = &omap_mpuio_driver.driver,
1555 }
1556 /* could list the /proc/iomem resources */
1557};
1558
1559static inline void mpuio_init(void)
1560{
fcf126d8
DB		 1561 platform_set_drvdata(&omap_mpuio_device, &gpio_bank_1610[0]);
1562
11a78b79
DB		 1563 if (platform_driver_register(&omap_mpuio_driver) == 0)
1564 (void) platform_device_register(&omap_mpuio_device);
1565}
1566
1567#else
1568static inline void mpuio_init(void) {}
1569#endif /* 16xx */
1570
e5c56ed3
DB		 1571#else
1572
1573extern struct irq_chip mpuio_irq_chip;
1574
1575#define bank_is_mpuio(bank) 0
11a78b79 1576static inline void mpuio_init(void) {}
e5c56ed3
DB		 1577
1578#endif
1579
1580/*---------------------------------------------------------------------*/
5e1c5ff4 1581
52e31344
DB		 1582/* REVISIT these are stupid implementations! replace by ones that
1583 * don't switch on METHOD_* and which mostly avoid spinlocks
1584 */
1585
1586static int gpio_input(struct gpio_chip *chip, unsigned offset)
1587{
1588 struct gpio_bank *bank;
1589 unsigned long flags;
1590
1591 bank = container_of(chip, struct gpio_bank, chip);
1592 spin_lock_irqsave(&bank->lock, flags);
1593 _set_gpio_direction(bank, offset, 1);
1594 spin_unlock_irqrestore(&bank->lock, flags);
1595 return 0;
1596}
1597
b37c45b8
RQ		 1598static int gpio_is_input(struct gpio_bank *bank, int mask)
1599{
1600 void __iomem *reg = bank->base;
1601
1602 switch (bank->method) {
1603 case METHOD_MPUIO:
1604 reg += OMAP_MPUIO_IO_CNTL;
1605 break;
1606 case METHOD_GPIO_1510:
1607 reg += OMAP1510_GPIO_DIR_CONTROL;
1608 break;
1609 case METHOD_GPIO_1610:
1610 reg += OMAP1610_GPIO_DIRECTION;
1611 break;
7c006926
AB		 1612 case METHOD_GPIO_7XX:
1613 reg += OMAP7XX_GPIO_DIR_CONTROL;
b37c45b8
RQ		 1614 break;
1615 case METHOD_GPIO_24XX:
1616 reg += OMAP24XX_GPIO_OE;
1617 break;
9f096868
C		 1618 case METHOD_GPIO_44XX:
1619 reg += OMAP4_GPIO_OE;
1620 break;
1621 default:
1622 WARN_ONCE(1, "gpio_is_input: incorrect OMAP GPIO method");
1623 return -EINVAL;
b37c45b8
RQ		 1624 }
1625 return __raw_readl(reg) & mask;
1626}
1627
52e31344
DB		 1628static int gpio_get(struct gpio_chip *chip, unsigned offset)
1629{
b37c45b8
RQ		 1630 struct gpio_bank *bank;
1631 void __iomem *reg;
1632 int gpio;
1633 u32 mask;
1634
1635 gpio = chip->base + offset;
1636 bank = get_gpio_bank(gpio);
1637 reg = bank->base;
1638 mask = 1 << get_gpio_index(gpio);
1639
1640 if (gpio_is_input(bank, mask))
1641 return _get_gpio_datain(bank, gpio);
1642 else
1643 return _get_gpio_dataout(bank, gpio);
52e31344
DB		 1644}
1645
1646static int gpio_output(struct gpio_chip *chip, unsigned offset, int value)
1647{
1648 struct gpio_bank *bank;
1649 unsigned long flags;
1650
1651 bank = container_of(chip, struct gpio_bank, chip);
1652 spin_lock_irqsave(&bank->lock, flags);
1653 _set_gpio_dataout(bank, offset, value);
1654 _set_gpio_direction(bank, offset, 0);
1655 spin_unlock_irqrestore(&bank->lock, flags);
1656 return 0;
1657}
1658
1659static void gpio_set(struct gpio_chip *chip, unsigned offset, int value)
1660{
1661 struct gpio_bank *bank;
1662 unsigned long flags;
1663
1664 bank = container_of(chip, struct gpio_bank, chip);
1665 spin_lock_irqsave(&bank->lock, flags);
1666 _set_gpio_dataout(bank, offset, value);
1667 spin_unlock_irqrestore(&bank->lock, flags);
1668}
1669
a007b709
DB		 1670static int gpio_2irq(struct gpio_chip *chip, unsigned offset)
1671{
1672 struct gpio_bank *bank;
1673
1674 bank = container_of(chip, struct gpio_bank, chip);
1675 return bank->virtual_irq_start + offset;
1676}
1677
52e31344
DB		 1678/*---------------------------------------------------------------------*/
1679
1a8bfa1e 1680static int initialized;
56213ca4 1681#if defined(CONFIG_ARCH_OMAP1) || defined(CONFIG_ARCH_OMAP2)
1a8bfa1e 1682static struct clk * gpio_ick;
5492fb1a
SMK		 1683#endif
1684
1685#if defined(CONFIG_ARCH_OMAP2)
1a8bfa1e 1686static struct clk * gpio_fck;
5492fb1a 1687#endif
5e1c5ff4 1688
5492fb1a 1689#if defined(CONFIG_ARCH_OMAP2430)
56a25641
SMK		 1690static struct clk * gpio5_ick;
1691static struct clk * gpio5_fck;
1692#endif
1693
44169075 1694#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)
5492fb1a
SMK		 1695static struct clk *gpio_iclks[OMAP34XX_NR_GPIOS];
1696#endif
1697
9f7065da
TL		 1698static void __init omap_gpio_show_rev(void)
1699{
1700 u32 rev;
1701
1702 if (cpu_is_omap16xx())
1703 rev = __raw_readw(gpio_bank[1].base + OMAP1610_GPIO_REVISION);
1704 else if (cpu_is_omap24xx() || cpu_is_omap34xx())
1705 rev = __raw_readl(gpio_bank[0].base + OMAP24XX_GPIO_REVISION);
1706 else if (cpu_is_omap44xx())
1707 rev = __raw_readl(gpio_bank[0].base + OMAP4_GPIO_REVISION);
1708 else
1709 return;
1710
1711 printk(KERN_INFO "OMAP GPIO hardware version %d.%d\n",
1712 (rev >> 4) & 0x0f, rev & 0x0f);
1713}
1714
8ba55c5c
DB		 1715/* This lock class tells lockdep that GPIO irqs are in a different
1716 * category than their parents, so it won't report false recursion.
1717 */
1718static struct lock_class_key gpio_lock_class;
1719
5e1c5ff4
TL		 1720static int __init _omap_gpio_init(void)
1721{
1722 int i;
52e31344 1723 int gpio = 0;
5e1c5ff4 1724 struct gpio_bank *bank;
9f7065da 1725 int bank_size = SZ_8K; /* Module 4KB + L4 4KB except on omap1 */
5492fb1a 1726 char clk_name[11];
5e1c5ff4
TL		 1727
1728 initialized = 1;
1729
5492fb1a 1730#if defined(CONFIG_ARCH_OMAP1)
6e60e79a 1731 if (cpu_is_omap15xx()) {
1a8bfa1e
TL		 1732 gpio_ick = clk_get(NULL, "arm_gpio_ck");
1733 if (IS_ERR(gpio_ick))
92105bb7
TL		 1734 printk("Could not get arm_gpio_ck\n");
1735 else
30ff720b 1736 clk_enable(gpio_ick);
1a8bfa1e 1737 }
5492fb1a
SMK		 1738#endif
1739#if defined(CONFIG_ARCH_OMAP2)
1740 if (cpu_class_is_omap2()) {
1a8bfa1e
TL		 1741 gpio_ick = clk_get(NULL, "gpios_ick");
1742 if (IS_ERR(gpio_ick))
1743 printk("Could not get gpios_ick\n");
1744 else
30ff720b 1745 clk_enable(gpio_ick);
1a8bfa1e 1746 gpio_fck = clk_get(NULL, "gpios_fck");
1630b52d 1747 if (IS_ERR(gpio_fck))
1a8bfa1e
TL		 1748 printk("Could not get gpios_fck\n");
1749 else
30ff720b 1750 clk_enable(gpio_fck);
56a25641
SMK		 1751
1752 /*
5492fb1a 1753 * On 2430 & 3430 GPIO 5 uses CORE L4 ICLK
56a25641 1754 */
5492fb1a 1755#if defined(CONFIG_ARCH_OMAP2430)
56a25641
SMK		 1756 if (cpu_is_omap2430()) {
1757 gpio5_ick = clk_get(NULL, "gpio5_ick");
1758 if (IS_ERR(gpio5_ick))
1759 printk("Could not get gpio5_ick\n");
1760 else
1761 clk_enable(gpio5_ick);
1762 gpio5_fck = clk_get(NULL, "gpio5_fck");
1763 if (IS_ERR(gpio5_fck))
1764 printk("Could not get gpio5_fck\n");
1765 else
1766 clk_enable(gpio5_fck);
1767 }
1768#endif
5492fb1a
SMK		 1769 }
1770#endif
1771
44169075
SS		 1772#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)
1773 if (cpu_is_omap34xx() || cpu_is_omap44xx()) {
5492fb1a
SMK		 1774 for (i = 0; i < OMAP34XX_NR_GPIOS; i++) {
1775 sprintf(clk_name, "gpio%d_ick", i + 1);
1776 gpio_iclks[i] = clk_get(NULL, clk_name);
1777 if (IS_ERR(gpio_iclks[i]))
1778 printk(KERN_ERR "Could not get %s\n", clk_name);
1779 else
1780 clk_enable(gpio_iclks[i]);
5492fb1a
SMK		 1781 }
1782 }
1783#endif
1784
92105bb7 1785
1a8bfa1e 1786#ifdef CONFIG_ARCH_OMAP15XX
6e60e79a 1787 if (cpu_is_omap15xx()) {
5e1c5ff4
TL		 1788 gpio_bank_count = 2;
1789 gpio_bank = gpio_bank_1510;
9f7065da 1790 bank_size = SZ_2K;
5e1c5ff4
TL		 1791 }
1792#endif
1793#if defined(CONFIG_ARCH_OMAP16XX)
1794 if (cpu_is_omap16xx()) {
5e1c5ff4
TL		 1795 gpio_bank_count = 5;
1796 gpio_bank = gpio_bank_1610;
9f7065da 1797 bank_size = SZ_2K;
5e1c5ff4
TL		 1798 }
1799#endif
b718aa81
AB		 1800#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
1801 if (cpu_is_omap7xx()) {
56739a69 1802 gpio_bank_count = 7;
7c006926 1803 gpio_bank = gpio_bank_7xx;
9f7065da 1804 bank_size = SZ_2K;
56739a69
ZM		 1805 }
1806#endif
088ef950 1807#ifdef CONFIG_ARCH_OMAP2
56a25641 1808 if (cpu_is_omap242x()) {
92105bb7 1809 gpio_bank_count = 4;
56a25641 1810 gpio_bank = gpio_bank_242x;
56a25641
SMK		 1811 }
1812 if (cpu_is_omap243x()) {
56a25641
SMK		 1813 gpio_bank_count = 5;
1814 gpio_bank = gpio_bank_243x;
92105bb7 1815 }
5492fb1a 1816#endif
a8eb7ca0 1817#ifdef CONFIG_ARCH_OMAP3
5492fb1a 1818 if (cpu_is_omap34xx()) {
5492fb1a
SMK		 1819 gpio_bank_count = OMAP34XX_NR_GPIOS;
1820 gpio_bank = gpio_bank_34xx;
5492fb1a 1821 }
44169075
SS		 1822#endif
1823#ifdef CONFIG_ARCH_OMAP4
1824 if (cpu_is_omap44xx()) {
44169075
SS		 1825 gpio_bank_count = OMAP34XX_NR_GPIOS;
1826 gpio_bank = gpio_bank_44xx;
44169075 1827 }
5e1c5ff4
TL		 1828#endif
1829 for (i = 0; i < gpio_bank_count; i++) {
1830 int j, gpio_count = 16;
1831
1832 bank = &gpio_bank[i];
5e1c5ff4 1833 spin_lock_init(&bank->lock);
9f7065da
TL		 1834
1835 /* Static mapping, never released */
1836 bank->base = ioremap(bank->pbase, bank_size);
1837 if (!bank->base) {
1838 printk(KERN_ERR "Could not ioremap gpio bank%i\n", i);
1839 continue;
1840 }
1841
e5c56ed3 1842 if (bank_is_mpuio(bank))
7c7095aa 1843 __raw_writew(0xffff, bank->base + OMAP_MPUIO_GPIO_MASKIT);
d11ac979 1844 if (cpu_is_omap15xx() && bank->method == METHOD_GPIO_1510) {
5e1c5ff4
TL		 1845 __raw_writew(0xffff, bank->base + OMAP1510_GPIO_INT_MASK);
1846 __raw_writew(0x0000, bank->base + OMAP1510_GPIO_INT_STATUS);
1847 }
d11ac979 1848 if (cpu_is_omap16xx() && bank->method == METHOD_GPIO_1610) {
5e1c5ff4
TL		 1849 __raw_writew(0x0000, bank->base + OMAP1610_GPIO_IRQENABLE1);
1850 __raw_writew(0xffff, bank->base + OMAP1610_GPIO_IRQSTATUS1);
92105bb7 1851 __raw_writew(0x0014, bank->base + OMAP1610_GPIO_SYSCONFIG);
5e1c5ff4 1852 }
7c006926
AB		 1853 if (cpu_is_omap7xx() && bank->method == METHOD_GPIO_7XX) {
1854 __raw_writel(0xffffffff, bank->base + OMAP7XX_GPIO_INT_MASK);
1855 __raw_writel(0x00000000, bank->base + OMAP7XX_GPIO_INT_STATUS);
5e1c5ff4 1856
7c006926 1857 gpio_count = 32; /* 7xx has 32-bit GPIOs */
5e1c5ff4 1858 }
d11ac979 1859
140455fa 1860#ifdef CONFIG_ARCH_OMAP2PLUS
3f1686a9
TL		 1861 if ((bank->method == METHOD_GPIO_24XX) ||
1862 (bank->method == METHOD_GPIO_44XX)) {
3ac4fa99
JY		 1863 static const u32 non_wakeup_gpios[] = {
1864 0xe203ffc0, 0x08700040
1865 };
3f1686a9
TL		 1866
1867 if (cpu_is_omap44xx()) {
1868 __raw_writel(0xffffffff, bank->base +
78a1a6d3 1869 OMAP4_GPIO_IRQSTATUSCLR0);
3f1686a9 1870 __raw_writew(0x0015, bank->base +
78a1a6d3 1871 OMAP4_GPIO_SYSCONFIG);
3f1686a9 1872 __raw_writel(0x00000000, bank->base +
78a1a6d3 1873 OMAP4_GPIO_DEBOUNCENABLE);
3f1686a9
TL		 1874 /*
1875 * Initialize interface clock ungated,
1876 * module enabled
1877 */
1878 __raw_writel(0, bank->base + OMAP4_GPIO_CTRL);
1879 } else {
1880 __raw_writel(0x00000000, bank->base +
1881 OMAP24XX_GPIO_IRQENABLE1);
1882 __raw_writel(0xffffffff, bank->base +
1883 OMAP24XX_GPIO_IRQSTATUS1);
1884 __raw_writew(0x0015, bank->base +
1885 OMAP24XX_GPIO_SYSCONFIG);
1886 __raw_writel(0x00000000, bank->base +
1887 OMAP24XX_GPIO_DEBOUNCE_EN);
1888
1889 /*
1890 * Initialize interface clock ungated,
1891 * module enabled
1892 */
1893 __raw_writel(0, bank->base +
1894 OMAP24XX_GPIO_CTRL);
1895 }
a118b5f3
TK		 1896 if (cpu_is_omap24xx() &&
1897 i < ARRAY_SIZE(non_wakeup_gpios))
3ac4fa99 1898 bank->non_wakeup_gpios = non_wakeup_gpios[i];
92105bb7
TL		 1899 gpio_count = 32;
1900 }
5e1c5ff4 1901#endif
058af1ea
C		 1902
1903 bank->mod_usage = 0;
52e31344
DB		 1904 /* REVISIT eventually switch from OMAP-specific gpio structs
1905 * over to the generic ones
1906 */
3ff164e1
JN		 1907 bank->chip.request = omap_gpio_request;
1908 bank->chip.free = omap_gpio_free;
52e31344
DB		 1909 bank->chip.direction_input = gpio_input;
1910 bank->chip.get = gpio_get;
1911 bank->chip.direction_output = gpio_output;
1912 bank->chip.set = gpio_set;
a007b709 1913 bank->chip.to_irq = gpio_2irq;
52e31344
DB		 1914 if (bank_is_mpuio(bank)) {
1915 bank->chip.label = "mpuio";
69114a47 1916#ifdef CONFIG_ARCH_OMAP16XX
d8f388d8
DB		 1917 bank->chip.dev = &omap_mpuio_device.dev;
1918#endif
52e31344
DB		 1919 bank->chip.base = OMAP_MPUIO(0);
1920 } else {
1921 bank->chip.label = "gpio";
1922 bank->chip.base = gpio;
1923 gpio += gpio_count;
1924 }
1925 bank->chip.ngpio = gpio_count;
1926
1927 gpiochip_add(&bank->chip);
1928
5e1c5ff4
TL		 1929 for (j = bank->virtual_irq_start;
1930 j < bank->virtual_irq_start + gpio_count; j++) {
8ba55c5c 1931 lockdep_set_class(&irq_desc[j].lock, &gpio_lock_class);
58781016 1932 set_irq_chip_data(j, bank);
e5c56ed3 1933 if (bank_is_mpuio(bank))
5e1c5ff4
TL		 1934 set_irq_chip(j, &mpuio_irq_chip);
1935 else
1936 set_irq_chip(j, &gpio_irq_chip);
10dd5ce2 1937 set_irq_handler(j, handle_simple_irq);
5e1c5ff4
TL		 1938 set_irq_flags(j, IRQF_VALID);
1939 }
1940 set_irq_chained_handler(bank->irq, gpio_irq_handler);
1941 set_irq_data(bank->irq, bank);
89db9482 1942
44169075 1943 if (cpu_is_omap34xx() || cpu_is_omap44xx()) {
89db9482
JH		 1944 sprintf(clk_name, "gpio%d_dbck", i + 1);
1945 bank->dbck = clk_get(NULL, clk_name);
1946 if (IS_ERR(bank->dbck))
1947 printk(KERN_ERR "Could not get %s\n", clk_name);
1948 }
5e1c5ff4
TL		 1949 }
1950
1951 /* Enable system clock for GPIO module.
1952 * The CAM_CLK_CTRL *is* really the right place. */
92105bb7 1953 if (cpu_is_omap16xx())
5e1c5ff4
TL		 1954 omap_writel(omap_readl(ULPD_CAM_CLK_CTRL) | 0x04, ULPD_CAM_CLK_CTRL);
1955
14f1c3bf
JY		 1956 /* Enable autoidle for the OCP interface */
1957 if (cpu_is_omap24xx())
1958 omap_writel(1 << 0, 0x48019010);
5492fb1a
SMK		 1959 if (cpu_is_omap34xx())
1960 omap_writel(1 << 0, 0x48306814);
d11ac979 1961
9f7065da
TL		 1962 omap_gpio_show_rev();
1963
5e1c5ff4
TL		 1964 return 0;
1965}
1966
140455fa 1967#if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP2PLUS)
92105bb7
TL		 1968static int omap_gpio_suspend(struct sys_device *dev, pm_message_t mesg)
1969{
1970 int i;
1971
5492fb1a 1972 if (!cpu_class_is_omap2() && !cpu_is_omap16xx())
92105bb7
TL		 1973 return 0;
1974
1975 for (i = 0; i < gpio_bank_count; i++) {
1976 struct gpio_bank *bank = &gpio_bank[i];
1977 void __iomem *wake_status;
1978 void __iomem *wake_clear;
1979 void __iomem *wake_set;
a6472533 1980 unsigned long flags;
92105bb7
TL		 1981
1982 switch (bank->method) {
e5c56ed3 1983#ifdef CONFIG_ARCH_OMAP16XX
92105bb7
TL		 1984 case METHOD_GPIO_1610:
1985 wake_status = bank->base + OMAP1610_GPIO_WAKEUPENABLE;
1986 wake_clear = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
1987 wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA;
1988 break;
e5c56ed3 1989#endif
a8eb7ca0 1990#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
92105bb7 1991 case METHOD_GPIO_24XX:
723fdb78 1992 wake_status = bank->base + OMAP24XX_GPIO_WAKE_EN;
92105bb7
TL		 1993 wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
1994 wake_set = bank->base + OMAP24XX_GPIO_SETWKUENA;
1995 break;
78a1a6d3
SR		 1996#endif
1997#ifdef CONFIG_ARCH_OMAP4
3f1686a9 1998 case METHOD_GPIO_44XX:
78a1a6d3
SR		 1999 wake_status = bank->base + OMAP4_GPIO_IRQWAKEN0;
2000 wake_clear = bank->base + OMAP4_GPIO_IRQWAKEN0;
2001 wake_set = bank->base + OMAP4_GPIO_IRQWAKEN0;
2002 break;
e5c56ed3 2003#endif
92105bb7
TL		 2004 default:
2005 continue;
2006 }
2007
a6472533 2008 spin_lock_irqsave(&bank->lock, flags);
92105bb7
TL		 2009 bank->saved_wakeup = __raw_readl(wake_status);
2010 __raw_writel(0xffffffff, wake_clear);
2011 __raw_writel(bank->suspend_wakeup, wake_set);
a6472533 2012 spin_unlock_irqrestore(&bank->lock, flags);
92105bb7
TL		 2013 }
2014
2015 return 0;
2016}
2017
2018static int omap_gpio_resume(struct sys_device *dev)
2019{
2020 int i;
2021
723fdb78 2022 if (!cpu_class_is_omap2() && !cpu_is_omap16xx())
92105bb7
TL		 2023 return 0;
2024
2025 for (i = 0; i < gpio_bank_count; i++) {
2026 struct gpio_bank *bank = &gpio_bank[i];
2027 void __iomem *wake_clear;
2028 void __iomem *wake_set;
a6472533 2029 unsigned long flags;
92105bb7
TL		 2030
2031 switch (bank->method) {
e5c56ed3 2032#ifdef CONFIG_ARCH_OMAP16XX
92105bb7
TL		 2033 case METHOD_GPIO_1610:
2034 wake_clear = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
2035 wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA;
2036 break;
e5c56ed3 2037#endif
a8eb7ca0 2038#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
92105bb7 2039 case METHOD_GPIO_24XX:
0d9356cb
TL		 2040 wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
2041 wake_set = bank->base + OMAP24XX_GPIO_SETWKUENA;
92105bb7 2042 break;
78a1a6d3
SR		 2043#endif
2044#ifdef CONFIG_ARCH_OMAP4
3f1686a9 2045 case METHOD_GPIO_44XX:
78a1a6d3
SR		 2046 wake_clear = bank->base + OMAP4_GPIO_IRQWAKEN0;
2047 wake_set = bank->base + OMAP4_GPIO_IRQWAKEN0;
2048 break;
e5c56ed3 2049#endif
92105bb7
TL		 2050 default:
2051 continue;
2052 }
2053
a6472533 2054 spin_lock_irqsave(&bank->lock, flags);
92105bb7
TL		 2055 __raw_writel(0xffffffff, wake_clear);
2056 __raw_writel(bank->saved_wakeup, wake_set);
a6472533 2057 spin_unlock_irqrestore(&bank->lock, flags);
92105bb7
TL		 2058 }
2059
2060 return 0;
2061}
2062
2063static struct sysdev_class omap_gpio_sysclass = {
af5ca3f4 2064 .name = "gpio",
92105bb7
TL		 2065 .suspend = omap_gpio_suspend,
2066 .resume = omap_gpio_resume,
2067};
2068
2069static struct sys_device omap_gpio_device = {
2070 .id = 0,
2071 .cls = &omap_gpio_sysclass,
2072};
3ac4fa99
JY		 2073
2074#endif
2075
140455fa 2076#ifdef CONFIG_ARCH_OMAP2PLUS
3ac4fa99
JY		 2077
2078static int workaround_enabled;
2079
43ffcd9a 2080void omap2_gpio_prepare_for_idle(int power_state)
3ac4fa99
JY		 2081{
2082 int i, c = 0;
a118b5f3 2083 int min = 0;
3ac4fa99 2084
a118b5f3
TK		 2085 if (cpu_is_omap34xx())
2086 min = 1;
43ffcd9a 2087
a118b5f3 2088 for (i = min; i < gpio_bank_count; i++) {
3ac4fa99
JY		 2089 struct gpio_bank *bank = &gpio_bank[i];
2090 u32 l1, l2;
2091
8865b9b6
KH		 2092 if (bank->dbck_enable_mask)
2093 clk_disable(bank->dbck);
2094
43ffcd9a
KH		 2095 if (power_state > PWRDM_POWER_OFF)
2096 continue;
2097
2098 /* If going to OFF, remove triggering for all
2099 * non-wakeup GPIOs. Otherwise spurious IRQs will be
2100 * generated. See OMAP2420 Errata item 1.101. */
3ac4fa99
JY		 2101 if (!(bank->enabled_non_wakeup_gpios))
2102 continue;
3f1686a9
TL		 2103
2104 if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
2105 bank->saved_datain = __raw_readl(bank->base +
2106 OMAP24XX_GPIO_DATAIN);
2107 l1 = __raw_readl(bank->base +
2108 OMAP24XX_GPIO_FALLINGDETECT);
2109 l2 = __raw_readl(bank->base +
2110 OMAP24XX_GPIO_RISINGDETECT);
2111 }
2112
2113 if (cpu_is_omap44xx()) {
2114 bank->saved_datain = __raw_readl(bank->base +
2115 OMAP4_GPIO_DATAIN);
2116 l1 = __raw_readl(bank->base +
2117 OMAP4_GPIO_FALLINGDETECT);
2118 l2 = __raw_readl(bank->base +
2119 OMAP4_GPIO_RISINGDETECT);
2120 }
2121
3ac4fa99
JY		 2122 bank->saved_fallingdetect = l1;
2123 bank->saved_risingdetect = l2;
2124 l1 &= ~bank->enabled_non_wakeup_gpios;
2125 l2 &= ~bank->enabled_non_wakeup_gpios;
3f1686a9
TL		 2126
2127 if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
2128 __raw_writel(l1, bank->base +
2129 OMAP24XX_GPIO_FALLINGDETECT);
2130 __raw_writel(l2, bank->base +
2131 OMAP24XX_GPIO_RISINGDETECT);
2132 }
2133
2134 if (cpu_is_omap44xx()) {
2135 __raw_writel(l1, bank->base + OMAP4_GPIO_FALLINGDETECT);
2136 __raw_writel(l2, bank->base + OMAP4_GPIO_RISINGDETECT);
2137 }
2138
3ac4fa99
JY		 2139 c++;
2140 }
2141 if (!c) {
2142 workaround_enabled = 0;
2143 return;
2144 }
2145 workaround_enabled = 1;
2146}
2147
43ffcd9a 2148void omap2_gpio_resume_after_idle(void)
3ac4fa99
JY		 2149{
2150 int i;
a118b5f3 2151 int min = 0;
3ac4fa99 2152
a118b5f3
TK		 2153 if (cpu_is_omap34xx())
2154 min = 1;
2155 for (i = min; i < gpio_bank_count; i++) {
3ac4fa99 2156 struct gpio_bank *bank = &gpio_bank[i];
82dbb9d3 2157 u32 l, gen, gen0, gen1;
3ac4fa99 2158
8865b9b6
KH		 2159 if (bank->dbck_enable_mask)
2160 clk_enable(bank->dbck);
2161
43ffcd9a
KH		 2162 if (!workaround_enabled)
2163 continue;
2164
3ac4fa99
JY		 2165 if (!(bank->enabled_non_wakeup_gpios))
2166 continue;
3f1686a9
TL		 2167
2168 if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
2169 __raw_writel(bank->saved_fallingdetect,
3ac4fa99 2170 bank->base + OMAP24XX_GPIO_FALLINGDETECT);
3f1686a9 2171 __raw_writel(bank->saved_risingdetect,
3ac4fa99 2172 bank->base + OMAP24XX_GPIO_RISINGDETECT);
3f1686a9
TL		 2173 l = __raw_readl(bank->base + OMAP24XX_GPIO_DATAIN);
2174 }
2175
2176 if (cpu_is_omap44xx()) {
2177 __raw_writel(bank->saved_fallingdetect,
78a1a6d3 2178 bank->base + OMAP4_GPIO_FALLINGDETECT);
3f1686a9 2179 __raw_writel(bank->saved_risingdetect,
78a1a6d3 2180 bank->base + OMAP4_GPIO_RISINGDETECT);
3f1686a9
TL		 2181 l = __raw_readl(bank->base + OMAP4_GPIO_DATAIN);
2182 }
2183
3ac4fa99
JY		 2184 /* Check if any of the non-wakeup interrupt GPIOs have changed
2185 * state. If so, generate an IRQ by software. This is
2186 * horribly racy, but it's the best we can do to work around
2187 * this silicon bug. */
3ac4fa99 2188 l ^= bank->saved_datain;
a118b5f3 2189 l &= bank->enabled_non_wakeup_gpios;
82dbb9d3
EN		 2190
2191 /*
2192 * No need to generate IRQs for the rising edge for gpio IRQs
2193 * configured with falling edge only; and vice versa.
2194 */
2195 gen0 = l & bank->saved_fallingdetect;
2196 gen0 &= bank->saved_datain;
2197
2198 gen1 = l & bank->saved_risingdetect;
2199 gen1 &= ~(bank->saved_datain);
2200
2201 /* FIXME: Consider GPIO IRQs with level detections properly! */
2202 gen = l & (~(bank->saved_fallingdetect) &
2203 ~(bank->saved_risingdetect));
2204 /* Consider all GPIO IRQs needed to be updated */
2205 gen |= gen0 | gen1;
2206
2207 if (gen) {
3ac4fa99 2208 u32 old0, old1;
3f1686a9 2209
f00d6497 2210 if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
3f1686a9
TL		 2211 old0 = __raw_readl(bank->base +
2212 OMAP24XX_GPIO_LEVELDETECT0);
2213 old1 = __raw_readl(bank->base +
2214 OMAP24XX_GPIO_LEVELDETECT1);
f00d6497 2215 __raw_writel(old0 | gen, bank->base +
82dbb9d3 2216 OMAP24XX_GPIO_LEVELDETECT0);
f00d6497 2217 __raw_writel(old1 | gen, bank->base +
82dbb9d3 2218 OMAP24XX_GPIO_LEVELDETECT1);
f00d6497 2219 __raw_writel(old0, bank->base +
3f1686a9 2220 OMAP24XX_GPIO_LEVELDETECT0);
f00d6497 2221 __raw_writel(old1, bank->base +
3f1686a9
TL		 2222 OMAP24XX_GPIO_LEVELDETECT1);
2223 }
2224
2225 if (cpu_is_omap44xx()) {
2226 old0 = __raw_readl(bank->base +
78a1a6d3 2227 OMAP4_GPIO_LEVELDETECT0);
3f1686a9 2228 old1 = __raw_readl(bank->base +
78a1a6d3 2229 OMAP4_GPIO_LEVELDETECT1);
3f1686a9 2230 __raw_writel(old0 | l, bank->base +
78a1a6d3 2231 OMAP4_GPIO_LEVELDETECT0);
3f1686a9 2232 __raw_writel(old1 | l, bank->base +
78a1a6d3 2233 OMAP4_GPIO_LEVELDETECT1);
3f1686a9 2234 __raw_writel(old0, bank->base +
78a1a6d3 2235 OMAP4_GPIO_LEVELDETECT0);
3f1686a9 2236 __raw_writel(old1, bank->base +
78a1a6d3 2237 OMAP4_GPIO_LEVELDETECT1);
3f1686a9 2238 }
3ac4fa99
JY		 2239 }
2240 }
2241
2242}
2243
92105bb7
TL		 2244#endif
2245
a8eb7ca0 2246#ifdef CONFIG_ARCH_OMAP3
40c670f0
RN		 2247/* save the registers of bank 2-6 */
2248void omap_gpio_save_context(void)
2249{
2250 int i;
2251
2252 /* saving banks from 2-6 only since GPIO1 is in WKUP */
2253 for (i = 1; i < gpio_bank_count; i++) {
2254 struct gpio_bank *bank = &gpio_bank[i];
2255 gpio_context[i].sysconfig =
2256 __raw_readl(bank->base + OMAP24XX_GPIO_SYSCONFIG);
2257 gpio_context[i].irqenable1 =
2258 __raw_readl(bank->base + OMAP24XX_GPIO_IRQENABLE1);
2259 gpio_context[i].irqenable2 =
2260 __raw_readl(bank->base + OMAP24XX_GPIO_IRQENABLE2);
2261 gpio_context[i].wake_en =
2262 __raw_readl(bank->base + OMAP24XX_GPIO_WAKE_EN);
2263 gpio_context[i].ctrl =
2264 __raw_readl(bank->base + OMAP24XX_GPIO_CTRL);
2265 gpio_context[i].oe =
2266 __raw_readl(bank->base + OMAP24XX_GPIO_OE);
2267 gpio_context[i].leveldetect0 =
2268 __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT0);
2269 gpio_context[i].leveldetect1 =
2270 __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT1);
2271 gpio_context[i].risingdetect =
2272 __raw_readl(bank->base + OMAP24XX_GPIO_RISINGDETECT);
2273 gpio_context[i].fallingdetect =
2274 __raw_readl(bank->base + OMAP24XX_GPIO_FALLINGDETECT);
2275 gpio_context[i].dataout =
2276 __raw_readl(bank->base + OMAP24XX_GPIO_DATAOUT);
40c670f0
RN		 2277 }
2278}
2279
2280/* restore the required registers of bank 2-6 */
2281void omap_gpio_restore_context(void)
2282{
2283 int i;
2284
2285 for (i = 1; i < gpio_bank_count; i++) {
2286 struct gpio_bank *bank = &gpio_bank[i];
2287 __raw_writel(gpio_context[i].sysconfig,
2288 bank->base + OMAP24XX_GPIO_SYSCONFIG);
2289 __raw_writel(gpio_context[i].irqenable1,
2290 bank->base + OMAP24XX_GPIO_IRQENABLE1);
2291 __raw_writel(gpio_context[i].irqenable2,
2292 bank->base + OMAP24XX_GPIO_IRQENABLE2);
2293 __raw_writel(gpio_context[i].wake_en,
2294 bank->base + OMAP24XX_GPIO_WAKE_EN);
2295 __raw_writel(gpio_context[i].ctrl,
2296 bank->base + OMAP24XX_GPIO_CTRL);
2297 __raw_writel(gpio_context[i].oe,
2298 bank->base + OMAP24XX_GPIO_OE);
2299 __raw_writel(gpio_context[i].leveldetect0,
2300 bank->base + OMAP24XX_GPIO_LEVELDETECT0);
2301 __raw_writel(gpio_context[i].leveldetect1,
2302 bank->base + OMAP24XX_GPIO_LEVELDETECT1);
2303 __raw_writel(gpio_context[i].risingdetect,
2304 bank->base + OMAP24XX_GPIO_RISINGDETECT);
2305 __raw_writel(gpio_context[i].fallingdetect,
2306 bank->base + OMAP24XX_GPIO_FALLINGDETECT);
2307 __raw_writel(gpio_context[i].dataout,
2308 bank->base + OMAP24XX_GPIO_DATAOUT);
40c670f0
RN		 2309 }
2310}
2311#endif
2312
5e1c5ff4
TL		 2313/*
2314 * This may get called early from board specific init
1a8bfa1e 2315 * for boards that have interrupts routed via FPGA.
5e1c5ff4 2316 */
277d58ef 2317int __init omap_gpio_init(void)
5e1c5ff4
TL		 2318{
2319 if (!initialized)
2320 return _omap_gpio_init();
2321 else
2322 return 0;
2323}
2324
92105bb7
TL		 2325static int __init omap_gpio_sysinit(void)
2326{
2327 int ret = 0;
2328
2329 if (!initialized)
2330 ret = _omap_gpio_init();
2331
11a78b79
DB		 2332 mpuio_init();
2333
140455fa 2334#if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP2PLUS)
5492fb1a 2335 if (cpu_is_omap16xx() || cpu_class_is_omap2()) {
92105bb7
TL		 2336 if (ret == 0) {
2337 ret = sysdev_class_register(&omap_gpio_sysclass);
2338 if (ret == 0)
2339 ret = sysdev_register(&omap_gpio_device);
2340 }
2341 }
2342#endif
2343
2344 return ret;
2345}
2346
92105bb7 2347arch_initcall(omap_gpio_sysinit);
Linux 6.x block layer and io_uring tree(s)