Commit | Line | Data |
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5e1c5ff4 TL |
1 | /* |
2 | * linux/arch/arm/plat-omap/gpio.c | |
3 | * | |
4 | * Support functions for OMAP GPIO | |
5 | * | |
92105bb7 | 6 | * Copyright (C) 2003-2005 Nokia Corporation |
96de0e25 | 7 | * Written by Juha Yrjölä <juha.yrjola@nokia.com> |
5e1c5ff4 | 8 | * |
44169075 SS |
9 | * Copyright (C) 2009 Texas Instruments |
10 | * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com> | |
11 | * | |
5e1c5ff4 TL |
12 | * This program is free software; you can redistribute it and/or modify |
13 | * it under the terms of the GNU General Public License version 2 as | |
14 | * published by the Free Software Foundation. | |
15 | */ | |
16 | ||
5e1c5ff4 TL |
17 | #include <linux/init.h> |
18 | #include <linux/module.h> | |
5e1c5ff4 | 19 | #include <linux/interrupt.h> |
92105bb7 TL |
20 | #include <linux/sysdev.h> |
21 | #include <linux/err.h> | |
f8ce2547 | 22 | #include <linux/clk.h> |
fced80c7 | 23 | #include <linux/io.h> |
5e1c5ff4 | 24 | |
a09e64fb | 25 | #include <mach/hardware.h> |
5e1c5ff4 | 26 | #include <asm/irq.h> |
a09e64fb RK |
27 | #include <mach/irqs.h> |
28 | #include <mach/gpio.h> | |
5e1c5ff4 TL |
29 | #include <asm/mach/irq.h> |
30 | ||
5e1c5ff4 TL |
31 | /* |
32 | * OMAP1510 GPIO registers | |
33 | */ | |
9f7065da | 34 | #define OMAP1510_GPIO_BASE 0xfffce000 |
5e1c5ff4 TL |
35 | #define OMAP1510_GPIO_DATA_INPUT 0x00 |
36 | #define OMAP1510_GPIO_DATA_OUTPUT 0x04 | |
37 | #define OMAP1510_GPIO_DIR_CONTROL 0x08 | |
38 | #define OMAP1510_GPIO_INT_CONTROL 0x0c | |
39 | #define OMAP1510_GPIO_INT_MASK 0x10 | |
40 | #define OMAP1510_GPIO_INT_STATUS 0x14 | |
41 | #define OMAP1510_GPIO_PIN_CONTROL 0x18 | |
42 | ||
43 | #define OMAP1510_IH_GPIO_BASE 64 | |
44 | ||
45 | /* | |
46 | * OMAP1610 specific GPIO registers | |
47 | */ | |
9f7065da TL |
48 | #define OMAP1610_GPIO1_BASE 0xfffbe400 |
49 | #define OMAP1610_GPIO2_BASE 0xfffbec00 | |
50 | #define OMAP1610_GPIO3_BASE 0xfffbb400 | |
51 | #define OMAP1610_GPIO4_BASE 0xfffbbc00 | |
5e1c5ff4 TL |
52 | #define OMAP1610_GPIO_REVISION 0x0000 |
53 | #define OMAP1610_GPIO_SYSCONFIG 0x0010 | |
54 | #define OMAP1610_GPIO_SYSSTATUS 0x0014 | |
55 | #define OMAP1610_GPIO_IRQSTATUS1 0x0018 | |
56 | #define OMAP1610_GPIO_IRQENABLE1 0x001c | |
92105bb7 | 57 | #define OMAP1610_GPIO_WAKEUPENABLE 0x0028 |
5e1c5ff4 TL |
58 | #define OMAP1610_GPIO_DATAIN 0x002c |
59 | #define OMAP1610_GPIO_DATAOUT 0x0030 | |
60 | #define OMAP1610_GPIO_DIRECTION 0x0034 | |
61 | #define OMAP1610_GPIO_EDGE_CTRL1 0x0038 | |
62 | #define OMAP1610_GPIO_EDGE_CTRL2 0x003c | |
63 | #define OMAP1610_GPIO_CLEAR_IRQENABLE1 0x009c | |
92105bb7 | 64 | #define OMAP1610_GPIO_CLEAR_WAKEUPENA 0x00a8 |
5e1c5ff4 TL |
65 | #define OMAP1610_GPIO_CLEAR_DATAOUT 0x00b0 |
66 | #define OMAP1610_GPIO_SET_IRQENABLE1 0x00dc | |
92105bb7 | 67 | #define OMAP1610_GPIO_SET_WAKEUPENA 0x00e8 |
5e1c5ff4 TL |
68 | #define OMAP1610_GPIO_SET_DATAOUT 0x00f0 |
69 | ||
70 | /* | |
7c006926 | 71 | * OMAP7XX specific GPIO registers |
5e1c5ff4 | 72 | */ |
9f7065da TL |
73 | #define OMAP7XX_GPIO1_BASE 0xfffbc000 |
74 | #define OMAP7XX_GPIO2_BASE 0xfffbc800 | |
75 | #define OMAP7XX_GPIO3_BASE 0xfffbd000 | |
76 | #define OMAP7XX_GPIO4_BASE 0xfffbd800 | |
77 | #define OMAP7XX_GPIO5_BASE 0xfffbe000 | |
78 | #define OMAP7XX_GPIO6_BASE 0xfffbe800 | |
7c006926 AB |
79 | #define OMAP7XX_GPIO_DATA_INPUT 0x00 |
80 | #define OMAP7XX_GPIO_DATA_OUTPUT 0x04 | |
81 | #define OMAP7XX_GPIO_DIR_CONTROL 0x08 | |
82 | #define OMAP7XX_GPIO_INT_CONTROL 0x0c | |
83 | #define OMAP7XX_GPIO_INT_MASK 0x10 | |
84 | #define OMAP7XX_GPIO_INT_STATUS 0x14 | |
5e1c5ff4 | 85 | |
9f7065da | 86 | #define OMAP1_MPUIO_VBASE OMAP1_MPUIO_BASE |
94113260 | 87 | |
92105bb7 TL |
88 | /* |
89 | * omap24xx specific GPIO registers | |
90 | */ | |
9f7065da TL |
91 | #define OMAP242X_GPIO1_BASE 0x48018000 |
92 | #define OMAP242X_GPIO2_BASE 0x4801a000 | |
93 | #define OMAP242X_GPIO3_BASE 0x4801c000 | |
94 | #define OMAP242X_GPIO4_BASE 0x4801e000 | |
56a25641 | 95 | |
9f7065da TL |
96 | #define OMAP243X_GPIO1_BASE 0x4900C000 |
97 | #define OMAP243X_GPIO2_BASE 0x4900E000 | |
98 | #define OMAP243X_GPIO3_BASE 0x49010000 | |
99 | #define OMAP243X_GPIO4_BASE 0x49012000 | |
100 | #define OMAP243X_GPIO5_BASE 0x480B6000 | |
56a25641 | 101 | |
92105bb7 TL |
102 | #define OMAP24XX_GPIO_REVISION 0x0000 |
103 | #define OMAP24XX_GPIO_SYSCONFIG 0x0010 | |
104 | #define OMAP24XX_GPIO_SYSSTATUS 0x0014 | |
105 | #define OMAP24XX_GPIO_IRQSTATUS1 0x0018 | |
bee7930f HD |
106 | #define OMAP24XX_GPIO_IRQSTATUS2 0x0028 |
107 | #define OMAP24XX_GPIO_IRQENABLE2 0x002c | |
92105bb7 | 108 | #define OMAP24XX_GPIO_IRQENABLE1 0x001c |
723fdb78 | 109 | #define OMAP24XX_GPIO_WAKE_EN 0x0020 |
92105bb7 TL |
110 | #define OMAP24XX_GPIO_CTRL 0x0030 |
111 | #define OMAP24XX_GPIO_OE 0x0034 | |
112 | #define OMAP24XX_GPIO_DATAIN 0x0038 | |
113 | #define OMAP24XX_GPIO_DATAOUT 0x003c | |
114 | #define OMAP24XX_GPIO_LEVELDETECT0 0x0040 | |
115 | #define OMAP24XX_GPIO_LEVELDETECT1 0x0044 | |
116 | #define OMAP24XX_GPIO_RISINGDETECT 0x0048 | |
117 | #define OMAP24XX_GPIO_FALLINGDETECT 0x004c | |
5eb3bb9c KH |
118 | #define OMAP24XX_GPIO_DEBOUNCE_EN 0x0050 |
119 | #define OMAP24XX_GPIO_DEBOUNCE_VAL 0x0054 | |
92105bb7 TL |
120 | #define OMAP24XX_GPIO_CLEARIRQENABLE1 0x0060 |
121 | #define OMAP24XX_GPIO_SETIRQENABLE1 0x0064 | |
122 | #define OMAP24XX_GPIO_CLEARWKUENA 0x0080 | |
123 | #define OMAP24XX_GPIO_SETWKUENA 0x0084 | |
124 | #define OMAP24XX_GPIO_CLEARDATAOUT 0x0090 | |
125 | #define OMAP24XX_GPIO_SETDATAOUT 0x0094 | |
126 | ||
78a1a6d3 SR |
127 | #define OMAP4_GPIO_REVISION 0x0000 |
128 | #define OMAP4_GPIO_SYSCONFIG 0x0010 | |
129 | #define OMAP4_GPIO_EOI 0x0020 | |
130 | #define OMAP4_GPIO_IRQSTATUSRAW0 0x0024 | |
131 | #define OMAP4_GPIO_IRQSTATUSRAW1 0x0028 | |
132 | #define OMAP4_GPIO_IRQSTATUS0 0x002c | |
133 | #define OMAP4_GPIO_IRQSTATUS1 0x0030 | |
134 | #define OMAP4_GPIO_IRQSTATUSSET0 0x0034 | |
135 | #define OMAP4_GPIO_IRQSTATUSSET1 0x0038 | |
136 | #define OMAP4_GPIO_IRQSTATUSCLR0 0x003c | |
137 | #define OMAP4_GPIO_IRQSTATUSCLR1 0x0040 | |
138 | #define OMAP4_GPIO_IRQWAKEN0 0x0044 | |
139 | #define OMAP4_GPIO_IRQWAKEN1 0x0048 | |
140 | #define OMAP4_GPIO_SYSSTATUS 0x0104 | |
141 | #define OMAP4_GPIO_CTRL 0x0130 | |
142 | #define OMAP4_GPIO_OE 0x0134 | |
143 | #define OMAP4_GPIO_DATAIN 0x0138 | |
144 | #define OMAP4_GPIO_DATAOUT 0x013c | |
145 | #define OMAP4_GPIO_LEVELDETECT0 0x0140 | |
146 | #define OMAP4_GPIO_LEVELDETECT1 0x0144 | |
147 | #define OMAP4_GPIO_RISINGDETECT 0x0148 | |
148 | #define OMAP4_GPIO_FALLINGDETECT 0x014c | |
149 | #define OMAP4_GPIO_DEBOUNCENABLE 0x0150 | |
150 | #define OMAP4_GPIO_DEBOUNCINGTIME 0x0154 | |
151 | #define OMAP4_GPIO_CLEARDATAOUT 0x0190 | |
152 | #define OMAP4_GPIO_SETDATAOUT 0x0194 | |
5492fb1a SMK |
153 | /* |
154 | * omap34xx specific GPIO registers | |
155 | */ | |
156 | ||
9f7065da TL |
157 | #define OMAP34XX_GPIO1_BASE 0x48310000 |
158 | #define OMAP34XX_GPIO2_BASE 0x49050000 | |
159 | #define OMAP34XX_GPIO3_BASE 0x49052000 | |
160 | #define OMAP34XX_GPIO4_BASE 0x49054000 | |
161 | #define OMAP34XX_GPIO5_BASE 0x49056000 | |
162 | #define OMAP34XX_GPIO6_BASE 0x49058000 | |
5492fb1a | 163 | |
44169075 SS |
164 | /* |
165 | * OMAP44XX specific GPIO registers | |
166 | */ | |
9f7065da TL |
167 | #define OMAP44XX_GPIO1_BASE 0x4a310000 |
168 | #define OMAP44XX_GPIO2_BASE 0x48055000 | |
169 | #define OMAP44XX_GPIO3_BASE 0x48057000 | |
170 | #define OMAP44XX_GPIO4_BASE 0x48059000 | |
171 | #define OMAP44XX_GPIO5_BASE 0x4805B000 | |
172 | #define OMAP44XX_GPIO6_BASE 0x4805D000 | |
5492fb1a | 173 | |
5e1c5ff4 | 174 | struct gpio_bank { |
9f7065da | 175 | unsigned long pbase; |
92105bb7 | 176 | void __iomem *base; |
5e1c5ff4 TL |
177 | u16 irq; |
178 | u16 virtual_irq_start; | |
92105bb7 | 179 | int method; |
140455fa | 180 | #if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP2PLUS) |
92105bb7 TL |
181 | u32 suspend_wakeup; |
182 | u32 saved_wakeup; | |
3ac4fa99 | 183 | #endif |
140455fa | 184 | #ifdef CONFIG_ARCH_OMAP2PLUS |
3ac4fa99 JY |
185 | u32 non_wakeup_gpios; |
186 | u32 enabled_non_wakeup_gpios; | |
187 | ||
188 | u32 saved_datain; | |
189 | u32 saved_fallingdetect; | |
190 | u32 saved_risingdetect; | |
191 | #endif | |
b144ff6f | 192 | u32 level_mask; |
4318f36b | 193 | u32 toggle_mask; |
5e1c5ff4 | 194 | spinlock_t lock; |
52e31344 | 195 | struct gpio_chip chip; |
89db9482 | 196 | struct clk *dbck; |
058af1ea | 197 | u32 mod_usage; |
5e1c5ff4 TL |
198 | }; |
199 | ||
200 | #define METHOD_MPUIO 0 | |
201 | #define METHOD_GPIO_1510 1 | |
202 | #define METHOD_GPIO_1610 2 | |
7c006926 | 203 | #define METHOD_GPIO_7XX 3 |
56739a69 | 204 | #define METHOD_GPIO_24XX 5 |
3f1686a9 | 205 | #define METHOD_GPIO_44XX 6 |
5e1c5ff4 | 206 | |
92105bb7 | 207 | #ifdef CONFIG_ARCH_OMAP16XX |
5e1c5ff4 | 208 | static struct gpio_bank gpio_bank_1610[5] = { |
9f7065da TL |
209 | { OMAP1_MPUIO_VBASE, NULL, INT_MPUIO, IH_MPUIO_BASE, |
210 | METHOD_MPUIO }, | |
211 | { OMAP1610_GPIO1_BASE, NULL, INT_GPIO_BANK1, IH_GPIO_BASE, | |
212 | METHOD_GPIO_1610 }, | |
213 | { OMAP1610_GPIO2_BASE, NULL, INT_1610_GPIO_BANK2, IH_GPIO_BASE + 16, | |
214 | METHOD_GPIO_1610 }, | |
215 | { OMAP1610_GPIO3_BASE, NULL, INT_1610_GPIO_BANK3, IH_GPIO_BASE + 32, | |
216 | METHOD_GPIO_1610 }, | |
217 | { OMAP1610_GPIO4_BASE, NULL, INT_1610_GPIO_BANK4, IH_GPIO_BASE + 48, | |
218 | METHOD_GPIO_1610 }, | |
5e1c5ff4 TL |
219 | }; |
220 | #endif | |
221 | ||
1a8bfa1e | 222 | #ifdef CONFIG_ARCH_OMAP15XX |
5e1c5ff4 | 223 | static struct gpio_bank gpio_bank_1510[2] = { |
9f7065da TL |
224 | { OMAP1_MPUIO_VBASE, NULL, INT_MPUIO, IH_MPUIO_BASE, |
225 | METHOD_MPUIO }, | |
226 | { OMAP1510_GPIO_BASE, NULL, INT_GPIO_BANK1, IH_GPIO_BASE, | |
227 | METHOD_GPIO_1510 } | |
5e1c5ff4 TL |
228 | }; |
229 | #endif | |
230 | ||
b718aa81 | 231 | #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850) |
7c006926 | 232 | static struct gpio_bank gpio_bank_7xx[7] = { |
9f7065da TL |
233 | { OMAP1_MPUIO_VBASE, NULL, INT_7XX_MPUIO, IH_MPUIO_BASE, |
234 | METHOD_MPUIO }, | |
235 | { OMAP7XX_GPIO1_BASE, NULL, INT_7XX_GPIO_BANK1, IH_GPIO_BASE, | |
236 | METHOD_GPIO_7XX }, | |
237 | { OMAP7XX_GPIO2_BASE, NULL, INT_7XX_GPIO_BANK2, IH_GPIO_BASE + 32, | |
238 | METHOD_GPIO_7XX }, | |
239 | { OMAP7XX_GPIO3_BASE, NULL, INT_7XX_GPIO_BANK3, IH_GPIO_BASE + 64, | |
240 | METHOD_GPIO_7XX }, | |
241 | { OMAP7XX_GPIO4_BASE, NULL, INT_7XX_GPIO_BANK4, IH_GPIO_BASE + 96, | |
242 | METHOD_GPIO_7XX }, | |
243 | { OMAP7XX_GPIO5_BASE, NULL, INT_7XX_GPIO_BANK5, IH_GPIO_BASE + 128, | |
244 | METHOD_GPIO_7XX }, | |
245 | { OMAP7XX_GPIO6_BASE, NULL, INT_7XX_GPIO_BANK6, IH_GPIO_BASE + 160, | |
246 | METHOD_GPIO_7XX }, | |
5e1c5ff4 TL |
247 | }; |
248 | #endif | |
249 | ||
088ef950 | 250 | #ifdef CONFIG_ARCH_OMAP2 |
56a25641 SMK |
251 | |
252 | static struct gpio_bank gpio_bank_242x[4] = { | |
9f7065da TL |
253 | { OMAP242X_GPIO1_BASE, NULL, INT_24XX_GPIO_BANK1, IH_GPIO_BASE, |
254 | METHOD_GPIO_24XX }, | |
255 | { OMAP242X_GPIO2_BASE, NULL, INT_24XX_GPIO_BANK2, IH_GPIO_BASE + 32, | |
256 | METHOD_GPIO_24XX }, | |
257 | { OMAP242X_GPIO3_BASE, NULL, INT_24XX_GPIO_BANK3, IH_GPIO_BASE + 64, | |
258 | METHOD_GPIO_24XX }, | |
259 | { OMAP242X_GPIO4_BASE, NULL, INT_24XX_GPIO_BANK4, IH_GPIO_BASE + 96, | |
260 | METHOD_GPIO_24XX }, | |
92105bb7 | 261 | }; |
56a25641 SMK |
262 | |
263 | static struct gpio_bank gpio_bank_243x[5] = { | |
9f7065da TL |
264 | { OMAP243X_GPIO1_BASE, NULL, INT_24XX_GPIO_BANK1, IH_GPIO_BASE, |
265 | METHOD_GPIO_24XX }, | |
266 | { OMAP243X_GPIO2_BASE, NULL, INT_24XX_GPIO_BANK2, IH_GPIO_BASE + 32, | |
267 | METHOD_GPIO_24XX }, | |
268 | { OMAP243X_GPIO3_BASE, NULL, INT_24XX_GPIO_BANK3, IH_GPIO_BASE + 64, | |
269 | METHOD_GPIO_24XX }, | |
270 | { OMAP243X_GPIO4_BASE, NULL, INT_24XX_GPIO_BANK4, IH_GPIO_BASE + 96, | |
271 | METHOD_GPIO_24XX }, | |
272 | { OMAP243X_GPIO5_BASE, NULL, INT_24XX_GPIO_BANK5, IH_GPIO_BASE + 128, | |
273 | METHOD_GPIO_24XX }, | |
56a25641 SMK |
274 | }; |
275 | ||
92105bb7 TL |
276 | #endif |
277 | ||
a8eb7ca0 | 278 | #ifdef CONFIG_ARCH_OMAP3 |
5492fb1a | 279 | static struct gpio_bank gpio_bank_34xx[6] = { |
9f7065da TL |
280 | { OMAP34XX_GPIO1_BASE, NULL, INT_34XX_GPIO_BANK1, IH_GPIO_BASE, |
281 | METHOD_GPIO_24XX }, | |
282 | { OMAP34XX_GPIO2_BASE, NULL, INT_34XX_GPIO_BANK2, IH_GPIO_BASE + 32, | |
283 | METHOD_GPIO_24XX }, | |
284 | { OMAP34XX_GPIO3_BASE, NULL, INT_34XX_GPIO_BANK3, IH_GPIO_BASE + 64, | |
285 | METHOD_GPIO_24XX }, | |
286 | { OMAP34XX_GPIO4_BASE, NULL, INT_34XX_GPIO_BANK4, IH_GPIO_BASE + 96, | |
287 | METHOD_GPIO_24XX }, | |
288 | { OMAP34XX_GPIO5_BASE, NULL, INT_34XX_GPIO_BANK5, IH_GPIO_BASE + 128, | |
289 | METHOD_GPIO_24XX }, | |
290 | { OMAP34XX_GPIO6_BASE, NULL, INT_34XX_GPIO_BANK6, IH_GPIO_BASE + 160, | |
291 | METHOD_GPIO_24XX }, | |
5492fb1a SMK |
292 | }; |
293 | ||
40c670f0 RN |
294 | struct omap3_gpio_regs { |
295 | u32 sysconfig; | |
296 | u32 irqenable1; | |
297 | u32 irqenable2; | |
298 | u32 wake_en; | |
299 | u32 ctrl; | |
300 | u32 oe; | |
301 | u32 leveldetect0; | |
302 | u32 leveldetect1; | |
303 | u32 risingdetect; | |
304 | u32 fallingdetect; | |
305 | u32 dataout; | |
306 | u32 setwkuena; | |
307 | u32 setdataout; | |
5492fb1a SMK |
308 | }; |
309 | ||
40c670f0 | 310 | static struct omap3_gpio_regs gpio_context[OMAP34XX_NR_GPIOS]; |
5492fb1a SMK |
311 | #endif |
312 | ||
44169075 SS |
313 | #ifdef CONFIG_ARCH_OMAP4 |
314 | static struct gpio_bank gpio_bank_44xx[6] = { | |
5772ca7d | 315 | { OMAP44XX_GPIO1_BASE, NULL, OMAP44XX_IRQ_GPIO1, IH_GPIO_BASE, |
3f1686a9 | 316 | METHOD_GPIO_44XX }, |
5772ca7d | 317 | { OMAP44XX_GPIO2_BASE, NULL, OMAP44XX_IRQ_GPIO2, IH_GPIO_BASE + 32, |
3f1686a9 | 318 | METHOD_GPIO_44XX }, |
5772ca7d | 319 | { OMAP44XX_GPIO3_BASE, NULL, OMAP44XX_IRQ_GPIO3, IH_GPIO_BASE + 64, |
3f1686a9 | 320 | METHOD_GPIO_44XX }, |
5772ca7d | 321 | { OMAP44XX_GPIO4_BASE, NULL, OMAP44XX_IRQ_GPIO4, IH_GPIO_BASE + 96, |
3f1686a9 | 322 | METHOD_GPIO_44XX }, |
5772ca7d | 323 | { OMAP44XX_GPIO5_BASE, NULL, OMAP44XX_IRQ_GPIO5, IH_GPIO_BASE + 128, |
3f1686a9 | 324 | METHOD_GPIO_44XX }, |
5772ca7d | 325 | { OMAP44XX_GPIO6_BASE, NULL, OMAP44XX_IRQ_GPIO6, IH_GPIO_BASE + 160, |
3f1686a9 | 326 | METHOD_GPIO_44XX }, |
44169075 SS |
327 | }; |
328 | ||
329 | #endif | |
330 | ||
5e1c5ff4 TL |
331 | static struct gpio_bank *gpio_bank; |
332 | static int gpio_bank_count; | |
333 | ||
334 | static inline struct gpio_bank *get_gpio_bank(int gpio) | |
335 | { | |
6e60e79a | 336 | if (cpu_is_omap15xx()) { |
5e1c5ff4 TL |
337 | if (OMAP_GPIO_IS_MPUIO(gpio)) |
338 | return &gpio_bank[0]; | |
339 | return &gpio_bank[1]; | |
340 | } | |
5e1c5ff4 TL |
341 | if (cpu_is_omap16xx()) { |
342 | if (OMAP_GPIO_IS_MPUIO(gpio)) | |
343 | return &gpio_bank[0]; | |
344 | return &gpio_bank[1 + (gpio >> 4)]; | |
345 | } | |
56739a69 | 346 | if (cpu_is_omap7xx()) { |
5e1c5ff4 TL |
347 | if (OMAP_GPIO_IS_MPUIO(gpio)) |
348 | return &gpio_bank[0]; | |
349 | return &gpio_bank[1 + (gpio >> 5)]; | |
350 | } | |
92105bb7 TL |
351 | if (cpu_is_omap24xx()) |
352 | return &gpio_bank[gpio >> 5]; | |
44169075 | 353 | if (cpu_is_omap34xx() || cpu_is_omap44xx()) |
5492fb1a | 354 | return &gpio_bank[gpio >> 5]; |
e031ab23 DB |
355 | BUG(); |
356 | return NULL; | |
5e1c5ff4 TL |
357 | } |
358 | ||
359 | static inline int get_gpio_index(int gpio) | |
360 | { | |
56739a69 | 361 | if (cpu_is_omap7xx()) |
5e1c5ff4 | 362 | return gpio & 0x1f; |
92105bb7 TL |
363 | if (cpu_is_omap24xx()) |
364 | return gpio & 0x1f; | |
44169075 | 365 | if (cpu_is_omap34xx() || cpu_is_omap44xx()) |
5492fb1a | 366 | return gpio & 0x1f; |
92105bb7 | 367 | return gpio & 0x0f; |
5e1c5ff4 TL |
368 | } |
369 | ||
370 | static inline int gpio_valid(int gpio) | |
371 | { | |
372 | if (gpio < 0) | |
373 | return -1; | |
d11ac979 | 374 | if (cpu_class_is_omap1() && OMAP_GPIO_IS_MPUIO(gpio)) { |
193e68be | 375 | if (gpio >= OMAP_MAX_GPIO_LINES + 16) |
5e1c5ff4 TL |
376 | return -1; |
377 | return 0; | |
378 | } | |
6e60e79a | 379 | if (cpu_is_omap15xx() && gpio < 16) |
5e1c5ff4 | 380 | return 0; |
5e1c5ff4 TL |
381 | if ((cpu_is_omap16xx()) && gpio < 64) |
382 | return 0; | |
56739a69 | 383 | if (cpu_is_omap7xx() && gpio < 192) |
5e1c5ff4 | 384 | return 0; |
92105bb7 TL |
385 | if (cpu_is_omap24xx() && gpio < 128) |
386 | return 0; | |
44169075 | 387 | if ((cpu_is_omap34xx() || cpu_is_omap44xx()) && gpio < 192) |
5492fb1a | 388 | return 0; |
5e1c5ff4 TL |
389 | return -1; |
390 | } | |
391 | ||
392 | static int check_gpio(int gpio) | |
393 | { | |
d32b20fc | 394 | if (unlikely(gpio_valid(gpio) < 0)) { |
5e1c5ff4 TL |
395 | printk(KERN_ERR "omap-gpio: invalid GPIO %d\n", gpio); |
396 | dump_stack(); | |
397 | return -1; | |
398 | } | |
399 | return 0; | |
400 | } | |
401 | ||
402 | static void _set_gpio_direction(struct gpio_bank *bank, int gpio, int is_input) | |
403 | { | |
92105bb7 | 404 | void __iomem *reg = bank->base; |
5e1c5ff4 TL |
405 | u32 l; |
406 | ||
407 | switch (bank->method) { | |
e5c56ed3 | 408 | #ifdef CONFIG_ARCH_OMAP1 |
5e1c5ff4 TL |
409 | case METHOD_MPUIO: |
410 | reg += OMAP_MPUIO_IO_CNTL; | |
411 | break; | |
e5c56ed3 DB |
412 | #endif |
413 | #ifdef CONFIG_ARCH_OMAP15XX | |
5e1c5ff4 TL |
414 | case METHOD_GPIO_1510: |
415 | reg += OMAP1510_GPIO_DIR_CONTROL; | |
416 | break; | |
e5c56ed3 DB |
417 | #endif |
418 | #ifdef CONFIG_ARCH_OMAP16XX | |
5e1c5ff4 TL |
419 | case METHOD_GPIO_1610: |
420 | reg += OMAP1610_GPIO_DIRECTION; | |
421 | break; | |
e5c56ed3 | 422 | #endif |
b718aa81 | 423 | #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850) |
7c006926 AB |
424 | case METHOD_GPIO_7XX: |
425 | reg += OMAP7XX_GPIO_DIR_CONTROL; | |
56739a69 ZM |
426 | break; |
427 | #endif | |
a8eb7ca0 | 428 | #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) |
92105bb7 TL |
429 | case METHOD_GPIO_24XX: |
430 | reg += OMAP24XX_GPIO_OE; | |
431 | break; | |
78a1a6d3 SR |
432 | #endif |
433 | #if defined(CONFIG_ARCH_OMAP4) | |
3f1686a9 | 434 | case METHOD_GPIO_44XX: |
78a1a6d3 SR |
435 | reg += OMAP4_GPIO_OE; |
436 | break; | |
e5c56ed3 DB |
437 | #endif |
438 | default: | |
439 | WARN_ON(1); | |
440 | return; | |
5e1c5ff4 TL |
441 | } |
442 | l = __raw_readl(reg); | |
443 | if (is_input) | |
444 | l |= 1 << gpio; | |
445 | else | |
446 | l &= ~(1 << gpio); | |
447 | __raw_writel(l, reg); | |
448 | } | |
449 | ||
5e1c5ff4 TL |
450 | static void _set_gpio_dataout(struct gpio_bank *bank, int gpio, int enable) |
451 | { | |
92105bb7 | 452 | void __iomem *reg = bank->base; |
5e1c5ff4 TL |
453 | u32 l = 0; |
454 | ||
455 | switch (bank->method) { | |
e5c56ed3 | 456 | #ifdef CONFIG_ARCH_OMAP1 |
5e1c5ff4 TL |
457 | case METHOD_MPUIO: |
458 | reg += OMAP_MPUIO_OUTPUT; | |
459 | l = __raw_readl(reg); | |
460 | if (enable) | |
461 | l |= 1 << gpio; | |
462 | else | |
463 | l &= ~(1 << gpio); | |
464 | break; | |
e5c56ed3 DB |
465 | #endif |
466 | #ifdef CONFIG_ARCH_OMAP15XX | |
5e1c5ff4 TL |
467 | case METHOD_GPIO_1510: |
468 | reg += OMAP1510_GPIO_DATA_OUTPUT; | |
469 | l = __raw_readl(reg); | |
470 | if (enable) | |
471 | l |= 1 << gpio; | |
472 | else | |
473 | l &= ~(1 << gpio); | |
474 | break; | |
e5c56ed3 DB |
475 | #endif |
476 | #ifdef CONFIG_ARCH_OMAP16XX | |
5e1c5ff4 TL |
477 | case METHOD_GPIO_1610: |
478 | if (enable) | |
479 | reg += OMAP1610_GPIO_SET_DATAOUT; | |
480 | else | |
481 | reg += OMAP1610_GPIO_CLEAR_DATAOUT; | |
482 | l = 1 << gpio; | |
483 | break; | |
e5c56ed3 | 484 | #endif |
b718aa81 | 485 | #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850) |
7c006926 AB |
486 | case METHOD_GPIO_7XX: |
487 | reg += OMAP7XX_GPIO_DATA_OUTPUT; | |
56739a69 ZM |
488 | l = __raw_readl(reg); |
489 | if (enable) | |
490 | l |= 1 << gpio; | |
491 | else | |
492 | l &= ~(1 << gpio); | |
493 | break; | |
494 | #endif | |
a8eb7ca0 | 495 | #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) |
92105bb7 TL |
496 | case METHOD_GPIO_24XX: |
497 | if (enable) | |
498 | reg += OMAP24XX_GPIO_SETDATAOUT; | |
499 | else | |
500 | reg += OMAP24XX_GPIO_CLEARDATAOUT; | |
501 | l = 1 << gpio; | |
502 | break; | |
78a1a6d3 SR |
503 | #endif |
504 | #ifdef CONFIG_ARCH_OMAP4 | |
3f1686a9 | 505 | case METHOD_GPIO_44XX: |
78a1a6d3 SR |
506 | if (enable) |
507 | reg += OMAP4_GPIO_SETDATAOUT; | |
508 | else | |
509 | reg += OMAP4_GPIO_CLEARDATAOUT; | |
510 | l = 1 << gpio; | |
511 | break; | |
e5c56ed3 | 512 | #endif |
5e1c5ff4 | 513 | default: |
e5c56ed3 | 514 | WARN_ON(1); |
5e1c5ff4 TL |
515 | return; |
516 | } | |
517 | __raw_writel(l, reg); | |
518 | } | |
519 | ||
b37c45b8 | 520 | static int _get_gpio_datain(struct gpio_bank *bank, int gpio) |
5e1c5ff4 | 521 | { |
92105bb7 | 522 | void __iomem *reg; |
5e1c5ff4 TL |
523 | |
524 | if (check_gpio(gpio) < 0) | |
e5c56ed3 | 525 | return -EINVAL; |
5e1c5ff4 TL |
526 | reg = bank->base; |
527 | switch (bank->method) { | |
e5c56ed3 | 528 | #ifdef CONFIG_ARCH_OMAP1 |
5e1c5ff4 TL |
529 | case METHOD_MPUIO: |
530 | reg += OMAP_MPUIO_INPUT_LATCH; | |
531 | break; | |
e5c56ed3 DB |
532 | #endif |
533 | #ifdef CONFIG_ARCH_OMAP15XX | |
5e1c5ff4 TL |
534 | case METHOD_GPIO_1510: |
535 | reg += OMAP1510_GPIO_DATA_INPUT; | |
536 | break; | |
e5c56ed3 DB |
537 | #endif |
538 | #ifdef CONFIG_ARCH_OMAP16XX | |
5e1c5ff4 TL |
539 | case METHOD_GPIO_1610: |
540 | reg += OMAP1610_GPIO_DATAIN; | |
541 | break; | |
e5c56ed3 | 542 | #endif |
b718aa81 | 543 | #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850) |
7c006926 AB |
544 | case METHOD_GPIO_7XX: |
545 | reg += OMAP7XX_GPIO_DATA_INPUT; | |
56739a69 ZM |
546 | break; |
547 | #endif | |
a8eb7ca0 | 548 | #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) |
92105bb7 TL |
549 | case METHOD_GPIO_24XX: |
550 | reg += OMAP24XX_GPIO_DATAIN; | |
551 | break; | |
78a1a6d3 SR |
552 | #endif |
553 | #ifdef CONFIG_ARCH_OMAP4 | |
3f1686a9 | 554 | case METHOD_GPIO_44XX: |
78a1a6d3 SR |
555 | reg += OMAP4_GPIO_DATAIN; |
556 | break; | |
e5c56ed3 | 557 | #endif |
5e1c5ff4 | 558 | default: |
e5c56ed3 | 559 | return -EINVAL; |
5e1c5ff4 | 560 | } |
92105bb7 TL |
561 | return (__raw_readl(reg) |
562 | & (1 << get_gpio_index(gpio))) != 0; | |
5e1c5ff4 TL |
563 | } |
564 | ||
b37c45b8 RQ |
565 | static int _get_gpio_dataout(struct gpio_bank *bank, int gpio) |
566 | { | |
567 | void __iomem *reg; | |
568 | ||
569 | if (check_gpio(gpio) < 0) | |
570 | return -EINVAL; | |
571 | reg = bank->base; | |
572 | ||
573 | switch (bank->method) { | |
574 | #ifdef CONFIG_ARCH_OMAP1 | |
575 | case METHOD_MPUIO: | |
576 | reg += OMAP_MPUIO_OUTPUT; | |
577 | break; | |
578 | #endif | |
579 | #ifdef CONFIG_ARCH_OMAP15XX | |
580 | case METHOD_GPIO_1510: | |
581 | reg += OMAP1510_GPIO_DATA_OUTPUT; | |
582 | break; | |
583 | #endif | |
584 | #ifdef CONFIG_ARCH_OMAP16XX | |
585 | case METHOD_GPIO_1610: | |
586 | reg += OMAP1610_GPIO_DATAOUT; | |
587 | break; | |
588 | #endif | |
b718aa81 | 589 | #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850) |
7c006926 AB |
590 | case METHOD_GPIO_7XX: |
591 | reg += OMAP7XX_GPIO_DATA_OUTPUT; | |
b37c45b8 RQ |
592 | break; |
593 | #endif | |
140455fa | 594 | #ifdef CONFIG_ARCH_OMAP2PLUS |
b37c45b8 | 595 | case METHOD_GPIO_24XX: |
3f1686a9 | 596 | case METHOD_GPIO_44XX: |
b37c45b8 RQ |
597 | reg += OMAP24XX_GPIO_DATAOUT; |
598 | break; | |
599 | #endif | |
600 | default: | |
601 | return -EINVAL; | |
602 | } | |
603 | ||
604 | return (__raw_readl(reg) & (1 << get_gpio_index(gpio))) != 0; | |
605 | } | |
606 | ||
92105bb7 TL |
607 | #define MOD_REG_BIT(reg, bit_mask, set) \ |
608 | do { \ | |
609 | int l = __raw_readl(base + reg); \ | |
610 | if (set) l |= bit_mask; \ | |
611 | else l &= ~bit_mask; \ | |
612 | __raw_writel(l, base + reg); \ | |
613 | } while(0) | |
614 | ||
5eb3bb9c KH |
615 | void omap_set_gpio_debounce(int gpio, int enable) |
616 | { | |
617 | struct gpio_bank *bank; | |
618 | void __iomem *reg; | |
e031ab23 | 619 | unsigned long flags; |
5eb3bb9c KH |
620 | u32 val, l = 1 << get_gpio_index(gpio); |
621 | ||
622 | if (cpu_class_is_omap1()) | |
623 | return; | |
624 | ||
625 | bank = get_gpio_bank(gpio); | |
626 | reg = bank->base; | |
3f1686a9 TL |
627 | |
628 | if (cpu_is_omap44xx()) | |
629 | reg += OMAP4_GPIO_DEBOUNCENABLE; | |
630 | else | |
631 | reg += OMAP24XX_GPIO_DEBOUNCE_EN; | |
632 | ||
058af1ea C |
633 | if (!(bank->mod_usage & l)) { |
634 | printk(KERN_ERR "GPIO %d not requested\n", gpio); | |
635 | return; | |
636 | } | |
e031ab23 DB |
637 | |
638 | spin_lock_irqsave(&bank->lock, flags); | |
5eb3bb9c KH |
639 | val = __raw_readl(reg); |
640 | ||
89db9482 | 641 | if (enable && !(val & l)) |
5eb3bb9c | 642 | val |= l; |
e031ab23 | 643 | else if (!enable && (val & l)) |
5eb3bb9c | 644 | val &= ~l; |
89db9482 | 645 | else |
e031ab23 | 646 | goto done; |
89db9482 | 647 | |
44169075 | 648 | if (cpu_is_omap34xx() || cpu_is_omap44xx()) { |
e031ab23 DB |
649 | if (enable) |
650 | clk_enable(bank->dbck); | |
651 | else | |
652 | clk_disable(bank->dbck); | |
653 | } | |
5eb3bb9c KH |
654 | |
655 | __raw_writel(val, reg); | |
e031ab23 DB |
656 | done: |
657 | spin_unlock_irqrestore(&bank->lock, flags); | |
5eb3bb9c KH |
658 | } |
659 | EXPORT_SYMBOL(omap_set_gpio_debounce); | |
660 | ||
661 | void omap_set_gpio_debounce_time(int gpio, int enc_time) | |
662 | { | |
663 | struct gpio_bank *bank; | |
664 | void __iomem *reg; | |
665 | ||
666 | if (cpu_class_is_omap1()) | |
667 | return; | |
668 | ||
669 | bank = get_gpio_bank(gpio); | |
670 | reg = bank->base; | |
671 | ||
058af1ea C |
672 | if (!bank->mod_usage) { |
673 | printk(KERN_ERR "GPIO not requested\n"); | |
674 | return; | |
675 | } | |
676 | ||
5eb3bb9c | 677 | enc_time &= 0xff; |
3f1686a9 TL |
678 | |
679 | if (cpu_is_omap44xx()) | |
680 | reg += OMAP4_GPIO_DEBOUNCINGTIME; | |
681 | else | |
682 | reg += OMAP24XX_GPIO_DEBOUNCE_VAL; | |
683 | ||
5eb3bb9c KH |
684 | __raw_writel(enc_time, reg); |
685 | } | |
686 | EXPORT_SYMBOL(omap_set_gpio_debounce_time); | |
687 | ||
140455fa | 688 | #ifdef CONFIG_ARCH_OMAP2PLUS |
5eb3bb9c KH |
689 | static inline void set_24xx_gpio_triggering(struct gpio_bank *bank, int gpio, |
690 | int trigger) | |
5e1c5ff4 | 691 | { |
3ac4fa99 | 692 | void __iomem *base = bank->base; |
92105bb7 | 693 | u32 gpio_bit = 1 << gpio; |
78a1a6d3 | 694 | u32 val; |
92105bb7 | 695 | |
78a1a6d3 SR |
696 | if (cpu_is_omap44xx()) { |
697 | MOD_REG_BIT(OMAP4_GPIO_LEVELDETECT0, gpio_bit, | |
698 | trigger & IRQ_TYPE_LEVEL_LOW); | |
699 | MOD_REG_BIT(OMAP4_GPIO_LEVELDETECT1, gpio_bit, | |
700 | trigger & IRQ_TYPE_LEVEL_HIGH); | |
701 | MOD_REG_BIT(OMAP4_GPIO_RISINGDETECT, gpio_bit, | |
702 | trigger & IRQ_TYPE_EDGE_RISING); | |
703 | MOD_REG_BIT(OMAP4_GPIO_FALLINGDETECT, gpio_bit, | |
704 | trigger & IRQ_TYPE_EDGE_FALLING); | |
705 | } else { | |
706 | MOD_REG_BIT(OMAP24XX_GPIO_LEVELDETECT0, gpio_bit, | |
707 | trigger & IRQ_TYPE_LEVEL_LOW); | |
708 | MOD_REG_BIT(OMAP24XX_GPIO_LEVELDETECT1, gpio_bit, | |
709 | trigger & IRQ_TYPE_LEVEL_HIGH); | |
710 | MOD_REG_BIT(OMAP24XX_GPIO_RISINGDETECT, gpio_bit, | |
711 | trigger & IRQ_TYPE_EDGE_RISING); | |
712 | MOD_REG_BIT(OMAP24XX_GPIO_FALLINGDETECT, gpio_bit, | |
713 | trigger & IRQ_TYPE_EDGE_FALLING); | |
714 | } | |
3ac4fa99 | 715 | if (likely(!(bank->non_wakeup_gpios & gpio_bit))) { |
78a1a6d3 SR |
716 | if (cpu_is_omap44xx()) { |
717 | if (trigger != 0) | |
718 | __raw_writel(1 << gpio, bank->base+ | |
719 | OMAP4_GPIO_IRQWAKEN0); | |
720 | else { | |
721 | val = __raw_readl(bank->base + | |
722 | OMAP4_GPIO_IRQWAKEN0); | |
723 | __raw_writel(val & (~(1 << gpio)), bank->base + | |
724 | OMAP4_GPIO_IRQWAKEN0); | |
725 | } | |
726 | } else { | |
727 | if (trigger != 0) | |
728 | __raw_writel(1 << gpio, bank->base | |
5eb3bb9c | 729 | + OMAP24XX_GPIO_SETWKUENA); |
78a1a6d3 SR |
730 | else |
731 | __raw_writel(1 << gpio, bank->base | |
5eb3bb9c | 732 | + OMAP24XX_GPIO_CLEARWKUENA); |
78a1a6d3 | 733 | } |
3ac4fa99 JY |
734 | } else { |
735 | if (trigger != 0) | |
736 | bank->enabled_non_wakeup_gpios |= gpio_bit; | |
737 | else | |
738 | bank->enabled_non_wakeup_gpios &= ~gpio_bit; | |
739 | } | |
5eb3bb9c | 740 | |
78a1a6d3 SR |
741 | if (cpu_is_omap44xx()) { |
742 | bank->level_mask = | |
743 | __raw_readl(bank->base + OMAP4_GPIO_LEVELDETECT0) | | |
744 | __raw_readl(bank->base + OMAP4_GPIO_LEVELDETECT1); | |
745 | } else { | |
746 | bank->level_mask = | |
747 | __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT0) | | |
748 | __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT1); | |
749 | } | |
92105bb7 | 750 | } |
3ac4fa99 | 751 | #endif |
92105bb7 | 752 | |
9198bcd3 | 753 | #ifdef CONFIG_ARCH_OMAP1 |
4318f36b CM |
754 | /* |
755 | * This only applies to chips that can't do both rising and falling edge | |
756 | * detection at once. For all other chips, this function is a noop. | |
757 | */ | |
758 | static void _toggle_gpio_edge_triggering(struct gpio_bank *bank, int gpio) | |
759 | { | |
760 | void __iomem *reg = bank->base; | |
761 | u32 l = 0; | |
762 | ||
763 | switch (bank->method) { | |
4318f36b CM |
764 | case METHOD_MPUIO: |
765 | reg += OMAP_MPUIO_GPIO_INT_EDGE; | |
766 | break; | |
4318f36b CM |
767 | #ifdef CONFIG_ARCH_OMAP15XX |
768 | case METHOD_GPIO_1510: | |
769 | reg += OMAP1510_GPIO_INT_CONTROL; | |
770 | break; | |
771 | #endif | |
772 | #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850) | |
773 | case METHOD_GPIO_7XX: | |
774 | reg += OMAP7XX_GPIO_INT_CONTROL; | |
775 | break; | |
776 | #endif | |
777 | default: | |
778 | return; | |
779 | } | |
780 | ||
781 | l = __raw_readl(reg); | |
782 | if ((l >> gpio) & 1) | |
783 | l &= ~(1 << gpio); | |
784 | else | |
785 | l |= 1 << gpio; | |
786 | ||
787 | __raw_writel(l, reg); | |
788 | } | |
9198bcd3 | 789 | #endif |
4318f36b | 790 | |
92105bb7 TL |
791 | static int _set_gpio_triggering(struct gpio_bank *bank, int gpio, int trigger) |
792 | { | |
793 | void __iomem *reg = bank->base; | |
794 | u32 l = 0; | |
5e1c5ff4 TL |
795 | |
796 | switch (bank->method) { | |
e5c56ed3 | 797 | #ifdef CONFIG_ARCH_OMAP1 |
5e1c5ff4 TL |
798 | case METHOD_MPUIO: |
799 | reg += OMAP_MPUIO_GPIO_INT_EDGE; | |
800 | l = __raw_readl(reg); | |
29501577 | 801 | if ((trigger & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) |
4318f36b | 802 | bank->toggle_mask |= 1 << gpio; |
6cab4860 | 803 | if (trigger & IRQ_TYPE_EDGE_RISING) |
5e1c5ff4 | 804 | l |= 1 << gpio; |
6cab4860 | 805 | else if (trigger & IRQ_TYPE_EDGE_FALLING) |
5e1c5ff4 | 806 | l &= ~(1 << gpio); |
92105bb7 TL |
807 | else |
808 | goto bad; | |
5e1c5ff4 | 809 | break; |
e5c56ed3 DB |
810 | #endif |
811 | #ifdef CONFIG_ARCH_OMAP15XX | |
5e1c5ff4 TL |
812 | case METHOD_GPIO_1510: |
813 | reg += OMAP1510_GPIO_INT_CONTROL; | |
814 | l = __raw_readl(reg); | |
29501577 | 815 | if ((trigger & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) |
4318f36b | 816 | bank->toggle_mask |= 1 << gpio; |
6cab4860 | 817 | if (trigger & IRQ_TYPE_EDGE_RISING) |
5e1c5ff4 | 818 | l |= 1 << gpio; |
6cab4860 | 819 | else if (trigger & IRQ_TYPE_EDGE_FALLING) |
5e1c5ff4 | 820 | l &= ~(1 << gpio); |
92105bb7 TL |
821 | else |
822 | goto bad; | |
5e1c5ff4 | 823 | break; |
e5c56ed3 | 824 | #endif |
3ac4fa99 | 825 | #ifdef CONFIG_ARCH_OMAP16XX |
5e1c5ff4 | 826 | case METHOD_GPIO_1610: |
5e1c5ff4 TL |
827 | if (gpio & 0x08) |
828 | reg += OMAP1610_GPIO_EDGE_CTRL2; | |
829 | else | |
830 | reg += OMAP1610_GPIO_EDGE_CTRL1; | |
831 | gpio &= 0x07; | |
832 | l = __raw_readl(reg); | |
833 | l &= ~(3 << (gpio << 1)); | |
6cab4860 | 834 | if (trigger & IRQ_TYPE_EDGE_RISING) |
6e60e79a | 835 | l |= 2 << (gpio << 1); |
6cab4860 | 836 | if (trigger & IRQ_TYPE_EDGE_FALLING) |
6e60e79a | 837 | l |= 1 << (gpio << 1); |
3ac4fa99 JY |
838 | if (trigger) |
839 | /* Enable wake-up during idle for dynamic tick */ | |
840 | __raw_writel(1 << gpio, bank->base + OMAP1610_GPIO_SET_WAKEUPENA); | |
841 | else | |
842 | __raw_writel(1 << gpio, bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA); | |
5e1c5ff4 | 843 | break; |
3ac4fa99 | 844 | #endif |
b718aa81 | 845 | #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850) |
7c006926 AB |
846 | case METHOD_GPIO_7XX: |
847 | reg += OMAP7XX_GPIO_INT_CONTROL; | |
56739a69 | 848 | l = __raw_readl(reg); |
29501577 | 849 | if ((trigger & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) |
4318f36b | 850 | bank->toggle_mask |= 1 << gpio; |
56739a69 ZM |
851 | if (trigger & IRQ_TYPE_EDGE_RISING) |
852 | l |= 1 << gpio; | |
853 | else if (trigger & IRQ_TYPE_EDGE_FALLING) | |
854 | l &= ~(1 << gpio); | |
855 | else | |
856 | goto bad; | |
857 | break; | |
858 | #endif | |
140455fa | 859 | #ifdef CONFIG_ARCH_OMAP2PLUS |
92105bb7 | 860 | case METHOD_GPIO_24XX: |
3f1686a9 | 861 | case METHOD_GPIO_44XX: |
3ac4fa99 | 862 | set_24xx_gpio_triggering(bank, gpio, trigger); |
5e1c5ff4 | 863 | break; |
3ac4fa99 | 864 | #endif |
5e1c5ff4 | 865 | default: |
92105bb7 | 866 | goto bad; |
5e1c5ff4 | 867 | } |
92105bb7 TL |
868 | __raw_writel(l, reg); |
869 | return 0; | |
870 | bad: | |
871 | return -EINVAL; | |
5e1c5ff4 TL |
872 | } |
873 | ||
92105bb7 | 874 | static int gpio_irq_type(unsigned irq, unsigned type) |
5e1c5ff4 TL |
875 | { |
876 | struct gpio_bank *bank; | |
92105bb7 TL |
877 | unsigned gpio; |
878 | int retval; | |
a6472533 | 879 | unsigned long flags; |
92105bb7 | 880 | |
5492fb1a | 881 | if (!cpu_class_is_omap2() && irq > IH_MPUIO_BASE) |
92105bb7 TL |
882 | gpio = OMAP_MPUIO(irq - IH_MPUIO_BASE); |
883 | else | |
884 | gpio = irq - IH_GPIO_BASE; | |
5e1c5ff4 TL |
885 | |
886 | if (check_gpio(gpio) < 0) | |
92105bb7 TL |
887 | return -EINVAL; |
888 | ||
e5c56ed3 | 889 | if (type & ~IRQ_TYPE_SENSE_MASK) |
6e60e79a | 890 | return -EINVAL; |
e5c56ed3 DB |
891 | |
892 | /* OMAP1 allows only only edge triggering */ | |
5492fb1a | 893 | if (!cpu_class_is_omap2() |
e5c56ed3 | 894 | && (type & (IRQ_TYPE_LEVEL_LOW|IRQ_TYPE_LEVEL_HIGH))) |
92105bb7 TL |
895 | return -EINVAL; |
896 | ||
58781016 | 897 | bank = get_irq_chip_data(irq); |
a6472533 | 898 | spin_lock_irqsave(&bank->lock, flags); |
92105bb7 | 899 | retval = _set_gpio_triggering(bank, get_gpio_index(gpio), type); |
b9772a22 DB |
900 | if (retval == 0) { |
901 | irq_desc[irq].status &= ~IRQ_TYPE_SENSE_MASK; | |
902 | irq_desc[irq].status |= type; | |
903 | } | |
a6472533 | 904 | spin_unlock_irqrestore(&bank->lock, flags); |
672e302e KH |
905 | |
906 | if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH)) | |
907 | __set_irq_handler_unlocked(irq, handle_level_irq); | |
908 | else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)) | |
909 | __set_irq_handler_unlocked(irq, handle_edge_irq); | |
910 | ||
92105bb7 | 911 | return retval; |
5e1c5ff4 TL |
912 | } |
913 | ||
914 | static void _clear_gpio_irqbank(struct gpio_bank *bank, int gpio_mask) | |
915 | { | |
92105bb7 | 916 | void __iomem *reg = bank->base; |
5e1c5ff4 TL |
917 | |
918 | switch (bank->method) { | |
e5c56ed3 | 919 | #ifdef CONFIG_ARCH_OMAP1 |
5e1c5ff4 TL |
920 | case METHOD_MPUIO: |
921 | /* MPUIO irqstatus is reset by reading the status register, | |
922 | * so do nothing here */ | |
923 | return; | |
e5c56ed3 DB |
924 | #endif |
925 | #ifdef CONFIG_ARCH_OMAP15XX | |
5e1c5ff4 TL |
926 | case METHOD_GPIO_1510: |
927 | reg += OMAP1510_GPIO_INT_STATUS; | |
928 | break; | |
e5c56ed3 DB |
929 | #endif |
930 | #ifdef CONFIG_ARCH_OMAP16XX | |
5e1c5ff4 TL |
931 | case METHOD_GPIO_1610: |
932 | reg += OMAP1610_GPIO_IRQSTATUS1; | |
933 | break; | |
e5c56ed3 | 934 | #endif |
b718aa81 | 935 | #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850) |
7c006926 AB |
936 | case METHOD_GPIO_7XX: |
937 | reg += OMAP7XX_GPIO_INT_STATUS; | |
56739a69 ZM |
938 | break; |
939 | #endif | |
a8eb7ca0 | 940 | #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) |
92105bb7 TL |
941 | case METHOD_GPIO_24XX: |
942 | reg += OMAP24XX_GPIO_IRQSTATUS1; | |
943 | break; | |
78a1a6d3 SR |
944 | #endif |
945 | #if defined(CONFIG_ARCH_OMAP4) | |
3f1686a9 | 946 | case METHOD_GPIO_44XX: |
78a1a6d3 SR |
947 | reg += OMAP4_GPIO_IRQSTATUS0; |
948 | break; | |
e5c56ed3 | 949 | #endif |
5e1c5ff4 | 950 | default: |
e5c56ed3 | 951 | WARN_ON(1); |
5e1c5ff4 TL |
952 | return; |
953 | } | |
954 | __raw_writel(gpio_mask, reg); | |
bee7930f HD |
955 | |
956 | /* Workaround for clearing DSP GPIO interrupts to allow retention */ | |
3f1686a9 TL |
957 | if (cpu_is_omap24xx() || cpu_is_omap34xx()) |
958 | reg = bank->base + OMAP24XX_GPIO_IRQSTATUS2; | |
959 | else if (cpu_is_omap44xx()) | |
960 | reg = bank->base + OMAP4_GPIO_IRQSTATUS1; | |
961 | ||
78a1a6d3 | 962 | if (cpu_is_omap24xx() || cpu_is_omap34xx() || cpu_is_omap44xx()) { |
bedfd154 RQ |
963 | __raw_writel(gpio_mask, reg); |
964 | ||
965 | /* Flush posted write for the irq status to avoid spurious interrupts */ | |
966 | __raw_readl(reg); | |
78a1a6d3 | 967 | } |
5e1c5ff4 TL |
968 | } |
969 | ||
970 | static inline void _clear_gpio_irqstatus(struct gpio_bank *bank, int gpio) | |
971 | { | |
972 | _clear_gpio_irqbank(bank, 1 << get_gpio_index(gpio)); | |
973 | } | |
974 | ||
ea6dedd7 ID |
975 | static u32 _get_gpio_irqbank_mask(struct gpio_bank *bank) |
976 | { | |
977 | void __iomem *reg = bank->base; | |
99c47707 ID |
978 | int inv = 0; |
979 | u32 l; | |
980 | u32 mask; | |
ea6dedd7 ID |
981 | |
982 | switch (bank->method) { | |
e5c56ed3 | 983 | #ifdef CONFIG_ARCH_OMAP1 |
ea6dedd7 ID |
984 | case METHOD_MPUIO: |
985 | reg += OMAP_MPUIO_GPIO_MASKIT; | |
99c47707 ID |
986 | mask = 0xffff; |
987 | inv = 1; | |
ea6dedd7 | 988 | break; |
e5c56ed3 DB |
989 | #endif |
990 | #ifdef CONFIG_ARCH_OMAP15XX | |
ea6dedd7 ID |
991 | case METHOD_GPIO_1510: |
992 | reg += OMAP1510_GPIO_INT_MASK; | |
99c47707 ID |
993 | mask = 0xffff; |
994 | inv = 1; | |
ea6dedd7 | 995 | break; |
e5c56ed3 DB |
996 | #endif |
997 | #ifdef CONFIG_ARCH_OMAP16XX | |
ea6dedd7 ID |
998 | case METHOD_GPIO_1610: |
999 | reg += OMAP1610_GPIO_IRQENABLE1; | |
99c47707 | 1000 | mask = 0xffff; |
ea6dedd7 | 1001 | break; |
e5c56ed3 | 1002 | #endif |
b718aa81 | 1003 | #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850) |
7c006926 AB |
1004 | case METHOD_GPIO_7XX: |
1005 | reg += OMAP7XX_GPIO_INT_MASK; | |
56739a69 ZM |
1006 | mask = 0xffffffff; |
1007 | inv = 1; | |
1008 | break; | |
1009 | #endif | |
a8eb7ca0 | 1010 | #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) |
ea6dedd7 ID |
1011 | case METHOD_GPIO_24XX: |
1012 | reg += OMAP24XX_GPIO_IRQENABLE1; | |
99c47707 | 1013 | mask = 0xffffffff; |
ea6dedd7 | 1014 | break; |
78a1a6d3 SR |
1015 | #endif |
1016 | #if defined(CONFIG_ARCH_OMAP4) | |
3f1686a9 | 1017 | case METHOD_GPIO_44XX: |
78a1a6d3 SR |
1018 | reg += OMAP4_GPIO_IRQSTATUSSET0; |
1019 | mask = 0xffffffff; | |
1020 | break; | |
e5c56ed3 | 1021 | #endif |
ea6dedd7 | 1022 | default: |
e5c56ed3 | 1023 | WARN_ON(1); |
ea6dedd7 ID |
1024 | return 0; |
1025 | } | |
1026 | ||
99c47707 ID |
1027 | l = __raw_readl(reg); |
1028 | if (inv) | |
1029 | l = ~l; | |
1030 | l &= mask; | |
1031 | return l; | |
ea6dedd7 ID |
1032 | } |
1033 | ||
5e1c5ff4 TL |
1034 | static void _enable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask, int enable) |
1035 | { | |
92105bb7 | 1036 | void __iomem *reg = bank->base; |
5e1c5ff4 TL |
1037 | u32 l; |
1038 | ||
1039 | switch (bank->method) { | |
e5c56ed3 | 1040 | #ifdef CONFIG_ARCH_OMAP1 |
5e1c5ff4 TL |
1041 | case METHOD_MPUIO: |
1042 | reg += OMAP_MPUIO_GPIO_MASKIT; | |
1043 | l = __raw_readl(reg); | |
1044 | if (enable) | |
1045 | l &= ~(gpio_mask); | |
1046 | else | |
1047 | l |= gpio_mask; | |
1048 | break; | |
e5c56ed3 DB |
1049 | #endif |
1050 | #ifdef CONFIG_ARCH_OMAP15XX | |
5e1c5ff4 TL |
1051 | case METHOD_GPIO_1510: |
1052 | reg += OMAP1510_GPIO_INT_MASK; | |
1053 | l = __raw_readl(reg); | |
1054 | if (enable) | |
1055 | l &= ~(gpio_mask); | |
1056 | else | |
1057 | l |= gpio_mask; | |
1058 | break; | |
e5c56ed3 DB |
1059 | #endif |
1060 | #ifdef CONFIG_ARCH_OMAP16XX | |
5e1c5ff4 TL |
1061 | case METHOD_GPIO_1610: |
1062 | if (enable) | |
1063 | reg += OMAP1610_GPIO_SET_IRQENABLE1; | |
1064 | else | |
1065 | reg += OMAP1610_GPIO_CLEAR_IRQENABLE1; | |
1066 | l = gpio_mask; | |
1067 | break; | |
e5c56ed3 | 1068 | #endif |
b718aa81 | 1069 | #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850) |
7c006926 AB |
1070 | case METHOD_GPIO_7XX: |
1071 | reg += OMAP7XX_GPIO_INT_MASK; | |
56739a69 ZM |
1072 | l = __raw_readl(reg); |
1073 | if (enable) | |
1074 | l &= ~(gpio_mask); | |
1075 | else | |
1076 | l |= gpio_mask; | |
1077 | break; | |
1078 | #endif | |
a8eb7ca0 | 1079 | #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) |
92105bb7 TL |
1080 | case METHOD_GPIO_24XX: |
1081 | if (enable) | |
1082 | reg += OMAP24XX_GPIO_SETIRQENABLE1; | |
1083 | else | |
1084 | reg += OMAP24XX_GPIO_CLEARIRQENABLE1; | |
1085 | l = gpio_mask; | |
1086 | break; | |
78a1a6d3 SR |
1087 | #endif |
1088 | #ifdef CONFIG_ARCH_OMAP4 | |
3f1686a9 | 1089 | case METHOD_GPIO_44XX: |
78a1a6d3 SR |
1090 | if (enable) |
1091 | reg += OMAP4_GPIO_IRQSTATUSSET0; | |
1092 | else | |
1093 | reg += OMAP4_GPIO_IRQSTATUSCLR0; | |
1094 | l = gpio_mask; | |
1095 | break; | |
e5c56ed3 | 1096 | #endif |
5e1c5ff4 | 1097 | default: |
e5c56ed3 | 1098 | WARN_ON(1); |
5e1c5ff4 TL |
1099 | return; |
1100 | } | |
1101 | __raw_writel(l, reg); | |
1102 | } | |
1103 | ||
1104 | static inline void _set_gpio_irqenable(struct gpio_bank *bank, int gpio, int enable) | |
1105 | { | |
1106 | _enable_gpio_irqbank(bank, 1 << get_gpio_index(gpio), enable); | |
1107 | } | |
1108 | ||
92105bb7 TL |
1109 | /* |
1110 | * Note that ENAWAKEUP needs to be enabled in GPIO_SYSCONFIG register. | |
1111 | * 1510 does not seem to have a wake-up register. If JTAG is connected | |
1112 | * to the target, system will wake up always on GPIO events. While | |
1113 | * system is running all registered GPIO interrupts need to have wake-up | |
1114 | * enabled. When system is suspended, only selected GPIO interrupts need | |
1115 | * to have wake-up enabled. | |
1116 | */ | |
1117 | static int _set_gpio_wakeup(struct gpio_bank *bank, int gpio, int enable) | |
1118 | { | |
4cc6420c | 1119 | unsigned long uninitialized_var(flags); |
a6472533 | 1120 | |
92105bb7 | 1121 | switch (bank->method) { |
3ac4fa99 | 1122 | #ifdef CONFIG_ARCH_OMAP16XX |
11a78b79 | 1123 | case METHOD_MPUIO: |
92105bb7 | 1124 | case METHOD_GPIO_1610: |
a6472533 | 1125 | spin_lock_irqsave(&bank->lock, flags); |
b3bb4f68 | 1126 | if (enable) |
92105bb7 | 1127 | bank->suspend_wakeup |= (1 << gpio); |
b3bb4f68 | 1128 | else |
92105bb7 | 1129 | bank->suspend_wakeup &= ~(1 << gpio); |
a6472533 | 1130 | spin_unlock_irqrestore(&bank->lock, flags); |
92105bb7 | 1131 | return 0; |
3ac4fa99 | 1132 | #endif |
140455fa | 1133 | #ifdef CONFIG_ARCH_OMAP2PLUS |
3ac4fa99 | 1134 | case METHOD_GPIO_24XX: |
3f1686a9 | 1135 | case METHOD_GPIO_44XX: |
11a78b79 DB |
1136 | if (bank->non_wakeup_gpios & (1 << gpio)) { |
1137 | printk(KERN_ERR "Unable to modify wakeup on " | |
1138 | "non-wakeup GPIO%d\n", | |
1139 | (bank - gpio_bank) * 32 + gpio); | |
1140 | return -EINVAL; | |
1141 | } | |
a6472533 | 1142 | spin_lock_irqsave(&bank->lock, flags); |
b3bb4f68 | 1143 | if (enable) |
3ac4fa99 | 1144 | bank->suspend_wakeup |= (1 << gpio); |
b3bb4f68 | 1145 | else |
3ac4fa99 | 1146 | bank->suspend_wakeup &= ~(1 << gpio); |
a6472533 | 1147 | spin_unlock_irqrestore(&bank->lock, flags); |
3ac4fa99 JY |
1148 | return 0; |
1149 | #endif | |
92105bb7 TL |
1150 | default: |
1151 | printk(KERN_ERR "Can't enable GPIO wakeup for method %i\n", | |
1152 | bank->method); | |
1153 | return -EINVAL; | |
1154 | } | |
1155 | } | |
1156 | ||
4196dd6b TL |
1157 | static void _reset_gpio(struct gpio_bank *bank, int gpio) |
1158 | { | |
1159 | _set_gpio_direction(bank, get_gpio_index(gpio), 1); | |
1160 | _set_gpio_irqenable(bank, gpio, 0); | |
1161 | _clear_gpio_irqstatus(bank, gpio); | |
6cab4860 | 1162 | _set_gpio_triggering(bank, get_gpio_index(gpio), IRQ_TYPE_NONE); |
4196dd6b TL |
1163 | } |
1164 | ||
92105bb7 TL |
1165 | /* Use disable_irq_wake() and enable_irq_wake() functions from drivers */ |
1166 | static int gpio_wake_enable(unsigned int irq, unsigned int enable) | |
1167 | { | |
1168 | unsigned int gpio = irq - IH_GPIO_BASE; | |
1169 | struct gpio_bank *bank; | |
1170 | int retval; | |
1171 | ||
1172 | if (check_gpio(gpio) < 0) | |
1173 | return -ENODEV; | |
58781016 | 1174 | bank = get_irq_chip_data(irq); |
92105bb7 | 1175 | retval = _set_gpio_wakeup(bank, get_gpio_index(gpio), enable); |
92105bb7 TL |
1176 | |
1177 | return retval; | |
1178 | } | |
1179 | ||
3ff164e1 | 1180 | static int omap_gpio_request(struct gpio_chip *chip, unsigned offset) |
5e1c5ff4 | 1181 | { |
3ff164e1 | 1182 | struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip); |
a6472533 | 1183 | unsigned long flags; |
52e31344 | 1184 | |
a6472533 | 1185 | spin_lock_irqsave(&bank->lock, flags); |
92105bb7 | 1186 | |
4196dd6b TL |
1187 | /* Set trigger to none. You need to enable the desired trigger with |
1188 | * request_irq() or set_irq_type(). | |
1189 | */ | |
3ff164e1 | 1190 | _set_gpio_triggering(bank, offset, IRQ_TYPE_NONE); |
92105bb7 | 1191 | |
1a8bfa1e | 1192 | #ifdef CONFIG_ARCH_OMAP15XX |
5e1c5ff4 | 1193 | if (bank->method == METHOD_GPIO_1510) { |
92105bb7 | 1194 | void __iomem *reg; |
5e1c5ff4 | 1195 | |
92105bb7 | 1196 | /* Claim the pin for MPU */ |
5e1c5ff4 | 1197 | reg = bank->base + OMAP1510_GPIO_PIN_CONTROL; |
3ff164e1 | 1198 | __raw_writel(__raw_readl(reg) | (1 << offset), reg); |
5e1c5ff4 TL |
1199 | } |
1200 | #endif | |
058af1ea C |
1201 | if (!cpu_class_is_omap1()) { |
1202 | if (!bank->mod_usage) { | |
1203 | u32 ctrl; | |
1204 | ctrl = __raw_readl(bank->base + OMAP24XX_GPIO_CTRL); | |
1205 | ctrl &= 0xFFFFFFFE; | |
1206 | /* Module is enabled, clocks are not gated */ | |
1207 | __raw_writel(ctrl, bank->base + OMAP24XX_GPIO_CTRL); | |
1208 | } | |
1209 | bank->mod_usage |= 1 << offset; | |
1210 | } | |
a6472533 | 1211 | spin_unlock_irqrestore(&bank->lock, flags); |
5e1c5ff4 TL |
1212 | |
1213 | return 0; | |
1214 | } | |
1215 | ||
3ff164e1 | 1216 | static void omap_gpio_free(struct gpio_chip *chip, unsigned offset) |
5e1c5ff4 | 1217 | { |
3ff164e1 | 1218 | struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip); |
a6472533 | 1219 | unsigned long flags; |
5e1c5ff4 | 1220 | |
a6472533 | 1221 | spin_lock_irqsave(&bank->lock, flags); |
92105bb7 TL |
1222 | #ifdef CONFIG_ARCH_OMAP16XX |
1223 | if (bank->method == METHOD_GPIO_1610) { | |
1224 | /* Disable wake-up during idle for dynamic tick */ | |
1225 | void __iomem *reg = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA; | |
3ff164e1 | 1226 | __raw_writel(1 << offset, reg); |
92105bb7 TL |
1227 | } |
1228 | #endif | |
140455fa | 1229 | #ifdef CONFIG_ARCH_OMAP2PLUS |
3f1686a9 TL |
1230 | if ((bank->method == METHOD_GPIO_24XX) || |
1231 | (bank->method == METHOD_GPIO_44XX)) { | |
92105bb7 TL |
1232 | /* Disable wake-up during idle for dynamic tick */ |
1233 | void __iomem *reg = bank->base + OMAP24XX_GPIO_CLEARWKUENA; | |
3ff164e1 | 1234 | __raw_writel(1 << offset, reg); |
92105bb7 TL |
1235 | } |
1236 | #endif | |
058af1ea C |
1237 | if (!cpu_class_is_omap1()) { |
1238 | bank->mod_usage &= ~(1 << offset); | |
1239 | if (!bank->mod_usage) { | |
1240 | u32 ctrl; | |
1241 | ctrl = __raw_readl(bank->base + OMAP24XX_GPIO_CTRL); | |
1242 | /* Module is disabled, clocks are gated */ | |
1243 | ctrl |= 1; | |
1244 | __raw_writel(ctrl, bank->base + OMAP24XX_GPIO_CTRL); | |
1245 | } | |
1246 | } | |
3ff164e1 | 1247 | _reset_gpio(bank, bank->chip.base + offset); |
a6472533 | 1248 | spin_unlock_irqrestore(&bank->lock, flags); |
5e1c5ff4 TL |
1249 | } |
1250 | ||
1251 | /* | |
1252 | * We need to unmask the GPIO bank interrupt as soon as possible to | |
1253 | * avoid missing GPIO interrupts for other lines in the bank. | |
1254 | * Then we need to mask-read-clear-unmask the triggered GPIO lines | |
1255 | * in the bank to avoid missing nested interrupts for a GPIO line. | |
1256 | * If we wait to unmask individual GPIO lines in the bank after the | |
1257 | * line's interrupt handler has been run, we may miss some nested | |
1258 | * interrupts. | |
1259 | */ | |
10dd5ce2 | 1260 | static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc) |
5e1c5ff4 | 1261 | { |
92105bb7 | 1262 | void __iomem *isr_reg = NULL; |
5e1c5ff4 | 1263 | u32 isr; |
4318f36b | 1264 | unsigned int gpio_irq, gpio_index; |
5e1c5ff4 | 1265 | struct gpio_bank *bank; |
ea6dedd7 ID |
1266 | u32 retrigger = 0; |
1267 | int unmasked = 0; | |
5e1c5ff4 TL |
1268 | |
1269 | desc->chip->ack(irq); | |
1270 | ||
418ca1f0 | 1271 | bank = get_irq_data(irq); |
e5c56ed3 | 1272 | #ifdef CONFIG_ARCH_OMAP1 |
5e1c5ff4 TL |
1273 | if (bank->method == METHOD_MPUIO) |
1274 | isr_reg = bank->base + OMAP_MPUIO_GPIO_INT; | |
e5c56ed3 | 1275 | #endif |
1a8bfa1e | 1276 | #ifdef CONFIG_ARCH_OMAP15XX |
5e1c5ff4 TL |
1277 | if (bank->method == METHOD_GPIO_1510) |
1278 | isr_reg = bank->base + OMAP1510_GPIO_INT_STATUS; | |
1279 | #endif | |
1280 | #if defined(CONFIG_ARCH_OMAP16XX) | |
1281 | if (bank->method == METHOD_GPIO_1610) | |
1282 | isr_reg = bank->base + OMAP1610_GPIO_IRQSTATUS1; | |
1283 | #endif | |
b718aa81 | 1284 | #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850) |
7c006926 AB |
1285 | if (bank->method == METHOD_GPIO_7XX) |
1286 | isr_reg = bank->base + OMAP7XX_GPIO_INT_STATUS; | |
56739a69 | 1287 | #endif |
a8eb7ca0 | 1288 | #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) |
92105bb7 TL |
1289 | if (bank->method == METHOD_GPIO_24XX) |
1290 | isr_reg = bank->base + OMAP24XX_GPIO_IRQSTATUS1; | |
78a1a6d3 SR |
1291 | #endif |
1292 | #if defined(CONFIG_ARCH_OMAP4) | |
3f1686a9 | 1293 | if (bank->method == METHOD_GPIO_44XX) |
78a1a6d3 | 1294 | isr_reg = bank->base + OMAP4_GPIO_IRQSTATUS0; |
92105bb7 | 1295 | #endif |
92105bb7 | 1296 | while(1) { |
6e60e79a | 1297 | u32 isr_saved, level_mask = 0; |
ea6dedd7 | 1298 | u32 enabled; |
6e60e79a | 1299 | |
ea6dedd7 ID |
1300 | enabled = _get_gpio_irqbank_mask(bank); |
1301 | isr_saved = isr = __raw_readl(isr_reg) & enabled; | |
6e60e79a TL |
1302 | |
1303 | if (cpu_is_omap15xx() && (bank->method == METHOD_MPUIO)) | |
1304 | isr &= 0x0000ffff; | |
1305 | ||
5492fb1a | 1306 | if (cpu_class_is_omap2()) { |
b144ff6f | 1307 | level_mask = bank->level_mask & enabled; |
ea6dedd7 | 1308 | } |
6e60e79a TL |
1309 | |
1310 | /* clear edge sensitive interrupts before handler(s) are | |
1311 | called so that we don't miss any interrupt occurred while | |
1312 | executing them */ | |
1313 | _enable_gpio_irqbank(bank, isr_saved & ~level_mask, 0); | |
1314 | _clear_gpio_irqbank(bank, isr_saved & ~level_mask); | |
1315 | _enable_gpio_irqbank(bank, isr_saved & ~level_mask, 1); | |
1316 | ||
1317 | /* if there is only edge sensitive GPIO pin interrupts | |
1318 | configured, we could unmask GPIO bank interrupt immediately */ | |
ea6dedd7 ID |
1319 | if (!level_mask && !unmasked) { |
1320 | unmasked = 1; | |
6e60e79a | 1321 | desc->chip->unmask(irq); |
ea6dedd7 | 1322 | } |
92105bb7 | 1323 | |
ea6dedd7 ID |
1324 | isr |= retrigger; |
1325 | retrigger = 0; | |
92105bb7 TL |
1326 | if (!isr) |
1327 | break; | |
1328 | ||
1329 | gpio_irq = bank->virtual_irq_start; | |
1330 | for (; isr != 0; isr >>= 1, gpio_irq++) { | |
4318f36b CM |
1331 | gpio_index = get_gpio_index(irq_to_gpio(gpio_irq)); |
1332 | ||
92105bb7 TL |
1333 | if (!(isr & 1)) |
1334 | continue; | |
29454dde | 1335 | |
4318f36b CM |
1336 | #ifdef CONFIG_ARCH_OMAP1 |
1337 | /* | |
1338 | * Some chips can't respond to both rising and falling | |
1339 | * at the same time. If this irq was requested with | |
1340 | * both flags, we need to flip the ICR data for the IRQ | |
1341 | * to respond to the IRQ for the opposite direction. | |
1342 | * This will be indicated in the bank toggle_mask. | |
1343 | */ | |
1344 | if (bank->toggle_mask & (1 << gpio_index)) | |
1345 | _toggle_gpio_edge_triggering(bank, gpio_index); | |
1346 | #endif | |
1347 | ||
d8aa0251 | 1348 | generic_handle_irq(gpio_irq); |
92105bb7 | 1349 | } |
1a8bfa1e | 1350 | } |
ea6dedd7 ID |
1351 | /* if bank has any level sensitive GPIO pin interrupt |
1352 | configured, we must unmask the bank interrupt only after | |
1353 | handler(s) are executed in order to avoid spurious bank | |
1354 | interrupt */ | |
1355 | if (!unmasked) | |
1356 | desc->chip->unmask(irq); | |
1357 | ||
5e1c5ff4 TL |
1358 | } |
1359 | ||
4196dd6b TL |
1360 | static void gpio_irq_shutdown(unsigned int irq) |
1361 | { | |
1362 | unsigned int gpio = irq - IH_GPIO_BASE; | |
58781016 | 1363 | struct gpio_bank *bank = get_irq_chip_data(irq); |
4196dd6b TL |
1364 | |
1365 | _reset_gpio(bank, gpio); | |
1366 | } | |
1367 | ||
5e1c5ff4 TL |
1368 | static void gpio_ack_irq(unsigned int irq) |
1369 | { | |
1370 | unsigned int gpio = irq - IH_GPIO_BASE; | |
58781016 | 1371 | struct gpio_bank *bank = get_irq_chip_data(irq); |
5e1c5ff4 TL |
1372 | |
1373 | _clear_gpio_irqstatus(bank, gpio); | |
1374 | } | |
1375 | ||
1376 | static void gpio_mask_irq(unsigned int irq) | |
1377 | { | |
1378 | unsigned int gpio = irq - IH_GPIO_BASE; | |
58781016 | 1379 | struct gpio_bank *bank = get_irq_chip_data(irq); |
5e1c5ff4 TL |
1380 | |
1381 | _set_gpio_irqenable(bank, gpio, 0); | |
55b6019a | 1382 | _set_gpio_triggering(bank, get_gpio_index(gpio), IRQ_TYPE_NONE); |
5e1c5ff4 TL |
1383 | } |
1384 | ||
1385 | static void gpio_unmask_irq(unsigned int irq) | |
1386 | { | |
1387 | unsigned int gpio = irq - IH_GPIO_BASE; | |
58781016 | 1388 | struct gpio_bank *bank = get_irq_chip_data(irq); |
b144ff6f | 1389 | unsigned int irq_mask = 1 << get_gpio_index(gpio); |
55b6019a KH |
1390 | struct irq_desc *desc = irq_to_desc(irq); |
1391 | u32 trigger = desc->status & IRQ_TYPE_SENSE_MASK; | |
1392 | ||
1393 | if (trigger) | |
1394 | _set_gpio_triggering(bank, get_gpio_index(gpio), trigger); | |
b144ff6f KH |
1395 | |
1396 | /* For level-triggered GPIOs, the clearing must be done after | |
1397 | * the HW source is cleared, thus after the handler has run */ | |
1398 | if (bank->level_mask & irq_mask) { | |
1399 | _set_gpio_irqenable(bank, gpio, 0); | |
1400 | _clear_gpio_irqstatus(bank, gpio); | |
1401 | } | |
5e1c5ff4 | 1402 | |
4de8c75b | 1403 | _set_gpio_irqenable(bank, gpio, 1); |
5e1c5ff4 TL |
1404 | } |
1405 | ||
e5c56ed3 DB |
1406 | static struct irq_chip gpio_irq_chip = { |
1407 | .name = "GPIO", | |
1408 | .shutdown = gpio_irq_shutdown, | |
1409 | .ack = gpio_ack_irq, | |
1410 | .mask = gpio_mask_irq, | |
1411 | .unmask = gpio_unmask_irq, | |
1412 | .set_type = gpio_irq_type, | |
1413 | .set_wake = gpio_wake_enable, | |
1414 | }; | |
1415 | ||
1416 | /*---------------------------------------------------------------------*/ | |
1417 | ||
1418 | #ifdef CONFIG_ARCH_OMAP1 | |
1419 | ||
1420 | /* MPUIO uses the always-on 32k clock */ | |
1421 | ||
5e1c5ff4 TL |
1422 | static void mpuio_ack_irq(unsigned int irq) |
1423 | { | |
1424 | /* The ISR is reset automatically, so do nothing here. */ | |
1425 | } | |
1426 | ||
1427 | static void mpuio_mask_irq(unsigned int irq) | |
1428 | { | |
1429 | unsigned int gpio = OMAP_MPUIO(irq - IH_MPUIO_BASE); | |
58781016 | 1430 | struct gpio_bank *bank = get_irq_chip_data(irq); |
5e1c5ff4 TL |
1431 | |
1432 | _set_gpio_irqenable(bank, gpio, 0); | |
1433 | } | |
1434 | ||
1435 | static void mpuio_unmask_irq(unsigned int irq) | |
1436 | { | |
1437 | unsigned int gpio = OMAP_MPUIO(irq - IH_MPUIO_BASE); | |
58781016 | 1438 | struct gpio_bank *bank = get_irq_chip_data(irq); |
5e1c5ff4 TL |
1439 | |
1440 | _set_gpio_irqenable(bank, gpio, 1); | |
1441 | } | |
1442 | ||
e5c56ed3 DB |
1443 | static struct irq_chip mpuio_irq_chip = { |
1444 | .name = "MPUIO", | |
1445 | .ack = mpuio_ack_irq, | |
1446 | .mask = mpuio_mask_irq, | |
1447 | .unmask = mpuio_unmask_irq, | |
92105bb7 | 1448 | .set_type = gpio_irq_type, |
11a78b79 DB |
1449 | #ifdef CONFIG_ARCH_OMAP16XX |
1450 | /* REVISIT: assuming only 16xx supports MPUIO wake events */ | |
1451 | .set_wake = gpio_wake_enable, | |
1452 | #endif | |
5e1c5ff4 TL |
1453 | }; |
1454 | ||
e5c56ed3 DB |
1455 | |
1456 | #define bank_is_mpuio(bank) ((bank)->method == METHOD_MPUIO) | |
1457 | ||
11a78b79 DB |
1458 | |
1459 | #ifdef CONFIG_ARCH_OMAP16XX | |
1460 | ||
1461 | #include <linux/platform_device.h> | |
1462 | ||
79ee031f | 1463 | static int omap_mpuio_suspend_noirq(struct device *dev) |
11a78b79 | 1464 | { |
79ee031f | 1465 | struct platform_device *pdev = to_platform_device(dev); |
11a78b79 DB |
1466 | struct gpio_bank *bank = platform_get_drvdata(pdev); |
1467 | void __iomem *mask_reg = bank->base + OMAP_MPUIO_GPIO_MASKIT; | |
a6472533 | 1468 | unsigned long flags; |
11a78b79 | 1469 | |
a6472533 | 1470 | spin_lock_irqsave(&bank->lock, flags); |
11a78b79 DB |
1471 | bank->saved_wakeup = __raw_readl(mask_reg); |
1472 | __raw_writel(0xffff & ~bank->suspend_wakeup, mask_reg); | |
a6472533 | 1473 | spin_unlock_irqrestore(&bank->lock, flags); |
11a78b79 DB |
1474 | |
1475 | return 0; | |
1476 | } | |
1477 | ||
79ee031f | 1478 | static int omap_mpuio_resume_noirq(struct device *dev) |
11a78b79 | 1479 | { |
79ee031f | 1480 | struct platform_device *pdev = to_platform_device(dev); |
11a78b79 DB |
1481 | struct gpio_bank *bank = platform_get_drvdata(pdev); |
1482 | void __iomem *mask_reg = bank->base + OMAP_MPUIO_GPIO_MASKIT; | |
a6472533 | 1483 | unsigned long flags; |
11a78b79 | 1484 | |
a6472533 | 1485 | spin_lock_irqsave(&bank->lock, flags); |
11a78b79 | 1486 | __raw_writel(bank->saved_wakeup, mask_reg); |
a6472533 | 1487 | spin_unlock_irqrestore(&bank->lock, flags); |
11a78b79 DB |
1488 | |
1489 | return 0; | |
1490 | } | |
1491 | ||
47145210 | 1492 | static const struct dev_pm_ops omap_mpuio_dev_pm_ops = { |
79ee031f MD |
1493 | .suspend_noirq = omap_mpuio_suspend_noirq, |
1494 | .resume_noirq = omap_mpuio_resume_noirq, | |
1495 | }; | |
1496 | ||
11a78b79 DB |
1497 | /* use platform_driver for this, now that there's no longer any |
1498 | * point to sys_device (other than not disturbing old code). | |
1499 | */ | |
1500 | static struct platform_driver omap_mpuio_driver = { | |
11a78b79 DB |
1501 | .driver = { |
1502 | .name = "mpuio", | |
79ee031f | 1503 | .pm = &omap_mpuio_dev_pm_ops, |
11a78b79 DB |
1504 | }, |
1505 | }; | |
1506 | ||
1507 | static struct platform_device omap_mpuio_device = { | |
1508 | .name = "mpuio", | |
1509 | .id = -1, | |
1510 | .dev = { | |
1511 | .driver = &omap_mpuio_driver.driver, | |
1512 | } | |
1513 | /* could list the /proc/iomem resources */ | |
1514 | }; | |
1515 | ||
1516 | static inline void mpuio_init(void) | |
1517 | { | |
fcf126d8 DB |
1518 | platform_set_drvdata(&omap_mpuio_device, &gpio_bank_1610[0]); |
1519 | ||
11a78b79 DB |
1520 | if (platform_driver_register(&omap_mpuio_driver) == 0) |
1521 | (void) platform_device_register(&omap_mpuio_device); | |
1522 | } | |
1523 | ||
1524 | #else | |
1525 | static inline void mpuio_init(void) {} | |
1526 | #endif /* 16xx */ | |
1527 | ||
e5c56ed3 DB |
1528 | #else |
1529 | ||
1530 | extern struct irq_chip mpuio_irq_chip; | |
1531 | ||
1532 | #define bank_is_mpuio(bank) 0 | |
11a78b79 | 1533 | static inline void mpuio_init(void) {} |
e5c56ed3 DB |
1534 | |
1535 | #endif | |
1536 | ||
1537 | /*---------------------------------------------------------------------*/ | |
5e1c5ff4 | 1538 | |
52e31344 DB |
1539 | /* REVISIT these are stupid implementations! replace by ones that |
1540 | * don't switch on METHOD_* and which mostly avoid spinlocks | |
1541 | */ | |
1542 | ||
1543 | static int gpio_input(struct gpio_chip *chip, unsigned offset) | |
1544 | { | |
1545 | struct gpio_bank *bank; | |
1546 | unsigned long flags; | |
1547 | ||
1548 | bank = container_of(chip, struct gpio_bank, chip); | |
1549 | spin_lock_irqsave(&bank->lock, flags); | |
1550 | _set_gpio_direction(bank, offset, 1); | |
1551 | spin_unlock_irqrestore(&bank->lock, flags); | |
1552 | return 0; | |
1553 | } | |
1554 | ||
b37c45b8 RQ |
1555 | static int gpio_is_input(struct gpio_bank *bank, int mask) |
1556 | { | |
1557 | void __iomem *reg = bank->base; | |
1558 | ||
1559 | switch (bank->method) { | |
1560 | case METHOD_MPUIO: | |
1561 | reg += OMAP_MPUIO_IO_CNTL; | |
1562 | break; | |
1563 | case METHOD_GPIO_1510: | |
1564 | reg += OMAP1510_GPIO_DIR_CONTROL; | |
1565 | break; | |
1566 | case METHOD_GPIO_1610: | |
1567 | reg += OMAP1610_GPIO_DIRECTION; | |
1568 | break; | |
7c006926 AB |
1569 | case METHOD_GPIO_7XX: |
1570 | reg += OMAP7XX_GPIO_DIR_CONTROL; | |
b37c45b8 RQ |
1571 | break; |
1572 | case METHOD_GPIO_24XX: | |
3f1686a9 | 1573 | case METHOD_GPIO_44XX: |
b37c45b8 RQ |
1574 | reg += OMAP24XX_GPIO_OE; |
1575 | break; | |
1576 | } | |
1577 | return __raw_readl(reg) & mask; | |
1578 | } | |
1579 | ||
52e31344 DB |
1580 | static int gpio_get(struct gpio_chip *chip, unsigned offset) |
1581 | { | |
b37c45b8 RQ |
1582 | struct gpio_bank *bank; |
1583 | void __iomem *reg; | |
1584 | int gpio; | |
1585 | u32 mask; | |
1586 | ||
1587 | gpio = chip->base + offset; | |
1588 | bank = get_gpio_bank(gpio); | |
1589 | reg = bank->base; | |
1590 | mask = 1 << get_gpio_index(gpio); | |
1591 | ||
1592 | if (gpio_is_input(bank, mask)) | |
1593 | return _get_gpio_datain(bank, gpio); | |
1594 | else | |
1595 | return _get_gpio_dataout(bank, gpio); | |
52e31344 DB |
1596 | } |
1597 | ||
1598 | static int gpio_output(struct gpio_chip *chip, unsigned offset, int value) | |
1599 | { | |
1600 | struct gpio_bank *bank; | |
1601 | unsigned long flags; | |
1602 | ||
1603 | bank = container_of(chip, struct gpio_bank, chip); | |
1604 | spin_lock_irqsave(&bank->lock, flags); | |
1605 | _set_gpio_dataout(bank, offset, value); | |
1606 | _set_gpio_direction(bank, offset, 0); | |
1607 | spin_unlock_irqrestore(&bank->lock, flags); | |
1608 | return 0; | |
1609 | } | |
1610 | ||
1611 | static void gpio_set(struct gpio_chip *chip, unsigned offset, int value) | |
1612 | { | |
1613 | struct gpio_bank *bank; | |
1614 | unsigned long flags; | |
1615 | ||
1616 | bank = container_of(chip, struct gpio_bank, chip); | |
1617 | spin_lock_irqsave(&bank->lock, flags); | |
1618 | _set_gpio_dataout(bank, offset, value); | |
1619 | spin_unlock_irqrestore(&bank->lock, flags); | |
1620 | } | |
1621 | ||
a007b709 DB |
1622 | static int gpio_2irq(struct gpio_chip *chip, unsigned offset) |
1623 | { | |
1624 | struct gpio_bank *bank; | |
1625 | ||
1626 | bank = container_of(chip, struct gpio_bank, chip); | |
1627 | return bank->virtual_irq_start + offset; | |
1628 | } | |
1629 | ||
52e31344 DB |
1630 | /*---------------------------------------------------------------------*/ |
1631 | ||
1a8bfa1e | 1632 | static int initialized; |
56213ca4 | 1633 | #if defined(CONFIG_ARCH_OMAP1) || defined(CONFIG_ARCH_OMAP2) |
1a8bfa1e | 1634 | static struct clk * gpio_ick; |
5492fb1a SMK |
1635 | #endif |
1636 | ||
1637 | #if defined(CONFIG_ARCH_OMAP2) | |
1a8bfa1e | 1638 | static struct clk * gpio_fck; |
5492fb1a | 1639 | #endif |
5e1c5ff4 | 1640 | |
5492fb1a | 1641 | #if defined(CONFIG_ARCH_OMAP2430) |
56a25641 SMK |
1642 | static struct clk * gpio5_ick; |
1643 | static struct clk * gpio5_fck; | |
1644 | #endif | |
1645 | ||
44169075 | 1646 | #if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4) |
5492fb1a SMK |
1647 | static struct clk *gpio_iclks[OMAP34XX_NR_GPIOS]; |
1648 | #endif | |
1649 | ||
9f7065da TL |
1650 | static void __init omap_gpio_show_rev(void) |
1651 | { | |
1652 | u32 rev; | |
1653 | ||
1654 | if (cpu_is_omap16xx()) | |
1655 | rev = __raw_readw(gpio_bank[1].base + OMAP1610_GPIO_REVISION); | |
1656 | else if (cpu_is_omap24xx() || cpu_is_omap34xx()) | |
1657 | rev = __raw_readl(gpio_bank[0].base + OMAP24XX_GPIO_REVISION); | |
1658 | else if (cpu_is_omap44xx()) | |
1659 | rev = __raw_readl(gpio_bank[0].base + OMAP4_GPIO_REVISION); | |
1660 | else | |
1661 | return; | |
1662 | ||
1663 | printk(KERN_INFO "OMAP GPIO hardware version %d.%d\n", | |
1664 | (rev >> 4) & 0x0f, rev & 0x0f); | |
1665 | } | |
1666 | ||
8ba55c5c DB |
1667 | /* This lock class tells lockdep that GPIO irqs are in a different |
1668 | * category than their parents, so it won't report false recursion. | |
1669 | */ | |
1670 | static struct lock_class_key gpio_lock_class; | |
1671 | ||
5e1c5ff4 TL |
1672 | static int __init _omap_gpio_init(void) |
1673 | { | |
1674 | int i; | |
52e31344 | 1675 | int gpio = 0; |
5e1c5ff4 | 1676 | struct gpio_bank *bank; |
9f7065da | 1677 | int bank_size = SZ_8K; /* Module 4KB + L4 4KB except on omap1 */ |
5492fb1a | 1678 | char clk_name[11]; |
5e1c5ff4 TL |
1679 | |
1680 | initialized = 1; | |
1681 | ||
5492fb1a | 1682 | #if defined(CONFIG_ARCH_OMAP1) |
6e60e79a | 1683 | if (cpu_is_omap15xx()) { |
1a8bfa1e TL |
1684 | gpio_ick = clk_get(NULL, "arm_gpio_ck"); |
1685 | if (IS_ERR(gpio_ick)) | |
92105bb7 TL |
1686 | printk("Could not get arm_gpio_ck\n"); |
1687 | else | |
30ff720b | 1688 | clk_enable(gpio_ick); |
1a8bfa1e | 1689 | } |
5492fb1a SMK |
1690 | #endif |
1691 | #if defined(CONFIG_ARCH_OMAP2) | |
1692 | if (cpu_class_is_omap2()) { | |
1a8bfa1e TL |
1693 | gpio_ick = clk_get(NULL, "gpios_ick"); |
1694 | if (IS_ERR(gpio_ick)) | |
1695 | printk("Could not get gpios_ick\n"); | |
1696 | else | |
30ff720b | 1697 | clk_enable(gpio_ick); |
1a8bfa1e | 1698 | gpio_fck = clk_get(NULL, "gpios_fck"); |
1630b52d | 1699 | if (IS_ERR(gpio_fck)) |
1a8bfa1e TL |
1700 | printk("Could not get gpios_fck\n"); |
1701 | else | |
30ff720b | 1702 | clk_enable(gpio_fck); |
56a25641 SMK |
1703 | |
1704 | /* | |
5492fb1a | 1705 | * On 2430 & 3430 GPIO 5 uses CORE L4 ICLK |
56a25641 | 1706 | */ |
5492fb1a | 1707 | #if defined(CONFIG_ARCH_OMAP2430) |
56a25641 SMK |
1708 | if (cpu_is_omap2430()) { |
1709 | gpio5_ick = clk_get(NULL, "gpio5_ick"); | |
1710 | if (IS_ERR(gpio5_ick)) | |
1711 | printk("Could not get gpio5_ick\n"); | |
1712 | else | |
1713 | clk_enable(gpio5_ick); | |
1714 | gpio5_fck = clk_get(NULL, "gpio5_fck"); | |
1715 | if (IS_ERR(gpio5_fck)) | |
1716 | printk("Could not get gpio5_fck\n"); | |
1717 | else | |
1718 | clk_enable(gpio5_fck); | |
1719 | } | |
1720 | #endif | |
5492fb1a SMK |
1721 | } |
1722 | #endif | |
1723 | ||
44169075 SS |
1724 | #if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4) |
1725 | if (cpu_is_omap34xx() || cpu_is_omap44xx()) { | |
5492fb1a SMK |
1726 | for (i = 0; i < OMAP34XX_NR_GPIOS; i++) { |
1727 | sprintf(clk_name, "gpio%d_ick", i + 1); | |
1728 | gpio_iclks[i] = clk_get(NULL, clk_name); | |
1729 | if (IS_ERR(gpio_iclks[i])) | |
1730 | printk(KERN_ERR "Could not get %s\n", clk_name); | |
1731 | else | |
1732 | clk_enable(gpio_iclks[i]); | |
5492fb1a SMK |
1733 | } |
1734 | } | |
1735 | #endif | |
1736 | ||
92105bb7 | 1737 | |
1a8bfa1e | 1738 | #ifdef CONFIG_ARCH_OMAP15XX |
6e60e79a | 1739 | if (cpu_is_omap15xx()) { |
5e1c5ff4 TL |
1740 | gpio_bank_count = 2; |
1741 | gpio_bank = gpio_bank_1510; | |
9f7065da | 1742 | bank_size = SZ_2K; |
5e1c5ff4 TL |
1743 | } |
1744 | #endif | |
1745 | #if defined(CONFIG_ARCH_OMAP16XX) | |
1746 | if (cpu_is_omap16xx()) { | |
5e1c5ff4 TL |
1747 | gpio_bank_count = 5; |
1748 | gpio_bank = gpio_bank_1610; | |
9f7065da | 1749 | bank_size = SZ_2K; |
5e1c5ff4 TL |
1750 | } |
1751 | #endif | |
b718aa81 AB |
1752 | #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850) |
1753 | if (cpu_is_omap7xx()) { | |
56739a69 | 1754 | gpio_bank_count = 7; |
7c006926 | 1755 | gpio_bank = gpio_bank_7xx; |
9f7065da | 1756 | bank_size = SZ_2K; |
56739a69 ZM |
1757 | } |
1758 | #endif | |
088ef950 | 1759 | #ifdef CONFIG_ARCH_OMAP2 |
56a25641 | 1760 | if (cpu_is_omap242x()) { |
92105bb7 | 1761 | gpio_bank_count = 4; |
56a25641 | 1762 | gpio_bank = gpio_bank_242x; |
56a25641 SMK |
1763 | } |
1764 | if (cpu_is_omap243x()) { | |
56a25641 SMK |
1765 | gpio_bank_count = 5; |
1766 | gpio_bank = gpio_bank_243x; | |
92105bb7 | 1767 | } |
5492fb1a | 1768 | #endif |
a8eb7ca0 | 1769 | #ifdef CONFIG_ARCH_OMAP3 |
5492fb1a | 1770 | if (cpu_is_omap34xx()) { |
5492fb1a SMK |
1771 | gpio_bank_count = OMAP34XX_NR_GPIOS; |
1772 | gpio_bank = gpio_bank_34xx; | |
5492fb1a | 1773 | } |
44169075 SS |
1774 | #endif |
1775 | #ifdef CONFIG_ARCH_OMAP4 | |
1776 | if (cpu_is_omap44xx()) { | |
44169075 SS |
1777 | gpio_bank_count = OMAP34XX_NR_GPIOS; |
1778 | gpio_bank = gpio_bank_44xx; | |
44169075 | 1779 | } |
5e1c5ff4 TL |
1780 | #endif |
1781 | for (i = 0; i < gpio_bank_count; i++) { | |
1782 | int j, gpio_count = 16; | |
1783 | ||
1784 | bank = &gpio_bank[i]; | |
5e1c5ff4 | 1785 | spin_lock_init(&bank->lock); |
9f7065da TL |
1786 | |
1787 | /* Static mapping, never released */ | |
1788 | bank->base = ioremap(bank->pbase, bank_size); | |
1789 | if (!bank->base) { | |
1790 | printk(KERN_ERR "Could not ioremap gpio bank%i\n", i); | |
1791 | continue; | |
1792 | } | |
1793 | ||
e5c56ed3 | 1794 | if (bank_is_mpuio(bank)) |
7c7095aa | 1795 | __raw_writew(0xffff, bank->base + OMAP_MPUIO_GPIO_MASKIT); |
d11ac979 | 1796 | if (cpu_is_omap15xx() && bank->method == METHOD_GPIO_1510) { |
5e1c5ff4 TL |
1797 | __raw_writew(0xffff, bank->base + OMAP1510_GPIO_INT_MASK); |
1798 | __raw_writew(0x0000, bank->base + OMAP1510_GPIO_INT_STATUS); | |
1799 | } | |
d11ac979 | 1800 | if (cpu_is_omap16xx() && bank->method == METHOD_GPIO_1610) { |
5e1c5ff4 TL |
1801 | __raw_writew(0x0000, bank->base + OMAP1610_GPIO_IRQENABLE1); |
1802 | __raw_writew(0xffff, bank->base + OMAP1610_GPIO_IRQSTATUS1); | |
92105bb7 | 1803 | __raw_writew(0x0014, bank->base + OMAP1610_GPIO_SYSCONFIG); |
5e1c5ff4 | 1804 | } |
7c006926 AB |
1805 | if (cpu_is_omap7xx() && bank->method == METHOD_GPIO_7XX) { |
1806 | __raw_writel(0xffffffff, bank->base + OMAP7XX_GPIO_INT_MASK); | |
1807 | __raw_writel(0x00000000, bank->base + OMAP7XX_GPIO_INT_STATUS); | |
5e1c5ff4 | 1808 | |
7c006926 | 1809 | gpio_count = 32; /* 7xx has 32-bit GPIOs */ |
5e1c5ff4 | 1810 | } |
d11ac979 | 1811 | |
140455fa | 1812 | #ifdef CONFIG_ARCH_OMAP2PLUS |
3f1686a9 TL |
1813 | if ((bank->method == METHOD_GPIO_24XX) || |
1814 | (bank->method == METHOD_GPIO_44XX)) { | |
3ac4fa99 JY |
1815 | static const u32 non_wakeup_gpios[] = { |
1816 | 0xe203ffc0, 0x08700040 | |
1817 | }; | |
3f1686a9 TL |
1818 | |
1819 | if (cpu_is_omap44xx()) { | |
1820 | __raw_writel(0xffffffff, bank->base + | |
78a1a6d3 | 1821 | OMAP4_GPIO_IRQSTATUSCLR0); |
3f1686a9 | 1822 | __raw_writew(0x0015, bank->base + |
78a1a6d3 | 1823 | OMAP4_GPIO_SYSCONFIG); |
3f1686a9 | 1824 | __raw_writel(0x00000000, bank->base + |
78a1a6d3 | 1825 | OMAP4_GPIO_DEBOUNCENABLE); |
3f1686a9 TL |
1826 | /* |
1827 | * Initialize interface clock ungated, | |
1828 | * module enabled | |
1829 | */ | |
1830 | __raw_writel(0, bank->base + OMAP4_GPIO_CTRL); | |
1831 | } else { | |
1832 | __raw_writel(0x00000000, bank->base + | |
1833 | OMAP24XX_GPIO_IRQENABLE1); | |
1834 | __raw_writel(0xffffffff, bank->base + | |
1835 | OMAP24XX_GPIO_IRQSTATUS1); | |
1836 | __raw_writew(0x0015, bank->base + | |
1837 | OMAP24XX_GPIO_SYSCONFIG); | |
1838 | __raw_writel(0x00000000, bank->base + | |
1839 | OMAP24XX_GPIO_DEBOUNCE_EN); | |
1840 | ||
1841 | /* | |
1842 | * Initialize interface clock ungated, | |
1843 | * module enabled | |
1844 | */ | |
1845 | __raw_writel(0, bank->base + | |
1846 | OMAP24XX_GPIO_CTRL); | |
1847 | } | |
3ac4fa99 JY |
1848 | if (i < ARRAY_SIZE(non_wakeup_gpios)) |
1849 | bank->non_wakeup_gpios = non_wakeup_gpios[i]; | |
92105bb7 TL |
1850 | gpio_count = 32; |
1851 | } | |
5e1c5ff4 | 1852 | #endif |
058af1ea C |
1853 | |
1854 | bank->mod_usage = 0; | |
52e31344 DB |
1855 | /* REVISIT eventually switch from OMAP-specific gpio structs |
1856 | * over to the generic ones | |
1857 | */ | |
3ff164e1 JN |
1858 | bank->chip.request = omap_gpio_request; |
1859 | bank->chip.free = omap_gpio_free; | |
52e31344 DB |
1860 | bank->chip.direction_input = gpio_input; |
1861 | bank->chip.get = gpio_get; | |
1862 | bank->chip.direction_output = gpio_output; | |
1863 | bank->chip.set = gpio_set; | |
a007b709 | 1864 | bank->chip.to_irq = gpio_2irq; |
52e31344 DB |
1865 | if (bank_is_mpuio(bank)) { |
1866 | bank->chip.label = "mpuio"; | |
69114a47 | 1867 | #ifdef CONFIG_ARCH_OMAP16XX |
d8f388d8 DB |
1868 | bank->chip.dev = &omap_mpuio_device.dev; |
1869 | #endif | |
52e31344 DB |
1870 | bank->chip.base = OMAP_MPUIO(0); |
1871 | } else { | |
1872 | bank->chip.label = "gpio"; | |
1873 | bank->chip.base = gpio; | |
1874 | gpio += gpio_count; | |
1875 | } | |
1876 | bank->chip.ngpio = gpio_count; | |
1877 | ||
1878 | gpiochip_add(&bank->chip); | |
1879 | ||
5e1c5ff4 TL |
1880 | for (j = bank->virtual_irq_start; |
1881 | j < bank->virtual_irq_start + gpio_count; j++) { | |
8ba55c5c | 1882 | lockdep_set_class(&irq_desc[j].lock, &gpio_lock_class); |
58781016 | 1883 | set_irq_chip_data(j, bank); |
e5c56ed3 | 1884 | if (bank_is_mpuio(bank)) |
5e1c5ff4 TL |
1885 | set_irq_chip(j, &mpuio_irq_chip); |
1886 | else | |
1887 | set_irq_chip(j, &gpio_irq_chip); | |
10dd5ce2 | 1888 | set_irq_handler(j, handle_simple_irq); |
5e1c5ff4 TL |
1889 | set_irq_flags(j, IRQF_VALID); |
1890 | } | |
1891 | set_irq_chained_handler(bank->irq, gpio_irq_handler); | |
1892 | set_irq_data(bank->irq, bank); | |
89db9482 | 1893 | |
44169075 | 1894 | if (cpu_is_omap34xx() || cpu_is_omap44xx()) { |
89db9482 JH |
1895 | sprintf(clk_name, "gpio%d_dbck", i + 1); |
1896 | bank->dbck = clk_get(NULL, clk_name); | |
1897 | if (IS_ERR(bank->dbck)) | |
1898 | printk(KERN_ERR "Could not get %s\n", clk_name); | |
1899 | } | |
5e1c5ff4 TL |
1900 | } |
1901 | ||
1902 | /* Enable system clock for GPIO module. | |
1903 | * The CAM_CLK_CTRL *is* really the right place. */ | |
92105bb7 | 1904 | if (cpu_is_omap16xx()) |
5e1c5ff4 TL |
1905 | omap_writel(omap_readl(ULPD_CAM_CLK_CTRL) | 0x04, ULPD_CAM_CLK_CTRL); |
1906 | ||
14f1c3bf JY |
1907 | /* Enable autoidle for the OCP interface */ |
1908 | if (cpu_is_omap24xx()) | |
1909 | omap_writel(1 << 0, 0x48019010); | |
5492fb1a SMK |
1910 | if (cpu_is_omap34xx()) |
1911 | omap_writel(1 << 0, 0x48306814); | |
d11ac979 | 1912 | |
9f7065da TL |
1913 | omap_gpio_show_rev(); |
1914 | ||
5e1c5ff4 TL |
1915 | return 0; |
1916 | } | |
1917 | ||
140455fa | 1918 | #if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP2PLUS) |
92105bb7 TL |
1919 | static int omap_gpio_suspend(struct sys_device *dev, pm_message_t mesg) |
1920 | { | |
1921 | int i; | |
1922 | ||
5492fb1a | 1923 | if (!cpu_class_is_omap2() && !cpu_is_omap16xx()) |
92105bb7 TL |
1924 | return 0; |
1925 | ||
1926 | for (i = 0; i < gpio_bank_count; i++) { | |
1927 | struct gpio_bank *bank = &gpio_bank[i]; | |
1928 | void __iomem *wake_status; | |
1929 | void __iomem *wake_clear; | |
1930 | void __iomem *wake_set; | |
a6472533 | 1931 | unsigned long flags; |
92105bb7 TL |
1932 | |
1933 | switch (bank->method) { | |
e5c56ed3 | 1934 | #ifdef CONFIG_ARCH_OMAP16XX |
92105bb7 TL |
1935 | case METHOD_GPIO_1610: |
1936 | wake_status = bank->base + OMAP1610_GPIO_WAKEUPENABLE; | |
1937 | wake_clear = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA; | |
1938 | wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA; | |
1939 | break; | |
e5c56ed3 | 1940 | #endif |
a8eb7ca0 | 1941 | #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) |
92105bb7 | 1942 | case METHOD_GPIO_24XX: |
723fdb78 | 1943 | wake_status = bank->base + OMAP24XX_GPIO_WAKE_EN; |
92105bb7 TL |
1944 | wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA; |
1945 | wake_set = bank->base + OMAP24XX_GPIO_SETWKUENA; | |
1946 | break; | |
78a1a6d3 SR |
1947 | #endif |
1948 | #ifdef CONFIG_ARCH_OMAP4 | |
3f1686a9 | 1949 | case METHOD_GPIO_44XX: |
78a1a6d3 SR |
1950 | wake_status = bank->base + OMAP4_GPIO_IRQWAKEN0; |
1951 | wake_clear = bank->base + OMAP4_GPIO_IRQWAKEN0; | |
1952 | wake_set = bank->base + OMAP4_GPIO_IRQWAKEN0; | |
1953 | break; | |
e5c56ed3 | 1954 | #endif |
92105bb7 TL |
1955 | default: |
1956 | continue; | |
1957 | } | |
1958 | ||
a6472533 | 1959 | spin_lock_irqsave(&bank->lock, flags); |
92105bb7 TL |
1960 | bank->saved_wakeup = __raw_readl(wake_status); |
1961 | __raw_writel(0xffffffff, wake_clear); | |
1962 | __raw_writel(bank->suspend_wakeup, wake_set); | |
a6472533 | 1963 | spin_unlock_irqrestore(&bank->lock, flags); |
92105bb7 TL |
1964 | } |
1965 | ||
1966 | return 0; | |
1967 | } | |
1968 | ||
1969 | static int omap_gpio_resume(struct sys_device *dev) | |
1970 | { | |
1971 | int i; | |
1972 | ||
723fdb78 | 1973 | if (!cpu_class_is_omap2() && !cpu_is_omap16xx()) |
92105bb7 TL |
1974 | return 0; |
1975 | ||
1976 | for (i = 0; i < gpio_bank_count; i++) { | |
1977 | struct gpio_bank *bank = &gpio_bank[i]; | |
1978 | void __iomem *wake_clear; | |
1979 | void __iomem *wake_set; | |
a6472533 | 1980 | unsigned long flags; |
92105bb7 TL |
1981 | |
1982 | switch (bank->method) { | |
e5c56ed3 | 1983 | #ifdef CONFIG_ARCH_OMAP16XX |
92105bb7 TL |
1984 | case METHOD_GPIO_1610: |
1985 | wake_clear = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA; | |
1986 | wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA; | |
1987 | break; | |
e5c56ed3 | 1988 | #endif |
a8eb7ca0 | 1989 | #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) |
92105bb7 | 1990 | case METHOD_GPIO_24XX: |
0d9356cb TL |
1991 | wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA; |
1992 | wake_set = bank->base + OMAP24XX_GPIO_SETWKUENA; | |
92105bb7 | 1993 | break; |
78a1a6d3 SR |
1994 | #endif |
1995 | #ifdef CONFIG_ARCH_OMAP4 | |
3f1686a9 | 1996 | case METHOD_GPIO_44XX: |
78a1a6d3 SR |
1997 | wake_clear = bank->base + OMAP4_GPIO_IRQWAKEN0; |
1998 | wake_set = bank->base + OMAP4_GPIO_IRQWAKEN0; | |
1999 | break; | |
e5c56ed3 | 2000 | #endif |
92105bb7 TL |
2001 | default: |
2002 | continue; | |
2003 | } | |
2004 | ||
a6472533 | 2005 | spin_lock_irqsave(&bank->lock, flags); |
92105bb7 TL |
2006 | __raw_writel(0xffffffff, wake_clear); |
2007 | __raw_writel(bank->saved_wakeup, wake_set); | |
a6472533 | 2008 | spin_unlock_irqrestore(&bank->lock, flags); |
92105bb7 TL |
2009 | } |
2010 | ||
2011 | return 0; | |
2012 | } | |
2013 | ||
2014 | static struct sysdev_class omap_gpio_sysclass = { | |
af5ca3f4 | 2015 | .name = "gpio", |
92105bb7 TL |
2016 | .suspend = omap_gpio_suspend, |
2017 | .resume = omap_gpio_resume, | |
2018 | }; | |
2019 | ||
2020 | static struct sys_device omap_gpio_device = { | |
2021 | .id = 0, | |
2022 | .cls = &omap_gpio_sysclass, | |
2023 | }; | |
3ac4fa99 JY |
2024 | |
2025 | #endif | |
2026 | ||
140455fa | 2027 | #ifdef CONFIG_ARCH_OMAP2PLUS |
3ac4fa99 JY |
2028 | |
2029 | static int workaround_enabled; | |
2030 | ||
2031 | void omap2_gpio_prepare_for_retention(void) | |
2032 | { | |
2033 | int i, c = 0; | |
2034 | ||
2035 | /* Remove triggering for all non-wakeup GPIOs. Otherwise spurious | |
2036 | * IRQs will be generated. See OMAP2420 Errata item 1.101. */ | |
2037 | for (i = 0; i < gpio_bank_count; i++) { | |
2038 | struct gpio_bank *bank = &gpio_bank[i]; | |
2039 | u32 l1, l2; | |
2040 | ||
2041 | if (!(bank->enabled_non_wakeup_gpios)) | |
2042 | continue; | |
3f1686a9 TL |
2043 | |
2044 | if (cpu_is_omap24xx() || cpu_is_omap34xx()) { | |
2045 | bank->saved_datain = __raw_readl(bank->base + | |
2046 | OMAP24XX_GPIO_DATAIN); | |
2047 | l1 = __raw_readl(bank->base + | |
2048 | OMAP24XX_GPIO_FALLINGDETECT); | |
2049 | l2 = __raw_readl(bank->base + | |
2050 | OMAP24XX_GPIO_RISINGDETECT); | |
2051 | } | |
2052 | ||
2053 | if (cpu_is_omap44xx()) { | |
2054 | bank->saved_datain = __raw_readl(bank->base + | |
2055 | OMAP4_GPIO_DATAIN); | |
2056 | l1 = __raw_readl(bank->base + | |
2057 | OMAP4_GPIO_FALLINGDETECT); | |
2058 | l2 = __raw_readl(bank->base + | |
2059 | OMAP4_GPIO_RISINGDETECT); | |
2060 | } | |
2061 | ||
3ac4fa99 JY |
2062 | bank->saved_fallingdetect = l1; |
2063 | bank->saved_risingdetect = l2; | |
2064 | l1 &= ~bank->enabled_non_wakeup_gpios; | |
2065 | l2 &= ~bank->enabled_non_wakeup_gpios; | |
3f1686a9 TL |
2066 | |
2067 | if (cpu_is_omap24xx() || cpu_is_omap34xx()) { | |
2068 | __raw_writel(l1, bank->base + | |
2069 | OMAP24XX_GPIO_FALLINGDETECT); | |
2070 | __raw_writel(l2, bank->base + | |
2071 | OMAP24XX_GPIO_RISINGDETECT); | |
2072 | } | |
2073 | ||
2074 | if (cpu_is_omap44xx()) { | |
2075 | __raw_writel(l1, bank->base + OMAP4_GPIO_FALLINGDETECT); | |
2076 | __raw_writel(l2, bank->base + OMAP4_GPIO_RISINGDETECT); | |
2077 | } | |
2078 | ||
3ac4fa99 JY |
2079 | c++; |
2080 | } | |
2081 | if (!c) { | |
2082 | workaround_enabled = 0; | |
2083 | return; | |
2084 | } | |
2085 | workaround_enabled = 1; | |
2086 | } | |
2087 | ||
2088 | void omap2_gpio_resume_after_retention(void) | |
2089 | { | |
2090 | int i; | |
2091 | ||
2092 | if (!workaround_enabled) | |
2093 | return; | |
2094 | for (i = 0; i < gpio_bank_count; i++) { | |
2095 | struct gpio_bank *bank = &gpio_bank[i]; | |
82dbb9d3 | 2096 | u32 l, gen, gen0, gen1; |
3ac4fa99 JY |
2097 | |
2098 | if (!(bank->enabled_non_wakeup_gpios)) | |
2099 | continue; | |
3f1686a9 TL |
2100 | |
2101 | if (cpu_is_omap24xx() || cpu_is_omap34xx()) { | |
2102 | __raw_writel(bank->saved_fallingdetect, | |
3ac4fa99 | 2103 | bank->base + OMAP24XX_GPIO_FALLINGDETECT); |
3f1686a9 | 2104 | __raw_writel(bank->saved_risingdetect, |
3ac4fa99 | 2105 | bank->base + OMAP24XX_GPIO_RISINGDETECT); |
3f1686a9 TL |
2106 | l = __raw_readl(bank->base + OMAP24XX_GPIO_DATAIN); |
2107 | } | |
2108 | ||
2109 | if (cpu_is_omap44xx()) { | |
2110 | __raw_writel(bank->saved_fallingdetect, | |
78a1a6d3 | 2111 | bank->base + OMAP4_GPIO_FALLINGDETECT); |
3f1686a9 | 2112 | __raw_writel(bank->saved_risingdetect, |
78a1a6d3 | 2113 | bank->base + OMAP4_GPIO_RISINGDETECT); |
3f1686a9 TL |
2114 | l = __raw_readl(bank->base + OMAP4_GPIO_DATAIN); |
2115 | } | |
2116 | ||
3ac4fa99 JY |
2117 | /* Check if any of the non-wakeup interrupt GPIOs have changed |
2118 | * state. If so, generate an IRQ by software. This is | |
2119 | * horribly racy, but it's the best we can do to work around | |
2120 | * this silicon bug. */ | |
3ac4fa99 JY |
2121 | l ^= bank->saved_datain; |
2122 | l &= bank->non_wakeup_gpios; | |
82dbb9d3 EN |
2123 | |
2124 | /* | |
2125 | * No need to generate IRQs for the rising edge for gpio IRQs | |
2126 | * configured with falling edge only; and vice versa. | |
2127 | */ | |
2128 | gen0 = l & bank->saved_fallingdetect; | |
2129 | gen0 &= bank->saved_datain; | |
2130 | ||
2131 | gen1 = l & bank->saved_risingdetect; | |
2132 | gen1 &= ~(bank->saved_datain); | |
2133 | ||
2134 | /* FIXME: Consider GPIO IRQs with level detections properly! */ | |
2135 | gen = l & (~(bank->saved_fallingdetect) & | |
2136 | ~(bank->saved_risingdetect)); | |
2137 | /* Consider all GPIO IRQs needed to be updated */ | |
2138 | gen |= gen0 | gen1; | |
2139 | ||
2140 | if (gen) { | |
3ac4fa99 | 2141 | u32 old0, old1; |
3f1686a9 | 2142 | |
f00d6497 | 2143 | if (cpu_is_omap24xx() || cpu_is_omap34xx()) { |
3f1686a9 TL |
2144 | old0 = __raw_readl(bank->base + |
2145 | OMAP24XX_GPIO_LEVELDETECT0); | |
2146 | old1 = __raw_readl(bank->base + | |
2147 | OMAP24XX_GPIO_LEVELDETECT1); | |
f00d6497 | 2148 | __raw_writel(old0 | gen, bank->base + |
82dbb9d3 | 2149 | OMAP24XX_GPIO_LEVELDETECT0); |
f00d6497 | 2150 | __raw_writel(old1 | gen, bank->base + |
82dbb9d3 | 2151 | OMAP24XX_GPIO_LEVELDETECT1); |
f00d6497 | 2152 | __raw_writel(old0, bank->base + |
3f1686a9 | 2153 | OMAP24XX_GPIO_LEVELDETECT0); |
f00d6497 | 2154 | __raw_writel(old1, bank->base + |
3f1686a9 TL |
2155 | OMAP24XX_GPIO_LEVELDETECT1); |
2156 | } | |
2157 | ||
2158 | if (cpu_is_omap44xx()) { | |
2159 | old0 = __raw_readl(bank->base + | |
78a1a6d3 | 2160 | OMAP4_GPIO_LEVELDETECT0); |
3f1686a9 | 2161 | old1 = __raw_readl(bank->base + |
78a1a6d3 | 2162 | OMAP4_GPIO_LEVELDETECT1); |
3f1686a9 | 2163 | __raw_writel(old0 | l, bank->base + |
78a1a6d3 | 2164 | OMAP4_GPIO_LEVELDETECT0); |
3f1686a9 | 2165 | __raw_writel(old1 | l, bank->base + |
78a1a6d3 | 2166 | OMAP4_GPIO_LEVELDETECT1); |
3f1686a9 | 2167 | __raw_writel(old0, bank->base + |
78a1a6d3 | 2168 | OMAP4_GPIO_LEVELDETECT0); |
3f1686a9 | 2169 | __raw_writel(old1, bank->base + |
78a1a6d3 | 2170 | OMAP4_GPIO_LEVELDETECT1); |
3f1686a9 | 2171 | } |
3ac4fa99 JY |
2172 | } |
2173 | } | |
2174 | ||
2175 | } | |
2176 | ||
92105bb7 TL |
2177 | #endif |
2178 | ||
a8eb7ca0 | 2179 | #ifdef CONFIG_ARCH_OMAP3 |
40c670f0 RN |
2180 | /* save the registers of bank 2-6 */ |
2181 | void omap_gpio_save_context(void) | |
2182 | { | |
2183 | int i; | |
2184 | ||
2185 | /* saving banks from 2-6 only since GPIO1 is in WKUP */ | |
2186 | for (i = 1; i < gpio_bank_count; i++) { | |
2187 | struct gpio_bank *bank = &gpio_bank[i]; | |
2188 | gpio_context[i].sysconfig = | |
2189 | __raw_readl(bank->base + OMAP24XX_GPIO_SYSCONFIG); | |
2190 | gpio_context[i].irqenable1 = | |
2191 | __raw_readl(bank->base + OMAP24XX_GPIO_IRQENABLE1); | |
2192 | gpio_context[i].irqenable2 = | |
2193 | __raw_readl(bank->base + OMAP24XX_GPIO_IRQENABLE2); | |
2194 | gpio_context[i].wake_en = | |
2195 | __raw_readl(bank->base + OMAP24XX_GPIO_WAKE_EN); | |
2196 | gpio_context[i].ctrl = | |
2197 | __raw_readl(bank->base + OMAP24XX_GPIO_CTRL); | |
2198 | gpio_context[i].oe = | |
2199 | __raw_readl(bank->base + OMAP24XX_GPIO_OE); | |
2200 | gpio_context[i].leveldetect0 = | |
2201 | __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT0); | |
2202 | gpio_context[i].leveldetect1 = | |
2203 | __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT1); | |
2204 | gpio_context[i].risingdetect = | |
2205 | __raw_readl(bank->base + OMAP24XX_GPIO_RISINGDETECT); | |
2206 | gpio_context[i].fallingdetect = | |
2207 | __raw_readl(bank->base + OMAP24XX_GPIO_FALLINGDETECT); | |
2208 | gpio_context[i].dataout = | |
2209 | __raw_readl(bank->base + OMAP24XX_GPIO_DATAOUT); | |
2210 | gpio_context[i].setwkuena = | |
2211 | __raw_readl(bank->base + OMAP24XX_GPIO_SETWKUENA); | |
2212 | gpio_context[i].setdataout = | |
2213 | __raw_readl(bank->base + OMAP24XX_GPIO_SETDATAOUT); | |
2214 | } | |
2215 | } | |
2216 | ||
2217 | /* restore the required registers of bank 2-6 */ | |
2218 | void omap_gpio_restore_context(void) | |
2219 | { | |
2220 | int i; | |
2221 | ||
2222 | for (i = 1; i < gpio_bank_count; i++) { | |
2223 | struct gpio_bank *bank = &gpio_bank[i]; | |
2224 | __raw_writel(gpio_context[i].sysconfig, | |
2225 | bank->base + OMAP24XX_GPIO_SYSCONFIG); | |
2226 | __raw_writel(gpio_context[i].irqenable1, | |
2227 | bank->base + OMAP24XX_GPIO_IRQENABLE1); | |
2228 | __raw_writel(gpio_context[i].irqenable2, | |
2229 | bank->base + OMAP24XX_GPIO_IRQENABLE2); | |
2230 | __raw_writel(gpio_context[i].wake_en, | |
2231 | bank->base + OMAP24XX_GPIO_WAKE_EN); | |
2232 | __raw_writel(gpio_context[i].ctrl, | |
2233 | bank->base + OMAP24XX_GPIO_CTRL); | |
2234 | __raw_writel(gpio_context[i].oe, | |
2235 | bank->base + OMAP24XX_GPIO_OE); | |
2236 | __raw_writel(gpio_context[i].leveldetect0, | |
2237 | bank->base + OMAP24XX_GPIO_LEVELDETECT0); | |
2238 | __raw_writel(gpio_context[i].leveldetect1, | |
2239 | bank->base + OMAP24XX_GPIO_LEVELDETECT1); | |
2240 | __raw_writel(gpio_context[i].risingdetect, | |
2241 | bank->base + OMAP24XX_GPIO_RISINGDETECT); | |
2242 | __raw_writel(gpio_context[i].fallingdetect, | |
2243 | bank->base + OMAP24XX_GPIO_FALLINGDETECT); | |
2244 | __raw_writel(gpio_context[i].dataout, | |
2245 | bank->base + OMAP24XX_GPIO_DATAOUT); | |
2246 | __raw_writel(gpio_context[i].setwkuena, | |
2247 | bank->base + OMAP24XX_GPIO_SETWKUENA); | |
2248 | __raw_writel(gpio_context[i].setdataout, | |
2249 | bank->base + OMAP24XX_GPIO_SETDATAOUT); | |
2250 | } | |
2251 | } | |
2252 | #endif | |
2253 | ||
5e1c5ff4 TL |
2254 | /* |
2255 | * This may get called early from board specific init | |
1a8bfa1e | 2256 | * for boards that have interrupts routed via FPGA. |
5e1c5ff4 | 2257 | */ |
277d58ef | 2258 | int __init omap_gpio_init(void) |
5e1c5ff4 TL |
2259 | { |
2260 | if (!initialized) | |
2261 | return _omap_gpio_init(); | |
2262 | else | |
2263 | return 0; | |
2264 | } | |
2265 | ||
92105bb7 TL |
2266 | static int __init omap_gpio_sysinit(void) |
2267 | { | |
2268 | int ret = 0; | |
2269 | ||
2270 | if (!initialized) | |
2271 | ret = _omap_gpio_init(); | |
2272 | ||
11a78b79 DB |
2273 | mpuio_init(); |
2274 | ||
140455fa | 2275 | #if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP2PLUS) |
5492fb1a | 2276 | if (cpu_is_omap16xx() || cpu_class_is_omap2()) { |
92105bb7 TL |
2277 | if (ret == 0) { |
2278 | ret = sysdev_class_register(&omap_gpio_sysclass); | |
2279 | if (ret == 0) | |
2280 | ret = sysdev_register(&omap_gpio_device); | |
2281 | } | |
2282 | } | |
2283 | #endif | |
2284 | ||
2285 | return ret; | |
2286 | } | |
2287 | ||
92105bb7 | 2288 | arch_initcall(omap_gpio_sysinit); |
b9772a22 DB |
2289 | |
2290 | ||
2291 | #ifdef CONFIG_DEBUG_FS | |
2292 | ||
2293 | #include <linux/debugfs.h> | |
2294 | #include <linux/seq_file.h> | |
2295 | ||
b9772a22 DB |
2296 | static int dbg_gpio_show(struct seq_file *s, void *unused) |
2297 | { | |
2298 | unsigned i, j, gpio; | |
2299 | ||
2300 | for (i = 0, gpio = 0; i < gpio_bank_count; i++) { | |
2301 | struct gpio_bank *bank = gpio_bank + i; | |
2302 | unsigned bankwidth = 16; | |
2303 | u32 mask = 1; | |
2304 | ||
e5c56ed3 | 2305 | if (bank_is_mpuio(bank)) |
b9772a22 | 2306 | gpio = OMAP_MPUIO(0); |
b718aa81 | 2307 | else if (cpu_class_is_omap2() || cpu_is_omap7xx()) |
b9772a22 DB |
2308 | bankwidth = 32; |
2309 | ||
2310 | for (j = 0; j < bankwidth; j++, gpio++, mask <<= 1) { | |
2311 | unsigned irq, value, is_in, irqstat; | |
52e31344 | 2312 | const char *label; |
b9772a22 | 2313 | |
52e31344 DB |
2314 | label = gpiochip_is_requested(&bank->chip, j); |
2315 | if (!label) | |
b9772a22 DB |
2316 | continue; |
2317 | ||
2318 | irq = bank->virtual_irq_start + j; | |
0b84b5ca | 2319 | value = gpio_get_value(gpio); |
b9772a22 DB |
2320 | is_in = gpio_is_input(bank, mask); |
2321 | ||
e5c56ed3 | 2322 | if (bank_is_mpuio(bank)) |
52e31344 | 2323 | seq_printf(s, "MPUIO %2d ", j); |
b9772a22 | 2324 | else |
52e31344 | 2325 | seq_printf(s, "GPIO %3d ", gpio); |
21c867f1 | 2326 | seq_printf(s, "(%-20.20s): %s %s", |
52e31344 | 2327 | label, |
b9772a22 DB |
2328 | is_in ? "in " : "out", |
2329 | value ? "hi" : "lo"); | |
2330 | ||
52e31344 DB |
2331 | /* FIXME for at least omap2, show pullup/pulldown state */ |
2332 | ||
b9772a22 | 2333 | irqstat = irq_desc[irq].status; |
140455fa | 2334 | #if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP2PLUS) |
b9772a22 DB |
2335 | if (is_in && ((bank->suspend_wakeup & mask) |
2336 | || irqstat & IRQ_TYPE_SENSE_MASK)) { | |
2337 | char *trigger = NULL; | |
2338 | ||
2339 | switch (irqstat & IRQ_TYPE_SENSE_MASK) { | |
2340 | case IRQ_TYPE_EDGE_FALLING: | |
2341 | trigger = "falling"; | |
2342 | break; | |
2343 | case IRQ_TYPE_EDGE_RISING: | |
2344 | trigger = "rising"; | |
2345 | break; | |
2346 | case IRQ_TYPE_EDGE_BOTH: | |
2347 | trigger = "bothedge"; | |
2348 | break; | |
2349 | case IRQ_TYPE_LEVEL_LOW: | |
2350 | trigger = "low"; | |
2351 | break; | |
2352 | case IRQ_TYPE_LEVEL_HIGH: | |
2353 | trigger = "high"; | |
2354 | break; | |
2355 | case IRQ_TYPE_NONE: | |
52e31344 | 2356 | trigger = "(?)"; |
b9772a22 DB |
2357 | break; |
2358 | } | |
52e31344 | 2359 | seq_printf(s, ", irq-%d %-8s%s", |
b9772a22 DB |
2360 | irq, trigger, |
2361 | (bank->suspend_wakeup & mask) | |
2362 | ? " wakeup" : ""); | |
2363 | } | |
3a26e331 | 2364 | #endif |
b9772a22 DB |
2365 | seq_printf(s, "\n"); |
2366 | } | |
2367 | ||
e5c56ed3 | 2368 | if (bank_is_mpuio(bank)) { |
b9772a22 DB |
2369 | seq_printf(s, "\n"); |
2370 | gpio = 0; | |
2371 | } | |
2372 | } | |
2373 | return 0; | |
2374 | } | |
2375 | ||
2376 | static int dbg_gpio_open(struct inode *inode, struct file *file) | |
2377 | { | |
e5c56ed3 | 2378 | return single_open(file, dbg_gpio_show, &inode->i_private); |
b9772a22 DB |
2379 | } |
2380 | ||
2381 | static const struct file_operations debug_fops = { | |
2382 | .open = dbg_gpio_open, | |
2383 | .read = seq_read, | |
2384 | .llseek = seq_lseek, | |
2385 | .release = single_release, | |
2386 | }; | |
2387 | ||
2388 | static int __init omap_gpio_debuginit(void) | |
2389 | { | |
e5c56ed3 DB |
2390 | (void) debugfs_create_file("omap_gpio", S_IRUGO, |
2391 | NULL, NULL, &debug_fops); | |
b9772a22 DB |
2392 | return 0; |
2393 | } | |
2394 | late_initcall(omap_gpio_debuginit); | |
2395 | #endif |