Commit | Line | Data |
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5e1c5ff4 TL |
1 | /* |
2 | * linux/arch/arm/plat-omap/gpio.c | |
3 | * | |
4 | * Support functions for OMAP GPIO | |
5 | * | |
92105bb7 | 6 | * Copyright (C) 2003-2005 Nokia Corporation |
96de0e25 | 7 | * Written by Juha Yrjölä <juha.yrjola@nokia.com> |
5e1c5ff4 TL |
8 | * |
9 | * This program is free software; you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License version 2 as | |
11 | * published by the Free Software Foundation. | |
12 | */ | |
13 | ||
5e1c5ff4 TL |
14 | #include <linux/init.h> |
15 | #include <linux/module.h> | |
5e1c5ff4 | 16 | #include <linux/interrupt.h> |
92105bb7 TL |
17 | #include <linux/sysdev.h> |
18 | #include <linux/err.h> | |
f8ce2547 | 19 | #include <linux/clk.h> |
5e1c5ff4 TL |
20 | |
21 | #include <asm/hardware.h> | |
22 | #include <asm/irq.h> | |
23 | #include <asm/arch/irqs.h> | |
24 | #include <asm/arch/gpio.h> | |
25 | #include <asm/mach/irq.h> | |
26 | ||
27 | #include <asm/io.h> | |
28 | ||
29 | /* | |
30 | * OMAP1510 GPIO registers | |
31 | */ | |
92105bb7 | 32 | #define OMAP1510_GPIO_BASE (void __iomem *)0xfffce000 |
5e1c5ff4 TL |
33 | #define OMAP1510_GPIO_DATA_INPUT 0x00 |
34 | #define OMAP1510_GPIO_DATA_OUTPUT 0x04 | |
35 | #define OMAP1510_GPIO_DIR_CONTROL 0x08 | |
36 | #define OMAP1510_GPIO_INT_CONTROL 0x0c | |
37 | #define OMAP1510_GPIO_INT_MASK 0x10 | |
38 | #define OMAP1510_GPIO_INT_STATUS 0x14 | |
39 | #define OMAP1510_GPIO_PIN_CONTROL 0x18 | |
40 | ||
41 | #define OMAP1510_IH_GPIO_BASE 64 | |
42 | ||
43 | /* | |
44 | * OMAP1610 specific GPIO registers | |
45 | */ | |
92105bb7 TL |
46 | #define OMAP1610_GPIO1_BASE (void __iomem *)0xfffbe400 |
47 | #define OMAP1610_GPIO2_BASE (void __iomem *)0xfffbec00 | |
48 | #define OMAP1610_GPIO3_BASE (void __iomem *)0xfffbb400 | |
49 | #define OMAP1610_GPIO4_BASE (void __iomem *)0xfffbbc00 | |
5e1c5ff4 TL |
50 | #define OMAP1610_GPIO_REVISION 0x0000 |
51 | #define OMAP1610_GPIO_SYSCONFIG 0x0010 | |
52 | #define OMAP1610_GPIO_SYSSTATUS 0x0014 | |
53 | #define OMAP1610_GPIO_IRQSTATUS1 0x0018 | |
54 | #define OMAP1610_GPIO_IRQENABLE1 0x001c | |
92105bb7 | 55 | #define OMAP1610_GPIO_WAKEUPENABLE 0x0028 |
5e1c5ff4 TL |
56 | #define OMAP1610_GPIO_DATAIN 0x002c |
57 | #define OMAP1610_GPIO_DATAOUT 0x0030 | |
58 | #define OMAP1610_GPIO_DIRECTION 0x0034 | |
59 | #define OMAP1610_GPIO_EDGE_CTRL1 0x0038 | |
60 | #define OMAP1610_GPIO_EDGE_CTRL2 0x003c | |
61 | #define OMAP1610_GPIO_CLEAR_IRQENABLE1 0x009c | |
92105bb7 | 62 | #define OMAP1610_GPIO_CLEAR_WAKEUPENA 0x00a8 |
5e1c5ff4 TL |
63 | #define OMAP1610_GPIO_CLEAR_DATAOUT 0x00b0 |
64 | #define OMAP1610_GPIO_SET_IRQENABLE1 0x00dc | |
92105bb7 | 65 | #define OMAP1610_GPIO_SET_WAKEUPENA 0x00e8 |
5e1c5ff4 TL |
66 | #define OMAP1610_GPIO_SET_DATAOUT 0x00f0 |
67 | ||
68 | /* | |
69 | * OMAP730 specific GPIO registers | |
70 | */ | |
92105bb7 TL |
71 | #define OMAP730_GPIO1_BASE (void __iomem *)0xfffbc000 |
72 | #define OMAP730_GPIO2_BASE (void __iomem *)0xfffbc800 | |
73 | #define OMAP730_GPIO3_BASE (void __iomem *)0xfffbd000 | |
74 | #define OMAP730_GPIO4_BASE (void __iomem *)0xfffbd800 | |
75 | #define OMAP730_GPIO5_BASE (void __iomem *)0xfffbe000 | |
76 | #define OMAP730_GPIO6_BASE (void __iomem *)0xfffbe800 | |
5e1c5ff4 TL |
77 | #define OMAP730_GPIO_DATA_INPUT 0x00 |
78 | #define OMAP730_GPIO_DATA_OUTPUT 0x04 | |
79 | #define OMAP730_GPIO_DIR_CONTROL 0x08 | |
80 | #define OMAP730_GPIO_INT_CONTROL 0x0c | |
81 | #define OMAP730_GPIO_INT_MASK 0x10 | |
82 | #define OMAP730_GPIO_INT_STATUS 0x14 | |
83 | ||
92105bb7 TL |
84 | /* |
85 | * omap24xx specific GPIO registers | |
86 | */ | |
56a25641 SMK |
87 | #define OMAP242X_GPIO1_BASE (void __iomem *)0x48018000 |
88 | #define OMAP242X_GPIO2_BASE (void __iomem *)0x4801a000 | |
89 | #define OMAP242X_GPIO3_BASE (void __iomem *)0x4801c000 | |
90 | #define OMAP242X_GPIO4_BASE (void __iomem *)0x4801e000 | |
91 | ||
92 | #define OMAP243X_GPIO1_BASE (void __iomem *)0x4900C000 | |
93 | #define OMAP243X_GPIO2_BASE (void __iomem *)0x4900E000 | |
94 | #define OMAP243X_GPIO3_BASE (void __iomem *)0x49010000 | |
95 | #define OMAP243X_GPIO4_BASE (void __iomem *)0x49012000 | |
96 | #define OMAP243X_GPIO5_BASE (void __iomem *)0x480B6000 | |
97 | ||
92105bb7 TL |
98 | #define OMAP24XX_GPIO_REVISION 0x0000 |
99 | #define OMAP24XX_GPIO_SYSCONFIG 0x0010 | |
100 | #define OMAP24XX_GPIO_SYSSTATUS 0x0014 | |
101 | #define OMAP24XX_GPIO_IRQSTATUS1 0x0018 | |
bee7930f HD |
102 | #define OMAP24XX_GPIO_IRQSTATUS2 0x0028 |
103 | #define OMAP24XX_GPIO_IRQENABLE2 0x002c | |
92105bb7 TL |
104 | #define OMAP24XX_GPIO_IRQENABLE1 0x001c |
105 | #define OMAP24XX_GPIO_CTRL 0x0030 | |
106 | #define OMAP24XX_GPIO_OE 0x0034 | |
107 | #define OMAP24XX_GPIO_DATAIN 0x0038 | |
108 | #define OMAP24XX_GPIO_DATAOUT 0x003c | |
109 | #define OMAP24XX_GPIO_LEVELDETECT0 0x0040 | |
110 | #define OMAP24XX_GPIO_LEVELDETECT1 0x0044 | |
111 | #define OMAP24XX_GPIO_RISINGDETECT 0x0048 | |
112 | #define OMAP24XX_GPIO_FALLINGDETECT 0x004c | |
113 | #define OMAP24XX_GPIO_CLEARIRQENABLE1 0x0060 | |
114 | #define OMAP24XX_GPIO_SETIRQENABLE1 0x0064 | |
115 | #define OMAP24XX_GPIO_CLEARWKUENA 0x0080 | |
116 | #define OMAP24XX_GPIO_SETWKUENA 0x0084 | |
117 | #define OMAP24XX_GPIO_CLEARDATAOUT 0x0090 | |
118 | #define OMAP24XX_GPIO_SETDATAOUT 0x0094 | |
119 | ||
5e1c5ff4 | 120 | struct gpio_bank { |
92105bb7 | 121 | void __iomem *base; |
5e1c5ff4 TL |
122 | u16 irq; |
123 | u16 virtual_irq_start; | |
92105bb7 | 124 | int method; |
5e1c5ff4 | 125 | u32 reserved_map; |
3ac4fa99 | 126 | #if defined (CONFIG_ARCH_OMAP16XX) || defined (CONFIG_ARCH_OMAP24XX) |
92105bb7 TL |
127 | u32 suspend_wakeup; |
128 | u32 saved_wakeup; | |
3ac4fa99 JY |
129 | #endif |
130 | #ifdef CONFIG_ARCH_OMAP24XX | |
131 | u32 non_wakeup_gpios; | |
132 | u32 enabled_non_wakeup_gpios; | |
133 | ||
134 | u32 saved_datain; | |
135 | u32 saved_fallingdetect; | |
136 | u32 saved_risingdetect; | |
137 | #endif | |
5e1c5ff4 TL |
138 | spinlock_t lock; |
139 | }; | |
140 | ||
141 | #define METHOD_MPUIO 0 | |
142 | #define METHOD_GPIO_1510 1 | |
143 | #define METHOD_GPIO_1610 2 | |
144 | #define METHOD_GPIO_730 3 | |
92105bb7 | 145 | #define METHOD_GPIO_24XX 4 |
5e1c5ff4 | 146 | |
92105bb7 | 147 | #ifdef CONFIG_ARCH_OMAP16XX |
5e1c5ff4 TL |
148 | static struct gpio_bank gpio_bank_1610[5] = { |
149 | { OMAP_MPUIO_BASE, INT_MPUIO, IH_MPUIO_BASE, METHOD_MPUIO}, | |
150 | { OMAP1610_GPIO1_BASE, INT_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_1610 }, | |
151 | { OMAP1610_GPIO2_BASE, INT_1610_GPIO_BANK2, IH_GPIO_BASE + 16, METHOD_GPIO_1610 }, | |
152 | { OMAP1610_GPIO3_BASE, INT_1610_GPIO_BANK3, IH_GPIO_BASE + 32, METHOD_GPIO_1610 }, | |
153 | { OMAP1610_GPIO4_BASE, INT_1610_GPIO_BANK4, IH_GPIO_BASE + 48, METHOD_GPIO_1610 }, | |
154 | }; | |
155 | #endif | |
156 | ||
1a8bfa1e | 157 | #ifdef CONFIG_ARCH_OMAP15XX |
5e1c5ff4 TL |
158 | static struct gpio_bank gpio_bank_1510[2] = { |
159 | { OMAP_MPUIO_BASE, INT_MPUIO, IH_MPUIO_BASE, METHOD_MPUIO }, | |
160 | { OMAP1510_GPIO_BASE, INT_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_1510 } | |
161 | }; | |
162 | #endif | |
163 | ||
164 | #ifdef CONFIG_ARCH_OMAP730 | |
165 | static struct gpio_bank gpio_bank_730[7] = { | |
166 | { OMAP_MPUIO_BASE, INT_730_MPUIO, IH_MPUIO_BASE, METHOD_MPUIO }, | |
167 | { OMAP730_GPIO1_BASE, INT_730_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_730 }, | |
168 | { OMAP730_GPIO2_BASE, INT_730_GPIO_BANK2, IH_GPIO_BASE + 32, METHOD_GPIO_730 }, | |
169 | { OMAP730_GPIO3_BASE, INT_730_GPIO_BANK3, IH_GPIO_BASE + 64, METHOD_GPIO_730 }, | |
170 | { OMAP730_GPIO4_BASE, INT_730_GPIO_BANK4, IH_GPIO_BASE + 96, METHOD_GPIO_730 }, | |
171 | { OMAP730_GPIO5_BASE, INT_730_GPIO_BANK5, IH_GPIO_BASE + 128, METHOD_GPIO_730 }, | |
172 | { OMAP730_GPIO6_BASE, INT_730_GPIO_BANK6, IH_GPIO_BASE + 160, METHOD_GPIO_730 }, | |
173 | }; | |
174 | #endif | |
175 | ||
92105bb7 | 176 | #ifdef CONFIG_ARCH_OMAP24XX |
56a25641 SMK |
177 | |
178 | static struct gpio_bank gpio_bank_242x[4] = { | |
179 | { OMAP242X_GPIO1_BASE, INT_24XX_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_24XX }, | |
180 | { OMAP242X_GPIO2_BASE, INT_24XX_GPIO_BANK2, IH_GPIO_BASE + 32, METHOD_GPIO_24XX }, | |
181 | { OMAP242X_GPIO3_BASE, INT_24XX_GPIO_BANK3, IH_GPIO_BASE + 64, METHOD_GPIO_24XX }, | |
182 | { OMAP242X_GPIO4_BASE, INT_24XX_GPIO_BANK4, IH_GPIO_BASE + 96, METHOD_GPIO_24XX }, | |
92105bb7 | 183 | }; |
56a25641 SMK |
184 | |
185 | static struct gpio_bank gpio_bank_243x[5] = { | |
186 | { OMAP243X_GPIO1_BASE, INT_24XX_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_24XX }, | |
187 | { OMAP243X_GPIO2_BASE, INT_24XX_GPIO_BANK2, IH_GPIO_BASE + 32, METHOD_GPIO_24XX }, | |
188 | { OMAP243X_GPIO3_BASE, INT_24XX_GPIO_BANK3, IH_GPIO_BASE + 64, METHOD_GPIO_24XX }, | |
189 | { OMAP243X_GPIO4_BASE, INT_24XX_GPIO_BANK4, IH_GPIO_BASE + 96, METHOD_GPIO_24XX }, | |
190 | { OMAP243X_GPIO5_BASE, INT_24XX_GPIO_BANK5, IH_GPIO_BASE + 128, METHOD_GPIO_24XX }, | |
191 | }; | |
192 | ||
92105bb7 TL |
193 | #endif |
194 | ||
5e1c5ff4 TL |
195 | static struct gpio_bank *gpio_bank; |
196 | static int gpio_bank_count; | |
197 | ||
198 | static inline struct gpio_bank *get_gpio_bank(int gpio) | |
199 | { | |
1a8bfa1e | 200 | #ifdef CONFIG_ARCH_OMAP15XX |
6e60e79a | 201 | if (cpu_is_omap15xx()) { |
5e1c5ff4 TL |
202 | if (OMAP_GPIO_IS_MPUIO(gpio)) |
203 | return &gpio_bank[0]; | |
204 | return &gpio_bank[1]; | |
205 | } | |
206 | #endif | |
207 | #if defined(CONFIG_ARCH_OMAP16XX) | |
208 | if (cpu_is_omap16xx()) { | |
209 | if (OMAP_GPIO_IS_MPUIO(gpio)) | |
210 | return &gpio_bank[0]; | |
211 | return &gpio_bank[1 + (gpio >> 4)]; | |
212 | } | |
213 | #endif | |
214 | #ifdef CONFIG_ARCH_OMAP730 | |
215 | if (cpu_is_omap730()) { | |
216 | if (OMAP_GPIO_IS_MPUIO(gpio)) | |
217 | return &gpio_bank[0]; | |
218 | return &gpio_bank[1 + (gpio >> 5)]; | |
219 | } | |
220 | #endif | |
92105bb7 TL |
221 | #ifdef CONFIG_ARCH_OMAP24XX |
222 | if (cpu_is_omap24xx()) | |
223 | return &gpio_bank[gpio >> 5]; | |
224 | #endif | |
5e1c5ff4 TL |
225 | } |
226 | ||
227 | static inline int get_gpio_index(int gpio) | |
228 | { | |
92105bb7 | 229 | #ifdef CONFIG_ARCH_OMAP730 |
5e1c5ff4 TL |
230 | if (cpu_is_omap730()) |
231 | return gpio & 0x1f; | |
92105bb7 TL |
232 | #endif |
233 | #ifdef CONFIG_ARCH_OMAP24XX | |
234 | if (cpu_is_omap24xx()) | |
235 | return gpio & 0x1f; | |
236 | #endif | |
237 | return gpio & 0x0f; | |
5e1c5ff4 TL |
238 | } |
239 | ||
240 | static inline int gpio_valid(int gpio) | |
241 | { | |
242 | if (gpio < 0) | |
243 | return -1; | |
5a4e86da | 244 | #ifndef CONFIG_ARCH_OMAP24XX |
5e1c5ff4 | 245 | if (OMAP_GPIO_IS_MPUIO(gpio)) { |
193e68be | 246 | if (gpio >= OMAP_MAX_GPIO_LINES + 16) |
5e1c5ff4 TL |
247 | return -1; |
248 | return 0; | |
249 | } | |
5a4e86da | 250 | #endif |
1a8bfa1e | 251 | #ifdef CONFIG_ARCH_OMAP15XX |
6e60e79a | 252 | if (cpu_is_omap15xx() && gpio < 16) |
5e1c5ff4 TL |
253 | return 0; |
254 | #endif | |
255 | #if defined(CONFIG_ARCH_OMAP16XX) | |
256 | if ((cpu_is_omap16xx()) && gpio < 64) | |
257 | return 0; | |
258 | #endif | |
259 | #ifdef CONFIG_ARCH_OMAP730 | |
260 | if (cpu_is_omap730() && gpio < 192) | |
261 | return 0; | |
92105bb7 TL |
262 | #endif |
263 | #ifdef CONFIG_ARCH_OMAP24XX | |
264 | if (cpu_is_omap24xx() && gpio < 128) | |
265 | return 0; | |
5e1c5ff4 TL |
266 | #endif |
267 | return -1; | |
268 | } | |
269 | ||
270 | static int check_gpio(int gpio) | |
271 | { | |
272 | if (unlikely(gpio_valid(gpio)) < 0) { | |
273 | printk(KERN_ERR "omap-gpio: invalid GPIO %d\n", gpio); | |
274 | dump_stack(); | |
275 | return -1; | |
276 | } | |
277 | return 0; | |
278 | } | |
279 | ||
280 | static void _set_gpio_direction(struct gpio_bank *bank, int gpio, int is_input) | |
281 | { | |
92105bb7 | 282 | void __iomem *reg = bank->base; |
5e1c5ff4 TL |
283 | u32 l; |
284 | ||
285 | switch (bank->method) { | |
e5c56ed3 | 286 | #ifdef CONFIG_ARCH_OMAP1 |
5e1c5ff4 TL |
287 | case METHOD_MPUIO: |
288 | reg += OMAP_MPUIO_IO_CNTL; | |
289 | break; | |
e5c56ed3 DB |
290 | #endif |
291 | #ifdef CONFIG_ARCH_OMAP15XX | |
5e1c5ff4 TL |
292 | case METHOD_GPIO_1510: |
293 | reg += OMAP1510_GPIO_DIR_CONTROL; | |
294 | break; | |
e5c56ed3 DB |
295 | #endif |
296 | #ifdef CONFIG_ARCH_OMAP16XX | |
5e1c5ff4 TL |
297 | case METHOD_GPIO_1610: |
298 | reg += OMAP1610_GPIO_DIRECTION; | |
299 | break; | |
e5c56ed3 DB |
300 | #endif |
301 | #ifdef CONFIG_ARCH_OMAP730 | |
5e1c5ff4 TL |
302 | case METHOD_GPIO_730: |
303 | reg += OMAP730_GPIO_DIR_CONTROL; | |
304 | break; | |
e5c56ed3 DB |
305 | #endif |
306 | #ifdef CONFIG_ARCH_OMAP24XX | |
92105bb7 TL |
307 | case METHOD_GPIO_24XX: |
308 | reg += OMAP24XX_GPIO_OE; | |
309 | break; | |
e5c56ed3 DB |
310 | #endif |
311 | default: | |
312 | WARN_ON(1); | |
313 | return; | |
5e1c5ff4 TL |
314 | } |
315 | l = __raw_readl(reg); | |
316 | if (is_input) | |
317 | l |= 1 << gpio; | |
318 | else | |
319 | l &= ~(1 << gpio); | |
320 | __raw_writel(l, reg); | |
321 | } | |
322 | ||
323 | void omap_set_gpio_direction(int gpio, int is_input) | |
324 | { | |
325 | struct gpio_bank *bank; | |
326 | ||
327 | if (check_gpio(gpio) < 0) | |
328 | return; | |
329 | bank = get_gpio_bank(gpio); | |
330 | spin_lock(&bank->lock); | |
331 | _set_gpio_direction(bank, get_gpio_index(gpio), is_input); | |
332 | spin_unlock(&bank->lock); | |
333 | } | |
334 | ||
335 | static void _set_gpio_dataout(struct gpio_bank *bank, int gpio, int enable) | |
336 | { | |
92105bb7 | 337 | void __iomem *reg = bank->base; |
5e1c5ff4 TL |
338 | u32 l = 0; |
339 | ||
340 | switch (bank->method) { | |
e5c56ed3 | 341 | #ifdef CONFIG_ARCH_OMAP1 |
5e1c5ff4 TL |
342 | case METHOD_MPUIO: |
343 | reg += OMAP_MPUIO_OUTPUT; | |
344 | l = __raw_readl(reg); | |
345 | if (enable) | |
346 | l |= 1 << gpio; | |
347 | else | |
348 | l &= ~(1 << gpio); | |
349 | break; | |
e5c56ed3 DB |
350 | #endif |
351 | #ifdef CONFIG_ARCH_OMAP15XX | |
5e1c5ff4 TL |
352 | case METHOD_GPIO_1510: |
353 | reg += OMAP1510_GPIO_DATA_OUTPUT; | |
354 | l = __raw_readl(reg); | |
355 | if (enable) | |
356 | l |= 1 << gpio; | |
357 | else | |
358 | l &= ~(1 << gpio); | |
359 | break; | |
e5c56ed3 DB |
360 | #endif |
361 | #ifdef CONFIG_ARCH_OMAP16XX | |
5e1c5ff4 TL |
362 | case METHOD_GPIO_1610: |
363 | if (enable) | |
364 | reg += OMAP1610_GPIO_SET_DATAOUT; | |
365 | else | |
366 | reg += OMAP1610_GPIO_CLEAR_DATAOUT; | |
367 | l = 1 << gpio; | |
368 | break; | |
e5c56ed3 DB |
369 | #endif |
370 | #ifdef CONFIG_ARCH_OMAP730 | |
5e1c5ff4 TL |
371 | case METHOD_GPIO_730: |
372 | reg += OMAP730_GPIO_DATA_OUTPUT; | |
373 | l = __raw_readl(reg); | |
374 | if (enable) | |
375 | l |= 1 << gpio; | |
376 | else | |
377 | l &= ~(1 << gpio); | |
378 | break; | |
e5c56ed3 DB |
379 | #endif |
380 | #ifdef CONFIG_ARCH_OMAP24XX | |
92105bb7 TL |
381 | case METHOD_GPIO_24XX: |
382 | if (enable) | |
383 | reg += OMAP24XX_GPIO_SETDATAOUT; | |
384 | else | |
385 | reg += OMAP24XX_GPIO_CLEARDATAOUT; | |
386 | l = 1 << gpio; | |
387 | break; | |
e5c56ed3 | 388 | #endif |
5e1c5ff4 | 389 | default: |
e5c56ed3 | 390 | WARN_ON(1); |
5e1c5ff4 TL |
391 | return; |
392 | } | |
393 | __raw_writel(l, reg); | |
394 | } | |
395 | ||
396 | void omap_set_gpio_dataout(int gpio, int enable) | |
397 | { | |
398 | struct gpio_bank *bank; | |
399 | ||
400 | if (check_gpio(gpio) < 0) | |
401 | return; | |
402 | bank = get_gpio_bank(gpio); | |
403 | spin_lock(&bank->lock); | |
404 | _set_gpio_dataout(bank, get_gpio_index(gpio), enable); | |
405 | spin_unlock(&bank->lock); | |
406 | } | |
407 | ||
408 | int omap_get_gpio_datain(int gpio) | |
409 | { | |
410 | struct gpio_bank *bank; | |
92105bb7 | 411 | void __iomem *reg; |
5e1c5ff4 TL |
412 | |
413 | if (check_gpio(gpio) < 0) | |
e5c56ed3 | 414 | return -EINVAL; |
5e1c5ff4 TL |
415 | bank = get_gpio_bank(gpio); |
416 | reg = bank->base; | |
417 | switch (bank->method) { | |
e5c56ed3 | 418 | #ifdef CONFIG_ARCH_OMAP1 |
5e1c5ff4 TL |
419 | case METHOD_MPUIO: |
420 | reg += OMAP_MPUIO_INPUT_LATCH; | |
421 | break; | |
e5c56ed3 DB |
422 | #endif |
423 | #ifdef CONFIG_ARCH_OMAP15XX | |
5e1c5ff4 TL |
424 | case METHOD_GPIO_1510: |
425 | reg += OMAP1510_GPIO_DATA_INPUT; | |
426 | break; | |
e5c56ed3 DB |
427 | #endif |
428 | #ifdef CONFIG_ARCH_OMAP16XX | |
5e1c5ff4 TL |
429 | case METHOD_GPIO_1610: |
430 | reg += OMAP1610_GPIO_DATAIN; | |
431 | break; | |
e5c56ed3 DB |
432 | #endif |
433 | #ifdef CONFIG_ARCH_OMAP730 | |
5e1c5ff4 TL |
434 | case METHOD_GPIO_730: |
435 | reg += OMAP730_GPIO_DATA_INPUT; | |
436 | break; | |
e5c56ed3 DB |
437 | #endif |
438 | #ifdef CONFIG_ARCH_OMAP24XX | |
92105bb7 TL |
439 | case METHOD_GPIO_24XX: |
440 | reg += OMAP24XX_GPIO_DATAIN; | |
441 | break; | |
e5c56ed3 | 442 | #endif |
5e1c5ff4 | 443 | default: |
e5c56ed3 | 444 | return -EINVAL; |
5e1c5ff4 | 445 | } |
92105bb7 TL |
446 | return (__raw_readl(reg) |
447 | & (1 << get_gpio_index(gpio))) != 0; | |
5e1c5ff4 TL |
448 | } |
449 | ||
92105bb7 TL |
450 | #define MOD_REG_BIT(reg, bit_mask, set) \ |
451 | do { \ | |
452 | int l = __raw_readl(base + reg); \ | |
453 | if (set) l |= bit_mask; \ | |
454 | else l &= ~bit_mask; \ | |
455 | __raw_writel(l, base + reg); \ | |
456 | } while(0) | |
457 | ||
3ac4fa99 JY |
458 | #ifdef CONFIG_ARCH_OMAP24XX |
459 | static inline void set_24xx_gpio_triggering(struct gpio_bank *bank, int gpio, int trigger) | |
5e1c5ff4 | 460 | { |
3ac4fa99 | 461 | void __iomem *base = bank->base; |
92105bb7 TL |
462 | u32 gpio_bit = 1 << gpio; |
463 | ||
464 | MOD_REG_BIT(OMAP24XX_GPIO_LEVELDETECT0, gpio_bit, | |
6e60e79a | 465 | trigger & __IRQT_LOWLVL); |
92105bb7 | 466 | MOD_REG_BIT(OMAP24XX_GPIO_LEVELDETECT1, gpio_bit, |
6e60e79a | 467 | trigger & __IRQT_HIGHLVL); |
92105bb7 | 468 | MOD_REG_BIT(OMAP24XX_GPIO_RISINGDETECT, gpio_bit, |
6e60e79a | 469 | trigger & __IRQT_RISEDGE); |
92105bb7 | 470 | MOD_REG_BIT(OMAP24XX_GPIO_FALLINGDETECT, gpio_bit, |
6e60e79a | 471 | trigger & __IRQT_FALEDGE); |
3ac4fa99 JY |
472 | if (likely(!(bank->non_wakeup_gpios & gpio_bit))) { |
473 | if (trigger != 0) | |
474 | __raw_writel(1 << gpio, bank->base + OMAP24XX_GPIO_SETWKUENA); | |
475 | else | |
476 | __raw_writel(1 << gpio, bank->base + OMAP24XX_GPIO_CLEARWKUENA); | |
477 | } else { | |
478 | if (trigger != 0) | |
479 | bank->enabled_non_wakeup_gpios |= gpio_bit; | |
480 | else | |
481 | bank->enabled_non_wakeup_gpios &= ~gpio_bit; | |
482 | } | |
10dd5ce2 | 483 | /* FIXME: Possibly do 'set_irq_handler(j, handle_level_irq)' if only level |
92105bb7 TL |
484 | * triggering requested. */ |
485 | } | |
3ac4fa99 | 486 | #endif |
92105bb7 TL |
487 | |
488 | static int _set_gpio_triggering(struct gpio_bank *bank, int gpio, int trigger) | |
489 | { | |
490 | void __iomem *reg = bank->base; | |
491 | u32 l = 0; | |
5e1c5ff4 TL |
492 | |
493 | switch (bank->method) { | |
e5c56ed3 | 494 | #ifdef CONFIG_ARCH_OMAP1 |
5e1c5ff4 TL |
495 | case METHOD_MPUIO: |
496 | reg += OMAP_MPUIO_GPIO_INT_EDGE; | |
497 | l = __raw_readl(reg); | |
6e60e79a | 498 | if (trigger & __IRQT_RISEDGE) |
5e1c5ff4 | 499 | l |= 1 << gpio; |
6e60e79a | 500 | else if (trigger & __IRQT_FALEDGE) |
5e1c5ff4 | 501 | l &= ~(1 << gpio); |
92105bb7 TL |
502 | else |
503 | goto bad; | |
5e1c5ff4 | 504 | break; |
e5c56ed3 DB |
505 | #endif |
506 | #ifdef CONFIG_ARCH_OMAP15XX | |
5e1c5ff4 TL |
507 | case METHOD_GPIO_1510: |
508 | reg += OMAP1510_GPIO_INT_CONTROL; | |
509 | l = __raw_readl(reg); | |
6e60e79a | 510 | if (trigger & __IRQT_RISEDGE) |
5e1c5ff4 | 511 | l |= 1 << gpio; |
6e60e79a | 512 | else if (trigger & __IRQT_FALEDGE) |
5e1c5ff4 | 513 | l &= ~(1 << gpio); |
92105bb7 TL |
514 | else |
515 | goto bad; | |
5e1c5ff4 | 516 | break; |
e5c56ed3 | 517 | #endif |
3ac4fa99 | 518 | #ifdef CONFIG_ARCH_OMAP16XX |
5e1c5ff4 | 519 | case METHOD_GPIO_1610: |
5e1c5ff4 TL |
520 | if (gpio & 0x08) |
521 | reg += OMAP1610_GPIO_EDGE_CTRL2; | |
522 | else | |
523 | reg += OMAP1610_GPIO_EDGE_CTRL1; | |
524 | gpio &= 0x07; | |
525 | l = __raw_readl(reg); | |
526 | l &= ~(3 << (gpio << 1)); | |
6e60e79a TL |
527 | if (trigger & __IRQT_RISEDGE) |
528 | l |= 2 << (gpio << 1); | |
529 | if (trigger & __IRQT_FALEDGE) | |
530 | l |= 1 << (gpio << 1); | |
3ac4fa99 JY |
531 | if (trigger) |
532 | /* Enable wake-up during idle for dynamic tick */ | |
533 | __raw_writel(1 << gpio, bank->base + OMAP1610_GPIO_SET_WAKEUPENA); | |
534 | else | |
535 | __raw_writel(1 << gpio, bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA); | |
5e1c5ff4 | 536 | break; |
3ac4fa99 JY |
537 | #endif |
538 | #ifdef CONFIG_ARCH_OMAP730 | |
5e1c5ff4 TL |
539 | case METHOD_GPIO_730: |
540 | reg += OMAP730_GPIO_INT_CONTROL; | |
541 | l = __raw_readl(reg); | |
6e60e79a | 542 | if (trigger & __IRQT_RISEDGE) |
5e1c5ff4 | 543 | l |= 1 << gpio; |
6e60e79a | 544 | else if (trigger & __IRQT_FALEDGE) |
5e1c5ff4 | 545 | l &= ~(1 << gpio); |
92105bb7 TL |
546 | else |
547 | goto bad; | |
548 | break; | |
3ac4fa99 JY |
549 | #endif |
550 | #ifdef CONFIG_ARCH_OMAP24XX | |
92105bb7 | 551 | case METHOD_GPIO_24XX: |
3ac4fa99 | 552 | set_24xx_gpio_triggering(bank, gpio, trigger); |
5e1c5ff4 | 553 | break; |
3ac4fa99 | 554 | #endif |
5e1c5ff4 | 555 | default: |
92105bb7 | 556 | goto bad; |
5e1c5ff4 | 557 | } |
92105bb7 TL |
558 | __raw_writel(l, reg); |
559 | return 0; | |
560 | bad: | |
561 | return -EINVAL; | |
5e1c5ff4 TL |
562 | } |
563 | ||
92105bb7 | 564 | static int gpio_irq_type(unsigned irq, unsigned type) |
5e1c5ff4 TL |
565 | { |
566 | struct gpio_bank *bank; | |
92105bb7 TL |
567 | unsigned gpio; |
568 | int retval; | |
569 | ||
e5c56ed3 | 570 | if (!cpu_is_omap24xx() && irq > IH_MPUIO_BASE) |
92105bb7 TL |
571 | gpio = OMAP_MPUIO(irq - IH_MPUIO_BASE); |
572 | else | |
573 | gpio = irq - IH_GPIO_BASE; | |
5e1c5ff4 TL |
574 | |
575 | if (check_gpio(gpio) < 0) | |
92105bb7 TL |
576 | return -EINVAL; |
577 | ||
e5c56ed3 | 578 | if (type & ~IRQ_TYPE_SENSE_MASK) |
6e60e79a | 579 | return -EINVAL; |
e5c56ed3 DB |
580 | |
581 | /* OMAP1 allows only only edge triggering */ | |
582 | if (!cpu_is_omap24xx() | |
583 | && (type & (IRQ_TYPE_LEVEL_LOW|IRQ_TYPE_LEVEL_HIGH))) | |
92105bb7 TL |
584 | return -EINVAL; |
585 | ||
58781016 | 586 | bank = get_irq_chip_data(irq); |
5e1c5ff4 | 587 | spin_lock(&bank->lock); |
92105bb7 | 588 | retval = _set_gpio_triggering(bank, get_gpio_index(gpio), type); |
b9772a22 DB |
589 | if (retval == 0) { |
590 | irq_desc[irq].status &= ~IRQ_TYPE_SENSE_MASK; | |
591 | irq_desc[irq].status |= type; | |
592 | } | |
5e1c5ff4 | 593 | spin_unlock(&bank->lock); |
92105bb7 | 594 | return retval; |
5e1c5ff4 TL |
595 | } |
596 | ||
597 | static void _clear_gpio_irqbank(struct gpio_bank *bank, int gpio_mask) | |
598 | { | |
92105bb7 | 599 | void __iomem *reg = bank->base; |
5e1c5ff4 TL |
600 | |
601 | switch (bank->method) { | |
e5c56ed3 | 602 | #ifdef CONFIG_ARCH_OMAP1 |
5e1c5ff4 TL |
603 | case METHOD_MPUIO: |
604 | /* MPUIO irqstatus is reset by reading the status register, | |
605 | * so do nothing here */ | |
606 | return; | |
e5c56ed3 DB |
607 | #endif |
608 | #ifdef CONFIG_ARCH_OMAP15XX | |
5e1c5ff4 TL |
609 | case METHOD_GPIO_1510: |
610 | reg += OMAP1510_GPIO_INT_STATUS; | |
611 | break; | |
e5c56ed3 DB |
612 | #endif |
613 | #ifdef CONFIG_ARCH_OMAP16XX | |
5e1c5ff4 TL |
614 | case METHOD_GPIO_1610: |
615 | reg += OMAP1610_GPIO_IRQSTATUS1; | |
616 | break; | |
e5c56ed3 DB |
617 | #endif |
618 | #ifdef CONFIG_ARCH_OMAP730 | |
5e1c5ff4 TL |
619 | case METHOD_GPIO_730: |
620 | reg += OMAP730_GPIO_INT_STATUS; | |
621 | break; | |
e5c56ed3 DB |
622 | #endif |
623 | #ifdef CONFIG_ARCH_OMAP24XX | |
92105bb7 TL |
624 | case METHOD_GPIO_24XX: |
625 | reg += OMAP24XX_GPIO_IRQSTATUS1; | |
626 | break; | |
e5c56ed3 | 627 | #endif |
5e1c5ff4 | 628 | default: |
e5c56ed3 | 629 | WARN_ON(1); |
5e1c5ff4 TL |
630 | return; |
631 | } | |
632 | __raw_writel(gpio_mask, reg); | |
bee7930f HD |
633 | |
634 | /* Workaround for clearing DSP GPIO interrupts to allow retention */ | |
635 | if (cpu_is_omap2420()) | |
636 | __raw_writel(gpio_mask, bank->base + OMAP24XX_GPIO_IRQSTATUS2); | |
5e1c5ff4 TL |
637 | } |
638 | ||
639 | static inline void _clear_gpio_irqstatus(struct gpio_bank *bank, int gpio) | |
640 | { | |
641 | _clear_gpio_irqbank(bank, 1 << get_gpio_index(gpio)); | |
642 | } | |
643 | ||
ea6dedd7 ID |
644 | static u32 _get_gpio_irqbank_mask(struct gpio_bank *bank) |
645 | { | |
646 | void __iomem *reg = bank->base; | |
99c47707 ID |
647 | int inv = 0; |
648 | u32 l; | |
649 | u32 mask; | |
ea6dedd7 ID |
650 | |
651 | switch (bank->method) { | |
e5c56ed3 | 652 | #ifdef CONFIG_ARCH_OMAP1 |
ea6dedd7 ID |
653 | case METHOD_MPUIO: |
654 | reg += OMAP_MPUIO_GPIO_MASKIT; | |
99c47707 ID |
655 | mask = 0xffff; |
656 | inv = 1; | |
ea6dedd7 | 657 | break; |
e5c56ed3 DB |
658 | #endif |
659 | #ifdef CONFIG_ARCH_OMAP15XX | |
ea6dedd7 ID |
660 | case METHOD_GPIO_1510: |
661 | reg += OMAP1510_GPIO_INT_MASK; | |
99c47707 ID |
662 | mask = 0xffff; |
663 | inv = 1; | |
ea6dedd7 | 664 | break; |
e5c56ed3 DB |
665 | #endif |
666 | #ifdef CONFIG_ARCH_OMAP16XX | |
ea6dedd7 ID |
667 | case METHOD_GPIO_1610: |
668 | reg += OMAP1610_GPIO_IRQENABLE1; | |
99c47707 | 669 | mask = 0xffff; |
ea6dedd7 | 670 | break; |
e5c56ed3 DB |
671 | #endif |
672 | #ifdef CONFIG_ARCH_OMAP730 | |
ea6dedd7 ID |
673 | case METHOD_GPIO_730: |
674 | reg += OMAP730_GPIO_INT_MASK; | |
99c47707 ID |
675 | mask = 0xffffffff; |
676 | inv = 1; | |
ea6dedd7 | 677 | break; |
e5c56ed3 DB |
678 | #endif |
679 | #ifdef CONFIG_ARCH_OMAP24XX | |
ea6dedd7 ID |
680 | case METHOD_GPIO_24XX: |
681 | reg += OMAP24XX_GPIO_IRQENABLE1; | |
99c47707 | 682 | mask = 0xffffffff; |
ea6dedd7 | 683 | break; |
e5c56ed3 | 684 | #endif |
ea6dedd7 | 685 | default: |
e5c56ed3 | 686 | WARN_ON(1); |
ea6dedd7 ID |
687 | return 0; |
688 | } | |
689 | ||
99c47707 ID |
690 | l = __raw_readl(reg); |
691 | if (inv) | |
692 | l = ~l; | |
693 | l &= mask; | |
694 | return l; | |
ea6dedd7 ID |
695 | } |
696 | ||
5e1c5ff4 TL |
697 | static void _enable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask, int enable) |
698 | { | |
92105bb7 | 699 | void __iomem *reg = bank->base; |
5e1c5ff4 TL |
700 | u32 l; |
701 | ||
702 | switch (bank->method) { | |
e5c56ed3 | 703 | #ifdef CONFIG_ARCH_OMAP1 |
5e1c5ff4 TL |
704 | case METHOD_MPUIO: |
705 | reg += OMAP_MPUIO_GPIO_MASKIT; | |
706 | l = __raw_readl(reg); | |
707 | if (enable) | |
708 | l &= ~(gpio_mask); | |
709 | else | |
710 | l |= gpio_mask; | |
711 | break; | |
e5c56ed3 DB |
712 | #endif |
713 | #ifdef CONFIG_ARCH_OMAP15XX | |
5e1c5ff4 TL |
714 | case METHOD_GPIO_1510: |
715 | reg += OMAP1510_GPIO_INT_MASK; | |
716 | l = __raw_readl(reg); | |
717 | if (enable) | |
718 | l &= ~(gpio_mask); | |
719 | else | |
720 | l |= gpio_mask; | |
721 | break; | |
e5c56ed3 DB |
722 | #endif |
723 | #ifdef CONFIG_ARCH_OMAP16XX | |
5e1c5ff4 TL |
724 | case METHOD_GPIO_1610: |
725 | if (enable) | |
726 | reg += OMAP1610_GPIO_SET_IRQENABLE1; | |
727 | else | |
728 | reg += OMAP1610_GPIO_CLEAR_IRQENABLE1; | |
729 | l = gpio_mask; | |
730 | break; | |
e5c56ed3 DB |
731 | #endif |
732 | #ifdef CONFIG_ARCH_OMAP730 | |
5e1c5ff4 TL |
733 | case METHOD_GPIO_730: |
734 | reg += OMAP730_GPIO_INT_MASK; | |
735 | l = __raw_readl(reg); | |
736 | if (enable) | |
737 | l &= ~(gpio_mask); | |
738 | else | |
739 | l |= gpio_mask; | |
740 | break; | |
e5c56ed3 DB |
741 | #endif |
742 | #ifdef CONFIG_ARCH_OMAP24XX | |
92105bb7 TL |
743 | case METHOD_GPIO_24XX: |
744 | if (enable) | |
745 | reg += OMAP24XX_GPIO_SETIRQENABLE1; | |
746 | else | |
747 | reg += OMAP24XX_GPIO_CLEARIRQENABLE1; | |
748 | l = gpio_mask; | |
749 | break; | |
e5c56ed3 | 750 | #endif |
5e1c5ff4 | 751 | default: |
e5c56ed3 | 752 | WARN_ON(1); |
5e1c5ff4 TL |
753 | return; |
754 | } | |
755 | __raw_writel(l, reg); | |
756 | } | |
757 | ||
758 | static inline void _set_gpio_irqenable(struct gpio_bank *bank, int gpio, int enable) | |
759 | { | |
760 | _enable_gpio_irqbank(bank, 1 << get_gpio_index(gpio), enable); | |
761 | } | |
762 | ||
92105bb7 TL |
763 | /* |
764 | * Note that ENAWAKEUP needs to be enabled in GPIO_SYSCONFIG register. | |
765 | * 1510 does not seem to have a wake-up register. If JTAG is connected | |
766 | * to the target, system will wake up always on GPIO events. While | |
767 | * system is running all registered GPIO interrupts need to have wake-up | |
768 | * enabled. When system is suspended, only selected GPIO interrupts need | |
769 | * to have wake-up enabled. | |
770 | */ | |
771 | static int _set_gpio_wakeup(struct gpio_bank *bank, int gpio, int enable) | |
772 | { | |
773 | switch (bank->method) { | |
3ac4fa99 | 774 | #ifdef CONFIG_ARCH_OMAP16XX |
11a78b79 | 775 | case METHOD_MPUIO: |
92105bb7 | 776 | case METHOD_GPIO_1610: |
92105bb7 | 777 | spin_lock(&bank->lock); |
11a78b79 | 778 | if (enable) { |
92105bb7 | 779 | bank->suspend_wakeup |= (1 << gpio); |
11a78b79 DB |
780 | enable_irq_wake(bank->irq); |
781 | } else { | |
782 | disable_irq_wake(bank->irq); | |
92105bb7 | 783 | bank->suspend_wakeup &= ~(1 << gpio); |
11a78b79 | 784 | } |
92105bb7 TL |
785 | spin_unlock(&bank->lock); |
786 | return 0; | |
3ac4fa99 JY |
787 | #endif |
788 | #ifdef CONFIG_ARCH_OMAP24XX | |
789 | case METHOD_GPIO_24XX: | |
11a78b79 DB |
790 | if (bank->non_wakeup_gpios & (1 << gpio)) { |
791 | printk(KERN_ERR "Unable to modify wakeup on " | |
792 | "non-wakeup GPIO%d\n", | |
793 | (bank - gpio_bank) * 32 + gpio); | |
794 | return -EINVAL; | |
795 | } | |
3ac4fa99 JY |
796 | spin_lock(&bank->lock); |
797 | if (enable) { | |
3ac4fa99 | 798 | bank->suspend_wakeup |= (1 << gpio); |
11a78b79 DB |
799 | enable_irq_wake(bank->irq); |
800 | } else { | |
801 | disable_irq_wake(bank->irq); | |
3ac4fa99 | 802 | bank->suspend_wakeup &= ~(1 << gpio); |
11a78b79 | 803 | } |
3ac4fa99 JY |
804 | spin_unlock(&bank->lock); |
805 | return 0; | |
806 | #endif | |
92105bb7 TL |
807 | default: |
808 | printk(KERN_ERR "Can't enable GPIO wakeup for method %i\n", | |
809 | bank->method); | |
810 | return -EINVAL; | |
811 | } | |
812 | } | |
813 | ||
4196dd6b TL |
814 | static void _reset_gpio(struct gpio_bank *bank, int gpio) |
815 | { | |
816 | _set_gpio_direction(bank, get_gpio_index(gpio), 1); | |
817 | _set_gpio_irqenable(bank, gpio, 0); | |
818 | _clear_gpio_irqstatus(bank, gpio); | |
819 | _set_gpio_triggering(bank, get_gpio_index(gpio), IRQT_NOEDGE); | |
820 | } | |
821 | ||
92105bb7 TL |
822 | /* Use disable_irq_wake() and enable_irq_wake() functions from drivers */ |
823 | static int gpio_wake_enable(unsigned int irq, unsigned int enable) | |
824 | { | |
825 | unsigned int gpio = irq - IH_GPIO_BASE; | |
826 | struct gpio_bank *bank; | |
827 | int retval; | |
828 | ||
829 | if (check_gpio(gpio) < 0) | |
830 | return -ENODEV; | |
58781016 | 831 | bank = get_irq_chip_data(irq); |
92105bb7 | 832 | retval = _set_gpio_wakeup(bank, get_gpio_index(gpio), enable); |
92105bb7 TL |
833 | |
834 | return retval; | |
835 | } | |
836 | ||
5e1c5ff4 TL |
837 | int omap_request_gpio(int gpio) |
838 | { | |
839 | struct gpio_bank *bank; | |
840 | ||
841 | if (check_gpio(gpio) < 0) | |
842 | return -EINVAL; | |
843 | ||
844 | bank = get_gpio_bank(gpio); | |
845 | spin_lock(&bank->lock); | |
846 | if (unlikely(bank->reserved_map & (1 << get_gpio_index(gpio)))) { | |
847 | printk(KERN_ERR "omap-gpio: GPIO %d is already reserved!\n", gpio); | |
848 | dump_stack(); | |
849 | spin_unlock(&bank->lock); | |
850 | return -1; | |
851 | } | |
852 | bank->reserved_map |= (1 << get_gpio_index(gpio)); | |
92105bb7 | 853 | |
4196dd6b TL |
854 | /* Set trigger to none. You need to enable the desired trigger with |
855 | * request_irq() or set_irq_type(). | |
856 | */ | |
92105bb7 TL |
857 | _set_gpio_triggering(bank, get_gpio_index(gpio), IRQT_NOEDGE); |
858 | ||
1a8bfa1e | 859 | #ifdef CONFIG_ARCH_OMAP15XX |
5e1c5ff4 | 860 | if (bank->method == METHOD_GPIO_1510) { |
92105bb7 | 861 | void __iomem *reg; |
5e1c5ff4 | 862 | |
92105bb7 | 863 | /* Claim the pin for MPU */ |
5e1c5ff4 TL |
864 | reg = bank->base + OMAP1510_GPIO_PIN_CONTROL; |
865 | __raw_writel(__raw_readl(reg) | (1 << get_gpio_index(gpio)), reg); | |
866 | } | |
867 | #endif | |
868 | spin_unlock(&bank->lock); | |
869 | ||
870 | return 0; | |
871 | } | |
872 | ||
873 | void omap_free_gpio(int gpio) | |
874 | { | |
875 | struct gpio_bank *bank; | |
876 | ||
877 | if (check_gpio(gpio) < 0) | |
878 | return; | |
879 | bank = get_gpio_bank(gpio); | |
880 | spin_lock(&bank->lock); | |
881 | if (unlikely(!(bank->reserved_map & (1 << get_gpio_index(gpio))))) { | |
882 | printk(KERN_ERR "omap-gpio: GPIO %d wasn't reserved!\n", gpio); | |
883 | dump_stack(); | |
884 | spin_unlock(&bank->lock); | |
885 | return; | |
886 | } | |
92105bb7 TL |
887 | #ifdef CONFIG_ARCH_OMAP16XX |
888 | if (bank->method == METHOD_GPIO_1610) { | |
889 | /* Disable wake-up during idle for dynamic tick */ | |
890 | void __iomem *reg = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA; | |
891 | __raw_writel(1 << get_gpio_index(gpio), reg); | |
892 | } | |
893 | #endif | |
894 | #ifdef CONFIG_ARCH_OMAP24XX | |
895 | if (bank->method == METHOD_GPIO_24XX) { | |
896 | /* Disable wake-up during idle for dynamic tick */ | |
897 | void __iomem *reg = bank->base + OMAP24XX_GPIO_CLEARWKUENA; | |
898 | __raw_writel(1 << get_gpio_index(gpio), reg); | |
899 | } | |
900 | #endif | |
5e1c5ff4 | 901 | bank->reserved_map &= ~(1 << get_gpio_index(gpio)); |
4196dd6b | 902 | _reset_gpio(bank, gpio); |
5e1c5ff4 TL |
903 | spin_unlock(&bank->lock); |
904 | } | |
905 | ||
906 | /* | |
907 | * We need to unmask the GPIO bank interrupt as soon as possible to | |
908 | * avoid missing GPIO interrupts for other lines in the bank. | |
909 | * Then we need to mask-read-clear-unmask the triggered GPIO lines | |
910 | * in the bank to avoid missing nested interrupts for a GPIO line. | |
911 | * If we wait to unmask individual GPIO lines in the bank after the | |
912 | * line's interrupt handler has been run, we may miss some nested | |
913 | * interrupts. | |
914 | */ | |
10dd5ce2 | 915 | static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc) |
5e1c5ff4 | 916 | { |
92105bb7 | 917 | void __iomem *isr_reg = NULL; |
5e1c5ff4 TL |
918 | u32 isr; |
919 | unsigned int gpio_irq; | |
920 | struct gpio_bank *bank; | |
ea6dedd7 ID |
921 | u32 retrigger = 0; |
922 | int unmasked = 0; | |
5e1c5ff4 TL |
923 | |
924 | desc->chip->ack(irq); | |
925 | ||
418ca1f0 | 926 | bank = get_irq_data(irq); |
e5c56ed3 | 927 | #ifdef CONFIG_ARCH_OMAP1 |
5e1c5ff4 TL |
928 | if (bank->method == METHOD_MPUIO) |
929 | isr_reg = bank->base + OMAP_MPUIO_GPIO_INT; | |
e5c56ed3 | 930 | #endif |
1a8bfa1e | 931 | #ifdef CONFIG_ARCH_OMAP15XX |
5e1c5ff4 TL |
932 | if (bank->method == METHOD_GPIO_1510) |
933 | isr_reg = bank->base + OMAP1510_GPIO_INT_STATUS; | |
934 | #endif | |
935 | #if defined(CONFIG_ARCH_OMAP16XX) | |
936 | if (bank->method == METHOD_GPIO_1610) | |
937 | isr_reg = bank->base + OMAP1610_GPIO_IRQSTATUS1; | |
938 | #endif | |
939 | #ifdef CONFIG_ARCH_OMAP730 | |
940 | if (bank->method == METHOD_GPIO_730) | |
941 | isr_reg = bank->base + OMAP730_GPIO_INT_STATUS; | |
942 | #endif | |
92105bb7 TL |
943 | #ifdef CONFIG_ARCH_OMAP24XX |
944 | if (bank->method == METHOD_GPIO_24XX) | |
945 | isr_reg = bank->base + OMAP24XX_GPIO_IRQSTATUS1; | |
946 | #endif | |
92105bb7 | 947 | while(1) { |
6e60e79a | 948 | u32 isr_saved, level_mask = 0; |
ea6dedd7 | 949 | u32 enabled; |
6e60e79a | 950 | |
ea6dedd7 ID |
951 | enabled = _get_gpio_irqbank_mask(bank); |
952 | isr_saved = isr = __raw_readl(isr_reg) & enabled; | |
6e60e79a TL |
953 | |
954 | if (cpu_is_omap15xx() && (bank->method == METHOD_MPUIO)) | |
955 | isr &= 0x0000ffff; | |
956 | ||
ea6dedd7 | 957 | if (cpu_is_omap24xx()) { |
6e60e79a TL |
958 | level_mask = |
959 | __raw_readl(bank->base + | |
960 | OMAP24XX_GPIO_LEVELDETECT0) | | |
961 | __raw_readl(bank->base + | |
962 | OMAP24XX_GPIO_LEVELDETECT1); | |
ea6dedd7 ID |
963 | level_mask &= enabled; |
964 | } | |
6e60e79a TL |
965 | |
966 | /* clear edge sensitive interrupts before handler(s) are | |
967 | called so that we don't miss any interrupt occurred while | |
968 | executing them */ | |
969 | _enable_gpio_irqbank(bank, isr_saved & ~level_mask, 0); | |
970 | _clear_gpio_irqbank(bank, isr_saved & ~level_mask); | |
971 | _enable_gpio_irqbank(bank, isr_saved & ~level_mask, 1); | |
972 | ||
973 | /* if there is only edge sensitive GPIO pin interrupts | |
974 | configured, we could unmask GPIO bank interrupt immediately */ | |
ea6dedd7 ID |
975 | if (!level_mask && !unmasked) { |
976 | unmasked = 1; | |
6e60e79a | 977 | desc->chip->unmask(irq); |
ea6dedd7 | 978 | } |
92105bb7 | 979 | |
ea6dedd7 ID |
980 | isr |= retrigger; |
981 | retrigger = 0; | |
92105bb7 TL |
982 | if (!isr) |
983 | break; | |
984 | ||
985 | gpio_irq = bank->virtual_irq_start; | |
986 | for (; isr != 0; isr >>= 1, gpio_irq++) { | |
10dd5ce2 | 987 | struct irq_desc *d; |
ea6dedd7 | 988 | int irq_mask; |
92105bb7 TL |
989 | if (!(isr & 1)) |
990 | continue; | |
991 | d = irq_desc + gpio_irq; | |
ea6dedd7 ID |
992 | /* Don't run the handler if it's already running |
993 | * or was disabled lazely. | |
994 | */ | |
29454dde TG |
995 | if (unlikely((d->depth || |
996 | (d->status & IRQ_INPROGRESS)))) { | |
ea6dedd7 ID |
997 | irq_mask = 1 << |
998 | (gpio_irq - bank->virtual_irq_start); | |
999 | /* The unmasking will be done by | |
1000 | * enable_irq in case it is disabled or | |
1001 | * after returning from the handler if | |
1002 | * it's already running. | |
1003 | */ | |
1004 | _enable_gpio_irqbank(bank, irq_mask, 0); | |
29454dde | 1005 | if (!d->depth) { |
ea6dedd7 ID |
1006 | /* Level triggered interrupts |
1007 | * won't ever be reentered | |
1008 | */ | |
1009 | BUG_ON(level_mask & irq_mask); | |
29454dde | 1010 | d->status |= IRQ_PENDING; |
ea6dedd7 ID |
1011 | } |
1012 | continue; | |
1013 | } | |
29454dde | 1014 | |
0cd61b68 | 1015 | desc_handle_irq(gpio_irq, d); |
29454dde TG |
1016 | |
1017 | if (unlikely((d->status & IRQ_PENDING) && !d->depth)) { | |
ea6dedd7 ID |
1018 | irq_mask = 1 << |
1019 | (gpio_irq - bank->virtual_irq_start); | |
29454dde | 1020 | d->status &= ~IRQ_PENDING; |
ea6dedd7 ID |
1021 | _enable_gpio_irqbank(bank, irq_mask, 1); |
1022 | retrigger |= irq_mask; | |
1023 | } | |
92105bb7 | 1024 | } |
6e60e79a TL |
1025 | |
1026 | if (cpu_is_omap24xx()) { | |
1027 | /* clear level sensitive interrupts after handler(s) */ | |
1028 | _enable_gpio_irqbank(bank, isr_saved & level_mask, 0); | |
1029 | _clear_gpio_irqbank(bank, isr_saved & level_mask); | |
1030 | _enable_gpio_irqbank(bank, isr_saved & level_mask, 1); | |
1031 | } | |
1032 | ||
1a8bfa1e | 1033 | } |
ea6dedd7 ID |
1034 | /* if bank has any level sensitive GPIO pin interrupt |
1035 | configured, we must unmask the bank interrupt only after | |
1036 | handler(s) are executed in order to avoid spurious bank | |
1037 | interrupt */ | |
1038 | if (!unmasked) | |
1039 | desc->chip->unmask(irq); | |
1040 | ||
5e1c5ff4 TL |
1041 | } |
1042 | ||
4196dd6b TL |
1043 | static void gpio_irq_shutdown(unsigned int irq) |
1044 | { | |
1045 | unsigned int gpio = irq - IH_GPIO_BASE; | |
58781016 | 1046 | struct gpio_bank *bank = get_irq_chip_data(irq); |
4196dd6b TL |
1047 | |
1048 | _reset_gpio(bank, gpio); | |
1049 | } | |
1050 | ||
5e1c5ff4 TL |
1051 | static void gpio_ack_irq(unsigned int irq) |
1052 | { | |
1053 | unsigned int gpio = irq - IH_GPIO_BASE; | |
58781016 | 1054 | struct gpio_bank *bank = get_irq_chip_data(irq); |
5e1c5ff4 TL |
1055 | |
1056 | _clear_gpio_irqstatus(bank, gpio); | |
1057 | } | |
1058 | ||
1059 | static void gpio_mask_irq(unsigned int irq) | |
1060 | { | |
1061 | unsigned int gpio = irq - IH_GPIO_BASE; | |
58781016 | 1062 | struct gpio_bank *bank = get_irq_chip_data(irq); |
5e1c5ff4 TL |
1063 | |
1064 | _set_gpio_irqenable(bank, gpio, 0); | |
1065 | } | |
1066 | ||
1067 | static void gpio_unmask_irq(unsigned int irq) | |
1068 | { | |
1069 | unsigned int gpio = irq - IH_GPIO_BASE; | |
92105bb7 | 1070 | unsigned int gpio_idx = get_gpio_index(gpio); |
58781016 | 1071 | struct gpio_bank *bank = get_irq_chip_data(irq); |
5e1c5ff4 | 1072 | |
92105bb7 | 1073 | _set_gpio_irqenable(bank, gpio_idx, 1); |
5e1c5ff4 TL |
1074 | } |
1075 | ||
e5c56ed3 DB |
1076 | static struct irq_chip gpio_irq_chip = { |
1077 | .name = "GPIO", | |
1078 | .shutdown = gpio_irq_shutdown, | |
1079 | .ack = gpio_ack_irq, | |
1080 | .mask = gpio_mask_irq, | |
1081 | .unmask = gpio_unmask_irq, | |
1082 | .set_type = gpio_irq_type, | |
1083 | .set_wake = gpio_wake_enable, | |
1084 | }; | |
1085 | ||
1086 | /*---------------------------------------------------------------------*/ | |
1087 | ||
1088 | #ifdef CONFIG_ARCH_OMAP1 | |
1089 | ||
1090 | /* MPUIO uses the always-on 32k clock */ | |
1091 | ||
5e1c5ff4 TL |
1092 | static void mpuio_ack_irq(unsigned int irq) |
1093 | { | |
1094 | /* The ISR is reset automatically, so do nothing here. */ | |
1095 | } | |
1096 | ||
1097 | static void mpuio_mask_irq(unsigned int irq) | |
1098 | { | |
1099 | unsigned int gpio = OMAP_MPUIO(irq - IH_MPUIO_BASE); | |
58781016 | 1100 | struct gpio_bank *bank = get_irq_chip_data(irq); |
5e1c5ff4 TL |
1101 | |
1102 | _set_gpio_irqenable(bank, gpio, 0); | |
1103 | } | |
1104 | ||
1105 | static void mpuio_unmask_irq(unsigned int irq) | |
1106 | { | |
1107 | unsigned int gpio = OMAP_MPUIO(irq - IH_MPUIO_BASE); | |
58781016 | 1108 | struct gpio_bank *bank = get_irq_chip_data(irq); |
5e1c5ff4 TL |
1109 | |
1110 | _set_gpio_irqenable(bank, gpio, 1); | |
1111 | } | |
1112 | ||
e5c56ed3 DB |
1113 | static struct irq_chip mpuio_irq_chip = { |
1114 | .name = "MPUIO", | |
1115 | .ack = mpuio_ack_irq, | |
1116 | .mask = mpuio_mask_irq, | |
1117 | .unmask = mpuio_unmask_irq, | |
92105bb7 | 1118 | .set_type = gpio_irq_type, |
11a78b79 DB |
1119 | #ifdef CONFIG_ARCH_OMAP16XX |
1120 | /* REVISIT: assuming only 16xx supports MPUIO wake events */ | |
1121 | .set_wake = gpio_wake_enable, | |
1122 | #endif | |
5e1c5ff4 TL |
1123 | }; |
1124 | ||
e5c56ed3 DB |
1125 | |
1126 | #define bank_is_mpuio(bank) ((bank)->method == METHOD_MPUIO) | |
1127 | ||
11a78b79 DB |
1128 | |
1129 | #ifdef CONFIG_ARCH_OMAP16XX | |
1130 | ||
1131 | #include <linux/platform_device.h> | |
1132 | ||
1133 | static int omap_mpuio_suspend_late(struct platform_device *pdev, pm_message_t mesg) | |
1134 | { | |
1135 | struct gpio_bank *bank = platform_get_drvdata(pdev); | |
1136 | void __iomem *mask_reg = bank->base + OMAP_MPUIO_GPIO_MASKIT; | |
1137 | ||
1138 | spin_lock(&bank->lock); | |
1139 | bank->saved_wakeup = __raw_readl(mask_reg); | |
1140 | __raw_writel(0xffff & ~bank->suspend_wakeup, mask_reg); | |
1141 | spin_unlock(&bank->lock); | |
1142 | ||
1143 | return 0; | |
1144 | } | |
1145 | ||
1146 | static int omap_mpuio_resume_early(struct platform_device *pdev) | |
1147 | { | |
1148 | struct gpio_bank *bank = platform_get_drvdata(pdev); | |
1149 | void __iomem *mask_reg = bank->base + OMAP_MPUIO_GPIO_MASKIT; | |
1150 | ||
1151 | spin_lock(&bank->lock); | |
1152 | __raw_writel(bank->saved_wakeup, mask_reg); | |
1153 | spin_unlock(&bank->lock); | |
1154 | ||
1155 | return 0; | |
1156 | } | |
1157 | ||
1158 | /* use platform_driver for this, now that there's no longer any | |
1159 | * point to sys_device (other than not disturbing old code). | |
1160 | */ | |
1161 | static struct platform_driver omap_mpuio_driver = { | |
1162 | .suspend_late = omap_mpuio_suspend_late, | |
1163 | .resume_early = omap_mpuio_resume_early, | |
1164 | .driver = { | |
1165 | .name = "mpuio", | |
1166 | }, | |
1167 | }; | |
1168 | ||
1169 | static struct platform_device omap_mpuio_device = { | |
1170 | .name = "mpuio", | |
1171 | .id = -1, | |
1172 | .dev = { | |
1173 | .driver = &omap_mpuio_driver.driver, | |
1174 | } | |
1175 | /* could list the /proc/iomem resources */ | |
1176 | }; | |
1177 | ||
1178 | static inline void mpuio_init(void) | |
1179 | { | |
fcf126d8 DB |
1180 | platform_set_drvdata(&omap_mpuio_device, &gpio_bank_1610[0]); |
1181 | ||
11a78b79 DB |
1182 | if (platform_driver_register(&omap_mpuio_driver) == 0) |
1183 | (void) platform_device_register(&omap_mpuio_device); | |
1184 | } | |
1185 | ||
1186 | #else | |
1187 | static inline void mpuio_init(void) {} | |
1188 | #endif /* 16xx */ | |
1189 | ||
e5c56ed3 DB |
1190 | #else |
1191 | ||
1192 | extern struct irq_chip mpuio_irq_chip; | |
1193 | ||
1194 | #define bank_is_mpuio(bank) 0 | |
11a78b79 | 1195 | static inline void mpuio_init(void) {} |
e5c56ed3 DB |
1196 | |
1197 | #endif | |
1198 | ||
1199 | /*---------------------------------------------------------------------*/ | |
5e1c5ff4 | 1200 | |
1a8bfa1e TL |
1201 | static int initialized; |
1202 | static struct clk * gpio_ick; | |
1203 | static struct clk * gpio_fck; | |
5e1c5ff4 | 1204 | |
56a25641 SMK |
1205 | #ifdef CONFIG_ARCH_OMAP2430 |
1206 | static struct clk * gpio5_ick; | |
1207 | static struct clk * gpio5_fck; | |
1208 | #endif | |
1209 | ||
5e1c5ff4 TL |
1210 | static int __init _omap_gpio_init(void) |
1211 | { | |
1212 | int i; | |
1213 | struct gpio_bank *bank; | |
1214 | ||
1215 | initialized = 1; | |
1216 | ||
6e60e79a | 1217 | if (cpu_is_omap15xx()) { |
1a8bfa1e TL |
1218 | gpio_ick = clk_get(NULL, "arm_gpio_ck"); |
1219 | if (IS_ERR(gpio_ick)) | |
92105bb7 TL |
1220 | printk("Could not get arm_gpio_ck\n"); |
1221 | else | |
30ff720b | 1222 | clk_enable(gpio_ick); |
1a8bfa1e TL |
1223 | } |
1224 | if (cpu_is_omap24xx()) { | |
1225 | gpio_ick = clk_get(NULL, "gpios_ick"); | |
1226 | if (IS_ERR(gpio_ick)) | |
1227 | printk("Could not get gpios_ick\n"); | |
1228 | else | |
30ff720b | 1229 | clk_enable(gpio_ick); |
1a8bfa1e | 1230 | gpio_fck = clk_get(NULL, "gpios_fck"); |
1630b52d | 1231 | if (IS_ERR(gpio_fck)) |
1a8bfa1e TL |
1232 | printk("Could not get gpios_fck\n"); |
1233 | else | |
30ff720b | 1234 | clk_enable(gpio_fck); |
56a25641 SMK |
1235 | |
1236 | /* | |
1237 | * On 2430 GPIO 5 uses CORE L4 ICLK | |
1238 | */ | |
1239 | #ifdef CONFIG_ARCH_OMAP2430 | |
1240 | if (cpu_is_omap2430()) { | |
1241 | gpio5_ick = clk_get(NULL, "gpio5_ick"); | |
1242 | if (IS_ERR(gpio5_ick)) | |
1243 | printk("Could not get gpio5_ick\n"); | |
1244 | else | |
1245 | clk_enable(gpio5_ick); | |
1246 | gpio5_fck = clk_get(NULL, "gpio5_fck"); | |
1247 | if (IS_ERR(gpio5_fck)) | |
1248 | printk("Could not get gpio5_fck\n"); | |
1249 | else | |
1250 | clk_enable(gpio5_fck); | |
1251 | } | |
1252 | #endif | |
1253 | } | |
92105bb7 | 1254 | |
1a8bfa1e | 1255 | #ifdef CONFIG_ARCH_OMAP15XX |
6e60e79a | 1256 | if (cpu_is_omap15xx()) { |
5e1c5ff4 TL |
1257 | printk(KERN_INFO "OMAP1510 GPIO hardware\n"); |
1258 | gpio_bank_count = 2; | |
1259 | gpio_bank = gpio_bank_1510; | |
1260 | } | |
1261 | #endif | |
1262 | #if defined(CONFIG_ARCH_OMAP16XX) | |
1263 | if (cpu_is_omap16xx()) { | |
92105bb7 | 1264 | u32 rev; |
5e1c5ff4 TL |
1265 | |
1266 | gpio_bank_count = 5; | |
1267 | gpio_bank = gpio_bank_1610; | |
1268 | rev = omap_readw(gpio_bank[1].base + OMAP1610_GPIO_REVISION); | |
1269 | printk(KERN_INFO "OMAP GPIO hardware version %d.%d\n", | |
1270 | (rev >> 4) & 0x0f, rev & 0x0f); | |
1271 | } | |
1272 | #endif | |
1273 | #ifdef CONFIG_ARCH_OMAP730 | |
1274 | if (cpu_is_omap730()) { | |
1275 | printk(KERN_INFO "OMAP730 GPIO hardware\n"); | |
1276 | gpio_bank_count = 7; | |
1277 | gpio_bank = gpio_bank_730; | |
1278 | } | |
92105bb7 | 1279 | #endif |
56a25641 | 1280 | |
92105bb7 | 1281 | #ifdef CONFIG_ARCH_OMAP24XX |
56a25641 | 1282 | if (cpu_is_omap242x()) { |
92105bb7 TL |
1283 | int rev; |
1284 | ||
1285 | gpio_bank_count = 4; | |
56a25641 SMK |
1286 | gpio_bank = gpio_bank_242x; |
1287 | rev = omap_readl(gpio_bank[0].base + OMAP24XX_GPIO_REVISION); | |
1288 | printk(KERN_INFO "OMAP242x GPIO hardware version %d.%d\n", | |
1289 | (rev >> 4) & 0x0f, rev & 0x0f); | |
1290 | } | |
1291 | if (cpu_is_omap243x()) { | |
1292 | int rev; | |
1293 | ||
1294 | gpio_bank_count = 5; | |
1295 | gpio_bank = gpio_bank_243x; | |
92105bb7 | 1296 | rev = omap_readl(gpio_bank[0].base + OMAP24XX_GPIO_REVISION); |
56a25641 | 1297 | printk(KERN_INFO "OMAP243x GPIO hardware version %d.%d\n", |
92105bb7 TL |
1298 | (rev >> 4) & 0x0f, rev & 0x0f); |
1299 | } | |
5e1c5ff4 TL |
1300 | #endif |
1301 | for (i = 0; i < gpio_bank_count; i++) { | |
1302 | int j, gpio_count = 16; | |
1303 | ||
1304 | bank = &gpio_bank[i]; | |
1305 | bank->reserved_map = 0; | |
1306 | bank->base = IO_ADDRESS(bank->base); | |
1307 | spin_lock_init(&bank->lock); | |
e5c56ed3 | 1308 | if (bank_is_mpuio(bank)) |
5e1c5ff4 | 1309 | omap_writew(0xFFFF, OMAP_MPUIO_BASE + OMAP_MPUIO_GPIO_MASKIT); |
1a8bfa1e | 1310 | #ifdef CONFIG_ARCH_OMAP15XX |
5e1c5ff4 TL |
1311 | if (bank->method == METHOD_GPIO_1510) { |
1312 | __raw_writew(0xffff, bank->base + OMAP1510_GPIO_INT_MASK); | |
1313 | __raw_writew(0x0000, bank->base + OMAP1510_GPIO_INT_STATUS); | |
1314 | } | |
1315 | #endif | |
1316 | #if defined(CONFIG_ARCH_OMAP16XX) | |
1317 | if (bank->method == METHOD_GPIO_1610) { | |
1318 | __raw_writew(0x0000, bank->base + OMAP1610_GPIO_IRQENABLE1); | |
1319 | __raw_writew(0xffff, bank->base + OMAP1610_GPIO_IRQSTATUS1); | |
92105bb7 | 1320 | __raw_writew(0x0014, bank->base + OMAP1610_GPIO_SYSCONFIG); |
5e1c5ff4 TL |
1321 | } |
1322 | #endif | |
1323 | #ifdef CONFIG_ARCH_OMAP730 | |
1324 | if (bank->method == METHOD_GPIO_730) { | |
1325 | __raw_writel(0xffffffff, bank->base + OMAP730_GPIO_INT_MASK); | |
1326 | __raw_writel(0x00000000, bank->base + OMAP730_GPIO_INT_STATUS); | |
1327 | ||
1328 | gpio_count = 32; /* 730 has 32-bit GPIOs */ | |
1329 | } | |
92105bb7 TL |
1330 | #endif |
1331 | #ifdef CONFIG_ARCH_OMAP24XX | |
1332 | if (bank->method == METHOD_GPIO_24XX) { | |
3ac4fa99 JY |
1333 | static const u32 non_wakeup_gpios[] = { |
1334 | 0xe203ffc0, 0x08700040 | |
1335 | }; | |
1336 | ||
92105bb7 TL |
1337 | __raw_writel(0x00000000, bank->base + OMAP24XX_GPIO_IRQENABLE1); |
1338 | __raw_writel(0xffffffff, bank->base + OMAP24XX_GPIO_IRQSTATUS1); | |
14f1c3bf JY |
1339 | __raw_writew(0x0015, bank->base + OMAP24XX_GPIO_SYSCONFIG); |
1340 | ||
1341 | /* Initialize interface clock ungated, module enabled */ | |
1342 | __raw_writel(0, bank->base + OMAP24XX_GPIO_CTRL); | |
3ac4fa99 JY |
1343 | if (i < ARRAY_SIZE(non_wakeup_gpios)) |
1344 | bank->non_wakeup_gpios = non_wakeup_gpios[i]; | |
92105bb7 TL |
1345 | gpio_count = 32; |
1346 | } | |
5e1c5ff4 TL |
1347 | #endif |
1348 | for (j = bank->virtual_irq_start; | |
1349 | j < bank->virtual_irq_start + gpio_count; j++) { | |
58781016 | 1350 | set_irq_chip_data(j, bank); |
e5c56ed3 | 1351 | if (bank_is_mpuio(bank)) |
5e1c5ff4 TL |
1352 | set_irq_chip(j, &mpuio_irq_chip); |
1353 | else | |
1354 | set_irq_chip(j, &gpio_irq_chip); | |
10dd5ce2 | 1355 | set_irq_handler(j, handle_simple_irq); |
5e1c5ff4 TL |
1356 | set_irq_flags(j, IRQF_VALID); |
1357 | } | |
1358 | set_irq_chained_handler(bank->irq, gpio_irq_handler); | |
1359 | set_irq_data(bank->irq, bank); | |
1360 | } | |
1361 | ||
1362 | /* Enable system clock for GPIO module. | |
1363 | * The CAM_CLK_CTRL *is* really the right place. */ | |
92105bb7 | 1364 | if (cpu_is_omap16xx()) |
5e1c5ff4 TL |
1365 | omap_writel(omap_readl(ULPD_CAM_CLK_CTRL) | 0x04, ULPD_CAM_CLK_CTRL); |
1366 | ||
14f1c3bf JY |
1367 | #ifdef CONFIG_ARCH_OMAP24XX |
1368 | /* Enable autoidle for the OCP interface */ | |
1369 | if (cpu_is_omap24xx()) | |
1370 | omap_writel(1 << 0, 0x48019010); | |
1371 | #endif | |
1372 | ||
5e1c5ff4 TL |
1373 | return 0; |
1374 | } | |
1375 | ||
92105bb7 TL |
1376 | #if defined (CONFIG_ARCH_OMAP16XX) || defined (CONFIG_ARCH_OMAP24XX) |
1377 | static int omap_gpio_suspend(struct sys_device *dev, pm_message_t mesg) | |
1378 | { | |
1379 | int i; | |
1380 | ||
1381 | if (!cpu_is_omap24xx() && !cpu_is_omap16xx()) | |
1382 | return 0; | |
1383 | ||
1384 | for (i = 0; i < gpio_bank_count; i++) { | |
1385 | struct gpio_bank *bank = &gpio_bank[i]; | |
1386 | void __iomem *wake_status; | |
1387 | void __iomem *wake_clear; | |
1388 | void __iomem *wake_set; | |
1389 | ||
1390 | switch (bank->method) { | |
e5c56ed3 | 1391 | #ifdef CONFIG_ARCH_OMAP16XX |
92105bb7 TL |
1392 | case METHOD_GPIO_1610: |
1393 | wake_status = bank->base + OMAP1610_GPIO_WAKEUPENABLE; | |
1394 | wake_clear = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA; | |
1395 | wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA; | |
1396 | break; | |
e5c56ed3 DB |
1397 | #endif |
1398 | #ifdef CONFIG_ARCH_OMAP24XX | |
92105bb7 TL |
1399 | case METHOD_GPIO_24XX: |
1400 | wake_status = bank->base + OMAP24XX_GPIO_SETWKUENA; | |
1401 | wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA; | |
1402 | wake_set = bank->base + OMAP24XX_GPIO_SETWKUENA; | |
1403 | break; | |
e5c56ed3 | 1404 | #endif |
92105bb7 TL |
1405 | default: |
1406 | continue; | |
1407 | } | |
1408 | ||
1409 | spin_lock(&bank->lock); | |
1410 | bank->saved_wakeup = __raw_readl(wake_status); | |
1411 | __raw_writel(0xffffffff, wake_clear); | |
1412 | __raw_writel(bank->suspend_wakeup, wake_set); | |
1413 | spin_unlock(&bank->lock); | |
1414 | } | |
1415 | ||
1416 | return 0; | |
1417 | } | |
1418 | ||
1419 | static int omap_gpio_resume(struct sys_device *dev) | |
1420 | { | |
1421 | int i; | |
1422 | ||
1423 | if (!cpu_is_omap24xx() && !cpu_is_omap16xx()) | |
1424 | return 0; | |
1425 | ||
1426 | for (i = 0; i < gpio_bank_count; i++) { | |
1427 | struct gpio_bank *bank = &gpio_bank[i]; | |
1428 | void __iomem *wake_clear; | |
1429 | void __iomem *wake_set; | |
1430 | ||
1431 | switch (bank->method) { | |
e5c56ed3 | 1432 | #ifdef CONFIG_ARCH_OMAP16XX |
92105bb7 TL |
1433 | case METHOD_GPIO_1610: |
1434 | wake_clear = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA; | |
1435 | wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA; | |
1436 | break; | |
e5c56ed3 DB |
1437 | #endif |
1438 | #ifdef CONFIG_ARCH_OMAP24XX | |
92105bb7 | 1439 | case METHOD_GPIO_24XX: |
0d9356cb TL |
1440 | wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA; |
1441 | wake_set = bank->base + OMAP24XX_GPIO_SETWKUENA; | |
92105bb7 | 1442 | break; |
e5c56ed3 | 1443 | #endif |
92105bb7 TL |
1444 | default: |
1445 | continue; | |
1446 | } | |
1447 | ||
1448 | spin_lock(&bank->lock); | |
1449 | __raw_writel(0xffffffff, wake_clear); | |
1450 | __raw_writel(bank->saved_wakeup, wake_set); | |
1451 | spin_unlock(&bank->lock); | |
1452 | } | |
1453 | ||
1454 | return 0; | |
1455 | } | |
1456 | ||
1457 | static struct sysdev_class omap_gpio_sysclass = { | |
af5ca3f4 | 1458 | .name = "gpio", |
92105bb7 TL |
1459 | .suspend = omap_gpio_suspend, |
1460 | .resume = omap_gpio_resume, | |
1461 | }; | |
1462 | ||
1463 | static struct sys_device omap_gpio_device = { | |
1464 | .id = 0, | |
1465 | .cls = &omap_gpio_sysclass, | |
1466 | }; | |
3ac4fa99 JY |
1467 | |
1468 | #endif | |
1469 | ||
1470 | #ifdef CONFIG_ARCH_OMAP24XX | |
1471 | ||
1472 | static int workaround_enabled; | |
1473 | ||
1474 | void omap2_gpio_prepare_for_retention(void) | |
1475 | { | |
1476 | int i, c = 0; | |
1477 | ||
1478 | /* Remove triggering for all non-wakeup GPIOs. Otherwise spurious | |
1479 | * IRQs will be generated. See OMAP2420 Errata item 1.101. */ | |
1480 | for (i = 0; i < gpio_bank_count; i++) { | |
1481 | struct gpio_bank *bank = &gpio_bank[i]; | |
1482 | u32 l1, l2; | |
1483 | ||
1484 | if (!(bank->enabled_non_wakeup_gpios)) | |
1485 | continue; | |
1486 | bank->saved_datain = __raw_readl(bank->base + OMAP24XX_GPIO_DATAIN); | |
1487 | l1 = __raw_readl(bank->base + OMAP24XX_GPIO_FALLINGDETECT); | |
1488 | l2 = __raw_readl(bank->base + OMAP24XX_GPIO_RISINGDETECT); | |
1489 | bank->saved_fallingdetect = l1; | |
1490 | bank->saved_risingdetect = l2; | |
1491 | l1 &= ~bank->enabled_non_wakeup_gpios; | |
1492 | l2 &= ~bank->enabled_non_wakeup_gpios; | |
1493 | __raw_writel(l1, bank->base + OMAP24XX_GPIO_FALLINGDETECT); | |
1494 | __raw_writel(l2, bank->base + OMAP24XX_GPIO_RISINGDETECT); | |
1495 | c++; | |
1496 | } | |
1497 | if (!c) { | |
1498 | workaround_enabled = 0; | |
1499 | return; | |
1500 | } | |
1501 | workaround_enabled = 1; | |
1502 | } | |
1503 | ||
1504 | void omap2_gpio_resume_after_retention(void) | |
1505 | { | |
1506 | int i; | |
1507 | ||
1508 | if (!workaround_enabled) | |
1509 | return; | |
1510 | for (i = 0; i < gpio_bank_count; i++) { | |
1511 | struct gpio_bank *bank = &gpio_bank[i]; | |
1512 | u32 l; | |
1513 | ||
1514 | if (!(bank->enabled_non_wakeup_gpios)) | |
1515 | continue; | |
1516 | __raw_writel(bank->saved_fallingdetect, | |
1517 | bank->base + OMAP24XX_GPIO_FALLINGDETECT); | |
1518 | __raw_writel(bank->saved_risingdetect, | |
1519 | bank->base + OMAP24XX_GPIO_RISINGDETECT); | |
1520 | /* Check if any of the non-wakeup interrupt GPIOs have changed | |
1521 | * state. If so, generate an IRQ by software. This is | |
1522 | * horribly racy, but it's the best we can do to work around | |
1523 | * this silicon bug. */ | |
1524 | l = __raw_readl(bank->base + OMAP24XX_GPIO_DATAIN); | |
1525 | l ^= bank->saved_datain; | |
1526 | l &= bank->non_wakeup_gpios; | |
1527 | if (l) { | |
1528 | u32 old0, old1; | |
1529 | ||
1530 | old0 = __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT0); | |
1531 | old1 = __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT1); | |
1532 | __raw_writel(old0 | l, bank->base + OMAP24XX_GPIO_LEVELDETECT0); | |
1533 | __raw_writel(old1 | l, bank->base + OMAP24XX_GPIO_LEVELDETECT1); | |
1534 | __raw_writel(old0, bank->base + OMAP24XX_GPIO_LEVELDETECT0); | |
1535 | __raw_writel(old1, bank->base + OMAP24XX_GPIO_LEVELDETECT1); | |
1536 | } | |
1537 | } | |
1538 | ||
1539 | } | |
1540 | ||
92105bb7 TL |
1541 | #endif |
1542 | ||
5e1c5ff4 TL |
1543 | /* |
1544 | * This may get called early from board specific init | |
1a8bfa1e | 1545 | * for boards that have interrupts routed via FPGA. |
5e1c5ff4 | 1546 | */ |
277d58ef | 1547 | int __init omap_gpio_init(void) |
5e1c5ff4 TL |
1548 | { |
1549 | if (!initialized) | |
1550 | return _omap_gpio_init(); | |
1551 | else | |
1552 | return 0; | |
1553 | } | |
1554 | ||
92105bb7 TL |
1555 | static int __init omap_gpio_sysinit(void) |
1556 | { | |
1557 | int ret = 0; | |
1558 | ||
1559 | if (!initialized) | |
1560 | ret = _omap_gpio_init(); | |
1561 | ||
11a78b79 DB |
1562 | mpuio_init(); |
1563 | ||
92105bb7 TL |
1564 | #if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP24XX) |
1565 | if (cpu_is_omap16xx() || cpu_is_omap24xx()) { | |
1566 | if (ret == 0) { | |
1567 | ret = sysdev_class_register(&omap_gpio_sysclass); | |
1568 | if (ret == 0) | |
1569 | ret = sysdev_register(&omap_gpio_device); | |
1570 | } | |
1571 | } | |
1572 | #endif | |
1573 | ||
1574 | return ret; | |
1575 | } | |
1576 | ||
5e1c5ff4 TL |
1577 | EXPORT_SYMBOL(omap_request_gpio); |
1578 | EXPORT_SYMBOL(omap_free_gpio); | |
1579 | EXPORT_SYMBOL(omap_set_gpio_direction); | |
1580 | EXPORT_SYMBOL(omap_set_gpio_dataout); | |
1581 | EXPORT_SYMBOL(omap_get_gpio_datain); | |
5e1c5ff4 | 1582 | |
92105bb7 | 1583 | arch_initcall(omap_gpio_sysinit); |
b9772a22 DB |
1584 | |
1585 | ||
1586 | #ifdef CONFIG_DEBUG_FS | |
1587 | ||
1588 | #include <linux/debugfs.h> | |
1589 | #include <linux/seq_file.h> | |
1590 | ||
1591 | static int gpio_is_input(struct gpio_bank *bank, int mask) | |
1592 | { | |
1593 | void __iomem *reg = bank->base; | |
1594 | ||
1595 | switch (bank->method) { | |
1596 | case METHOD_MPUIO: | |
1597 | reg += OMAP_MPUIO_IO_CNTL; | |
1598 | break; | |
1599 | case METHOD_GPIO_1510: | |
1600 | reg += OMAP1510_GPIO_DIR_CONTROL; | |
1601 | break; | |
1602 | case METHOD_GPIO_1610: | |
1603 | reg += OMAP1610_GPIO_DIRECTION; | |
1604 | break; | |
1605 | case METHOD_GPIO_730: | |
1606 | reg += OMAP730_GPIO_DIR_CONTROL; | |
1607 | break; | |
1608 | case METHOD_GPIO_24XX: | |
1609 | reg += OMAP24XX_GPIO_OE; | |
1610 | break; | |
1611 | } | |
1612 | return __raw_readl(reg) & mask; | |
1613 | } | |
1614 | ||
1615 | ||
1616 | static int dbg_gpio_show(struct seq_file *s, void *unused) | |
1617 | { | |
1618 | unsigned i, j, gpio; | |
1619 | ||
1620 | for (i = 0, gpio = 0; i < gpio_bank_count; i++) { | |
1621 | struct gpio_bank *bank = gpio_bank + i; | |
1622 | unsigned bankwidth = 16; | |
1623 | u32 mask = 1; | |
1624 | ||
e5c56ed3 | 1625 | if (bank_is_mpuio(bank)) |
b9772a22 DB |
1626 | gpio = OMAP_MPUIO(0); |
1627 | else if (cpu_is_omap24xx() || cpu_is_omap730()) | |
1628 | bankwidth = 32; | |
1629 | ||
1630 | for (j = 0; j < bankwidth; j++, gpio++, mask <<= 1) { | |
1631 | unsigned irq, value, is_in, irqstat; | |
1632 | ||
1633 | if (!(bank->reserved_map & mask)) | |
1634 | continue; | |
1635 | ||
1636 | irq = bank->virtual_irq_start + j; | |
1637 | value = omap_get_gpio_datain(gpio); | |
1638 | is_in = gpio_is_input(bank, mask); | |
1639 | ||
e5c56ed3 | 1640 | if (bank_is_mpuio(bank)) |
b9772a22 DB |
1641 | seq_printf(s, "MPUIO %2d: ", j); |
1642 | else | |
1643 | seq_printf(s, "GPIO %3d: ", gpio); | |
1644 | seq_printf(s, "%s %s", | |
1645 | is_in ? "in " : "out", | |
1646 | value ? "hi" : "lo"); | |
1647 | ||
1648 | irqstat = irq_desc[irq].status; | |
1649 | if (is_in && ((bank->suspend_wakeup & mask) | |
1650 | || irqstat & IRQ_TYPE_SENSE_MASK)) { | |
1651 | char *trigger = NULL; | |
1652 | ||
1653 | switch (irqstat & IRQ_TYPE_SENSE_MASK) { | |
1654 | case IRQ_TYPE_EDGE_FALLING: | |
1655 | trigger = "falling"; | |
1656 | break; | |
1657 | case IRQ_TYPE_EDGE_RISING: | |
1658 | trigger = "rising"; | |
1659 | break; | |
1660 | case IRQ_TYPE_EDGE_BOTH: | |
1661 | trigger = "bothedge"; | |
1662 | break; | |
1663 | case IRQ_TYPE_LEVEL_LOW: | |
1664 | trigger = "low"; | |
1665 | break; | |
1666 | case IRQ_TYPE_LEVEL_HIGH: | |
1667 | trigger = "high"; | |
1668 | break; | |
1669 | case IRQ_TYPE_NONE: | |
1670 | trigger = "(unspecified)"; | |
1671 | break; | |
1672 | } | |
1673 | seq_printf(s, ", irq-%d %s%s", | |
1674 | irq, trigger, | |
1675 | (bank->suspend_wakeup & mask) | |
1676 | ? " wakeup" : ""); | |
1677 | } | |
1678 | seq_printf(s, "\n"); | |
1679 | } | |
1680 | ||
e5c56ed3 | 1681 | if (bank_is_mpuio(bank)) { |
b9772a22 DB |
1682 | seq_printf(s, "\n"); |
1683 | gpio = 0; | |
1684 | } | |
1685 | } | |
1686 | return 0; | |
1687 | } | |
1688 | ||
1689 | static int dbg_gpio_open(struct inode *inode, struct file *file) | |
1690 | { | |
e5c56ed3 | 1691 | return single_open(file, dbg_gpio_show, &inode->i_private); |
b9772a22 DB |
1692 | } |
1693 | ||
1694 | static const struct file_operations debug_fops = { | |
1695 | .open = dbg_gpio_open, | |
1696 | .read = seq_read, | |
1697 | .llseek = seq_lseek, | |
1698 | .release = single_release, | |
1699 | }; | |
1700 | ||
1701 | static int __init omap_gpio_debuginit(void) | |
1702 | { | |
e5c56ed3 DB |
1703 | (void) debugfs_create_file("omap_gpio", S_IRUGO, |
1704 | NULL, NULL, &debug_fops); | |
b9772a22 DB |
1705 | return 0; |
1706 | } | |
1707 | late_initcall(omap_gpio_debuginit); | |
1708 | #endif |