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OMAP: GPIO: Implement GPIO as a platform device
[linux-2.6-block.git] / arch / arm / plat-omap / gpio.c
CommitLineData
5e1c5ff4
TL		 1/*
2 * linux/arch/arm/plat-omap/gpio.c
3 *
4 * Support functions for OMAP GPIO
5 *
92105bb7 6 * Copyright (C) 2003-2005 Nokia Corporation
96de0e25 7 * Written by Juha Yrjölä <juha.yrjola@nokia.com>
5e1c5ff4 8 *
44169075
SS		 9 * Copyright (C) 2009 Texas Instruments
10 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
11 *
5e1c5ff4
TL		 12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License version 2 as
14 * published by the Free Software Foundation.
15 */
16
5e1c5ff4
TL		 17#include <linux/init.h>
18#include <linux/module.h>
5e1c5ff4 19#include <linux/interrupt.h>
92105bb7
TL		 20#include <linux/sysdev.h>
21#include <linux/err.h>
f8ce2547 22#include <linux/clk.h>
fced80c7 23#include <linux/io.h>
77640aab
VC		 24#include <linux/slab.h>
25#include <linux/pm_runtime.h>
5e1c5ff4 26
a09e64fb 27#include <mach/hardware.h>
5e1c5ff4 28#include <asm/irq.h>
a09e64fb
RK		 29#include <mach/irqs.h>
30#include <mach/gpio.h>
5e1c5ff4 31#include <asm/mach/irq.h>
43ffcd9a 32#include <plat/powerdomain.h>
5e1c5ff4 33
5e1c5ff4
TL		 34/*
35 * OMAP1510 GPIO registers
36 */
5e1c5ff4
TL		 37#define OMAP1510_GPIO_DATA_INPUT 0x00
38#define OMAP1510_GPIO_DATA_OUTPUT 0x04
39#define OMAP1510_GPIO_DIR_CONTROL 0x08
40#define OMAP1510_GPIO_INT_CONTROL 0x0c
41#define OMAP1510_GPIO_INT_MASK 0x10
42#define OMAP1510_GPIO_INT_STATUS 0x14
43#define OMAP1510_GPIO_PIN_CONTROL 0x18
44
45#define OMAP1510_IH_GPIO_BASE 64
46
47/*
48 * OMAP1610 specific GPIO registers
49 */
5e1c5ff4
TL		 50#define OMAP1610_GPIO_REVISION 0x0000
51#define OMAP1610_GPIO_SYSCONFIG 0x0010
52#define OMAP1610_GPIO_SYSSTATUS 0x0014
53#define OMAP1610_GPIO_IRQSTATUS1 0x0018
54#define OMAP1610_GPIO_IRQENABLE1 0x001c
92105bb7 55#define OMAP1610_GPIO_WAKEUPENABLE 0x0028
5e1c5ff4
TL		 56#define OMAP1610_GPIO_DATAIN 0x002c
57#define OMAP1610_GPIO_DATAOUT 0x0030
58#define OMAP1610_GPIO_DIRECTION 0x0034
59#define OMAP1610_GPIO_EDGE_CTRL1 0x0038
60#define OMAP1610_GPIO_EDGE_CTRL2 0x003c
61#define OMAP1610_GPIO_CLEAR_IRQENABLE1 0x009c
92105bb7 62#define OMAP1610_GPIO_CLEAR_WAKEUPENA 0x00a8
5e1c5ff4
TL		 63#define OMAP1610_GPIO_CLEAR_DATAOUT 0x00b0
64#define OMAP1610_GPIO_SET_IRQENABLE1 0x00dc
92105bb7 65#define OMAP1610_GPIO_SET_WAKEUPENA 0x00e8
5e1c5ff4
TL		 66#define OMAP1610_GPIO_SET_DATAOUT 0x00f0
67
68/*
7c006926 69 * OMAP7XX specific GPIO registers
5e1c5ff4 70 */
7c006926
AB		 71#define OMAP7XX_GPIO_DATA_INPUT 0x00
72#define OMAP7XX_GPIO_DATA_OUTPUT 0x04
73#define OMAP7XX_GPIO_DIR_CONTROL 0x08
74#define OMAP7XX_GPIO_INT_CONTROL 0x0c
75#define OMAP7XX_GPIO_INT_MASK 0x10
76#define OMAP7XX_GPIO_INT_STATUS 0x14
5e1c5ff4 77
92105bb7 78/*
77640aab 79 * omap2+ specific GPIO registers
92105bb7 80 */
92105bb7 81#define OMAP24XX_GPIO_REVISION 0x0000
92105bb7 82#define OMAP24XX_GPIO_IRQSTATUS1 0x0018
bee7930f
HD		 83#define OMAP24XX_GPIO_IRQSTATUS2 0x0028
84#define OMAP24XX_GPIO_IRQENABLE2 0x002c
92105bb7 85#define OMAP24XX_GPIO_IRQENABLE1 0x001c
723fdb78 86#define OMAP24XX_GPIO_WAKE_EN 0x0020
92105bb7
TL		 87#define OMAP24XX_GPIO_CTRL 0x0030
88#define OMAP24XX_GPIO_OE 0x0034
89#define OMAP24XX_GPIO_DATAIN 0x0038
90#define OMAP24XX_GPIO_DATAOUT 0x003c
91#define OMAP24XX_GPIO_LEVELDETECT0 0x0040
92#define OMAP24XX_GPIO_LEVELDETECT1 0x0044
93#define OMAP24XX_GPIO_RISINGDETECT 0x0048
94#define OMAP24XX_GPIO_FALLINGDETECT 0x004c
5eb3bb9c
KH		 95#define OMAP24XX_GPIO_DEBOUNCE_EN 0x0050
96#define OMAP24XX_GPIO_DEBOUNCE_VAL 0x0054
92105bb7
TL		 97#define OMAP24XX_GPIO_CLEARIRQENABLE1 0x0060
98#define OMAP24XX_GPIO_SETIRQENABLE1 0x0064
99#define OMAP24XX_GPIO_CLEARWKUENA 0x0080
100#define OMAP24XX_GPIO_SETWKUENA 0x0084
101#define OMAP24XX_GPIO_CLEARDATAOUT 0x0090
102#define OMAP24XX_GPIO_SETDATAOUT 0x0094
103
78a1a6d3 104#define OMAP4_GPIO_REVISION 0x0000
78a1a6d3
SR		 105#define OMAP4_GPIO_EOI 0x0020
106#define OMAP4_GPIO_IRQSTATUSRAW0 0x0024
107#define OMAP4_GPIO_IRQSTATUSRAW1 0x0028
108#define OMAP4_GPIO_IRQSTATUS0 0x002c
109#define OMAP4_GPIO_IRQSTATUS1 0x0030
110#define OMAP4_GPIO_IRQSTATUSSET0 0x0034
111#define OMAP4_GPIO_IRQSTATUSSET1 0x0038
112#define OMAP4_GPIO_IRQSTATUSCLR0 0x003c
113#define OMAP4_GPIO_IRQSTATUSCLR1 0x0040
114#define OMAP4_GPIO_IRQWAKEN0 0x0044
115#define OMAP4_GPIO_IRQWAKEN1 0x0048
9f096868
C		 116#define OMAP4_GPIO_IRQENABLE1 0x011c
117#define OMAP4_GPIO_WAKE_EN 0x0120
118#define OMAP4_GPIO_IRQSTATUS2 0x0128
119#define OMAP4_GPIO_IRQENABLE2 0x012c
78a1a6d3
SR		 120#define OMAP4_GPIO_CTRL 0x0130
121#define OMAP4_GPIO_OE 0x0134
122#define OMAP4_GPIO_DATAIN 0x0138
123#define OMAP4_GPIO_DATAOUT 0x013c
124#define OMAP4_GPIO_LEVELDETECT0 0x0140
125#define OMAP4_GPIO_LEVELDETECT1 0x0144
126#define OMAP4_GPIO_RISINGDETECT 0x0148
127#define OMAP4_GPIO_FALLINGDETECT 0x014c
128#define OMAP4_GPIO_DEBOUNCENABLE 0x0150
129#define OMAP4_GPIO_DEBOUNCINGTIME 0x0154
9f096868
C		 130#define OMAP4_GPIO_CLEARIRQENABLE1 0x0160
131#define OMAP4_GPIO_SETIRQENABLE1 0x0164
132#define OMAP4_GPIO_CLEARWKUENA 0x0180
133#define OMAP4_GPIO_SETWKUENA 0x0184
78a1a6d3
SR		 134#define OMAP4_GPIO_CLEARDATAOUT 0x0190
135#define OMAP4_GPIO_SETDATAOUT 0x0194
5492fb1a 136
5e1c5ff4 137struct gpio_bank {
9f7065da 138 unsigned long pbase;
92105bb7 139 void __iomem *base;
5e1c5ff4
TL		 140 u16 irq;
141 u16 virtual_irq_start;
92105bb7 142 int method;
140455fa 143#if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP2PLUS)
92105bb7
TL		 144 u32 suspend_wakeup;
145 u32 saved_wakeup;
3ac4fa99 146#endif
3ac4fa99
JY		 147 u32 non_wakeup_gpios;
148 u32 enabled_non_wakeup_gpios;
149
150 u32 saved_datain;
151 u32 saved_fallingdetect;
152 u32 saved_risingdetect;
b144ff6f 153 u32 level_mask;
4318f36b 154 u32 toggle_mask;
5e1c5ff4 155 spinlock_t lock;
52e31344 156 struct gpio_chip chip;
89db9482 157 struct clk *dbck;
058af1ea 158 u32 mod_usage;
8865b9b6 159 u32 dbck_enable_mask;
77640aab
VC		 160 struct device *dev;
161 bool dbck_flag;
5e1c5ff4
TL		 162};
163
a8eb7ca0 164#ifdef CONFIG_ARCH_OMAP3
40c670f0 165struct omap3_gpio_regs {
40c670f0
RN		 166 u32 irqenable1;
167 u32 irqenable2;
168 u32 wake_en;
169 u32 ctrl;
170 u32 oe;
171 u32 leveldetect0;
172 u32 leveldetect1;
173 u32 risingdetect;
174 u32 fallingdetect;
175 u32 dataout;
5492fb1a
SMK		 176};
177
40c670f0 178static struct omap3_gpio_regs gpio_context[OMAP34XX_NR_GPIOS];
5492fb1a
SMK		 179#endif
180
77640aab
VC		 181/*
182 * TODO: Cleanup gpio_bank usage as it is having information
183 * related to all instances of the device
184 */
185static struct gpio_bank *gpio_bank;
44169075 186
77640aab 187static int bank_width;
44169075 188
c95d10bc
VC		 189/* TODO: Analyze removing gpio_bank_count usage from driver code */
190int gpio_bank_count;
5e1c5ff4
TL		 191
192static inline struct gpio_bank *get_gpio_bank(int gpio)
193{
6e60e79a 194 if (cpu_is_omap15xx()) {
5e1c5ff4
TL		 195 if (OMAP_GPIO_IS_MPUIO(gpio))
196 return &gpio_bank[0];
197 return &gpio_bank[1];
198 }
5e1c5ff4
TL		 199 if (cpu_is_omap16xx()) {
200 if (OMAP_GPIO_IS_MPUIO(gpio))
201 return &gpio_bank[0];
202 return &gpio_bank[1 + (gpio >> 4)];
203 }
56739a69 204 if (cpu_is_omap7xx()) {
5e1c5ff4
TL		 205 if (OMAP_GPIO_IS_MPUIO(gpio))
206 return &gpio_bank[0];
207 return &gpio_bank[1 + (gpio >> 5)];
208 }
92105bb7
TL		 209 if (cpu_is_omap24xx())
210 return &gpio_bank[gpio >> 5];
44169075 211 if (cpu_is_omap34xx() || cpu_is_omap44xx())
5492fb1a 212 return &gpio_bank[gpio >> 5];
e031ab23
DB		 213 BUG();
214 return NULL;
5e1c5ff4
TL		 215}
216
217static inline int get_gpio_index(int gpio)
218{
56739a69 219 if (cpu_is_omap7xx())
5e1c5ff4 220 return gpio & 0x1f;
92105bb7
TL		 221 if (cpu_is_omap24xx())
222 return gpio & 0x1f;
44169075 223 if (cpu_is_omap34xx() || cpu_is_omap44xx())
5492fb1a 224 return gpio & 0x1f;
92105bb7 225 return gpio & 0x0f;
5e1c5ff4
TL		 226}
227
228static inline int gpio_valid(int gpio)
229{
230 if (gpio < 0)
231 return -1;
d11ac979 232 if (cpu_class_is_omap1() && OMAP_GPIO_IS_MPUIO(gpio)) {
193e68be 233 if (gpio >= OMAP_MAX_GPIO_LINES + 16)
5e1c5ff4
TL		 234 return -1;
235 return 0;
236 }
6e60e79a 237 if (cpu_is_omap15xx() && gpio < 16)
5e1c5ff4 238 return 0;
5e1c5ff4
TL		 239 if ((cpu_is_omap16xx()) && gpio < 64)
240 return 0;
56739a69 241 if (cpu_is_omap7xx() && gpio < 192)
5e1c5ff4 242 return 0;
25d6f630
TL		 243 if (cpu_is_omap2420() && gpio < 128)
244 return 0;
245 if (cpu_is_omap2430() && gpio < 160)
92105bb7 246 return 0;
44169075 247 if ((cpu_is_omap34xx() || cpu_is_omap44xx()) && gpio < 192)
5492fb1a 248 return 0;
5e1c5ff4
TL		 249 return -1;
250}
251
252static int check_gpio(int gpio)
253{
d32b20fc 254 if (unlikely(gpio_valid(gpio) < 0)) {
5e1c5ff4
TL		 255 printk(KERN_ERR "omap-gpio: invalid GPIO %d\n", gpio);
256 dump_stack();
257 return -1;
258 }
259 return 0;
260}
261
262static void _set_gpio_direction(struct gpio_bank *bank, int gpio, int is_input)
263{
92105bb7 264 void __iomem *reg = bank->base;
5e1c5ff4
TL		 265 u32 l;
266
267 switch (bank->method) {
e5c56ed3 268#ifdef CONFIG_ARCH_OMAP1
5e1c5ff4
TL		 269 case METHOD_MPUIO:
270 reg += OMAP_MPUIO_IO_CNTL;
271 break;
e5c56ed3
DB		 272#endif
273#ifdef CONFIG_ARCH_OMAP15XX
5e1c5ff4
TL		 274 case METHOD_GPIO_1510:
275 reg += OMAP1510_GPIO_DIR_CONTROL;
276 break;
e5c56ed3
DB		 277#endif
278#ifdef CONFIG_ARCH_OMAP16XX
5e1c5ff4
TL		 279 case METHOD_GPIO_1610:
280 reg += OMAP1610_GPIO_DIRECTION;
281 break;
e5c56ed3 282#endif
b718aa81 283#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
7c006926
AB		 284 case METHOD_GPIO_7XX:
285 reg += OMAP7XX_GPIO_DIR_CONTROL;
56739a69
ZM		 286 break;
287#endif
a8eb7ca0 288#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
92105bb7
TL		 289 case METHOD_GPIO_24XX:
290 reg += OMAP24XX_GPIO_OE;
291 break;
78a1a6d3
SR		 292#endif
293#if defined(CONFIG_ARCH_OMAP4)
3f1686a9 294 case METHOD_GPIO_44XX:
78a1a6d3
SR		 295 reg += OMAP4_GPIO_OE;
296 break;
e5c56ed3
DB		 297#endif
298 default:
299 WARN_ON(1);
300 return;
5e1c5ff4
TL		 301 }
302 l = __raw_readl(reg);
303 if (is_input)
304 l |= 1 << gpio;
305 else
306 l &= ~(1 << gpio);
307 __raw_writel(l, reg);
308}
309
5e1c5ff4
TL		 310static void _set_gpio_dataout(struct gpio_bank *bank, int gpio, int enable)
311{
92105bb7 312 void __iomem *reg = bank->base;
5e1c5ff4
TL		 313 u32 l = 0;
314
315 switch (bank->method) {
e5c56ed3 316#ifdef CONFIG_ARCH_OMAP1
5e1c5ff4
TL		 317 case METHOD_MPUIO:
318 reg += OMAP_MPUIO_OUTPUT;
319 l = __raw_readl(reg);
320 if (enable)
321 l |= 1 << gpio;
322 else
323 l &= ~(1 << gpio);
324 break;
e5c56ed3
DB		 325#endif
326#ifdef CONFIG_ARCH_OMAP15XX
5e1c5ff4
TL		 327 case METHOD_GPIO_1510:
328 reg += OMAP1510_GPIO_DATA_OUTPUT;
329 l = __raw_readl(reg);
330 if (enable)
331 l |= 1 << gpio;
332 else
333 l &= ~(1 << gpio);
334 break;
e5c56ed3
DB		 335#endif
336#ifdef CONFIG_ARCH_OMAP16XX
5e1c5ff4
TL		 337 case METHOD_GPIO_1610:
338 if (enable)
339 reg += OMAP1610_GPIO_SET_DATAOUT;
340 else
341 reg += OMAP1610_GPIO_CLEAR_DATAOUT;
342 l = 1 << gpio;
343 break;
e5c56ed3 344#endif
b718aa81 345#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
7c006926
AB		 346 case METHOD_GPIO_7XX:
347 reg += OMAP7XX_GPIO_DATA_OUTPUT;
56739a69
ZM		 348 l = __raw_readl(reg);
349 if (enable)
350 l |= 1 << gpio;
351 else
352 l &= ~(1 << gpio);
353 break;
354#endif
a8eb7ca0 355#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
92105bb7
TL		 356 case METHOD_GPIO_24XX:
357 if (enable)
358 reg += OMAP24XX_GPIO_SETDATAOUT;
359 else
360 reg += OMAP24XX_GPIO_CLEARDATAOUT;
361 l = 1 << gpio;
362 break;
78a1a6d3
SR		 363#endif
364#ifdef CONFIG_ARCH_OMAP4
3f1686a9 365 case METHOD_GPIO_44XX:
78a1a6d3
SR		 366 if (enable)
367 reg += OMAP4_GPIO_SETDATAOUT;
368 else
369 reg += OMAP4_GPIO_CLEARDATAOUT;
370 l = 1 << gpio;
371 break;
e5c56ed3 372#endif
5e1c5ff4 373 default:
e5c56ed3 374 WARN_ON(1);
5e1c5ff4
TL		 375 return;
376 }
377 __raw_writel(l, reg);
378}
379
b37c45b8 380static int _get_gpio_datain(struct gpio_bank *bank, int gpio)
5e1c5ff4 381{
92105bb7 382 void __iomem *reg;
5e1c5ff4
TL		 383
384 if (check_gpio(gpio) < 0)
e5c56ed3 385 return -EINVAL;
5e1c5ff4
TL		 386 reg = bank->base;
387 switch (bank->method) {
e5c56ed3 388#ifdef CONFIG_ARCH_OMAP1
5e1c5ff4
TL		 389 case METHOD_MPUIO:
390 reg += OMAP_MPUIO_INPUT_LATCH;
391 break;
e5c56ed3
DB		 392#endif
393#ifdef CONFIG_ARCH_OMAP15XX
5e1c5ff4
TL		 394 case METHOD_GPIO_1510:
395 reg += OMAP1510_GPIO_DATA_INPUT;
396 break;
e5c56ed3
DB		 397#endif
398#ifdef CONFIG_ARCH_OMAP16XX
5e1c5ff4
TL		 399 case METHOD_GPIO_1610:
400 reg += OMAP1610_GPIO_DATAIN;
401 break;
e5c56ed3 402#endif
b718aa81 403#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
7c006926
AB		 404 case METHOD_GPIO_7XX:
405 reg += OMAP7XX_GPIO_DATA_INPUT;
56739a69
ZM		 406 break;
407#endif
a8eb7ca0 408#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
92105bb7
TL		 409 case METHOD_GPIO_24XX:
410 reg += OMAP24XX_GPIO_DATAIN;
411 break;
78a1a6d3
SR		 412#endif
413#ifdef CONFIG_ARCH_OMAP4
3f1686a9 414 case METHOD_GPIO_44XX:
78a1a6d3
SR		 415 reg += OMAP4_GPIO_DATAIN;
416 break;
e5c56ed3 417#endif
5e1c5ff4 418 default:
e5c56ed3 419 return -EINVAL;
5e1c5ff4 420 }
92105bb7
TL		 421 return (__raw_readl(reg)
422 & (1 << get_gpio_index(gpio))) != 0;
5e1c5ff4
TL		 423}
424
b37c45b8
RQ		 425static int _get_gpio_dataout(struct gpio_bank *bank, int gpio)
426{
427 void __iomem *reg;
428
429 if (check_gpio(gpio) < 0)
430 return -EINVAL;
431 reg = bank->base;
432
433 switch (bank->method) {
434#ifdef CONFIG_ARCH_OMAP1
435 case METHOD_MPUIO:
436 reg += OMAP_MPUIO_OUTPUT;
437 break;
438#endif
439#ifdef CONFIG_ARCH_OMAP15XX
440 case METHOD_GPIO_1510:
441 reg += OMAP1510_GPIO_DATA_OUTPUT;
442 break;
443#endif
444#ifdef CONFIG_ARCH_OMAP16XX
445 case METHOD_GPIO_1610:
446 reg += OMAP1610_GPIO_DATAOUT;
447 break;
448#endif
b718aa81 449#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
7c006926
AB		 450 case METHOD_GPIO_7XX:
451 reg += OMAP7XX_GPIO_DATA_OUTPUT;
b37c45b8
RQ		 452 break;
453#endif
9f096868 454#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
b37c45b8
RQ		 455 case METHOD_GPIO_24XX:
456 reg += OMAP24XX_GPIO_DATAOUT;
457 break;
9f096868
C		 458#endif
459#ifdef CONFIG_ARCH_OMAP4
460 case METHOD_GPIO_44XX:
461 reg += OMAP4_GPIO_DATAOUT;
462 break;
b37c45b8
RQ		 463#endif
464 default:
465 return -EINVAL;
466 }
467
468 return (__raw_readl(reg) & (1 << get_gpio_index(gpio))) != 0;
469}
470
92105bb7
TL		 471#define MOD_REG_BIT(reg, bit_mask, set) \
472do { \
473 int l = __raw_readl(base + reg); \
474 if (set) l |= bit_mask; \
475 else l &= ~bit_mask; \
476 __raw_writel(l, base + reg); \
477} while(0)
478
168ef3d9
FB		 479/**
480 * _set_gpio_debounce - low level gpio debounce time
481 * @bank: the gpio bank we're acting upon
482 * @gpio: the gpio number on this @gpio
483 * @debounce: debounce time to use
484 *
485 * OMAP's debounce time is in 31us steps so we need
486 * to convert and round up to the closest unit.
487 */
488static void _set_gpio_debounce(struct gpio_bank *bank, unsigned gpio,
489 unsigned debounce)
490{
491 void __iomem *reg = bank->base;
492 u32 val;
493 u32 l;
494
77640aab
VC		 495 if (!bank->dbck_flag)
496 return;
497
168ef3d9
FB		 498 if (debounce < 32)
499 debounce = 0x01;
500 else if (debounce > 7936)
501 debounce = 0xff;
502 else
503 debounce = (debounce / 0x1f) - 1;
504
505 l = 1 << get_gpio_index(gpio);
506
77640aab 507 if (bank->method == METHOD_GPIO_44XX)
168ef3d9
FB		 508 reg += OMAP4_GPIO_DEBOUNCINGTIME;
509 else
510 reg += OMAP24XX_GPIO_DEBOUNCE_VAL;
511
512 __raw_writel(debounce, reg);
513
514 reg = bank->base;
77640aab 515 if (bank->method == METHOD_GPIO_44XX)
168ef3d9
FB		 516 reg += OMAP4_GPIO_DEBOUNCENABLE;
517 else
518 reg += OMAP24XX_GPIO_DEBOUNCE_EN;
519
520 val = __raw_readl(reg);
521
522 if (debounce) {
523 val |= l;
77640aab 524 clk_enable(bank->dbck);
168ef3d9
FB		 525 } else {
526 val &= ~l;
77640aab 527 clk_disable(bank->dbck);
168ef3d9 528 }
f7ec0b0b 529 bank->dbck_enable_mask = val;
168ef3d9
FB		 530
531 __raw_writel(val, reg);
532}
533
140455fa 534#ifdef CONFIG_ARCH_OMAP2PLUS
5eb3bb9c
KH		 535static inline void set_24xx_gpio_triggering(struct gpio_bank *bank, int gpio,
536 int trigger)
5e1c5ff4 537{
3ac4fa99 538 void __iomem *base = bank->base;
92105bb7 539 u32 gpio_bit = 1 << gpio;
78a1a6d3 540 u32 val;
92105bb7 541
78a1a6d3
SR		 542 if (cpu_is_omap44xx()) {
543 MOD_REG_BIT(OMAP4_GPIO_LEVELDETECT0, gpio_bit,
544 trigger & IRQ_TYPE_LEVEL_LOW);
545 MOD_REG_BIT(OMAP4_GPIO_LEVELDETECT1, gpio_bit,
546 trigger & IRQ_TYPE_LEVEL_HIGH);
547 MOD_REG_BIT(OMAP4_GPIO_RISINGDETECT, gpio_bit,
548 trigger & IRQ_TYPE_EDGE_RISING);
549 MOD_REG_BIT(OMAP4_GPIO_FALLINGDETECT, gpio_bit,
550 trigger & IRQ_TYPE_EDGE_FALLING);
551 } else {
552 MOD_REG_BIT(OMAP24XX_GPIO_LEVELDETECT0, gpio_bit,
553 trigger & IRQ_TYPE_LEVEL_LOW);
554 MOD_REG_BIT(OMAP24XX_GPIO_LEVELDETECT1, gpio_bit,
555 trigger & IRQ_TYPE_LEVEL_HIGH);
556 MOD_REG_BIT(OMAP24XX_GPIO_RISINGDETECT, gpio_bit,
557 trigger & IRQ_TYPE_EDGE_RISING);
558 MOD_REG_BIT(OMAP24XX_GPIO_FALLINGDETECT, gpio_bit,
559 trigger & IRQ_TYPE_EDGE_FALLING);
560 }
3ac4fa99 561 if (likely(!(bank->non_wakeup_gpios & gpio_bit))) {
78a1a6d3
SR		 562 if (cpu_is_omap44xx()) {
563 if (trigger != 0)
564 __raw_writel(1 << gpio, bank->base+
565 OMAP4_GPIO_IRQWAKEN0);
566 else {
567 val = __raw_readl(bank->base +
568 OMAP4_GPIO_IRQWAKEN0);
569 __raw_writel(val & (~(1 << gpio)), bank->base +
570 OMAP4_GPIO_IRQWAKEN0);
571 }
572 } else {
699117a6
CW		 573 /*
574 * GPIO wakeup request can only be generated on edge
575 * transitions
576 */
577 if (trigger & IRQ_TYPE_EDGE_BOTH)
78a1a6d3 578 __raw_writel(1 << gpio, bank->base
5eb3bb9c 579 + OMAP24XX_GPIO_SETWKUENA);
78a1a6d3
SR		 580 else
581 __raw_writel(1 << gpio, bank->base
5eb3bb9c 582 + OMAP24XX_GPIO_CLEARWKUENA);
78a1a6d3 583 }
a118b5f3
TK		 584 }
585 /* This part needs to be executed always for OMAP34xx */
586 if (cpu_is_omap34xx() || (bank->non_wakeup_gpios & gpio_bit)) {
699117a6
CW		 587 /*
588 * Log the edge gpio and manually trigger the IRQ
589 * after resume if the input level changes
590 * to avoid irq lost during PER RET/OFF mode
591 * Applies for omap2 non-wakeup gpio and all omap3 gpios
592 */
593 if (trigger & IRQ_TYPE_EDGE_BOTH)
3ac4fa99
JY		 594 bank->enabled_non_wakeup_gpios |= gpio_bit;
595 else
596 bank->enabled_non_wakeup_gpios &= ~gpio_bit;
597 }
5eb3bb9c 598
78a1a6d3
SR		 599 if (cpu_is_omap44xx()) {
600 bank->level_mask =
601 __raw_readl(bank->base + OMAP4_GPIO_LEVELDETECT0) |
602 __raw_readl(bank->base + OMAP4_GPIO_LEVELDETECT1);
603 } else {
604 bank->level_mask =
605 __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT0) |
606 __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT1);
607 }
92105bb7 608}
3ac4fa99 609#endif
92105bb7 610
9198bcd3 611#ifdef CONFIG_ARCH_OMAP1
4318f36b
CM		 612/*
613 * This only applies to chips that can't do both rising and falling edge
614 * detection at once. For all other chips, this function is a noop.
615 */
616static void _toggle_gpio_edge_triggering(struct gpio_bank *bank, int gpio)
617{
618 void __iomem *reg = bank->base;
619 u32 l = 0;
620
621 switch (bank->method) {
4318f36b
CM		 622 case METHOD_MPUIO:
623 reg += OMAP_MPUIO_GPIO_INT_EDGE;
624 break;
4318f36b
CM		 625#ifdef CONFIG_ARCH_OMAP15XX
626 case METHOD_GPIO_1510:
627 reg += OMAP1510_GPIO_INT_CONTROL;
628 break;
629#endif
630#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
631 case METHOD_GPIO_7XX:
632 reg += OMAP7XX_GPIO_INT_CONTROL;
633 break;
634#endif
635 default:
636 return;
637 }
638
639 l = __raw_readl(reg);
640 if ((l >> gpio) & 1)
641 l &= ~(1 << gpio);
642 else
643 l |= 1 << gpio;
644
645 __raw_writel(l, reg);
646}
9198bcd3 647#endif
4318f36b 648
92105bb7
TL		 649static int _set_gpio_triggering(struct gpio_bank *bank, int gpio, int trigger)
650{
651 void __iomem *reg = bank->base;
652 u32 l = 0;
5e1c5ff4
TL		 653
654 switch (bank->method) {
e5c56ed3 655#ifdef CONFIG_ARCH_OMAP1
5e1c5ff4
TL		 656 case METHOD_MPUIO:
657 reg += OMAP_MPUIO_GPIO_INT_EDGE;
658 l = __raw_readl(reg);
29501577 659 if ((trigger & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH)
4318f36b 660 bank->toggle_mask |= 1 << gpio;
6cab4860 661 if (trigger & IRQ_TYPE_EDGE_RISING)
5e1c5ff4 662 l |= 1 << gpio;
6cab4860 663 else if (trigger & IRQ_TYPE_EDGE_FALLING)
5e1c5ff4 664 l &= ~(1 << gpio);
92105bb7
TL		 665 else
666 goto bad;
5e1c5ff4 667 break;
e5c56ed3
DB		 668#endif
669#ifdef CONFIG_ARCH_OMAP15XX
5e1c5ff4
TL		 670 case METHOD_GPIO_1510:
671 reg += OMAP1510_GPIO_INT_CONTROL;
672 l = __raw_readl(reg);
29501577 673 if ((trigger & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH)
4318f36b 674 bank->toggle_mask |= 1 << gpio;
6cab4860 675 if (trigger & IRQ_TYPE_EDGE_RISING)
5e1c5ff4 676 l |= 1 << gpio;
6cab4860 677 else if (trigger & IRQ_TYPE_EDGE_FALLING)
5e1c5ff4 678 l &= ~(1 << gpio);
92105bb7
TL		 679 else
680 goto bad;
5e1c5ff4 681 break;
e5c56ed3 682#endif
3ac4fa99 683#ifdef CONFIG_ARCH_OMAP16XX
5e1c5ff4 684 case METHOD_GPIO_1610:
5e1c5ff4
TL		 685 if (gpio & 0x08)
686 reg += OMAP1610_GPIO_EDGE_CTRL2;
687 else
688 reg += OMAP1610_GPIO_EDGE_CTRL1;
689 gpio &= 0x07;
690 l = __raw_readl(reg);
691 l &= ~(3 << (gpio << 1));
6cab4860 692 if (trigger & IRQ_TYPE_EDGE_RISING)
6e60e79a 693 l |= 2 << (gpio << 1);
6cab4860 694 if (trigger & IRQ_TYPE_EDGE_FALLING)
6e60e79a 695 l |= 1 << (gpio << 1);
3ac4fa99
JY		 696 if (trigger)
697 /* Enable wake-up during idle for dynamic tick */
698 __raw_writel(1 << gpio, bank->base + OMAP1610_GPIO_SET_WAKEUPENA);
699 else
700 __raw_writel(1 << gpio, bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA);
5e1c5ff4 701 break;
3ac4fa99 702#endif
b718aa81 703#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
7c006926
AB		 704 case METHOD_GPIO_7XX:
705 reg += OMAP7XX_GPIO_INT_CONTROL;
56739a69 706 l = __raw_readl(reg);
29501577 707 if ((trigger & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH)
4318f36b 708 bank->toggle_mask |= 1 << gpio;
56739a69
ZM		 709 if (trigger & IRQ_TYPE_EDGE_RISING)
710 l |= 1 << gpio;
711 else if (trigger & IRQ_TYPE_EDGE_FALLING)
712 l &= ~(1 << gpio);
713 else
714 goto bad;
715 break;
716#endif
140455fa 717#ifdef CONFIG_ARCH_OMAP2PLUS
92105bb7 718 case METHOD_GPIO_24XX:
3f1686a9 719 case METHOD_GPIO_44XX:
3ac4fa99 720 set_24xx_gpio_triggering(bank, gpio, trigger);
5e1c5ff4 721 break;
3ac4fa99 722#endif
5e1c5ff4 723 default:
92105bb7 724 goto bad;
5e1c5ff4 725 }
92105bb7
TL		 726 __raw_writel(l, reg);
727 return 0;
728bad:
729 return -EINVAL;
5e1c5ff4
TL		 730}
731
92105bb7 732static int gpio_irq_type(unsigned irq, unsigned type)
5e1c5ff4
TL		 733{
734 struct gpio_bank *bank;
92105bb7
TL		 735 unsigned gpio;
736 int retval;
a6472533 737 unsigned long flags;
92105bb7 738
5492fb1a 739 if (!cpu_class_is_omap2() && irq > IH_MPUIO_BASE)
92105bb7
TL		 740 gpio = OMAP_MPUIO(irq - IH_MPUIO_BASE);
741 else
742 gpio = irq - IH_GPIO_BASE;
5e1c5ff4
TL		 743
744 if (check_gpio(gpio) < 0)
92105bb7
TL		 745 return -EINVAL;
746
e5c56ed3 747 if (type & ~IRQ_TYPE_SENSE_MASK)
6e60e79a 748 return -EINVAL;
e5c56ed3
DB		 749
750 /* OMAP1 allows only only edge triggering */
5492fb1a 751 if (!cpu_class_is_omap2()
e5c56ed3 752 && (type & (IRQ_TYPE_LEVEL_LOW|IRQ_TYPE_LEVEL_HIGH)))
92105bb7
TL		 753 return -EINVAL;
754
58781016 755 bank = get_irq_chip_data(irq);
a6472533 756 spin_lock_irqsave(&bank->lock, flags);
92105bb7 757 retval = _set_gpio_triggering(bank, get_gpio_index(gpio), type);
b9772a22
DB		 758 if (retval == 0) {
759 irq_desc[irq].status &= ~IRQ_TYPE_SENSE_MASK;
760 irq_desc[irq].status |= type;
761 }
a6472533 762 spin_unlock_irqrestore(&bank->lock, flags);
672e302e
KH		 763
764 if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
765 __set_irq_handler_unlocked(irq, handle_level_irq);
766 else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
767 __set_irq_handler_unlocked(irq, handle_edge_irq);
768
92105bb7 769 return retval;
5e1c5ff4
TL		 770}
771
772static void _clear_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
773{
92105bb7 774 void __iomem *reg = bank->base;
5e1c5ff4
TL		 775
776 switch (bank->method) {
e5c56ed3 777#ifdef CONFIG_ARCH_OMAP1
5e1c5ff4
TL		 778 case METHOD_MPUIO:
779 /* MPUIO irqstatus is reset by reading the status register,
780 * so do nothing here */
781 return;
e5c56ed3
DB		 782#endif
783#ifdef CONFIG_ARCH_OMAP15XX
5e1c5ff4
TL		 784 case METHOD_GPIO_1510:
785 reg += OMAP1510_GPIO_INT_STATUS;
786 break;
e5c56ed3
DB		 787#endif
788#ifdef CONFIG_ARCH_OMAP16XX
5e1c5ff4
TL		 789 case METHOD_GPIO_1610:
790 reg += OMAP1610_GPIO_IRQSTATUS1;
791 break;
e5c56ed3 792#endif
b718aa81 793#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
7c006926
AB		 794 case METHOD_GPIO_7XX:
795 reg += OMAP7XX_GPIO_INT_STATUS;
56739a69
ZM		 796 break;
797#endif
a8eb7ca0 798#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
92105bb7
TL		 799 case METHOD_GPIO_24XX:
800 reg += OMAP24XX_GPIO_IRQSTATUS1;
801 break;
78a1a6d3
SR		 802#endif
803#if defined(CONFIG_ARCH_OMAP4)
3f1686a9 804 case METHOD_GPIO_44XX:
78a1a6d3
SR		 805 reg += OMAP4_GPIO_IRQSTATUS0;
806 break;
e5c56ed3 807#endif
5e1c5ff4 808 default:
e5c56ed3 809 WARN_ON(1);
5e1c5ff4
TL		 810 return;
811 }
812 __raw_writel(gpio_mask, reg);
bee7930f
HD		 813
814 /* Workaround for clearing DSP GPIO interrupts to allow retention */
3f1686a9
TL		 815 if (cpu_is_omap24xx() || cpu_is_omap34xx())
816 reg = bank->base + OMAP24XX_GPIO_IRQSTATUS2;
817 else if (cpu_is_omap44xx())
818 reg = bank->base + OMAP4_GPIO_IRQSTATUS1;
819
78a1a6d3 820 if (cpu_is_omap24xx() || cpu_is_omap34xx() || cpu_is_omap44xx()) {
bedfd154
RQ		 821 __raw_writel(gpio_mask, reg);
822
823 /* Flush posted write for the irq status to avoid spurious interrupts */
824 __raw_readl(reg);
78a1a6d3 825 }
5e1c5ff4
TL		 826}
827
828static inline void _clear_gpio_irqstatus(struct gpio_bank *bank, int gpio)
829{
830 _clear_gpio_irqbank(bank, 1 << get_gpio_index(gpio));
831}
832
ea6dedd7
ID		 833static u32 _get_gpio_irqbank_mask(struct gpio_bank *bank)
834{
835 void __iomem *reg = bank->base;
99c47707
ID		 836 int inv = 0;
837 u32 l;
838 u32 mask;
ea6dedd7
ID		 839
840 switch (bank->method) {
e5c56ed3 841#ifdef CONFIG_ARCH_OMAP1
ea6dedd7
ID		 842 case METHOD_MPUIO:
843 reg += OMAP_MPUIO_GPIO_MASKIT;
99c47707
ID		 844 mask = 0xffff;
845 inv = 1;
ea6dedd7 846 break;
e5c56ed3
DB		 847#endif
848#ifdef CONFIG_ARCH_OMAP15XX
ea6dedd7
ID		 849 case METHOD_GPIO_1510:
850 reg += OMAP1510_GPIO_INT_MASK;
99c47707
ID		 851 mask = 0xffff;
852 inv = 1;
ea6dedd7 853 break;
e5c56ed3
DB		 854#endif
855#ifdef CONFIG_ARCH_OMAP16XX
ea6dedd7
ID		 856 case METHOD_GPIO_1610:
857 reg += OMAP1610_GPIO_IRQENABLE1;
99c47707 858 mask = 0xffff;
ea6dedd7 859 break;
e5c56ed3 860#endif
b718aa81 861#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
7c006926
AB		 862 case METHOD_GPIO_7XX:
863 reg += OMAP7XX_GPIO_INT_MASK;
56739a69
ZM		 864 mask = 0xffffffff;
865 inv = 1;
866 break;
867#endif
a8eb7ca0 868#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
ea6dedd7
ID		 869 case METHOD_GPIO_24XX:
870 reg += OMAP24XX_GPIO_IRQENABLE1;
99c47707 871 mask = 0xffffffff;
ea6dedd7 872 break;
78a1a6d3
SR		 873#endif
874#if defined(CONFIG_ARCH_OMAP4)
3f1686a9 875 case METHOD_GPIO_44XX:
78a1a6d3
SR		 876 reg += OMAP4_GPIO_IRQSTATUSSET0;
877 mask = 0xffffffff;
878 break;
e5c56ed3 879#endif
ea6dedd7 880 default:
e5c56ed3 881 WARN_ON(1);
ea6dedd7
ID		 882 return 0;
883 }
884
99c47707
ID		 885 l = __raw_readl(reg);
886 if (inv)
887 l = ~l;
888 l &= mask;
889 return l;
ea6dedd7
ID		 890}
891
5e1c5ff4
TL		 892static void _enable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask, int enable)
893{
92105bb7 894 void __iomem *reg = bank->base;
5e1c5ff4
TL		 895 u32 l;
896
897 switch (bank->method) {
e5c56ed3 898#ifdef CONFIG_ARCH_OMAP1
5e1c5ff4
TL		 899 case METHOD_MPUIO:
900 reg += OMAP_MPUIO_GPIO_MASKIT;
901 l = __raw_readl(reg);
902 if (enable)
903 l &= ~(gpio_mask);
904 else
905 l |= gpio_mask;
906 break;
e5c56ed3
DB		 907#endif
908#ifdef CONFIG_ARCH_OMAP15XX
5e1c5ff4
TL		 909 case METHOD_GPIO_1510:
910 reg += OMAP1510_GPIO_INT_MASK;
911 l = __raw_readl(reg);
912 if (enable)
913 l &= ~(gpio_mask);
914 else
915 l |= gpio_mask;
916 break;
e5c56ed3
DB		 917#endif
918#ifdef CONFIG_ARCH_OMAP16XX
5e1c5ff4
TL		 919 case METHOD_GPIO_1610:
920 if (enable)
921 reg += OMAP1610_GPIO_SET_IRQENABLE1;
922 else
923 reg += OMAP1610_GPIO_CLEAR_IRQENABLE1;
924 l = gpio_mask;
925 break;
e5c56ed3 926#endif
b718aa81 927#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
7c006926
AB		 928 case METHOD_GPIO_7XX:
929 reg += OMAP7XX_GPIO_INT_MASK;
56739a69
ZM		 930 l = __raw_readl(reg);
931 if (enable)
932 l &= ~(gpio_mask);
933 else
934 l |= gpio_mask;
935 break;
936#endif
a8eb7ca0 937#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
92105bb7
TL		 938 case METHOD_GPIO_24XX:
939 if (enable)
940 reg += OMAP24XX_GPIO_SETIRQENABLE1;
941 else
942 reg += OMAP24XX_GPIO_CLEARIRQENABLE1;
943 l = gpio_mask;
944 break;
78a1a6d3
SR		 945#endif
946#ifdef CONFIG_ARCH_OMAP4
3f1686a9 947 case METHOD_GPIO_44XX:
78a1a6d3
SR		 948 if (enable)
949 reg += OMAP4_GPIO_IRQSTATUSSET0;
950 else
951 reg += OMAP4_GPIO_IRQSTATUSCLR0;
952 l = gpio_mask;
953 break;
e5c56ed3 954#endif
5e1c5ff4 955 default:
e5c56ed3 956 WARN_ON(1);
5e1c5ff4
TL		 957 return;
958 }
959 __raw_writel(l, reg);
960}
961
962static inline void _set_gpio_irqenable(struct gpio_bank *bank, int gpio, int enable)
963{
964 _enable_gpio_irqbank(bank, 1 << get_gpio_index(gpio), enable);
965}
966
92105bb7
TL		 967/*
968 * Note that ENAWAKEUP needs to be enabled in GPIO_SYSCONFIG register.
969 * 1510 does not seem to have a wake-up register. If JTAG is connected
970 * to the target, system will wake up always on GPIO events. While
971 * system is running all registered GPIO interrupts need to have wake-up
972 * enabled. When system is suspended, only selected GPIO interrupts need
973 * to have wake-up enabled.
974 */
975static int _set_gpio_wakeup(struct gpio_bank *bank, int gpio, int enable)
976{
4cc6420c 977 unsigned long uninitialized_var(flags);
a6472533 978
92105bb7 979 switch (bank->method) {
3ac4fa99 980#ifdef CONFIG_ARCH_OMAP16XX
11a78b79 981 case METHOD_MPUIO:
92105bb7 982 case METHOD_GPIO_1610:
a6472533 983 spin_lock_irqsave(&bank->lock, flags);
b3bb4f68 984 if (enable)
92105bb7 985 bank->suspend_wakeup |= (1 << gpio);
b3bb4f68 986 else
92105bb7 987 bank->suspend_wakeup &= ~(1 << gpio);
a6472533 988 spin_unlock_irqrestore(&bank->lock, flags);
92105bb7 989 return 0;
3ac4fa99 990#endif
140455fa 991#ifdef CONFIG_ARCH_OMAP2PLUS
3ac4fa99 992 case METHOD_GPIO_24XX:
3f1686a9 993 case METHOD_GPIO_44XX:
11a78b79
DB		 994 if (bank->non_wakeup_gpios & (1 << gpio)) {
995 printk(KERN_ERR "Unable to modify wakeup on "
996 "non-wakeup GPIO%d\n",
997 (bank - gpio_bank) * 32 + gpio);
998 return -EINVAL;
999 }
a6472533 1000 spin_lock_irqsave(&bank->lock, flags);
b3bb4f68 1001 if (enable)
3ac4fa99 1002 bank->suspend_wakeup |= (1 << gpio);
b3bb4f68 1003 else
3ac4fa99 1004 bank->suspend_wakeup &= ~(1 << gpio);
a6472533 1005 spin_unlock_irqrestore(&bank->lock, flags);
3ac4fa99
JY		 1006 return 0;
1007#endif
92105bb7
TL		 1008 default:
1009 printk(KERN_ERR "Can't enable GPIO wakeup for method %i\n",
1010 bank->method);
1011 return -EINVAL;
1012 }
1013}
1014
4196dd6b
TL		 1015static void _reset_gpio(struct gpio_bank *bank, int gpio)
1016{
1017 _set_gpio_direction(bank, get_gpio_index(gpio), 1);
1018 _set_gpio_irqenable(bank, gpio, 0);
1019 _clear_gpio_irqstatus(bank, gpio);
6cab4860 1020 _set_gpio_triggering(bank, get_gpio_index(gpio), IRQ_TYPE_NONE);
4196dd6b
TL		 1021}
1022
92105bb7
TL		 1023/* Use disable_irq_wake() and enable_irq_wake() functions from drivers */
1024static int gpio_wake_enable(unsigned int irq, unsigned int enable)
1025{
1026 unsigned int gpio = irq - IH_GPIO_BASE;
1027 struct gpio_bank *bank;
1028 int retval;
1029
1030 if (check_gpio(gpio) < 0)
1031 return -ENODEV;
58781016 1032 bank = get_irq_chip_data(irq);
92105bb7 1033 retval = _set_gpio_wakeup(bank, get_gpio_index(gpio), enable);
92105bb7
TL		 1034
1035 return retval;
1036}
1037
3ff164e1 1038static int omap_gpio_request(struct gpio_chip *chip, unsigned offset)
5e1c5ff4 1039{
3ff164e1 1040 struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip);
a6472533 1041 unsigned long flags;
52e31344 1042
a6472533 1043 spin_lock_irqsave(&bank->lock, flags);
92105bb7 1044
4196dd6b
TL		 1045 /* Set trigger to none. You need to enable the desired trigger with
1046 * request_irq() or set_irq_type().
1047 */
3ff164e1 1048 _set_gpio_triggering(bank, offset, IRQ_TYPE_NONE);
92105bb7 1049
1a8bfa1e 1050#ifdef CONFIG_ARCH_OMAP15XX
5e1c5ff4 1051 if (bank->method == METHOD_GPIO_1510) {
92105bb7 1052 void __iomem *reg;
5e1c5ff4 1053
92105bb7 1054 /* Claim the pin for MPU */
5e1c5ff4 1055 reg = bank->base + OMAP1510_GPIO_PIN_CONTROL;
3ff164e1 1056 __raw_writel(__raw_readl(reg) | (1 << offset), reg);
5e1c5ff4
TL		 1057 }
1058#endif
058af1ea
C		 1059 if (!cpu_class_is_omap1()) {
1060 if (!bank->mod_usage) {
9f096868 1061 void __iomem *reg = bank->base;
058af1ea 1062 u32 ctrl;
9f096868
C		 1063
1064 if (cpu_is_omap24xx() || cpu_is_omap34xx())
1065 reg += OMAP24XX_GPIO_CTRL;
1066 else if (cpu_is_omap44xx())
1067 reg += OMAP4_GPIO_CTRL;
1068 ctrl = __raw_readl(reg);
058af1ea 1069 /* Module is enabled, clocks are not gated */
9f096868
C		 1070 ctrl &= 0xFFFFFFFE;
1071 __raw_writel(ctrl, reg);
058af1ea
C		 1072 }
1073 bank->mod_usage |= 1 << offset;
1074 }
a6472533 1075 spin_unlock_irqrestore(&bank->lock, flags);
5e1c5ff4
TL		 1076
1077 return 0;
1078}
1079
3ff164e1 1080static void omap_gpio_free(struct gpio_chip *chip, unsigned offset)
5e1c5ff4 1081{
3ff164e1 1082 struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip);
a6472533 1083 unsigned long flags;
5e1c5ff4 1084
a6472533 1085 spin_lock_irqsave(&bank->lock, flags);
92105bb7
TL		 1086#ifdef CONFIG_ARCH_OMAP16XX
1087 if (bank->method == METHOD_GPIO_1610) {
1088 /* Disable wake-up during idle for dynamic tick */
1089 void __iomem *reg = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
3ff164e1 1090 __raw_writel(1 << offset, reg);
92105bb7
TL		 1091 }
1092#endif
9f096868
C		 1093#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
1094 if (bank->method == METHOD_GPIO_24XX) {
92105bb7
TL		 1095 /* Disable wake-up during idle for dynamic tick */
1096 void __iomem *reg = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
3ff164e1 1097 __raw_writel(1 << offset, reg);
92105bb7 1098 }
9f096868
C		 1099#endif
1100#ifdef CONFIG_ARCH_OMAP4
1101 if (bank->method == METHOD_GPIO_44XX) {
1102 /* Disable wake-up during idle for dynamic tick */
1103 void __iomem *reg = bank->base + OMAP4_GPIO_IRQWAKEN0;
1104 __raw_writel(1 << offset, reg);
1105 }
92105bb7 1106#endif
058af1ea
C		 1107 if (!cpu_class_is_omap1()) {
1108 bank->mod_usage &= ~(1 << offset);
1109 if (!bank->mod_usage) {
9f096868 1110 void __iomem *reg = bank->base;
058af1ea 1111 u32 ctrl;
9f096868
C		 1112
1113 if (cpu_is_omap24xx() || cpu_is_omap34xx())
1114 reg += OMAP24XX_GPIO_CTRL;
1115 else if (cpu_is_omap44xx())
1116 reg += OMAP4_GPIO_CTRL;
1117 ctrl = __raw_readl(reg);
058af1ea
C		 1118 /* Module is disabled, clocks are gated */
1119 ctrl |= 1;
9f096868 1120 __raw_writel(ctrl, reg);
058af1ea
C		 1121 }
1122 }
3ff164e1 1123 _reset_gpio(bank, bank->chip.base + offset);
a6472533 1124 spin_unlock_irqrestore(&bank->lock, flags);
5e1c5ff4
TL		 1125}
1126
1127/*
1128 * We need to unmask the GPIO bank interrupt as soon as possible to
1129 * avoid missing GPIO interrupts for other lines in the bank.
1130 * Then we need to mask-read-clear-unmask the triggered GPIO lines
1131 * in the bank to avoid missing nested interrupts for a GPIO line.
1132 * If we wait to unmask individual GPIO lines in the bank after the
1133 * line's interrupt handler has been run, we may miss some nested
1134 * interrupts.
1135 */
10dd5ce2 1136static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
5e1c5ff4 1137{
92105bb7 1138 void __iomem *isr_reg = NULL;
5e1c5ff4 1139 u32 isr;
4318f36b 1140 unsigned int gpio_irq, gpio_index;
5e1c5ff4 1141 struct gpio_bank *bank;
ea6dedd7
ID		 1142 u32 retrigger = 0;
1143 int unmasked = 0;
5e1c5ff4
TL		 1144
1145 desc->chip->ack(irq);
1146
418ca1f0 1147 bank = get_irq_data(irq);
e5c56ed3 1148#ifdef CONFIG_ARCH_OMAP1
5e1c5ff4
TL		 1149 if (bank->method == METHOD_MPUIO)
1150 isr_reg = bank->base + OMAP_MPUIO_GPIO_INT;
e5c56ed3 1151#endif
1a8bfa1e 1152#ifdef CONFIG_ARCH_OMAP15XX
5e1c5ff4
TL		 1153 if (bank->method == METHOD_GPIO_1510)
1154 isr_reg = bank->base + OMAP1510_GPIO_INT_STATUS;
1155#endif
1156#if defined(CONFIG_ARCH_OMAP16XX)
1157 if (bank->method == METHOD_GPIO_1610)
1158 isr_reg = bank->base + OMAP1610_GPIO_IRQSTATUS1;
1159#endif
b718aa81 1160#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
7c006926
AB		 1161 if (bank->method == METHOD_GPIO_7XX)
1162 isr_reg = bank->base + OMAP7XX_GPIO_INT_STATUS;
56739a69 1163#endif
a8eb7ca0 1164#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
92105bb7
TL		 1165 if (bank->method == METHOD_GPIO_24XX)
1166 isr_reg = bank->base + OMAP24XX_GPIO_IRQSTATUS1;
78a1a6d3
SR		 1167#endif
1168#if defined(CONFIG_ARCH_OMAP4)
3f1686a9 1169 if (bank->method == METHOD_GPIO_44XX)
78a1a6d3 1170 isr_reg = bank->base + OMAP4_GPIO_IRQSTATUS0;
92105bb7 1171#endif
b1cc4c55
EK		 1172
1173 if (WARN_ON(!isr_reg))
1174 goto exit;
1175
92105bb7 1176 while(1) {
6e60e79a 1177 u32 isr_saved, level_mask = 0;
ea6dedd7 1178 u32 enabled;
6e60e79a 1179
ea6dedd7
ID		 1180 enabled = _get_gpio_irqbank_mask(bank);
1181 isr_saved = isr = __raw_readl(isr_reg) & enabled;
6e60e79a
TL		 1182
1183 if (cpu_is_omap15xx() && (bank->method == METHOD_MPUIO))
1184 isr &= 0x0000ffff;
1185
5492fb1a 1186 if (cpu_class_is_omap2()) {
b144ff6f 1187 level_mask = bank->level_mask & enabled;
ea6dedd7 1188 }
6e60e79a
TL		 1189
1190 /* clear edge sensitive interrupts before handler(s) are
1191 called so that we don't miss any interrupt occurred while
1192 executing them */
1193 _enable_gpio_irqbank(bank, isr_saved & ~level_mask, 0);
1194 _clear_gpio_irqbank(bank, isr_saved & ~level_mask);
1195 _enable_gpio_irqbank(bank, isr_saved & ~level_mask, 1);
1196
1197 /* if there is only edge sensitive GPIO pin interrupts
1198 configured, we could unmask GPIO bank interrupt immediately */
ea6dedd7
ID		 1199 if (!level_mask && !unmasked) {
1200 unmasked = 1;
6e60e79a 1201 desc->chip->unmask(irq);
ea6dedd7 1202 }
92105bb7 1203
ea6dedd7
ID		 1204 isr |= retrigger;
1205 retrigger = 0;
92105bb7
TL		 1206 if (!isr)
1207 break;
1208
1209 gpio_irq = bank->virtual_irq_start;
1210 for (; isr != 0; isr >>= 1, gpio_irq++) {
4318f36b
CM		 1211 gpio_index = get_gpio_index(irq_to_gpio(gpio_irq));
1212
92105bb7
TL		 1213 if (!(isr & 1))
1214 continue;
29454dde 1215
4318f36b
CM		 1216#ifdef CONFIG_ARCH_OMAP1
1217 /*
1218 * Some chips can't respond to both rising and falling
1219 * at the same time. If this irq was requested with
1220 * both flags, we need to flip the ICR data for the IRQ
1221 * to respond to the IRQ for the opposite direction.
1222 * This will be indicated in the bank toggle_mask.
1223 */
1224 if (bank->toggle_mask & (1 << gpio_index))
1225 _toggle_gpio_edge_triggering(bank, gpio_index);
1226#endif
1227
d8aa0251 1228 generic_handle_irq(gpio_irq);
92105bb7 1229 }
1a8bfa1e 1230 }
ea6dedd7
ID		 1231 /* if bank has any level sensitive GPIO pin interrupt
1232 configured, we must unmask the bank interrupt only after
1233 handler(s) are executed in order to avoid spurious bank
1234 interrupt */
b1cc4c55 1235exit:
ea6dedd7
ID		 1236 if (!unmasked)
1237 desc->chip->unmask(irq);
1238
5e1c5ff4
TL		 1239}
1240
4196dd6b
TL		 1241static void gpio_irq_shutdown(unsigned int irq)
1242{
1243 unsigned int gpio = irq - IH_GPIO_BASE;
58781016 1244 struct gpio_bank *bank = get_irq_chip_data(irq);
4196dd6b
TL		 1245
1246 _reset_gpio(bank, gpio);
1247}
1248
5e1c5ff4
TL		 1249static void gpio_ack_irq(unsigned int irq)
1250{
1251 unsigned int gpio = irq - IH_GPIO_BASE;
58781016 1252 struct gpio_bank *bank = get_irq_chip_data(irq);
5e1c5ff4
TL		 1253
1254 _clear_gpio_irqstatus(bank, gpio);
1255}
1256
1257static void gpio_mask_irq(unsigned int irq)
1258{
1259 unsigned int gpio = irq - IH_GPIO_BASE;
58781016 1260 struct gpio_bank *bank = get_irq_chip_data(irq);
5e1c5ff4
TL		 1261
1262 _set_gpio_irqenable(bank, gpio, 0);
55b6019a 1263 _set_gpio_triggering(bank, get_gpio_index(gpio), IRQ_TYPE_NONE);
5e1c5ff4
TL		 1264}
1265
1266static void gpio_unmask_irq(unsigned int irq)
1267{
1268 unsigned int gpio = irq - IH_GPIO_BASE;
58781016 1269 struct gpio_bank *bank = get_irq_chip_data(irq);
b144ff6f 1270 unsigned int irq_mask = 1 << get_gpio_index(gpio);
55b6019a
KH		 1271 struct irq_desc *desc = irq_to_desc(irq);
1272 u32 trigger = desc->status & IRQ_TYPE_SENSE_MASK;
1273
1274 if (trigger)
1275 _set_gpio_triggering(bank, get_gpio_index(gpio), trigger);
b144ff6f
KH		 1276
1277 /* For level-triggered GPIOs, the clearing must be done after
1278 * the HW source is cleared, thus after the handler has run */
1279 if (bank->level_mask & irq_mask) {
1280 _set_gpio_irqenable(bank, gpio, 0);
1281 _clear_gpio_irqstatus(bank, gpio);
1282 }
5e1c5ff4 1283
4de8c75b 1284 _set_gpio_irqenable(bank, gpio, 1);
5e1c5ff4
TL		 1285}
1286
e5c56ed3
DB		 1287static struct irq_chip gpio_irq_chip = {
1288 .name = "GPIO",
1289 .shutdown = gpio_irq_shutdown,
1290 .ack = gpio_ack_irq,
1291 .mask = gpio_mask_irq,
1292 .unmask = gpio_unmask_irq,
1293 .set_type = gpio_irq_type,
1294 .set_wake = gpio_wake_enable,
1295};
1296
1297/*---------------------------------------------------------------------*/
1298
1299#ifdef CONFIG_ARCH_OMAP1
1300
1301/* MPUIO uses the always-on 32k clock */
1302
5e1c5ff4
TL		 1303static void mpuio_ack_irq(unsigned int irq)
1304{
1305 /* The ISR is reset automatically, so do nothing here. */
1306}
1307
1308static void mpuio_mask_irq(unsigned int irq)
1309{
1310 unsigned int gpio = OMAP_MPUIO(irq - IH_MPUIO_BASE);
58781016 1311 struct gpio_bank *bank = get_irq_chip_data(irq);
5e1c5ff4
TL		 1312
1313 _set_gpio_irqenable(bank, gpio, 0);
1314}
1315
1316static void mpuio_unmask_irq(unsigned int irq)
1317{
1318 unsigned int gpio = OMAP_MPUIO(irq - IH_MPUIO_BASE);
58781016 1319 struct gpio_bank *bank = get_irq_chip_data(irq);
5e1c5ff4
TL		 1320
1321 _set_gpio_irqenable(bank, gpio, 1);
1322}
1323
e5c56ed3
DB		 1324static struct irq_chip mpuio_irq_chip = {
1325 .name = "MPUIO",
1326 .ack = mpuio_ack_irq,
1327 .mask = mpuio_mask_irq,
1328 .unmask = mpuio_unmask_irq,
92105bb7 1329 .set_type = gpio_irq_type,
11a78b79
DB		 1330#ifdef CONFIG_ARCH_OMAP16XX
1331 /* REVISIT: assuming only 16xx supports MPUIO wake events */
1332 .set_wake = gpio_wake_enable,
1333#endif
5e1c5ff4
TL		 1334};
1335
e5c56ed3
DB		 1336
1337#define bank_is_mpuio(bank) ((bank)->method == METHOD_MPUIO)
1338
11a78b79
DB		 1339
1340#ifdef CONFIG_ARCH_OMAP16XX
1341
1342#include <linux/platform_device.h>
1343
79ee031f 1344static int omap_mpuio_suspend_noirq(struct device *dev)
11a78b79 1345{
79ee031f 1346 struct platform_device *pdev = to_platform_device(dev);
11a78b79
DB		 1347 struct gpio_bank *bank = platform_get_drvdata(pdev);
1348 void __iomem *mask_reg = bank->base + OMAP_MPUIO_GPIO_MASKIT;
a6472533 1349 unsigned long flags;
11a78b79 1350
a6472533 1351 spin_lock_irqsave(&bank->lock, flags);
11a78b79
DB		 1352 bank->saved_wakeup = __raw_readl(mask_reg);
1353 __raw_writel(0xffff & ~bank->suspend_wakeup, mask_reg);
a6472533 1354 spin_unlock_irqrestore(&bank->lock, flags);
11a78b79
DB		 1355
1356 return 0;
1357}
1358
79ee031f 1359static int omap_mpuio_resume_noirq(struct device *dev)
11a78b79 1360{
79ee031f 1361 struct platform_device *pdev = to_platform_device(dev);
11a78b79
DB		 1362 struct gpio_bank *bank = platform_get_drvdata(pdev);
1363 void __iomem *mask_reg = bank->base + OMAP_MPUIO_GPIO_MASKIT;
a6472533 1364 unsigned long flags;
11a78b79 1365
a6472533 1366 spin_lock_irqsave(&bank->lock, flags);
11a78b79 1367 __raw_writel(bank->saved_wakeup, mask_reg);
a6472533 1368 spin_unlock_irqrestore(&bank->lock, flags);
11a78b79
DB		 1369
1370 return 0;
1371}
1372
47145210 1373static const struct dev_pm_ops omap_mpuio_dev_pm_ops = {
79ee031f
MD		 1374 .suspend_noirq = omap_mpuio_suspend_noirq,
1375 .resume_noirq = omap_mpuio_resume_noirq,
1376};
1377
11a78b79
DB		 1378/* use platform_driver for this, now that there's no longer any
1379 * point to sys_device (other than not disturbing old code).
1380 */
1381static struct platform_driver omap_mpuio_driver = {
11a78b79
DB		 1382 .driver = {
1383 .name = "mpuio",
79ee031f 1384 .pm = &omap_mpuio_dev_pm_ops,
11a78b79
DB		 1385 },
1386};
1387
1388static struct platform_device omap_mpuio_device = {
1389 .name = "mpuio",
1390 .id = -1,
1391 .dev = {
1392 .driver = &omap_mpuio_driver.driver,
1393 }
1394 /* could list the /proc/iomem resources */
1395};
1396
1397static inline void mpuio_init(void)
1398{
77640aab
VC		 1399 struct gpio_bank *bank = get_gpio_bank(OMAP_MPUIO(0));
1400 platform_set_drvdata(&omap_mpuio_device, bank);
fcf126d8 1401
11a78b79
DB		 1402 if (platform_driver_register(&omap_mpuio_driver) == 0)
1403 (void) platform_device_register(&omap_mpuio_device);
1404}
1405
1406#else
1407static inline void mpuio_init(void) {}
1408#endif /* 16xx */
1409
e5c56ed3
DB		 1410#else
1411
1412extern struct irq_chip mpuio_irq_chip;
1413
1414#define bank_is_mpuio(bank) 0
11a78b79 1415static inline void mpuio_init(void) {}
e5c56ed3
DB		 1416
1417#endif
1418
1419/*---------------------------------------------------------------------*/
5e1c5ff4 1420
52e31344
DB		 1421/* REVISIT these are stupid implementations! replace by ones that
1422 * don't switch on METHOD_* and which mostly avoid spinlocks
1423 */
1424
1425static int gpio_input(struct gpio_chip *chip, unsigned offset)
1426{
1427 struct gpio_bank *bank;
1428 unsigned long flags;
1429
1430 bank = container_of(chip, struct gpio_bank, chip);
1431 spin_lock_irqsave(&bank->lock, flags);
1432 _set_gpio_direction(bank, offset, 1);
1433 spin_unlock_irqrestore(&bank->lock, flags);
1434 return 0;
1435}
1436
b37c45b8
RQ		 1437static int gpio_is_input(struct gpio_bank *bank, int mask)
1438{
1439 void __iomem *reg = bank->base;
1440
1441 switch (bank->method) {
1442 case METHOD_MPUIO:
1443 reg += OMAP_MPUIO_IO_CNTL;
1444 break;
1445 case METHOD_GPIO_1510:
1446 reg += OMAP1510_GPIO_DIR_CONTROL;
1447 break;
1448 case METHOD_GPIO_1610:
1449 reg += OMAP1610_GPIO_DIRECTION;
1450 break;
7c006926
AB		 1451 case METHOD_GPIO_7XX:
1452 reg += OMAP7XX_GPIO_DIR_CONTROL;
b37c45b8
RQ		 1453 break;
1454 case METHOD_GPIO_24XX:
1455 reg += OMAP24XX_GPIO_OE;
1456 break;
9f096868
C		 1457 case METHOD_GPIO_44XX:
1458 reg += OMAP4_GPIO_OE;
1459 break;
1460 default:
1461 WARN_ONCE(1, "gpio_is_input: incorrect OMAP GPIO method");
1462 return -EINVAL;
b37c45b8
RQ		 1463 }
1464 return __raw_readl(reg) & mask;
1465}
1466
52e31344
DB		 1467static int gpio_get(struct gpio_chip *chip, unsigned offset)
1468{
b37c45b8
RQ		 1469 struct gpio_bank *bank;
1470 void __iomem *reg;
1471 int gpio;
1472 u32 mask;
1473
1474 gpio = chip->base + offset;
1475 bank = get_gpio_bank(gpio);
1476 reg = bank->base;
1477 mask = 1 << get_gpio_index(gpio);
1478
1479 if (gpio_is_input(bank, mask))
1480 return _get_gpio_datain(bank, gpio);
1481 else
1482 return _get_gpio_dataout(bank, gpio);
52e31344
DB		 1483}
1484
1485static int gpio_output(struct gpio_chip *chip, unsigned offset, int value)
1486{
1487 struct gpio_bank *bank;
1488 unsigned long flags;
1489
1490 bank = container_of(chip, struct gpio_bank, chip);
1491 spin_lock_irqsave(&bank->lock, flags);
1492 _set_gpio_dataout(bank, offset, value);
1493 _set_gpio_direction(bank, offset, 0);
1494 spin_unlock_irqrestore(&bank->lock, flags);
1495 return 0;
1496}
1497
168ef3d9
FB		 1498static int gpio_debounce(struct gpio_chip *chip, unsigned offset,
1499 unsigned debounce)
1500{
1501 struct gpio_bank *bank;
1502 unsigned long flags;
1503
1504 bank = container_of(chip, struct gpio_bank, chip);
77640aab
VC		 1505
1506 if (!bank->dbck) {
1507 bank->dbck = clk_get(bank->dev, "dbclk");
1508 if (IS_ERR(bank->dbck))
1509 dev_err(bank->dev, "Could not get gpio dbck\n");
1510 }
1511
168ef3d9
FB		 1512 spin_lock_irqsave(&bank->lock, flags);
1513 _set_gpio_debounce(bank, offset, debounce);
1514 spin_unlock_irqrestore(&bank->lock, flags);
1515
1516 return 0;
1517}
1518
52e31344
DB		 1519static void gpio_set(struct gpio_chip *chip, unsigned offset, int value)
1520{
1521 struct gpio_bank *bank;
1522 unsigned long flags;
1523
1524 bank = container_of(chip, struct gpio_bank, chip);
1525 spin_lock_irqsave(&bank->lock, flags);
1526 _set_gpio_dataout(bank, offset, value);
1527 spin_unlock_irqrestore(&bank->lock, flags);
1528}
1529
a007b709
DB		 1530static int gpio_2irq(struct gpio_chip *chip, unsigned offset)
1531{
1532 struct gpio_bank *bank;
1533
1534 bank = container_of(chip, struct gpio_bank, chip);
1535 return bank->virtual_irq_start + offset;
1536}
1537
52e31344
DB		 1538/*---------------------------------------------------------------------*/
1539
9a748053 1540static void __init omap_gpio_show_rev(struct gpio_bank *bank)
9f7065da
TL		 1541{
1542 u32 rev;
1543
9a748053
TL		 1544 if (cpu_is_omap16xx() && !(bank->method != METHOD_MPUIO))
1545 rev = __raw_readw(bank->base + OMAP1610_GPIO_REVISION);
9f7065da 1546 else if (cpu_is_omap24xx() || cpu_is_omap34xx())
9a748053 1547 rev = __raw_readl(bank->base + OMAP24XX_GPIO_REVISION);
9f7065da 1548 else if (cpu_is_omap44xx())
9a748053 1549 rev = __raw_readl(bank->base + OMAP4_GPIO_REVISION);
9f7065da
TL		 1550 else
1551 return;
1552
1553 printk(KERN_INFO "OMAP GPIO hardware version %d.%d\n",
1554 (rev >> 4) & 0x0f, rev & 0x0f);
1555}
1556
8ba55c5c
DB		 1557/* This lock class tells lockdep that GPIO irqs are in a different
1558 * category than their parents, so it won't report false recursion.
1559 */
1560static struct lock_class_key gpio_lock_class;
1561
77640aab
VC		 1562static inline int init_gpio_info(struct platform_device *pdev)
1563{
1564 /* TODO: Analyze removing gpio_bank_count usage from driver code */
1565 gpio_bank = kzalloc(gpio_bank_count * sizeof(struct gpio_bank),
1566 GFP_KERNEL);
1567 if (!gpio_bank) {
1568 dev_err(&pdev->dev, "Memory alloc failed for gpio_bank\n");
1569 return -ENOMEM;
1570 }
1571 return 0;
1572}
1573
1574/* TODO: Cleanup cpu_is_* checks */
2fae7fbe
VC		 1575static void omap_gpio_mod_init(struct gpio_bank *bank, int id)
1576{
1577 if (cpu_class_is_omap2()) {
1578 if (cpu_is_omap44xx()) {
1579 __raw_writel(0xffffffff, bank->base +
1580 OMAP4_GPIO_IRQSTATUSCLR0);
1581 __raw_writel(0x00000000, bank->base +
1582 OMAP4_GPIO_DEBOUNCENABLE);
1583 /* Initialize interface clk ungated, module enabled */
1584 __raw_writel(0, bank->base + OMAP4_GPIO_CTRL);
1585 } else if (cpu_is_omap34xx()) {
1586 __raw_writel(0x00000000, bank->base +
1587 OMAP24XX_GPIO_IRQENABLE1);
1588 __raw_writel(0xffffffff, bank->base +
1589 OMAP24XX_GPIO_IRQSTATUS1);
1590 __raw_writel(0x00000000, bank->base +
1591 OMAP24XX_GPIO_DEBOUNCE_EN);
1592
1593 /* Initialize interface clk ungated, module enabled */
1594 __raw_writel(0, bank->base + OMAP24XX_GPIO_CTRL);
1595 } else if (cpu_is_omap24xx()) {
1596 static const u32 non_wakeup_gpios[] = {
1597 0xe203ffc0, 0x08700040
1598 };
1599 if (id < ARRAY_SIZE(non_wakeup_gpios))
1600 bank->non_wakeup_gpios = non_wakeup_gpios[id];
1601 }
1602 } else if (cpu_class_is_omap1()) {
1603 if (bank_is_mpuio(bank))
1604 __raw_writew(0xffff, bank->base
1605 + OMAP_MPUIO_GPIO_MASKIT);
1606 if (cpu_is_omap15xx() && bank->method == METHOD_GPIO_1510) {
1607 __raw_writew(0xffff, bank->base
1608 + OMAP1510_GPIO_INT_MASK);
1609 __raw_writew(0x0000, bank->base
1610 + OMAP1510_GPIO_INT_STATUS);
1611 }
1612 if (cpu_is_omap16xx() && bank->method == METHOD_GPIO_1610) {
1613 __raw_writew(0x0000, bank->base
1614 + OMAP1610_GPIO_IRQENABLE1);
1615 __raw_writew(0xffff, bank->base
1616 + OMAP1610_GPIO_IRQSTATUS1);
1617 __raw_writew(0x0014, bank->base
1618 + OMAP1610_GPIO_SYSCONFIG);
1619
1620 /*
1621 * Enable system clock for GPIO module.
1622 * The CAM_CLK_CTRL *is* really the right place.
1623 */
1624 omap_writel(omap_readl(ULPD_CAM_CLK_CTRL) | 0x04,
1625 ULPD_CAM_CLK_CTRL);
1626 }
1627 if (cpu_is_omap7xx() && bank->method == METHOD_GPIO_7XX) {
1628 __raw_writel(0xffffffff, bank->base
1629 + OMAP7XX_GPIO_INT_MASK);
1630 __raw_writel(0x00000000, bank->base
1631 + OMAP7XX_GPIO_INT_STATUS);
1632 }
1633 }
1634}
1635
1636static void __init omap_gpio_chip_init(struct gpio_bank *bank)
1637{
77640aab 1638 int j;
2fae7fbe
VC		 1639 static int gpio;
1640
2fae7fbe
VC		 1641 bank->mod_usage = 0;
1642 /*
1643 * REVISIT eventually switch from OMAP-specific gpio structs
1644 * over to the generic ones
1645 */
1646 bank->chip.request = omap_gpio_request;
1647 bank->chip.free = omap_gpio_free;
1648 bank->chip.direction_input = gpio_input;
1649 bank->chip.get = gpio_get;
1650 bank->chip.direction_output = gpio_output;
1651 bank->chip.set_debounce = gpio_debounce;
1652 bank->chip.set = gpio_set;
1653 bank->chip.to_irq = gpio_2irq;
1654 if (bank_is_mpuio(bank)) {
1655 bank->chip.label = "mpuio";
1656#ifdef CONFIG_ARCH_OMAP16XX
1657 bank->chip.dev = &omap_mpuio_device.dev;
1658#endif
1659 bank->chip.base = OMAP_MPUIO(0);
1660 } else {
1661 bank->chip.label = "gpio";
1662 bank->chip.base = gpio;
1663 gpio += bank_width;
1664 }
1665 bank->chip.ngpio = bank_width;
1666
1667 gpiochip_add(&bank->chip);
1668
1669 for (j = bank->virtual_irq_start;
1670 j < bank->virtual_irq_start + bank_width; j++) {
1671 lockdep_set_class(&irq_desc[j].lock, &gpio_lock_class);
1672 set_irq_chip_data(j, bank);
1673 if (bank_is_mpuio(bank))
1674 set_irq_chip(j, &mpuio_irq_chip);
1675 else
1676 set_irq_chip(j, &gpio_irq_chip);
1677 set_irq_handler(j, handle_simple_irq);
1678 set_irq_flags(j, IRQF_VALID);
1679 }
1680 set_irq_chained_handler(bank->irq, gpio_irq_handler);
1681 set_irq_data(bank->irq, bank);
1682}
1683
77640aab 1684static int __devinit omap_gpio_probe(struct platform_device *pdev)
5e1c5ff4 1685{
77640aab
VC		 1686 static int gpio_init_done;
1687 struct omap_gpio_platform_data *pdata;
1688 struct resource *res;
1689 int id;
5e1c5ff4
TL		 1690 struct gpio_bank *bank;
1691
77640aab
VC		 1692 if (!pdev->dev.platform_data)
1693 return -EINVAL;
5e1c5ff4 1694
77640aab 1695 pdata = pdev->dev.platform_data;
56a25641 1696
77640aab
VC		 1697 if (!gpio_init_done) {
1698 int ret;
5492fb1a 1699
77640aab
VC		 1700 ret = init_gpio_info(pdev);
1701 if (ret)
1702 return ret;
5492fb1a 1703 }
5492fb1a 1704
77640aab
VC		 1705 id = pdev->id;
1706 bank = &gpio_bank[id];
92105bb7 1707
77640aab
VC		 1708 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1709 if (unlikely(!res)) {
1710 dev_err(&pdev->dev, "GPIO Bank %i Invalid IRQ resource\n", id);
1711 return -ENODEV;
44169075 1712 }
5e1c5ff4 1713
77640aab
VC		 1714 bank->irq = res->start;
1715 bank->virtual_irq_start = pdata->virtual_irq_start;
1716 bank->method = pdata->bank_type;
1717 bank->dev = &pdev->dev;
1718 bank->dbck_flag = pdata->dbck_flag;
1719 bank_width = pdata->bank_width;
9f7065da 1720
77640aab 1721 spin_lock_init(&bank->lock);
9f7065da 1722
77640aab
VC		 1723 /* Static mapping, never released */
1724 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1725 if (unlikely(!res)) {
1726 dev_err(&pdev->dev, "GPIO Bank %i Invalid mem resource\n", id);
1727 return -ENODEV;
1728 }
89db9482 1729
77640aab
VC		 1730 bank->base = ioremap(res->start, resource_size(res));
1731 if (!bank->base) {
1732 dev_err(&pdev->dev, "Could not ioremap gpio bank%i\n", id);
1733 return -ENOMEM;
5e1c5ff4
TL		 1734 }
1735
77640aab
VC		 1736 pm_runtime_enable(bank->dev);
1737 pm_runtime_get_sync(bank->dev);
1738
1739 omap_gpio_mod_init(bank, id);
1740 omap_gpio_chip_init(bank);
9a748053 1741 omap_gpio_show_rev(bank);
9f7065da 1742
77640aab
VC		 1743 if (!gpio_init_done)
1744 gpio_init_done = 1;
1745
5e1c5ff4
TL		 1746 return 0;
1747}
1748
140455fa 1749#if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP2PLUS)
92105bb7
TL		 1750static int omap_gpio_suspend(struct sys_device *dev, pm_message_t mesg)
1751{
1752 int i;
1753
5492fb1a 1754 if (!cpu_class_is_omap2() && !cpu_is_omap16xx())
92105bb7
TL		 1755 return 0;
1756
1757 for (i = 0; i < gpio_bank_count; i++) {
1758 struct gpio_bank *bank = &gpio_bank[i];
1759 void __iomem *wake_status;
1760 void __iomem *wake_clear;
1761 void __iomem *wake_set;
a6472533 1762 unsigned long flags;
92105bb7
TL		 1763
1764 switch (bank->method) {
e5c56ed3 1765#ifdef CONFIG_ARCH_OMAP16XX
92105bb7
TL		 1766 case METHOD_GPIO_1610:
1767 wake_status = bank->base + OMAP1610_GPIO_WAKEUPENABLE;
1768 wake_clear = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
1769 wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA;
1770 break;
e5c56ed3 1771#endif
a8eb7ca0 1772#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
92105bb7 1773 case METHOD_GPIO_24XX:
723fdb78 1774 wake_status = bank->base + OMAP24XX_GPIO_WAKE_EN;
92105bb7
TL		 1775 wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
1776 wake_set = bank->base + OMAP24XX_GPIO_SETWKUENA;
1777 break;
78a1a6d3
SR		 1778#endif
1779#ifdef CONFIG_ARCH_OMAP4
3f1686a9 1780 case METHOD_GPIO_44XX:
78a1a6d3
SR		 1781 wake_status = bank->base + OMAP4_GPIO_IRQWAKEN0;
1782 wake_clear = bank->base + OMAP4_GPIO_IRQWAKEN0;
1783 wake_set = bank->base + OMAP4_GPIO_IRQWAKEN0;
1784 break;
e5c56ed3 1785#endif
92105bb7
TL		 1786 default:
1787 continue;
1788 }
1789
a6472533 1790 spin_lock_irqsave(&bank->lock, flags);
92105bb7
TL		 1791 bank->saved_wakeup = __raw_readl(wake_status);
1792 __raw_writel(0xffffffff, wake_clear);
1793 __raw_writel(bank->suspend_wakeup, wake_set);
a6472533 1794 spin_unlock_irqrestore(&bank->lock, flags);
92105bb7
TL		 1795 }
1796
1797 return 0;
1798}
1799
1800static int omap_gpio_resume(struct sys_device *dev)
1801{
1802 int i;
1803
723fdb78 1804 if (!cpu_class_is_omap2() && !cpu_is_omap16xx())
92105bb7
TL		 1805 return 0;
1806
1807 for (i = 0; i < gpio_bank_count; i++) {
1808 struct gpio_bank *bank = &gpio_bank[i];
1809 void __iomem *wake_clear;
1810 void __iomem *wake_set;
a6472533 1811 unsigned long flags;
92105bb7
TL		 1812
1813 switch (bank->method) {
e5c56ed3 1814#ifdef CONFIG_ARCH_OMAP16XX
92105bb7
TL		 1815 case METHOD_GPIO_1610:
1816 wake_clear = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
1817 wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA;
1818 break;
e5c56ed3 1819#endif
a8eb7ca0 1820#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
92105bb7 1821 case METHOD_GPIO_24XX:
0d9356cb
TL		 1822 wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
1823 wake_set = bank->base + OMAP24XX_GPIO_SETWKUENA;
92105bb7 1824 break;
78a1a6d3
SR		 1825#endif
1826#ifdef CONFIG_ARCH_OMAP4
3f1686a9 1827 case METHOD_GPIO_44XX:
78a1a6d3
SR		 1828 wake_clear = bank->base + OMAP4_GPIO_IRQWAKEN0;
1829 wake_set = bank->base + OMAP4_GPIO_IRQWAKEN0;
1830 break;
e5c56ed3 1831#endif
92105bb7
TL		 1832 default:
1833 continue;
1834 }
1835
a6472533 1836 spin_lock_irqsave(&bank->lock, flags);
92105bb7
TL		 1837 __raw_writel(0xffffffff, wake_clear);
1838 __raw_writel(bank->saved_wakeup, wake_set);
a6472533 1839 spin_unlock_irqrestore(&bank->lock, flags);
92105bb7
TL		 1840 }
1841
1842 return 0;
1843}
1844
1845static struct sysdev_class omap_gpio_sysclass = {
af5ca3f4 1846 .name = "gpio",
92105bb7
TL		 1847 .suspend = omap_gpio_suspend,
1848 .resume = omap_gpio_resume,
1849};
1850
1851static struct sys_device omap_gpio_device = {
1852 .id = 0,
1853 .cls = &omap_gpio_sysclass,
1854};
3ac4fa99
JY		 1855
1856#endif
1857
140455fa 1858#ifdef CONFIG_ARCH_OMAP2PLUS
3ac4fa99
JY		 1859
1860static int workaround_enabled;
1861
43ffcd9a 1862void omap2_gpio_prepare_for_idle(int power_state)
3ac4fa99
JY		 1863{
1864 int i, c = 0;
a118b5f3 1865 int min = 0;
3ac4fa99 1866
a118b5f3
TK		 1867 if (cpu_is_omap34xx())
1868 min = 1;
43ffcd9a 1869
a118b5f3 1870 for (i = min; i < gpio_bank_count; i++) {
3ac4fa99 1871 struct gpio_bank *bank = &gpio_bank[i];
ca828760 1872 u32 l1 = 0, l2 = 0;
0aed0435 1873 int j;
3ac4fa99 1874
0aed0435 1875 for (j = 0; j < hweight_long(bank->dbck_enable_mask); j++)
8865b9b6
KH		 1876 clk_disable(bank->dbck);
1877
43ffcd9a
KH		 1878 if (power_state > PWRDM_POWER_OFF)
1879 continue;
1880
1881 /* If going to OFF, remove triggering for all
1882 * non-wakeup GPIOs. Otherwise spurious IRQs will be
1883 * generated. See OMAP2420 Errata item 1.101. */
3ac4fa99
JY		 1884 if (!(bank->enabled_non_wakeup_gpios))
1885 continue;
3f1686a9
TL		 1886
1887 if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
1888 bank->saved_datain = __raw_readl(bank->base +
1889 OMAP24XX_GPIO_DATAIN);
1890 l1 = __raw_readl(bank->base +
1891 OMAP24XX_GPIO_FALLINGDETECT);
1892 l2 = __raw_readl(bank->base +
1893 OMAP24XX_GPIO_RISINGDETECT);
1894 }
1895
1896 if (cpu_is_omap44xx()) {
1897 bank->saved_datain = __raw_readl(bank->base +
1898 OMAP4_GPIO_DATAIN);
1899 l1 = __raw_readl(bank->base +
1900 OMAP4_GPIO_FALLINGDETECT);
1901 l2 = __raw_readl(bank->base +
1902 OMAP4_GPIO_RISINGDETECT);
1903 }
1904
3ac4fa99
JY		 1905 bank->saved_fallingdetect = l1;
1906 bank->saved_risingdetect = l2;
1907 l1 &= ~bank->enabled_non_wakeup_gpios;
1908 l2 &= ~bank->enabled_non_wakeup_gpios;
3f1686a9
TL		 1909
1910 if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
1911 __raw_writel(l1, bank->base +
1912 OMAP24XX_GPIO_FALLINGDETECT);
1913 __raw_writel(l2, bank->base +
1914 OMAP24XX_GPIO_RISINGDETECT);
1915 }
1916
1917 if (cpu_is_omap44xx()) {
1918 __raw_writel(l1, bank->base + OMAP4_GPIO_FALLINGDETECT);
1919 __raw_writel(l2, bank->base + OMAP4_GPIO_RISINGDETECT);
1920 }
1921
3ac4fa99
JY		 1922 c++;
1923 }
1924 if (!c) {
1925 workaround_enabled = 0;
1926 return;
1927 }
1928 workaround_enabled = 1;
1929}
1930
43ffcd9a 1931void omap2_gpio_resume_after_idle(void)
3ac4fa99
JY		 1932{
1933 int i;
a118b5f3 1934 int min = 0;
3ac4fa99 1935
a118b5f3
TK		 1936 if (cpu_is_omap34xx())
1937 min = 1;
1938 for (i = min; i < gpio_bank_count; i++) {
3ac4fa99 1939 struct gpio_bank *bank = &gpio_bank[i];
ca828760 1940 u32 l = 0, gen, gen0, gen1;
0aed0435 1941 int j;
3ac4fa99 1942
0aed0435 1943 for (j = 0; j < hweight_long(bank->dbck_enable_mask); j++)
8865b9b6
KH		 1944 clk_enable(bank->dbck);
1945
43ffcd9a
KH		 1946 if (!workaround_enabled)
1947 continue;
1948
3ac4fa99
JY		 1949 if (!(bank->enabled_non_wakeup_gpios))
1950 continue;
3f1686a9
TL		 1951
1952 if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
1953 __raw_writel(bank->saved_fallingdetect,
3ac4fa99 1954 bank->base + OMAP24XX_GPIO_FALLINGDETECT);
3f1686a9 1955 __raw_writel(bank->saved_risingdetect,
3ac4fa99 1956 bank->base + OMAP24XX_GPIO_RISINGDETECT);
3f1686a9
TL		 1957 l = __raw_readl(bank->base + OMAP24XX_GPIO_DATAIN);
1958 }
1959
1960 if (cpu_is_omap44xx()) {
1961 __raw_writel(bank->saved_fallingdetect,
78a1a6d3 1962 bank->base + OMAP4_GPIO_FALLINGDETECT);
3f1686a9 1963 __raw_writel(bank->saved_risingdetect,
78a1a6d3 1964 bank->base + OMAP4_GPIO_RISINGDETECT);
3f1686a9
TL		 1965 l = __raw_readl(bank->base + OMAP4_GPIO_DATAIN);
1966 }
1967
3ac4fa99
JY		 1968 /* Check if any of the non-wakeup interrupt GPIOs have changed
1969 * state. If so, generate an IRQ by software. This is
1970 * horribly racy, but it's the best we can do to work around
1971 * this silicon bug. */
3ac4fa99 1972 l ^= bank->saved_datain;
a118b5f3 1973 l &= bank->enabled_non_wakeup_gpios;
82dbb9d3
EN		 1974
1975 /*
1976 * No need to generate IRQs for the rising edge for gpio IRQs
1977 * configured with falling edge only; and vice versa.
1978 */
1979 gen0 = l & bank->saved_fallingdetect;
1980 gen0 &= bank->saved_datain;
1981
1982 gen1 = l & bank->saved_risingdetect;
1983 gen1 &= ~(bank->saved_datain);
1984
1985 /* FIXME: Consider GPIO IRQs with level detections properly! */
1986 gen = l & (~(bank->saved_fallingdetect) &
1987 ~(bank->saved_risingdetect));
1988 /* Consider all GPIO IRQs needed to be updated */
1989 gen |= gen0 | gen1;
1990
1991 if (gen) {
3ac4fa99 1992 u32 old0, old1;
3f1686a9 1993
f00d6497 1994 if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
3f1686a9
TL		 1995 old0 = __raw_readl(bank->base +
1996 OMAP24XX_GPIO_LEVELDETECT0);
1997 old1 = __raw_readl(bank->base +
1998 OMAP24XX_GPIO_LEVELDETECT1);
f00d6497 1999 __raw_writel(old0 | gen, bank->base +
82dbb9d3 2000 OMAP24XX_GPIO_LEVELDETECT0);
f00d6497 2001 __raw_writel(old1 | gen, bank->base +
82dbb9d3 2002 OMAP24XX_GPIO_LEVELDETECT1);
f00d6497 2003 __raw_writel(old0, bank->base +
3f1686a9 2004 OMAP24XX_GPIO_LEVELDETECT0);
f00d6497 2005 __raw_writel(old1, bank->base +
3f1686a9
TL		 2006 OMAP24XX_GPIO_LEVELDETECT1);
2007 }
2008
2009 if (cpu_is_omap44xx()) {
2010 old0 = __raw_readl(bank->base +
78a1a6d3 2011 OMAP4_GPIO_LEVELDETECT0);
3f1686a9 2012 old1 = __raw_readl(bank->base +
78a1a6d3 2013 OMAP4_GPIO_LEVELDETECT1);
3f1686a9 2014 __raw_writel(old0 | l, bank->base +
78a1a6d3 2015 OMAP4_GPIO_LEVELDETECT0);
3f1686a9 2016 __raw_writel(old1 | l, bank->base +
78a1a6d3 2017 OMAP4_GPIO_LEVELDETECT1);
3f1686a9 2018 __raw_writel(old0, bank->base +
78a1a6d3 2019 OMAP4_GPIO_LEVELDETECT0);
3f1686a9 2020 __raw_writel(old1, bank->base +
78a1a6d3 2021 OMAP4_GPIO_LEVELDETECT1);
3f1686a9 2022 }
3ac4fa99
JY		 2023 }
2024 }
2025
2026}
2027
92105bb7
TL		 2028#endif
2029
a8eb7ca0 2030#ifdef CONFIG_ARCH_OMAP3
40c670f0
RN		 2031/* save the registers of bank 2-6 */
2032void omap_gpio_save_context(void)
2033{
2034 int i;
2035
2036 /* saving banks from 2-6 only since GPIO1 is in WKUP */
2037 for (i = 1; i < gpio_bank_count; i++) {
2038 struct gpio_bank *bank = &gpio_bank[i];
40c670f0
RN		 2039 gpio_context[i].irqenable1 =
2040 __raw_readl(bank->base + OMAP24XX_GPIO_IRQENABLE1);
2041 gpio_context[i].irqenable2 =
2042 __raw_readl(bank->base + OMAP24XX_GPIO_IRQENABLE2);
2043 gpio_context[i].wake_en =
2044 __raw_readl(bank->base + OMAP24XX_GPIO_WAKE_EN);
2045 gpio_context[i].ctrl =
2046 __raw_readl(bank->base + OMAP24XX_GPIO_CTRL);
2047 gpio_context[i].oe =
2048 __raw_readl(bank->base + OMAP24XX_GPIO_OE);
2049 gpio_context[i].leveldetect0 =
2050 __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT0);
2051 gpio_context[i].leveldetect1 =
2052 __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT1);
2053 gpio_context[i].risingdetect =
2054 __raw_readl(bank->base + OMAP24XX_GPIO_RISINGDETECT);
2055 gpio_context[i].fallingdetect =
2056 __raw_readl(bank->base + OMAP24XX_GPIO_FALLINGDETECT);
2057 gpio_context[i].dataout =
2058 __raw_readl(bank->base + OMAP24XX_GPIO_DATAOUT);
40c670f0
RN		 2059 }
2060}
2061
2062/* restore the required registers of bank 2-6 */
2063void omap_gpio_restore_context(void)
2064{
2065 int i;
2066
2067 for (i = 1; i < gpio_bank_count; i++) {
2068 struct gpio_bank *bank = &gpio_bank[i];
40c670f0
RN		 2069 __raw_writel(gpio_context[i].irqenable1,
2070 bank->base + OMAP24XX_GPIO_IRQENABLE1);
2071 __raw_writel(gpio_context[i].irqenable2,
2072 bank->base + OMAP24XX_GPIO_IRQENABLE2);
2073 __raw_writel(gpio_context[i].wake_en,
2074 bank->base + OMAP24XX_GPIO_WAKE_EN);
2075 __raw_writel(gpio_context[i].ctrl,
2076 bank->base + OMAP24XX_GPIO_CTRL);
2077 __raw_writel(gpio_context[i].oe,
2078 bank->base + OMAP24XX_GPIO_OE);
2079 __raw_writel(gpio_context[i].leveldetect0,
2080 bank->base + OMAP24XX_GPIO_LEVELDETECT0);
2081 __raw_writel(gpio_context[i].leveldetect1,
2082 bank->base + OMAP24XX_GPIO_LEVELDETECT1);
2083 __raw_writel(gpio_context[i].risingdetect,
2084 bank->base + OMAP24XX_GPIO_RISINGDETECT);
2085 __raw_writel(gpio_context[i].fallingdetect,
2086 bank->base + OMAP24XX_GPIO_FALLINGDETECT);
2087 __raw_writel(gpio_context[i].dataout,
2088 bank->base + OMAP24XX_GPIO_DATAOUT);
40c670f0
RN		 2089 }
2090}
2091#endif
2092
77640aab
VC		 2093static struct platform_driver omap_gpio_driver = {
2094 .probe = omap_gpio_probe,
2095 .driver = {
2096 .name = "omap_gpio",
2097 },
2098};
2099
5e1c5ff4 2100/*
77640aab
VC		 2101 * gpio driver register needs to be done before
2102 * machine_init functions access gpio APIs.
2103 * Hence omap_gpio_drv_reg() is a postcore_initcall.
5e1c5ff4 2104 */
77640aab 2105static int __init omap_gpio_drv_reg(void)
5e1c5ff4 2106{
77640aab 2107 return platform_driver_register(&omap_gpio_driver);
5e1c5ff4 2108}
77640aab 2109postcore_initcall(omap_gpio_drv_reg);
5e1c5ff4 2110
92105bb7
TL		 2111static int __init omap_gpio_sysinit(void)
2112{
2113 int ret = 0;
2114
11a78b79
DB		 2115 mpuio_init();
2116
140455fa 2117#if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP2PLUS)
5492fb1a 2118 if (cpu_is_omap16xx() || cpu_class_is_omap2()) {
92105bb7
TL		 2119 if (ret == 0) {
2120 ret = sysdev_class_register(&omap_gpio_sysclass);
2121 if (ret == 0)
2122 ret = sysdev_register(&omap_gpio_device);
2123 }
2124 }
2125#endif
2126
2127 return ret;
2128}
2129
92105bb7 2130arch_initcall(omap_gpio_sysinit);
Linux 6.x block layer and io_uring tree(s)