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OMAP3: GPIO: Only enable WAKEUPEN for edge detection GPIOs
[linux-block.git] / arch / arm / plat-omap / gpio.c
CommitLineData
5e1c5ff4
TL		 1/*
2 * linux/arch/arm/plat-omap/gpio.c
3 *
4 * Support functions for OMAP GPIO
5 *
92105bb7 6 * Copyright (C) 2003-2005 Nokia Corporation
96de0e25 7 * Written by Juha Yrjölä <juha.yrjola@nokia.com>
5e1c5ff4 8 *
44169075
SS		 9 * Copyright (C) 2009 Texas Instruments
10 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
11 *
5e1c5ff4
TL		 12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License version 2 as
14 * published by the Free Software Foundation.
15 */
16
5e1c5ff4
TL		 17#include <linux/init.h>
18#include <linux/module.h>
5e1c5ff4 19#include <linux/interrupt.h>
92105bb7
TL		 20#include <linux/sysdev.h>
21#include <linux/err.h>
f8ce2547 22#include <linux/clk.h>
fced80c7 23#include <linux/io.h>
5e1c5ff4 24
a09e64fb 25#include <mach/hardware.h>
5e1c5ff4 26#include <asm/irq.h>
a09e64fb
RK		 27#include <mach/irqs.h>
28#include <mach/gpio.h>
5e1c5ff4
TL		 29#include <asm/mach/irq.h>
30
5e1c5ff4
TL		 31/*
32 * OMAP1510 GPIO registers
33 */
9f7065da 34#define OMAP1510_GPIO_BASE 0xfffce000
5e1c5ff4
TL		 35#define OMAP1510_GPIO_DATA_INPUT 0x00
36#define OMAP1510_GPIO_DATA_OUTPUT 0x04
37#define OMAP1510_GPIO_DIR_CONTROL 0x08
38#define OMAP1510_GPIO_INT_CONTROL 0x0c
39#define OMAP1510_GPIO_INT_MASK 0x10
40#define OMAP1510_GPIO_INT_STATUS 0x14
41#define OMAP1510_GPIO_PIN_CONTROL 0x18
42
43#define OMAP1510_IH_GPIO_BASE 64
44
45/*
46 * OMAP1610 specific GPIO registers
47 */
9f7065da
TL		 48#define OMAP1610_GPIO1_BASE 0xfffbe400
49#define OMAP1610_GPIO2_BASE 0xfffbec00
50#define OMAP1610_GPIO3_BASE 0xfffbb400
51#define OMAP1610_GPIO4_BASE 0xfffbbc00
5e1c5ff4
TL		 52#define OMAP1610_GPIO_REVISION 0x0000
53#define OMAP1610_GPIO_SYSCONFIG 0x0010
54#define OMAP1610_GPIO_SYSSTATUS 0x0014
55#define OMAP1610_GPIO_IRQSTATUS1 0x0018
56#define OMAP1610_GPIO_IRQENABLE1 0x001c
92105bb7 57#define OMAP1610_GPIO_WAKEUPENABLE 0x0028
5e1c5ff4
TL		 58#define OMAP1610_GPIO_DATAIN 0x002c
59#define OMAP1610_GPIO_DATAOUT 0x0030
60#define OMAP1610_GPIO_DIRECTION 0x0034
61#define OMAP1610_GPIO_EDGE_CTRL1 0x0038
62#define OMAP1610_GPIO_EDGE_CTRL2 0x003c
63#define OMAP1610_GPIO_CLEAR_IRQENABLE1 0x009c
92105bb7 64#define OMAP1610_GPIO_CLEAR_WAKEUPENA 0x00a8
5e1c5ff4
TL		 65#define OMAP1610_GPIO_CLEAR_DATAOUT 0x00b0
66#define OMAP1610_GPIO_SET_IRQENABLE1 0x00dc
92105bb7 67#define OMAP1610_GPIO_SET_WAKEUPENA 0x00e8
5e1c5ff4
TL		 68#define OMAP1610_GPIO_SET_DATAOUT 0x00f0
69
70/*
7c006926 71 * OMAP7XX specific GPIO registers
5e1c5ff4 72 */
9f7065da
TL		 73#define OMAP7XX_GPIO1_BASE 0xfffbc000
74#define OMAP7XX_GPIO2_BASE 0xfffbc800
75#define OMAP7XX_GPIO3_BASE 0xfffbd000
76#define OMAP7XX_GPIO4_BASE 0xfffbd800
77#define OMAP7XX_GPIO5_BASE 0xfffbe000
78#define OMAP7XX_GPIO6_BASE 0xfffbe800
7c006926
AB		 79#define OMAP7XX_GPIO_DATA_INPUT 0x00
80#define OMAP7XX_GPIO_DATA_OUTPUT 0x04
81#define OMAP7XX_GPIO_DIR_CONTROL 0x08
82#define OMAP7XX_GPIO_INT_CONTROL 0x0c
83#define OMAP7XX_GPIO_INT_MASK 0x10
84#define OMAP7XX_GPIO_INT_STATUS 0x14
5e1c5ff4 85
9f7065da 86#define OMAP1_MPUIO_VBASE OMAP1_MPUIO_BASE
94113260 87
92105bb7
TL		 88/*
89 * omap24xx specific GPIO registers
90 */
9f7065da
TL		 91#define OMAP242X_GPIO1_BASE 0x48018000
92#define OMAP242X_GPIO2_BASE 0x4801a000
93#define OMAP242X_GPIO3_BASE 0x4801c000
94#define OMAP242X_GPIO4_BASE 0x4801e000
56a25641 95
9f7065da
TL		 96#define OMAP243X_GPIO1_BASE 0x4900C000
97#define OMAP243X_GPIO2_BASE 0x4900E000
98#define OMAP243X_GPIO3_BASE 0x49010000
99#define OMAP243X_GPIO4_BASE 0x49012000
100#define OMAP243X_GPIO5_BASE 0x480B6000
56a25641 101
92105bb7
TL		 102#define OMAP24XX_GPIO_REVISION 0x0000
103#define OMAP24XX_GPIO_SYSCONFIG 0x0010
104#define OMAP24XX_GPIO_SYSSTATUS 0x0014
105#define OMAP24XX_GPIO_IRQSTATUS1 0x0018
bee7930f
HD		 106#define OMAP24XX_GPIO_IRQSTATUS2 0x0028
107#define OMAP24XX_GPIO_IRQENABLE2 0x002c
92105bb7 108#define OMAP24XX_GPIO_IRQENABLE1 0x001c
723fdb78 109#define OMAP24XX_GPIO_WAKE_EN 0x0020
92105bb7
TL		 110#define OMAP24XX_GPIO_CTRL 0x0030
111#define OMAP24XX_GPIO_OE 0x0034
112#define OMAP24XX_GPIO_DATAIN 0x0038
113#define OMAP24XX_GPIO_DATAOUT 0x003c
114#define OMAP24XX_GPIO_LEVELDETECT0 0x0040
115#define OMAP24XX_GPIO_LEVELDETECT1 0x0044
116#define OMAP24XX_GPIO_RISINGDETECT 0x0048
117#define OMAP24XX_GPIO_FALLINGDETECT 0x004c
5eb3bb9c
KH		 118#define OMAP24XX_GPIO_DEBOUNCE_EN 0x0050
119#define OMAP24XX_GPIO_DEBOUNCE_VAL 0x0054
92105bb7
TL		 120#define OMAP24XX_GPIO_CLEARIRQENABLE1 0x0060
121#define OMAP24XX_GPIO_SETIRQENABLE1 0x0064
122#define OMAP24XX_GPIO_CLEARWKUENA 0x0080
123#define OMAP24XX_GPIO_SETWKUENA 0x0084
124#define OMAP24XX_GPIO_CLEARDATAOUT 0x0090
125#define OMAP24XX_GPIO_SETDATAOUT 0x0094
126
78a1a6d3
SR		 127#define OMAP4_GPIO_REVISION 0x0000
128#define OMAP4_GPIO_SYSCONFIG 0x0010
129#define OMAP4_GPIO_EOI 0x0020
130#define OMAP4_GPIO_IRQSTATUSRAW0 0x0024
131#define OMAP4_GPIO_IRQSTATUSRAW1 0x0028
132#define OMAP4_GPIO_IRQSTATUS0 0x002c
133#define OMAP4_GPIO_IRQSTATUS1 0x0030
134#define OMAP4_GPIO_IRQSTATUSSET0 0x0034
135#define OMAP4_GPIO_IRQSTATUSSET1 0x0038
136#define OMAP4_GPIO_IRQSTATUSCLR0 0x003c
137#define OMAP4_GPIO_IRQSTATUSCLR1 0x0040
138#define OMAP4_GPIO_IRQWAKEN0 0x0044
139#define OMAP4_GPIO_IRQWAKEN1 0x0048
140#define OMAP4_GPIO_SYSSTATUS 0x0104
141#define OMAP4_GPIO_CTRL 0x0130
142#define OMAP4_GPIO_OE 0x0134
143#define OMAP4_GPIO_DATAIN 0x0138
144#define OMAP4_GPIO_DATAOUT 0x013c
145#define OMAP4_GPIO_LEVELDETECT0 0x0140
146#define OMAP4_GPIO_LEVELDETECT1 0x0144
147#define OMAP4_GPIO_RISINGDETECT 0x0148
148#define OMAP4_GPIO_FALLINGDETECT 0x014c
149#define OMAP4_GPIO_DEBOUNCENABLE 0x0150
150#define OMAP4_GPIO_DEBOUNCINGTIME 0x0154
151#define OMAP4_GPIO_CLEARDATAOUT 0x0190
152#define OMAP4_GPIO_SETDATAOUT 0x0194
5492fb1a
SMK		 153/*
154 * omap34xx specific GPIO registers
155 */
156
9f7065da
TL		 157#define OMAP34XX_GPIO1_BASE 0x48310000
158#define OMAP34XX_GPIO2_BASE 0x49050000
159#define OMAP34XX_GPIO3_BASE 0x49052000
160#define OMAP34XX_GPIO4_BASE 0x49054000
161#define OMAP34XX_GPIO5_BASE 0x49056000
162#define OMAP34XX_GPIO6_BASE 0x49058000
5492fb1a 163
44169075
SS		 164/*
165 * OMAP44XX specific GPIO registers
166 */
9f7065da
TL		 167#define OMAP44XX_GPIO1_BASE 0x4a310000
168#define OMAP44XX_GPIO2_BASE 0x48055000
169#define OMAP44XX_GPIO3_BASE 0x48057000
170#define OMAP44XX_GPIO4_BASE 0x48059000
171#define OMAP44XX_GPIO5_BASE 0x4805B000
172#define OMAP44XX_GPIO6_BASE 0x4805D000
5492fb1a 173
5e1c5ff4 174struct gpio_bank {
9f7065da 175 unsigned long pbase;
92105bb7 176 void __iomem *base;
5e1c5ff4
TL		 177 u16 irq;
178 u16 virtual_irq_start;
92105bb7 179 int method;
140455fa 180#if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP2PLUS)
92105bb7
TL		 181 u32 suspend_wakeup;
182 u32 saved_wakeup;
3ac4fa99 183#endif
140455fa 184#ifdef CONFIG_ARCH_OMAP2PLUS
3ac4fa99
JY		 185 u32 non_wakeup_gpios;
186 u32 enabled_non_wakeup_gpios;
187
188 u32 saved_datain;
189 u32 saved_fallingdetect;
190 u32 saved_risingdetect;
191#endif
b144ff6f 192 u32 level_mask;
4318f36b 193 u32 toggle_mask;
5e1c5ff4 194 spinlock_t lock;
52e31344 195 struct gpio_chip chip;
89db9482 196 struct clk *dbck;
058af1ea 197 u32 mod_usage;
5e1c5ff4
TL		 198};
199
200#define METHOD_MPUIO 0
201#define METHOD_GPIO_1510 1
202#define METHOD_GPIO_1610 2
7c006926 203#define METHOD_GPIO_7XX 3
56739a69 204#define METHOD_GPIO_24XX 5
3f1686a9 205#define METHOD_GPIO_44XX 6
5e1c5ff4 206
92105bb7 207#ifdef CONFIG_ARCH_OMAP16XX
5e1c5ff4 208static struct gpio_bank gpio_bank_1610[5] = {
9f7065da
TL		 209 { OMAP1_MPUIO_VBASE, NULL, INT_MPUIO, IH_MPUIO_BASE,
210 METHOD_MPUIO },
211 { OMAP1610_GPIO1_BASE, NULL, INT_GPIO_BANK1, IH_GPIO_BASE,
212 METHOD_GPIO_1610 },
213 { OMAP1610_GPIO2_BASE, NULL, INT_1610_GPIO_BANK2, IH_GPIO_BASE + 16,
214 METHOD_GPIO_1610 },
215 { OMAP1610_GPIO3_BASE, NULL, INT_1610_GPIO_BANK3, IH_GPIO_BASE + 32,
216 METHOD_GPIO_1610 },
217 { OMAP1610_GPIO4_BASE, NULL, INT_1610_GPIO_BANK4, IH_GPIO_BASE + 48,
218 METHOD_GPIO_1610 },
5e1c5ff4
TL		 219};
220#endif
221
1a8bfa1e 222#ifdef CONFIG_ARCH_OMAP15XX
5e1c5ff4 223static struct gpio_bank gpio_bank_1510[2] = {
9f7065da
TL		 224 { OMAP1_MPUIO_VBASE, NULL, INT_MPUIO, IH_MPUIO_BASE,
225 METHOD_MPUIO },
226 { OMAP1510_GPIO_BASE, NULL, INT_GPIO_BANK1, IH_GPIO_BASE,
227 METHOD_GPIO_1510 }
5e1c5ff4
TL		 228};
229#endif
230
b718aa81 231#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
7c006926 232static struct gpio_bank gpio_bank_7xx[7] = {
9f7065da
TL		 233 { OMAP1_MPUIO_VBASE, NULL, INT_7XX_MPUIO, IH_MPUIO_BASE,
234 METHOD_MPUIO },
235 { OMAP7XX_GPIO1_BASE, NULL, INT_7XX_GPIO_BANK1, IH_GPIO_BASE,
236 METHOD_GPIO_7XX },
237 { OMAP7XX_GPIO2_BASE, NULL, INT_7XX_GPIO_BANK2, IH_GPIO_BASE + 32,
238 METHOD_GPIO_7XX },
239 { OMAP7XX_GPIO3_BASE, NULL, INT_7XX_GPIO_BANK3, IH_GPIO_BASE + 64,
240 METHOD_GPIO_7XX },
241 { OMAP7XX_GPIO4_BASE, NULL, INT_7XX_GPIO_BANK4, IH_GPIO_BASE + 96,
242 METHOD_GPIO_7XX },
243 { OMAP7XX_GPIO5_BASE, NULL, INT_7XX_GPIO_BANK5, IH_GPIO_BASE + 128,
244 METHOD_GPIO_7XX },
245 { OMAP7XX_GPIO6_BASE, NULL, INT_7XX_GPIO_BANK6, IH_GPIO_BASE + 160,
246 METHOD_GPIO_7XX },
5e1c5ff4
TL		 247};
248#endif
249
088ef950 250#ifdef CONFIG_ARCH_OMAP2
56a25641
SMK		 251
252static struct gpio_bank gpio_bank_242x[4] = {
9f7065da
TL		 253 { OMAP242X_GPIO1_BASE, NULL, INT_24XX_GPIO_BANK1, IH_GPIO_BASE,
254 METHOD_GPIO_24XX },
255 { OMAP242X_GPIO2_BASE, NULL, INT_24XX_GPIO_BANK2, IH_GPIO_BASE + 32,
256 METHOD_GPIO_24XX },
257 { OMAP242X_GPIO3_BASE, NULL, INT_24XX_GPIO_BANK3, IH_GPIO_BASE + 64,
258 METHOD_GPIO_24XX },
259 { OMAP242X_GPIO4_BASE, NULL, INT_24XX_GPIO_BANK4, IH_GPIO_BASE + 96,
260 METHOD_GPIO_24XX },
92105bb7 261};
56a25641
SMK		 262
263static struct gpio_bank gpio_bank_243x[5] = {
9f7065da
TL		 264 { OMAP243X_GPIO1_BASE, NULL, INT_24XX_GPIO_BANK1, IH_GPIO_BASE,
265 METHOD_GPIO_24XX },
266 { OMAP243X_GPIO2_BASE, NULL, INT_24XX_GPIO_BANK2, IH_GPIO_BASE + 32,
267 METHOD_GPIO_24XX },
268 { OMAP243X_GPIO3_BASE, NULL, INT_24XX_GPIO_BANK3, IH_GPIO_BASE + 64,
269 METHOD_GPIO_24XX },
270 { OMAP243X_GPIO4_BASE, NULL, INT_24XX_GPIO_BANK4, IH_GPIO_BASE + 96,
271 METHOD_GPIO_24XX },
272 { OMAP243X_GPIO5_BASE, NULL, INT_24XX_GPIO_BANK5, IH_GPIO_BASE + 128,
273 METHOD_GPIO_24XX },
56a25641
SMK		 274};
275
92105bb7
TL		 276#endif
277
a8eb7ca0 278#ifdef CONFIG_ARCH_OMAP3
5492fb1a 279static struct gpio_bank gpio_bank_34xx[6] = {
9f7065da
TL		 280 { OMAP34XX_GPIO1_BASE, NULL, INT_34XX_GPIO_BANK1, IH_GPIO_BASE,
281 METHOD_GPIO_24XX },
282 { OMAP34XX_GPIO2_BASE, NULL, INT_34XX_GPIO_BANK2, IH_GPIO_BASE + 32,
283 METHOD_GPIO_24XX },
284 { OMAP34XX_GPIO3_BASE, NULL, INT_34XX_GPIO_BANK3, IH_GPIO_BASE + 64,
285 METHOD_GPIO_24XX },
286 { OMAP34XX_GPIO4_BASE, NULL, INT_34XX_GPIO_BANK4, IH_GPIO_BASE + 96,
287 METHOD_GPIO_24XX },
288 { OMAP34XX_GPIO5_BASE, NULL, INT_34XX_GPIO_BANK5, IH_GPIO_BASE + 128,
289 METHOD_GPIO_24XX },
290 { OMAP34XX_GPIO6_BASE, NULL, INT_34XX_GPIO_BANK6, IH_GPIO_BASE + 160,
291 METHOD_GPIO_24XX },
5492fb1a
SMK		 292};
293
40c670f0
RN		 294struct omap3_gpio_regs {
295 u32 sysconfig;
296 u32 irqenable1;
297 u32 irqenable2;
298 u32 wake_en;
299 u32 ctrl;
300 u32 oe;
301 u32 leveldetect0;
302 u32 leveldetect1;
303 u32 risingdetect;
304 u32 fallingdetect;
305 u32 dataout;
306 u32 setwkuena;
307 u32 setdataout;
5492fb1a
SMK		 308};
309
40c670f0 310static struct omap3_gpio_regs gpio_context[OMAP34XX_NR_GPIOS];
5492fb1a
SMK		 311#endif
312
44169075
SS		 313#ifdef CONFIG_ARCH_OMAP4
314static struct gpio_bank gpio_bank_44xx[6] = {
5772ca7d 315 { OMAP44XX_GPIO1_BASE, NULL, OMAP44XX_IRQ_GPIO1, IH_GPIO_BASE,
3f1686a9 316 METHOD_GPIO_44XX },
5772ca7d 317 { OMAP44XX_GPIO2_BASE, NULL, OMAP44XX_IRQ_GPIO2, IH_GPIO_BASE + 32,
3f1686a9 318 METHOD_GPIO_44XX },
5772ca7d 319 { OMAP44XX_GPIO3_BASE, NULL, OMAP44XX_IRQ_GPIO3, IH_GPIO_BASE + 64,
3f1686a9 320 METHOD_GPIO_44XX },
5772ca7d 321 { OMAP44XX_GPIO4_BASE, NULL, OMAP44XX_IRQ_GPIO4, IH_GPIO_BASE + 96,
3f1686a9 322 METHOD_GPIO_44XX },
5772ca7d 323 { OMAP44XX_GPIO5_BASE, NULL, OMAP44XX_IRQ_GPIO5, IH_GPIO_BASE + 128,
3f1686a9 324 METHOD_GPIO_44XX },
5772ca7d 325 { OMAP44XX_GPIO6_BASE, NULL, OMAP44XX_IRQ_GPIO6, IH_GPIO_BASE + 160,
3f1686a9 326 METHOD_GPIO_44XX },
44169075
SS		 327};
328
329#endif
330
5e1c5ff4
TL		 331static struct gpio_bank *gpio_bank;
332static int gpio_bank_count;
333
334static inline struct gpio_bank *get_gpio_bank(int gpio)
335{
6e60e79a 336 if (cpu_is_omap15xx()) {
5e1c5ff4
TL		 337 if (OMAP_GPIO_IS_MPUIO(gpio))
338 return &gpio_bank[0];
339 return &gpio_bank[1];
340 }
5e1c5ff4
TL		 341 if (cpu_is_omap16xx()) {
342 if (OMAP_GPIO_IS_MPUIO(gpio))
343 return &gpio_bank[0];
344 return &gpio_bank[1 + (gpio >> 4)];
345 }
56739a69 346 if (cpu_is_omap7xx()) {
5e1c5ff4
TL		 347 if (OMAP_GPIO_IS_MPUIO(gpio))
348 return &gpio_bank[0];
349 return &gpio_bank[1 + (gpio >> 5)];
350 }
92105bb7
TL		 351 if (cpu_is_omap24xx())
352 return &gpio_bank[gpio >> 5];
44169075 353 if (cpu_is_omap34xx() || cpu_is_omap44xx())
5492fb1a 354 return &gpio_bank[gpio >> 5];
e031ab23
DB		 355 BUG();
356 return NULL;
5e1c5ff4
TL		 357}
358
359static inline int get_gpio_index(int gpio)
360{
56739a69 361 if (cpu_is_omap7xx())
5e1c5ff4 362 return gpio & 0x1f;
92105bb7
TL		 363 if (cpu_is_omap24xx())
364 return gpio & 0x1f;
44169075 365 if (cpu_is_omap34xx() || cpu_is_omap44xx())
5492fb1a 366 return gpio & 0x1f;
92105bb7 367 return gpio & 0x0f;
5e1c5ff4
TL		 368}
369
370static inline int gpio_valid(int gpio)
371{
372 if (gpio < 0)
373 return -1;
d11ac979 374 if (cpu_class_is_omap1() && OMAP_GPIO_IS_MPUIO(gpio)) {
193e68be 375 if (gpio >= OMAP_MAX_GPIO_LINES + 16)
5e1c5ff4
TL		 376 return -1;
377 return 0;
378 }
6e60e79a 379 if (cpu_is_omap15xx() && gpio < 16)
5e1c5ff4 380 return 0;
5e1c5ff4
TL		 381 if ((cpu_is_omap16xx()) && gpio < 64)
382 return 0;
56739a69 383 if (cpu_is_omap7xx() && gpio < 192)
5e1c5ff4 384 return 0;
92105bb7
TL		 385 if (cpu_is_omap24xx() && gpio < 128)
386 return 0;
44169075 387 if ((cpu_is_omap34xx() || cpu_is_omap44xx()) && gpio < 192)
5492fb1a 388 return 0;
5e1c5ff4
TL		 389 return -1;
390}
391
392static int check_gpio(int gpio)
393{
d32b20fc 394 if (unlikely(gpio_valid(gpio) < 0)) {
5e1c5ff4
TL		 395 printk(KERN_ERR "omap-gpio: invalid GPIO %d\n", gpio);
396 dump_stack();
397 return -1;
398 }
399 return 0;
400}
401
402static void _set_gpio_direction(struct gpio_bank *bank, int gpio, int is_input)
403{
92105bb7 404 void __iomem *reg = bank->base;
5e1c5ff4
TL		 405 u32 l;
406
407 switch (bank->method) {
e5c56ed3 408#ifdef CONFIG_ARCH_OMAP1
5e1c5ff4
TL		 409 case METHOD_MPUIO:
410 reg += OMAP_MPUIO_IO_CNTL;
411 break;
e5c56ed3
DB		 412#endif
413#ifdef CONFIG_ARCH_OMAP15XX
5e1c5ff4
TL		 414 case METHOD_GPIO_1510:
415 reg += OMAP1510_GPIO_DIR_CONTROL;
416 break;
e5c56ed3
DB		 417#endif
418#ifdef CONFIG_ARCH_OMAP16XX
5e1c5ff4
TL		 419 case METHOD_GPIO_1610:
420 reg += OMAP1610_GPIO_DIRECTION;
421 break;
e5c56ed3 422#endif
b718aa81 423#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
7c006926
AB		 424 case METHOD_GPIO_7XX:
425 reg += OMAP7XX_GPIO_DIR_CONTROL;
56739a69
ZM		 426 break;
427#endif
a8eb7ca0 428#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
92105bb7
TL		 429 case METHOD_GPIO_24XX:
430 reg += OMAP24XX_GPIO_OE;
431 break;
78a1a6d3
SR		 432#endif
433#if defined(CONFIG_ARCH_OMAP4)
3f1686a9 434 case METHOD_GPIO_44XX:
78a1a6d3
SR		 435 reg += OMAP4_GPIO_OE;
436 break;
e5c56ed3
DB		 437#endif
438 default:
439 WARN_ON(1);
440 return;
5e1c5ff4
TL		 441 }
442 l = __raw_readl(reg);
443 if (is_input)
444 l |= 1 << gpio;
445 else
446 l &= ~(1 << gpio);
447 __raw_writel(l, reg);
448}
449
5e1c5ff4
TL		 450static void _set_gpio_dataout(struct gpio_bank *bank, int gpio, int enable)
451{
92105bb7 452 void __iomem *reg = bank->base;
5e1c5ff4
TL		 453 u32 l = 0;
454
455 switch (bank->method) {
e5c56ed3 456#ifdef CONFIG_ARCH_OMAP1
5e1c5ff4
TL		 457 case METHOD_MPUIO:
458 reg += OMAP_MPUIO_OUTPUT;
459 l = __raw_readl(reg);
460 if (enable)
461 l |= 1 << gpio;
462 else
463 l &= ~(1 << gpio);
464 break;
e5c56ed3
DB		 465#endif
466#ifdef CONFIG_ARCH_OMAP15XX
5e1c5ff4
TL		 467 case METHOD_GPIO_1510:
468 reg += OMAP1510_GPIO_DATA_OUTPUT;
469 l = __raw_readl(reg);
470 if (enable)
471 l |= 1 << gpio;
472 else
473 l &= ~(1 << gpio);
474 break;
e5c56ed3
DB		 475#endif
476#ifdef CONFIG_ARCH_OMAP16XX
5e1c5ff4
TL		 477 case METHOD_GPIO_1610:
478 if (enable)
479 reg += OMAP1610_GPIO_SET_DATAOUT;
480 else
481 reg += OMAP1610_GPIO_CLEAR_DATAOUT;
482 l = 1 << gpio;
483 break;
e5c56ed3 484#endif
b718aa81 485#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
7c006926
AB		 486 case METHOD_GPIO_7XX:
487 reg += OMAP7XX_GPIO_DATA_OUTPUT;
56739a69
ZM		 488 l = __raw_readl(reg);
489 if (enable)
490 l |= 1 << gpio;
491 else
492 l &= ~(1 << gpio);
493 break;
494#endif
a8eb7ca0 495#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
92105bb7
TL		 496 case METHOD_GPIO_24XX:
497 if (enable)
498 reg += OMAP24XX_GPIO_SETDATAOUT;
499 else
500 reg += OMAP24XX_GPIO_CLEARDATAOUT;
501 l = 1 << gpio;
502 break;
78a1a6d3
SR		 503#endif
504#ifdef CONFIG_ARCH_OMAP4
3f1686a9 505 case METHOD_GPIO_44XX:
78a1a6d3
SR		 506 if (enable)
507 reg += OMAP4_GPIO_SETDATAOUT;
508 else
509 reg += OMAP4_GPIO_CLEARDATAOUT;
510 l = 1 << gpio;
511 break;
e5c56ed3 512#endif
5e1c5ff4 513 default:
e5c56ed3 514 WARN_ON(1);
5e1c5ff4
TL		 515 return;
516 }
517 __raw_writel(l, reg);
518}
519
b37c45b8 520static int _get_gpio_datain(struct gpio_bank *bank, int gpio)
5e1c5ff4 521{
92105bb7 522 void __iomem *reg;
5e1c5ff4
TL		 523
524 if (check_gpio(gpio) < 0)
e5c56ed3 525 return -EINVAL;
5e1c5ff4
TL		 526 reg = bank->base;
527 switch (bank->method) {
e5c56ed3 528#ifdef CONFIG_ARCH_OMAP1
5e1c5ff4
TL		 529 case METHOD_MPUIO:
530 reg += OMAP_MPUIO_INPUT_LATCH;
531 break;
e5c56ed3
DB		 532#endif
533#ifdef CONFIG_ARCH_OMAP15XX
5e1c5ff4
TL		 534 case METHOD_GPIO_1510:
535 reg += OMAP1510_GPIO_DATA_INPUT;
536 break;
e5c56ed3
DB		 537#endif
538#ifdef CONFIG_ARCH_OMAP16XX
5e1c5ff4
TL		 539 case METHOD_GPIO_1610:
540 reg += OMAP1610_GPIO_DATAIN;
541 break;
e5c56ed3 542#endif
b718aa81 543#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
7c006926
AB		 544 case METHOD_GPIO_7XX:
545 reg += OMAP7XX_GPIO_DATA_INPUT;
56739a69
ZM		 546 break;
547#endif
a8eb7ca0 548#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
92105bb7
TL		 549 case METHOD_GPIO_24XX:
550 reg += OMAP24XX_GPIO_DATAIN;
551 break;
78a1a6d3
SR		 552#endif
553#ifdef CONFIG_ARCH_OMAP4
3f1686a9 554 case METHOD_GPIO_44XX:
78a1a6d3
SR		 555 reg += OMAP4_GPIO_DATAIN;
556 break;
e5c56ed3 557#endif
5e1c5ff4 558 default:
e5c56ed3 559 return -EINVAL;
5e1c5ff4 560 }
92105bb7
TL		 561 return (__raw_readl(reg)
562 & (1 << get_gpio_index(gpio))) != 0;
5e1c5ff4
TL		 563}
564
b37c45b8
RQ		 565static int _get_gpio_dataout(struct gpio_bank *bank, int gpio)
566{
567 void __iomem *reg;
568
569 if (check_gpio(gpio) < 0)
570 return -EINVAL;
571 reg = bank->base;
572
573 switch (bank->method) {
574#ifdef CONFIG_ARCH_OMAP1
575 case METHOD_MPUIO:
576 reg += OMAP_MPUIO_OUTPUT;
577 break;
578#endif
579#ifdef CONFIG_ARCH_OMAP15XX
580 case METHOD_GPIO_1510:
581 reg += OMAP1510_GPIO_DATA_OUTPUT;
582 break;
583#endif
584#ifdef CONFIG_ARCH_OMAP16XX
585 case METHOD_GPIO_1610:
586 reg += OMAP1610_GPIO_DATAOUT;
587 break;
588#endif
b718aa81 589#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
7c006926
AB		 590 case METHOD_GPIO_7XX:
591 reg += OMAP7XX_GPIO_DATA_OUTPUT;
b37c45b8
RQ		 592 break;
593#endif
140455fa 594#ifdef CONFIG_ARCH_OMAP2PLUS
b37c45b8 595 case METHOD_GPIO_24XX:
3f1686a9 596 case METHOD_GPIO_44XX:
b37c45b8
RQ		 597 reg += OMAP24XX_GPIO_DATAOUT;
598 break;
599#endif
600 default:
601 return -EINVAL;
602 }
603
604 return (__raw_readl(reg) & (1 << get_gpio_index(gpio))) != 0;
605}
606
92105bb7
TL		 607#define MOD_REG_BIT(reg, bit_mask, set) \
608do { \
609 int l = __raw_readl(base + reg); \
610 if (set) l |= bit_mask; \
611 else l &= ~bit_mask; \
612 __raw_writel(l, base + reg); \
613} while(0)
614
5eb3bb9c
KH		 615void omap_set_gpio_debounce(int gpio, int enable)
616{
617 struct gpio_bank *bank;
618 void __iomem *reg;
e031ab23 619 unsigned long flags;
5eb3bb9c
KH		 620 u32 val, l = 1 << get_gpio_index(gpio);
621
622 if (cpu_class_is_omap1())
623 return;
624
625 bank = get_gpio_bank(gpio);
626 reg = bank->base;
3f1686a9
TL		 627
628 if (cpu_is_omap44xx())
629 reg += OMAP4_GPIO_DEBOUNCENABLE;
630 else
631 reg += OMAP24XX_GPIO_DEBOUNCE_EN;
632
058af1ea
C		 633 if (!(bank->mod_usage & l)) {
634 printk(KERN_ERR "GPIO %d not requested\n", gpio);
635 return;
636 }
e031ab23
DB		 637
638 spin_lock_irqsave(&bank->lock, flags);
5eb3bb9c
KH		 639 val = __raw_readl(reg);
640
89db9482 641 if (enable && !(val & l))
5eb3bb9c 642 val |= l;
e031ab23 643 else if (!enable && (val & l))
5eb3bb9c 644 val &= ~l;
89db9482 645 else
e031ab23 646 goto done;
89db9482 647
44169075 648 if (cpu_is_omap34xx() || cpu_is_omap44xx()) {
e031ab23
DB		 649 if (enable)
650 clk_enable(bank->dbck);
651 else
652 clk_disable(bank->dbck);
653 }
5eb3bb9c
KH		 654
655 __raw_writel(val, reg);
e031ab23
DB		 656done:
657 spin_unlock_irqrestore(&bank->lock, flags);
5eb3bb9c
KH		 658}
659EXPORT_SYMBOL(omap_set_gpio_debounce);
660
661void omap_set_gpio_debounce_time(int gpio, int enc_time)
662{
663 struct gpio_bank *bank;
664 void __iomem *reg;
665
666 if (cpu_class_is_omap1())
667 return;
668
669 bank = get_gpio_bank(gpio);
670 reg = bank->base;
671
058af1ea
C		 672 if (!bank->mod_usage) {
673 printk(KERN_ERR "GPIO not requested\n");
674 return;
675 }
676
5eb3bb9c 677 enc_time &= 0xff;
3f1686a9
TL		 678
679 if (cpu_is_omap44xx())
680 reg += OMAP4_GPIO_DEBOUNCINGTIME;
681 else
682 reg += OMAP24XX_GPIO_DEBOUNCE_VAL;
683
5eb3bb9c
KH		 684 __raw_writel(enc_time, reg);
685}
686EXPORT_SYMBOL(omap_set_gpio_debounce_time);
687
140455fa 688#ifdef CONFIG_ARCH_OMAP2PLUS
5eb3bb9c
KH		 689static inline void set_24xx_gpio_triggering(struct gpio_bank *bank, int gpio,
690 int trigger)
5e1c5ff4 691{
3ac4fa99 692 void __iomem *base = bank->base;
92105bb7 693 u32 gpio_bit = 1 << gpio;
78a1a6d3 694 u32 val;
92105bb7 695
78a1a6d3
SR		 696 if (cpu_is_omap44xx()) {
697 MOD_REG_BIT(OMAP4_GPIO_LEVELDETECT0, gpio_bit,
698 trigger & IRQ_TYPE_LEVEL_LOW);
699 MOD_REG_BIT(OMAP4_GPIO_LEVELDETECT1, gpio_bit,
700 trigger & IRQ_TYPE_LEVEL_HIGH);
701 MOD_REG_BIT(OMAP4_GPIO_RISINGDETECT, gpio_bit,
702 trigger & IRQ_TYPE_EDGE_RISING);
703 MOD_REG_BIT(OMAP4_GPIO_FALLINGDETECT, gpio_bit,
704 trigger & IRQ_TYPE_EDGE_FALLING);
705 } else {
706 MOD_REG_BIT(OMAP24XX_GPIO_LEVELDETECT0, gpio_bit,
707 trigger & IRQ_TYPE_LEVEL_LOW);
708 MOD_REG_BIT(OMAP24XX_GPIO_LEVELDETECT1, gpio_bit,
709 trigger & IRQ_TYPE_LEVEL_HIGH);
710 MOD_REG_BIT(OMAP24XX_GPIO_RISINGDETECT, gpio_bit,
711 trigger & IRQ_TYPE_EDGE_RISING);
712 MOD_REG_BIT(OMAP24XX_GPIO_FALLINGDETECT, gpio_bit,
713 trigger & IRQ_TYPE_EDGE_FALLING);
714 }
3ac4fa99 715 if (likely(!(bank->non_wakeup_gpios & gpio_bit))) {
78a1a6d3
SR		 716 if (cpu_is_omap44xx()) {
717 if (trigger != 0)
718 __raw_writel(1 << gpio, bank->base+
719 OMAP4_GPIO_IRQWAKEN0);
720 else {
721 val = __raw_readl(bank->base +
722 OMAP4_GPIO_IRQWAKEN0);
723 __raw_writel(val & (~(1 << gpio)), bank->base +
724 OMAP4_GPIO_IRQWAKEN0);
725 }
726 } else {
699117a6
CW		 727 /*
728 * GPIO wakeup request can only be generated on edge
729 * transitions
730 */
731 if (trigger & IRQ_TYPE_EDGE_BOTH)
78a1a6d3 732 __raw_writel(1 << gpio, bank->base
5eb3bb9c 733 + OMAP24XX_GPIO_SETWKUENA);
78a1a6d3
SR		 734 else
735 __raw_writel(1 << gpio, bank->base
5eb3bb9c 736 + OMAP24XX_GPIO_CLEARWKUENA);
78a1a6d3 737 }
a118b5f3
TK		 738 }
739 /* This part needs to be executed always for OMAP34xx */
740 if (cpu_is_omap34xx() || (bank->non_wakeup_gpios & gpio_bit)) {
699117a6
CW		 741 /*
742 * Log the edge gpio and manually trigger the IRQ
743 * after resume if the input level changes
744 * to avoid irq lost during PER RET/OFF mode
745 * Applies for omap2 non-wakeup gpio and all omap3 gpios
746 */
747 if (trigger & IRQ_TYPE_EDGE_BOTH)
3ac4fa99
JY		 748 bank->enabled_non_wakeup_gpios |= gpio_bit;
749 else
750 bank->enabled_non_wakeup_gpios &= ~gpio_bit;
751 }
5eb3bb9c 752
78a1a6d3
SR		 753 if (cpu_is_omap44xx()) {
754 bank->level_mask =
755 __raw_readl(bank->base + OMAP4_GPIO_LEVELDETECT0) |
756 __raw_readl(bank->base + OMAP4_GPIO_LEVELDETECT1);
757 } else {
758 bank->level_mask =
759 __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT0) |
760 __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT1);
761 }
92105bb7 762}
3ac4fa99 763#endif
92105bb7 764
9198bcd3 765#ifdef CONFIG_ARCH_OMAP1
4318f36b
CM		 766/*
767 * This only applies to chips that can't do both rising and falling edge
768 * detection at once. For all other chips, this function is a noop.
769 */
770static void _toggle_gpio_edge_triggering(struct gpio_bank *bank, int gpio)
771{
772 void __iomem *reg = bank->base;
773 u32 l = 0;
774
775 switch (bank->method) {
4318f36b
CM		 776 case METHOD_MPUIO:
777 reg += OMAP_MPUIO_GPIO_INT_EDGE;
778 break;
4318f36b
CM		 779#ifdef CONFIG_ARCH_OMAP15XX
780 case METHOD_GPIO_1510:
781 reg += OMAP1510_GPIO_INT_CONTROL;
782 break;
783#endif
784#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
785 case METHOD_GPIO_7XX:
786 reg += OMAP7XX_GPIO_INT_CONTROL;
787 break;
788#endif
789 default:
790 return;
791 }
792
793 l = __raw_readl(reg);
794 if ((l >> gpio) & 1)
795 l &= ~(1 << gpio);
796 else
797 l |= 1 << gpio;
798
799 __raw_writel(l, reg);
800}
9198bcd3 801#endif
4318f36b 802
92105bb7
TL		 803static int _set_gpio_triggering(struct gpio_bank *bank, int gpio, int trigger)
804{
805 void __iomem *reg = bank->base;
806 u32 l = 0;
5e1c5ff4
TL		 807
808 switch (bank->method) {
e5c56ed3 809#ifdef CONFIG_ARCH_OMAP1
5e1c5ff4
TL		 810 case METHOD_MPUIO:
811 reg += OMAP_MPUIO_GPIO_INT_EDGE;
812 l = __raw_readl(reg);
29501577 813 if ((trigger & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH)
4318f36b 814 bank->toggle_mask |= 1 << gpio;
6cab4860 815 if (trigger & IRQ_TYPE_EDGE_RISING)
5e1c5ff4 816 l |= 1 << gpio;
6cab4860 817 else if (trigger & IRQ_TYPE_EDGE_FALLING)
5e1c5ff4 818 l &= ~(1 << gpio);
92105bb7
TL		 819 else
820 goto bad;
5e1c5ff4 821 break;
e5c56ed3
DB		 822#endif
823#ifdef CONFIG_ARCH_OMAP15XX
5e1c5ff4
TL		 824 case METHOD_GPIO_1510:
825 reg += OMAP1510_GPIO_INT_CONTROL;
826 l = __raw_readl(reg);
29501577 827 if ((trigger & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH)
4318f36b 828 bank->toggle_mask |= 1 << gpio;
6cab4860 829 if (trigger & IRQ_TYPE_EDGE_RISING)
5e1c5ff4 830 l |= 1 << gpio;
6cab4860 831 else if (trigger & IRQ_TYPE_EDGE_FALLING)
5e1c5ff4 832 l &= ~(1 << gpio);
92105bb7
TL		 833 else
834 goto bad;
5e1c5ff4 835 break;
e5c56ed3 836#endif
3ac4fa99 837#ifdef CONFIG_ARCH_OMAP16XX
5e1c5ff4 838 case METHOD_GPIO_1610:
5e1c5ff4
TL		 839 if (gpio & 0x08)
840 reg += OMAP1610_GPIO_EDGE_CTRL2;
841 else
842 reg += OMAP1610_GPIO_EDGE_CTRL1;
843 gpio &= 0x07;
844 l = __raw_readl(reg);
845 l &= ~(3 << (gpio << 1));
6cab4860 846 if (trigger & IRQ_TYPE_EDGE_RISING)
6e60e79a 847 l |= 2 << (gpio << 1);
6cab4860 848 if (trigger & IRQ_TYPE_EDGE_FALLING)
6e60e79a 849 l |= 1 << (gpio << 1);
3ac4fa99
JY		 850 if (trigger)
851 /* Enable wake-up during idle for dynamic tick */
852 __raw_writel(1 << gpio, bank->base + OMAP1610_GPIO_SET_WAKEUPENA);
853 else
854 __raw_writel(1 << gpio, bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA);
5e1c5ff4 855 break;
3ac4fa99 856#endif
b718aa81 857#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
7c006926
AB		 858 case METHOD_GPIO_7XX:
859 reg += OMAP7XX_GPIO_INT_CONTROL;
56739a69 860 l = __raw_readl(reg);
29501577 861 if ((trigger & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH)
4318f36b 862 bank->toggle_mask |= 1 << gpio;
56739a69
ZM		 863 if (trigger & IRQ_TYPE_EDGE_RISING)
864 l |= 1 << gpio;
865 else if (trigger & IRQ_TYPE_EDGE_FALLING)
866 l &= ~(1 << gpio);
867 else
868 goto bad;
869 break;
870#endif
140455fa 871#ifdef CONFIG_ARCH_OMAP2PLUS
92105bb7 872 case METHOD_GPIO_24XX:
3f1686a9 873 case METHOD_GPIO_44XX:
3ac4fa99 874 set_24xx_gpio_triggering(bank, gpio, trigger);
5e1c5ff4 875 break;
3ac4fa99 876#endif
5e1c5ff4 877 default:
92105bb7 878 goto bad;
5e1c5ff4 879 }
92105bb7
TL		 880 __raw_writel(l, reg);
881 return 0;
882bad:
883 return -EINVAL;
5e1c5ff4
TL		 884}
885
92105bb7 886static int gpio_irq_type(unsigned irq, unsigned type)
5e1c5ff4
TL		 887{
888 struct gpio_bank *bank;
92105bb7
TL		 889 unsigned gpio;
890 int retval;
a6472533 891 unsigned long flags;
92105bb7 892
5492fb1a 893 if (!cpu_class_is_omap2() && irq > IH_MPUIO_BASE)
92105bb7
TL		 894 gpio = OMAP_MPUIO(irq - IH_MPUIO_BASE);
895 else
896 gpio = irq - IH_GPIO_BASE;
5e1c5ff4
TL		 897
898 if (check_gpio(gpio) < 0)
92105bb7
TL		 899 return -EINVAL;
900
e5c56ed3 901 if (type & ~IRQ_TYPE_SENSE_MASK)
6e60e79a 902 return -EINVAL;
e5c56ed3
DB		 903
904 /* OMAP1 allows only only edge triggering */
5492fb1a 905 if (!cpu_class_is_omap2()
e5c56ed3 906 && (type & (IRQ_TYPE_LEVEL_LOW|IRQ_TYPE_LEVEL_HIGH)))
92105bb7
TL		 907 return -EINVAL;
908
58781016 909 bank = get_irq_chip_data(irq);
a6472533 910 spin_lock_irqsave(&bank->lock, flags);
92105bb7 911 retval = _set_gpio_triggering(bank, get_gpio_index(gpio), type);
b9772a22
DB		 912 if (retval == 0) {
913 irq_desc[irq].status &= ~IRQ_TYPE_SENSE_MASK;
914 irq_desc[irq].status |= type;
915 }
a6472533 916 spin_unlock_irqrestore(&bank->lock, flags);
672e302e
KH		 917
918 if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
919 __set_irq_handler_unlocked(irq, handle_level_irq);
920 else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
921 __set_irq_handler_unlocked(irq, handle_edge_irq);
922
92105bb7 923 return retval;
5e1c5ff4
TL		 924}
925
926static void _clear_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
927{
92105bb7 928 void __iomem *reg = bank->base;
5e1c5ff4
TL		 929
930 switch (bank->method) {
e5c56ed3 931#ifdef CONFIG_ARCH_OMAP1
5e1c5ff4
TL		 932 case METHOD_MPUIO:
933 /* MPUIO irqstatus is reset by reading the status register,
934 * so do nothing here */
935 return;
e5c56ed3
DB		 936#endif
937#ifdef CONFIG_ARCH_OMAP15XX
5e1c5ff4
TL		 938 case METHOD_GPIO_1510:
939 reg += OMAP1510_GPIO_INT_STATUS;
940 break;
e5c56ed3
DB		 941#endif
942#ifdef CONFIG_ARCH_OMAP16XX
5e1c5ff4
TL		 943 case METHOD_GPIO_1610:
944 reg += OMAP1610_GPIO_IRQSTATUS1;
945 break;
e5c56ed3 946#endif
b718aa81 947#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
7c006926
AB		 948 case METHOD_GPIO_7XX:
949 reg += OMAP7XX_GPIO_INT_STATUS;
56739a69
ZM		 950 break;
951#endif
a8eb7ca0 952#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
92105bb7
TL		 953 case METHOD_GPIO_24XX:
954 reg += OMAP24XX_GPIO_IRQSTATUS1;
955 break;
78a1a6d3
SR		 956#endif
957#if defined(CONFIG_ARCH_OMAP4)
3f1686a9 958 case METHOD_GPIO_44XX:
78a1a6d3
SR		 959 reg += OMAP4_GPIO_IRQSTATUS0;
960 break;
e5c56ed3 961#endif
5e1c5ff4 962 default:
e5c56ed3 963 WARN_ON(1);
5e1c5ff4
TL		 964 return;
965 }
966 __raw_writel(gpio_mask, reg);
bee7930f
HD		 967
968 /* Workaround for clearing DSP GPIO interrupts to allow retention */
3f1686a9
TL		 969 if (cpu_is_omap24xx() || cpu_is_omap34xx())
970 reg = bank->base + OMAP24XX_GPIO_IRQSTATUS2;
971 else if (cpu_is_omap44xx())
972 reg = bank->base + OMAP4_GPIO_IRQSTATUS1;
973
78a1a6d3 974 if (cpu_is_omap24xx() || cpu_is_omap34xx() || cpu_is_omap44xx()) {
bedfd154
RQ		 975 __raw_writel(gpio_mask, reg);
976
977 /* Flush posted write for the irq status to avoid spurious interrupts */
978 __raw_readl(reg);
78a1a6d3 979 }
5e1c5ff4
TL		 980}
981
982static inline void _clear_gpio_irqstatus(struct gpio_bank *bank, int gpio)
983{
984 _clear_gpio_irqbank(bank, 1 << get_gpio_index(gpio));
985}
986
ea6dedd7
ID		 987static u32 _get_gpio_irqbank_mask(struct gpio_bank *bank)
988{
989 void __iomem *reg = bank->base;
99c47707
ID		 990 int inv = 0;
991 u32 l;
992 u32 mask;
ea6dedd7
ID		 993
994 switch (bank->method) {
e5c56ed3 995#ifdef CONFIG_ARCH_OMAP1
ea6dedd7
ID		 996 case METHOD_MPUIO:
997 reg += OMAP_MPUIO_GPIO_MASKIT;
99c47707
ID		 998 mask = 0xffff;
999 inv = 1;
ea6dedd7 1000 break;
e5c56ed3
DB		 1001#endif
1002#ifdef CONFIG_ARCH_OMAP15XX
ea6dedd7
ID		 1003 case METHOD_GPIO_1510:
1004 reg += OMAP1510_GPIO_INT_MASK;
99c47707
ID		 1005 mask = 0xffff;
1006 inv = 1;
ea6dedd7 1007 break;
e5c56ed3
DB		 1008#endif
1009#ifdef CONFIG_ARCH_OMAP16XX
ea6dedd7
ID		 1010 case METHOD_GPIO_1610:
1011 reg += OMAP1610_GPIO_IRQENABLE1;
99c47707 1012 mask = 0xffff;
ea6dedd7 1013 break;
e5c56ed3 1014#endif
b718aa81 1015#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
7c006926
AB		 1016 case METHOD_GPIO_7XX:
1017 reg += OMAP7XX_GPIO_INT_MASK;
56739a69
ZM		 1018 mask = 0xffffffff;
1019 inv = 1;
1020 break;
1021#endif
a8eb7ca0 1022#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
ea6dedd7
ID		 1023 case METHOD_GPIO_24XX:
1024 reg += OMAP24XX_GPIO_IRQENABLE1;
99c47707 1025 mask = 0xffffffff;
ea6dedd7 1026 break;
78a1a6d3
SR		 1027#endif
1028#if defined(CONFIG_ARCH_OMAP4)
3f1686a9 1029 case METHOD_GPIO_44XX:
78a1a6d3
SR		 1030 reg += OMAP4_GPIO_IRQSTATUSSET0;
1031 mask = 0xffffffff;
1032 break;
e5c56ed3 1033#endif
ea6dedd7 1034 default:
e5c56ed3 1035 WARN_ON(1);
ea6dedd7
ID		 1036 return 0;
1037 }
1038
99c47707
ID		 1039 l = __raw_readl(reg);
1040 if (inv)
1041 l = ~l;
1042 l &= mask;
1043 return l;
ea6dedd7
ID		 1044}
1045
5e1c5ff4
TL		 1046static void _enable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask, int enable)
1047{
92105bb7 1048 void __iomem *reg = bank->base;
5e1c5ff4
TL		 1049 u32 l;
1050
1051 switch (bank->method) {
e5c56ed3 1052#ifdef CONFIG_ARCH_OMAP1
5e1c5ff4
TL		 1053 case METHOD_MPUIO:
1054 reg += OMAP_MPUIO_GPIO_MASKIT;
1055 l = __raw_readl(reg);
1056 if (enable)
1057 l &= ~(gpio_mask);
1058 else
1059 l |= gpio_mask;
1060 break;
e5c56ed3
DB		 1061#endif
1062#ifdef CONFIG_ARCH_OMAP15XX
5e1c5ff4
TL		 1063 case METHOD_GPIO_1510:
1064 reg += OMAP1510_GPIO_INT_MASK;
1065 l = __raw_readl(reg);
1066 if (enable)
1067 l &= ~(gpio_mask);
1068 else
1069 l |= gpio_mask;
1070 break;
e5c56ed3
DB		 1071#endif
1072#ifdef CONFIG_ARCH_OMAP16XX
5e1c5ff4
TL		 1073 case METHOD_GPIO_1610:
1074 if (enable)
1075 reg += OMAP1610_GPIO_SET_IRQENABLE1;
1076 else
1077 reg += OMAP1610_GPIO_CLEAR_IRQENABLE1;
1078 l = gpio_mask;
1079 break;
e5c56ed3 1080#endif
b718aa81 1081#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
7c006926
AB		 1082 case METHOD_GPIO_7XX:
1083 reg += OMAP7XX_GPIO_INT_MASK;
56739a69
ZM		 1084 l = __raw_readl(reg);
1085 if (enable)
1086 l &= ~(gpio_mask);
1087 else
1088 l |= gpio_mask;
1089 break;
1090#endif
a8eb7ca0 1091#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
92105bb7
TL		 1092 case METHOD_GPIO_24XX:
1093 if (enable)
1094 reg += OMAP24XX_GPIO_SETIRQENABLE1;
1095 else
1096 reg += OMAP24XX_GPIO_CLEARIRQENABLE1;
1097 l = gpio_mask;
1098 break;
78a1a6d3
SR		 1099#endif
1100#ifdef CONFIG_ARCH_OMAP4
3f1686a9 1101 case METHOD_GPIO_44XX:
78a1a6d3
SR		 1102 if (enable)
1103 reg += OMAP4_GPIO_IRQSTATUSSET0;
1104 else
1105 reg += OMAP4_GPIO_IRQSTATUSCLR0;
1106 l = gpio_mask;
1107 break;
e5c56ed3 1108#endif
5e1c5ff4 1109 default:
e5c56ed3 1110 WARN_ON(1);
5e1c5ff4
TL		 1111 return;
1112 }
1113 __raw_writel(l, reg);
1114}
1115
1116static inline void _set_gpio_irqenable(struct gpio_bank *bank, int gpio, int enable)
1117{
1118 _enable_gpio_irqbank(bank, 1 << get_gpio_index(gpio), enable);
1119}
1120
92105bb7
TL		 1121/*
1122 * Note that ENAWAKEUP needs to be enabled in GPIO_SYSCONFIG register.
1123 * 1510 does not seem to have a wake-up register. If JTAG is connected
1124 * to the target, system will wake up always on GPIO events. While
1125 * system is running all registered GPIO interrupts need to have wake-up
1126 * enabled. When system is suspended, only selected GPIO interrupts need
1127 * to have wake-up enabled.
1128 */
1129static int _set_gpio_wakeup(struct gpio_bank *bank, int gpio, int enable)
1130{
4cc6420c 1131 unsigned long uninitialized_var(flags);
a6472533 1132
92105bb7 1133 switch (bank->method) {
3ac4fa99 1134#ifdef CONFIG_ARCH_OMAP16XX
11a78b79 1135 case METHOD_MPUIO:
92105bb7 1136 case METHOD_GPIO_1610:
a6472533 1137 spin_lock_irqsave(&bank->lock, flags);
b3bb4f68 1138 if (enable)
92105bb7 1139 bank->suspend_wakeup |= (1 << gpio);
b3bb4f68 1140 else
92105bb7 1141 bank->suspend_wakeup &= ~(1 << gpio);
a6472533 1142 spin_unlock_irqrestore(&bank->lock, flags);
92105bb7 1143 return 0;
3ac4fa99 1144#endif
140455fa 1145#ifdef CONFIG_ARCH_OMAP2PLUS
3ac4fa99 1146 case METHOD_GPIO_24XX:
3f1686a9 1147 case METHOD_GPIO_44XX:
11a78b79
DB		 1148 if (bank->non_wakeup_gpios & (1 << gpio)) {
1149 printk(KERN_ERR "Unable to modify wakeup on "
1150 "non-wakeup GPIO%d\n",
1151 (bank - gpio_bank) * 32 + gpio);
1152 return -EINVAL;
1153 }
a6472533 1154 spin_lock_irqsave(&bank->lock, flags);
b3bb4f68 1155 if (enable)
3ac4fa99 1156 bank->suspend_wakeup |= (1 << gpio);
b3bb4f68 1157 else
3ac4fa99 1158 bank->suspend_wakeup &= ~(1 << gpio);
a6472533 1159 spin_unlock_irqrestore(&bank->lock, flags);
3ac4fa99
JY		 1160 return 0;
1161#endif
92105bb7
TL		 1162 default:
1163 printk(KERN_ERR "Can't enable GPIO wakeup for method %i\n",
1164 bank->method);
1165 return -EINVAL;
1166 }
1167}
1168
4196dd6b
TL		 1169static void _reset_gpio(struct gpio_bank *bank, int gpio)
1170{
1171 _set_gpio_direction(bank, get_gpio_index(gpio), 1);
1172 _set_gpio_irqenable(bank, gpio, 0);
1173 _clear_gpio_irqstatus(bank, gpio);
6cab4860 1174 _set_gpio_triggering(bank, get_gpio_index(gpio), IRQ_TYPE_NONE);
4196dd6b
TL		 1175}
1176
92105bb7
TL		 1177/* Use disable_irq_wake() and enable_irq_wake() functions from drivers */
1178static int gpio_wake_enable(unsigned int irq, unsigned int enable)
1179{
1180 unsigned int gpio = irq - IH_GPIO_BASE;
1181 struct gpio_bank *bank;
1182 int retval;
1183
1184 if (check_gpio(gpio) < 0)
1185 return -ENODEV;
58781016 1186 bank = get_irq_chip_data(irq);
92105bb7 1187 retval = _set_gpio_wakeup(bank, get_gpio_index(gpio), enable);
92105bb7
TL		 1188
1189 return retval;
1190}
1191
3ff164e1 1192static int omap_gpio_request(struct gpio_chip *chip, unsigned offset)
5e1c5ff4 1193{
3ff164e1 1194 struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip);
a6472533 1195 unsigned long flags;
52e31344 1196
a6472533 1197 spin_lock_irqsave(&bank->lock, flags);
92105bb7 1198
4196dd6b
TL		 1199 /* Set trigger to none. You need to enable the desired trigger with
1200 * request_irq() or set_irq_type().
1201 */
3ff164e1 1202 _set_gpio_triggering(bank, offset, IRQ_TYPE_NONE);
92105bb7 1203
1a8bfa1e 1204#ifdef CONFIG_ARCH_OMAP15XX
5e1c5ff4 1205 if (bank->method == METHOD_GPIO_1510) {
92105bb7 1206 void __iomem *reg;
5e1c5ff4 1207
92105bb7 1208 /* Claim the pin for MPU */
5e1c5ff4 1209 reg = bank->base + OMAP1510_GPIO_PIN_CONTROL;
3ff164e1 1210 __raw_writel(__raw_readl(reg) | (1 << offset), reg);
5e1c5ff4
TL		 1211 }
1212#endif
058af1ea
C		 1213 if (!cpu_class_is_omap1()) {
1214 if (!bank->mod_usage) {
1215 u32 ctrl;
1216 ctrl = __raw_readl(bank->base + OMAP24XX_GPIO_CTRL);
1217 ctrl &= 0xFFFFFFFE;
1218 /* Module is enabled, clocks are not gated */
1219 __raw_writel(ctrl, bank->base + OMAP24XX_GPIO_CTRL);
1220 }
1221 bank->mod_usage |= 1 << offset;
1222 }
a6472533 1223 spin_unlock_irqrestore(&bank->lock, flags);
5e1c5ff4
TL		 1224
1225 return 0;
1226}
1227
3ff164e1 1228static void omap_gpio_free(struct gpio_chip *chip, unsigned offset)
5e1c5ff4 1229{
3ff164e1 1230 struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip);
a6472533 1231 unsigned long flags;
5e1c5ff4 1232
a6472533 1233 spin_lock_irqsave(&bank->lock, flags);
92105bb7
TL		 1234#ifdef CONFIG_ARCH_OMAP16XX
1235 if (bank->method == METHOD_GPIO_1610) {
1236 /* Disable wake-up during idle for dynamic tick */
1237 void __iomem *reg = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
3ff164e1 1238 __raw_writel(1 << offset, reg);
92105bb7
TL		 1239 }
1240#endif
140455fa 1241#ifdef CONFIG_ARCH_OMAP2PLUS
3f1686a9
TL		 1242 if ((bank->method == METHOD_GPIO_24XX) ||
1243 (bank->method == METHOD_GPIO_44XX)) {
92105bb7
TL		 1244 /* Disable wake-up during idle for dynamic tick */
1245 void __iomem *reg = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
3ff164e1 1246 __raw_writel(1 << offset, reg);
92105bb7
TL		 1247 }
1248#endif
058af1ea
C		 1249 if (!cpu_class_is_omap1()) {
1250 bank->mod_usage &= ~(1 << offset);
1251 if (!bank->mod_usage) {
1252 u32 ctrl;
1253 ctrl = __raw_readl(bank->base + OMAP24XX_GPIO_CTRL);
1254 /* Module is disabled, clocks are gated */
1255 ctrl |= 1;
1256 __raw_writel(ctrl, bank->base + OMAP24XX_GPIO_CTRL);
1257 }
1258 }
3ff164e1 1259 _reset_gpio(bank, bank->chip.base + offset);
a6472533 1260 spin_unlock_irqrestore(&bank->lock, flags);
5e1c5ff4
TL		 1261}
1262
1263/*
1264 * We need to unmask the GPIO bank interrupt as soon as possible to
1265 * avoid missing GPIO interrupts for other lines in the bank.
1266 * Then we need to mask-read-clear-unmask the triggered GPIO lines
1267 * in the bank to avoid missing nested interrupts for a GPIO line.
1268 * If we wait to unmask individual GPIO lines in the bank after the
1269 * line's interrupt handler has been run, we may miss some nested
1270 * interrupts.
1271 */
10dd5ce2 1272static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
5e1c5ff4 1273{
92105bb7 1274 void __iomem *isr_reg = NULL;
5e1c5ff4 1275 u32 isr;
4318f36b 1276 unsigned int gpio_irq, gpio_index;
5e1c5ff4 1277 struct gpio_bank *bank;
ea6dedd7
ID		 1278 u32 retrigger = 0;
1279 int unmasked = 0;
5e1c5ff4
TL		 1280
1281 desc->chip->ack(irq);
1282
418ca1f0 1283 bank = get_irq_data(irq);
e5c56ed3 1284#ifdef CONFIG_ARCH_OMAP1
5e1c5ff4
TL		 1285 if (bank->method == METHOD_MPUIO)
1286 isr_reg = bank->base + OMAP_MPUIO_GPIO_INT;
e5c56ed3 1287#endif
1a8bfa1e 1288#ifdef CONFIG_ARCH_OMAP15XX
5e1c5ff4
TL		 1289 if (bank->method == METHOD_GPIO_1510)
1290 isr_reg = bank->base + OMAP1510_GPIO_INT_STATUS;
1291#endif
1292#if defined(CONFIG_ARCH_OMAP16XX)
1293 if (bank->method == METHOD_GPIO_1610)
1294 isr_reg = bank->base + OMAP1610_GPIO_IRQSTATUS1;
1295#endif
b718aa81 1296#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
7c006926
AB		 1297 if (bank->method == METHOD_GPIO_7XX)
1298 isr_reg = bank->base + OMAP7XX_GPIO_INT_STATUS;
56739a69 1299#endif
a8eb7ca0 1300#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
92105bb7
TL		 1301 if (bank->method == METHOD_GPIO_24XX)
1302 isr_reg = bank->base + OMAP24XX_GPIO_IRQSTATUS1;
78a1a6d3
SR		 1303#endif
1304#if defined(CONFIG_ARCH_OMAP4)
3f1686a9 1305 if (bank->method == METHOD_GPIO_44XX)
78a1a6d3 1306 isr_reg = bank->base + OMAP4_GPIO_IRQSTATUS0;
92105bb7 1307#endif
92105bb7 1308 while(1) {
6e60e79a 1309 u32 isr_saved, level_mask = 0;
ea6dedd7 1310 u32 enabled;
6e60e79a 1311
ea6dedd7
ID		 1312 enabled = _get_gpio_irqbank_mask(bank);
1313 isr_saved = isr = __raw_readl(isr_reg) & enabled;
6e60e79a
TL		 1314
1315 if (cpu_is_omap15xx() && (bank->method == METHOD_MPUIO))
1316 isr &= 0x0000ffff;
1317
5492fb1a 1318 if (cpu_class_is_omap2()) {
b144ff6f 1319 level_mask = bank->level_mask & enabled;
ea6dedd7 1320 }
6e60e79a
TL		 1321
1322 /* clear edge sensitive interrupts before handler(s) are
1323 called so that we don't miss any interrupt occurred while
1324 executing them */
1325 _enable_gpio_irqbank(bank, isr_saved & ~level_mask, 0);
1326 _clear_gpio_irqbank(bank, isr_saved & ~level_mask);
1327 _enable_gpio_irqbank(bank, isr_saved & ~level_mask, 1);
1328
1329 /* if there is only edge sensitive GPIO pin interrupts
1330 configured, we could unmask GPIO bank interrupt immediately */
ea6dedd7
ID		 1331 if (!level_mask && !unmasked) {
1332 unmasked = 1;
6e60e79a 1333 desc->chip->unmask(irq);
ea6dedd7 1334 }
92105bb7 1335
ea6dedd7
ID		 1336 isr |= retrigger;
1337 retrigger = 0;
92105bb7
TL		 1338 if (!isr)
1339 break;
1340
1341 gpio_irq = bank->virtual_irq_start;
1342 for (; isr != 0; isr >>= 1, gpio_irq++) {
4318f36b
CM		 1343 gpio_index = get_gpio_index(irq_to_gpio(gpio_irq));
1344
92105bb7
TL		 1345 if (!(isr & 1))
1346 continue;
29454dde 1347
4318f36b
CM		 1348#ifdef CONFIG_ARCH_OMAP1
1349 /*
1350 * Some chips can't respond to both rising and falling
1351 * at the same time. If this irq was requested with
1352 * both flags, we need to flip the ICR data for the IRQ
1353 * to respond to the IRQ for the opposite direction.
1354 * This will be indicated in the bank toggle_mask.
1355 */
1356 if (bank->toggle_mask & (1 << gpio_index))
1357 _toggle_gpio_edge_triggering(bank, gpio_index);
1358#endif
1359
d8aa0251 1360 generic_handle_irq(gpio_irq);
92105bb7 1361 }
1a8bfa1e 1362 }
ea6dedd7
ID		 1363 /* if bank has any level sensitive GPIO pin interrupt
1364 configured, we must unmask the bank interrupt only after
1365 handler(s) are executed in order to avoid spurious bank
1366 interrupt */
1367 if (!unmasked)
1368 desc->chip->unmask(irq);
1369
5e1c5ff4
TL		 1370}
1371
4196dd6b
TL		 1372static void gpio_irq_shutdown(unsigned int irq)
1373{
1374 unsigned int gpio = irq - IH_GPIO_BASE;
58781016 1375 struct gpio_bank *bank = get_irq_chip_data(irq);
4196dd6b
TL		 1376
1377 _reset_gpio(bank, gpio);
1378}
1379
5e1c5ff4
TL		 1380static void gpio_ack_irq(unsigned int irq)
1381{
1382 unsigned int gpio = irq - IH_GPIO_BASE;
58781016 1383 struct gpio_bank *bank = get_irq_chip_data(irq);
5e1c5ff4
TL		 1384
1385 _clear_gpio_irqstatus(bank, gpio);
1386}
1387
1388static void gpio_mask_irq(unsigned int irq)
1389{
1390 unsigned int gpio = irq - IH_GPIO_BASE;
58781016 1391 struct gpio_bank *bank = get_irq_chip_data(irq);
5e1c5ff4
TL		 1392
1393 _set_gpio_irqenable(bank, gpio, 0);
55b6019a 1394 _set_gpio_triggering(bank, get_gpio_index(gpio), IRQ_TYPE_NONE);
5e1c5ff4
TL		 1395}
1396
1397static void gpio_unmask_irq(unsigned int irq)
1398{
1399 unsigned int gpio = irq - IH_GPIO_BASE;
58781016 1400 struct gpio_bank *bank = get_irq_chip_data(irq);
b144ff6f 1401 unsigned int irq_mask = 1 << get_gpio_index(gpio);
55b6019a
KH		 1402 struct irq_desc *desc = irq_to_desc(irq);
1403 u32 trigger = desc->status & IRQ_TYPE_SENSE_MASK;
1404
1405 if (trigger)
1406 _set_gpio_triggering(bank, get_gpio_index(gpio), trigger);
b144ff6f
KH		 1407
1408 /* For level-triggered GPIOs, the clearing must be done after
1409 * the HW source is cleared, thus after the handler has run */
1410 if (bank->level_mask & irq_mask) {
1411 _set_gpio_irqenable(bank, gpio, 0);
1412 _clear_gpio_irqstatus(bank, gpio);
1413 }
5e1c5ff4 1414
4de8c75b 1415 _set_gpio_irqenable(bank, gpio, 1);
5e1c5ff4
TL		 1416}
1417
e5c56ed3
DB		 1418static struct irq_chip gpio_irq_chip = {
1419 .name = "GPIO",
1420 .shutdown = gpio_irq_shutdown,
1421 .ack = gpio_ack_irq,
1422 .mask = gpio_mask_irq,
1423 .unmask = gpio_unmask_irq,
1424 .set_type = gpio_irq_type,
1425 .set_wake = gpio_wake_enable,
1426};
1427
1428/*---------------------------------------------------------------------*/
1429
1430#ifdef CONFIG_ARCH_OMAP1
1431
1432/* MPUIO uses the always-on 32k clock */
1433
5e1c5ff4
TL		 1434static void mpuio_ack_irq(unsigned int irq)
1435{
1436 /* The ISR is reset automatically, so do nothing here. */
1437}
1438
1439static void mpuio_mask_irq(unsigned int irq)
1440{
1441 unsigned int gpio = OMAP_MPUIO(irq - IH_MPUIO_BASE);
58781016 1442 struct gpio_bank *bank = get_irq_chip_data(irq);
5e1c5ff4
TL		 1443
1444 _set_gpio_irqenable(bank, gpio, 0);
1445}
1446
1447static void mpuio_unmask_irq(unsigned int irq)
1448{
1449 unsigned int gpio = OMAP_MPUIO(irq - IH_MPUIO_BASE);
58781016 1450 struct gpio_bank *bank = get_irq_chip_data(irq);
5e1c5ff4
TL		 1451
1452 _set_gpio_irqenable(bank, gpio, 1);
1453}
1454
e5c56ed3
DB		 1455static struct irq_chip mpuio_irq_chip = {
1456 .name = "MPUIO",
1457 .ack = mpuio_ack_irq,
1458 .mask = mpuio_mask_irq,
1459 .unmask = mpuio_unmask_irq,
92105bb7 1460 .set_type = gpio_irq_type,
11a78b79
DB		 1461#ifdef CONFIG_ARCH_OMAP16XX
1462 /* REVISIT: assuming only 16xx supports MPUIO wake events */
1463 .set_wake = gpio_wake_enable,
1464#endif
5e1c5ff4
TL		 1465};
1466
e5c56ed3
DB		 1467
1468#define bank_is_mpuio(bank) ((bank)->method == METHOD_MPUIO)
1469
11a78b79
DB		 1470
1471#ifdef CONFIG_ARCH_OMAP16XX
1472
1473#include <linux/platform_device.h>
1474
79ee031f 1475static int omap_mpuio_suspend_noirq(struct device *dev)
11a78b79 1476{
79ee031f 1477 struct platform_device *pdev = to_platform_device(dev);
11a78b79
DB		 1478 struct gpio_bank *bank = platform_get_drvdata(pdev);
1479 void __iomem *mask_reg = bank->base + OMAP_MPUIO_GPIO_MASKIT;
a6472533 1480 unsigned long flags;
11a78b79 1481
a6472533 1482 spin_lock_irqsave(&bank->lock, flags);
11a78b79
DB		 1483 bank->saved_wakeup = __raw_readl(mask_reg);
1484 __raw_writel(0xffff & ~bank->suspend_wakeup, mask_reg);
a6472533 1485 spin_unlock_irqrestore(&bank->lock, flags);
11a78b79
DB		 1486
1487 return 0;
1488}
1489
79ee031f 1490static int omap_mpuio_resume_noirq(struct device *dev)
11a78b79 1491{
79ee031f 1492 struct platform_device *pdev = to_platform_device(dev);
11a78b79
DB		 1493 struct gpio_bank *bank = platform_get_drvdata(pdev);
1494 void __iomem *mask_reg = bank->base + OMAP_MPUIO_GPIO_MASKIT;
a6472533 1495 unsigned long flags;
11a78b79 1496
a6472533 1497 spin_lock_irqsave(&bank->lock, flags);
11a78b79 1498 __raw_writel(bank->saved_wakeup, mask_reg);
a6472533 1499 spin_unlock_irqrestore(&bank->lock, flags);
11a78b79
DB		 1500
1501 return 0;
1502}
1503
47145210 1504static const struct dev_pm_ops omap_mpuio_dev_pm_ops = {
79ee031f
MD		 1505 .suspend_noirq = omap_mpuio_suspend_noirq,
1506 .resume_noirq = omap_mpuio_resume_noirq,
1507};
1508
11a78b79
DB		 1509/* use platform_driver for this, now that there's no longer any
1510 * point to sys_device (other than not disturbing old code).
1511 */
1512static struct platform_driver omap_mpuio_driver = {
11a78b79
DB		 1513 .driver = {
1514 .name = "mpuio",
79ee031f 1515 .pm = &omap_mpuio_dev_pm_ops,
11a78b79
DB		 1516 },
1517};
1518
1519static struct platform_device omap_mpuio_device = {
1520 .name = "mpuio",
1521 .id = -1,
1522 .dev = {
1523 .driver = &omap_mpuio_driver.driver,
1524 }
1525 /* could list the /proc/iomem resources */
1526};
1527
1528static inline void mpuio_init(void)
1529{
fcf126d8
DB		 1530 platform_set_drvdata(&omap_mpuio_device, &gpio_bank_1610[0]);
1531
11a78b79
DB		 1532 if (platform_driver_register(&omap_mpuio_driver) == 0)
1533 (void) platform_device_register(&omap_mpuio_device);
1534}
1535
1536#else
1537static inline void mpuio_init(void) {}
1538#endif /* 16xx */
1539
e5c56ed3
DB		 1540#else
1541
1542extern struct irq_chip mpuio_irq_chip;
1543
1544#define bank_is_mpuio(bank) 0
11a78b79 1545static inline void mpuio_init(void) {}
e5c56ed3
DB		 1546
1547#endif
1548
1549/*---------------------------------------------------------------------*/
5e1c5ff4 1550
52e31344
DB		 1551/* REVISIT these are stupid implementations! replace by ones that
1552 * don't switch on METHOD_* and which mostly avoid spinlocks
1553 */
1554
1555static int gpio_input(struct gpio_chip *chip, unsigned offset)
1556{
1557 struct gpio_bank *bank;
1558 unsigned long flags;
1559
1560 bank = container_of(chip, struct gpio_bank, chip);
1561 spin_lock_irqsave(&bank->lock, flags);
1562 _set_gpio_direction(bank, offset, 1);
1563 spin_unlock_irqrestore(&bank->lock, flags);
1564 return 0;
1565}
1566
b37c45b8
RQ		 1567static int gpio_is_input(struct gpio_bank *bank, int mask)
1568{
1569 void __iomem *reg = bank->base;
1570
1571 switch (bank->method) {
1572 case METHOD_MPUIO:
1573 reg += OMAP_MPUIO_IO_CNTL;
1574 break;
1575 case METHOD_GPIO_1510:
1576 reg += OMAP1510_GPIO_DIR_CONTROL;
1577 break;
1578 case METHOD_GPIO_1610:
1579 reg += OMAP1610_GPIO_DIRECTION;
1580 break;
7c006926
AB		 1581 case METHOD_GPIO_7XX:
1582 reg += OMAP7XX_GPIO_DIR_CONTROL;
b37c45b8
RQ		 1583 break;
1584 case METHOD_GPIO_24XX:
3f1686a9 1585 case METHOD_GPIO_44XX:
b37c45b8
RQ		 1586 reg += OMAP24XX_GPIO_OE;
1587 break;
1588 }
1589 return __raw_readl(reg) & mask;
1590}
1591
52e31344
DB		 1592static int gpio_get(struct gpio_chip *chip, unsigned offset)
1593{
b37c45b8
RQ		 1594 struct gpio_bank *bank;
1595 void __iomem *reg;
1596 int gpio;
1597 u32 mask;
1598
1599 gpio = chip->base + offset;
1600 bank = get_gpio_bank(gpio);
1601 reg = bank->base;
1602 mask = 1 << get_gpio_index(gpio);
1603
1604 if (gpio_is_input(bank, mask))
1605 return _get_gpio_datain(bank, gpio);
1606 else
1607 return _get_gpio_dataout(bank, gpio);
52e31344
DB		 1608}
1609
1610static int gpio_output(struct gpio_chip *chip, unsigned offset, int value)
1611{
1612 struct gpio_bank *bank;
1613 unsigned long flags;
1614
1615 bank = container_of(chip, struct gpio_bank, chip);
1616 spin_lock_irqsave(&bank->lock, flags);
1617 _set_gpio_dataout(bank, offset, value);
1618 _set_gpio_direction(bank, offset, 0);
1619 spin_unlock_irqrestore(&bank->lock, flags);
1620 return 0;
1621}
1622
1623static void gpio_set(struct gpio_chip *chip, unsigned offset, int value)
1624{
1625 struct gpio_bank *bank;
1626 unsigned long flags;
1627
1628 bank = container_of(chip, struct gpio_bank, chip);
1629 spin_lock_irqsave(&bank->lock, flags);
1630 _set_gpio_dataout(bank, offset, value);
1631 spin_unlock_irqrestore(&bank->lock, flags);
1632}
1633
a007b709
DB		 1634static int gpio_2irq(struct gpio_chip *chip, unsigned offset)
1635{
1636 struct gpio_bank *bank;
1637
1638 bank = container_of(chip, struct gpio_bank, chip);
1639 return bank->virtual_irq_start + offset;
1640}
1641
52e31344
DB		 1642/*---------------------------------------------------------------------*/
1643
1a8bfa1e 1644static int initialized;
56213ca4 1645#if defined(CONFIG_ARCH_OMAP1) || defined(CONFIG_ARCH_OMAP2)
1a8bfa1e 1646static struct clk * gpio_ick;
5492fb1a
SMK		 1647#endif
1648
1649#if defined(CONFIG_ARCH_OMAP2)
1a8bfa1e 1650static struct clk * gpio_fck;
5492fb1a 1651#endif
5e1c5ff4 1652
5492fb1a 1653#if defined(CONFIG_ARCH_OMAP2430)
56a25641
SMK		 1654static struct clk * gpio5_ick;
1655static struct clk * gpio5_fck;
1656#endif
1657
44169075 1658#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)
5492fb1a
SMK		 1659static struct clk *gpio_iclks[OMAP34XX_NR_GPIOS];
1660#endif
1661
9f7065da
TL		 1662static void __init omap_gpio_show_rev(void)
1663{
1664 u32 rev;
1665
1666 if (cpu_is_omap16xx())
1667 rev = __raw_readw(gpio_bank[1].base + OMAP1610_GPIO_REVISION);
1668 else if (cpu_is_omap24xx() || cpu_is_omap34xx())
1669 rev = __raw_readl(gpio_bank[0].base + OMAP24XX_GPIO_REVISION);
1670 else if (cpu_is_omap44xx())
1671 rev = __raw_readl(gpio_bank[0].base + OMAP4_GPIO_REVISION);
1672 else
1673 return;
1674
1675 printk(KERN_INFO "OMAP GPIO hardware version %d.%d\n",
1676 (rev >> 4) & 0x0f, rev & 0x0f);
1677}
1678
8ba55c5c
DB		 1679/* This lock class tells lockdep that GPIO irqs are in a different
1680 * category than their parents, so it won't report false recursion.
1681 */
1682static struct lock_class_key gpio_lock_class;
1683
5e1c5ff4
TL		 1684static int __init _omap_gpio_init(void)
1685{
1686 int i;
52e31344 1687 int gpio = 0;
5e1c5ff4 1688 struct gpio_bank *bank;
9f7065da 1689 int bank_size = SZ_8K; /* Module 4KB + L4 4KB except on omap1 */
5492fb1a 1690 char clk_name[11];
5e1c5ff4
TL		 1691
1692 initialized = 1;
1693
5492fb1a 1694#if defined(CONFIG_ARCH_OMAP1)
6e60e79a 1695 if (cpu_is_omap15xx()) {
1a8bfa1e
TL		 1696 gpio_ick = clk_get(NULL, "arm_gpio_ck");
1697 if (IS_ERR(gpio_ick))
92105bb7
TL		 1698 printk("Could not get arm_gpio_ck\n");
1699 else
30ff720b 1700 clk_enable(gpio_ick);
1a8bfa1e 1701 }
5492fb1a
SMK		 1702#endif
1703#if defined(CONFIG_ARCH_OMAP2)
1704 if (cpu_class_is_omap2()) {
1a8bfa1e
TL		 1705 gpio_ick = clk_get(NULL, "gpios_ick");
1706 if (IS_ERR(gpio_ick))
1707 printk("Could not get gpios_ick\n");
1708 else
30ff720b 1709 clk_enable(gpio_ick);
1a8bfa1e 1710 gpio_fck = clk_get(NULL, "gpios_fck");
1630b52d 1711 if (IS_ERR(gpio_fck))
1a8bfa1e
TL		 1712 printk("Could not get gpios_fck\n");
1713 else
30ff720b 1714 clk_enable(gpio_fck);
56a25641
SMK		 1715
1716 /*
5492fb1a 1717 * On 2430 & 3430 GPIO 5 uses CORE L4 ICLK
56a25641 1718 */
5492fb1a 1719#if defined(CONFIG_ARCH_OMAP2430)
56a25641
SMK		 1720 if (cpu_is_omap2430()) {
1721 gpio5_ick = clk_get(NULL, "gpio5_ick");
1722 if (IS_ERR(gpio5_ick))
1723 printk("Could not get gpio5_ick\n");
1724 else
1725 clk_enable(gpio5_ick);
1726 gpio5_fck = clk_get(NULL, "gpio5_fck");
1727 if (IS_ERR(gpio5_fck))
1728 printk("Could not get gpio5_fck\n");
1729 else
1730 clk_enable(gpio5_fck);
1731 }
1732#endif
5492fb1a
SMK		 1733 }
1734#endif
1735
44169075
SS		 1736#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)
1737 if (cpu_is_omap34xx() || cpu_is_omap44xx()) {
5492fb1a
SMK		 1738 for (i = 0; i < OMAP34XX_NR_GPIOS; i++) {
1739 sprintf(clk_name, "gpio%d_ick", i + 1);
1740 gpio_iclks[i] = clk_get(NULL, clk_name);
1741 if (IS_ERR(gpio_iclks[i]))
1742 printk(KERN_ERR "Could not get %s\n", clk_name);
1743 else
1744 clk_enable(gpio_iclks[i]);
5492fb1a
SMK		 1745 }
1746 }
1747#endif
1748
92105bb7 1749
1a8bfa1e 1750#ifdef CONFIG_ARCH_OMAP15XX
6e60e79a 1751 if (cpu_is_omap15xx()) {
5e1c5ff4
TL		 1752 gpio_bank_count = 2;
1753 gpio_bank = gpio_bank_1510;
9f7065da 1754 bank_size = SZ_2K;
5e1c5ff4
TL		 1755 }
1756#endif
1757#if defined(CONFIG_ARCH_OMAP16XX)
1758 if (cpu_is_omap16xx()) {
5e1c5ff4
TL		 1759 gpio_bank_count = 5;
1760 gpio_bank = gpio_bank_1610;
9f7065da 1761 bank_size = SZ_2K;
5e1c5ff4
TL		 1762 }
1763#endif
b718aa81
AB		 1764#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
1765 if (cpu_is_omap7xx()) {
56739a69 1766 gpio_bank_count = 7;
7c006926 1767 gpio_bank = gpio_bank_7xx;
9f7065da 1768 bank_size = SZ_2K;
56739a69
ZM		 1769 }
1770#endif
088ef950 1771#ifdef CONFIG_ARCH_OMAP2
56a25641 1772 if (cpu_is_omap242x()) {
92105bb7 1773 gpio_bank_count = 4;
56a25641 1774 gpio_bank = gpio_bank_242x;
56a25641
SMK		 1775 }
1776 if (cpu_is_omap243x()) {
56a25641
SMK		 1777 gpio_bank_count = 5;
1778 gpio_bank = gpio_bank_243x;
92105bb7 1779 }
5492fb1a 1780#endif
a8eb7ca0 1781#ifdef CONFIG_ARCH_OMAP3
5492fb1a 1782 if (cpu_is_omap34xx()) {
5492fb1a
SMK		 1783 gpio_bank_count = OMAP34XX_NR_GPIOS;
1784 gpio_bank = gpio_bank_34xx;
5492fb1a 1785 }
44169075
SS		 1786#endif
1787#ifdef CONFIG_ARCH_OMAP4
1788 if (cpu_is_omap44xx()) {
44169075
SS		 1789 gpio_bank_count = OMAP34XX_NR_GPIOS;
1790 gpio_bank = gpio_bank_44xx;
44169075 1791 }
5e1c5ff4
TL		 1792#endif
1793 for (i = 0; i < gpio_bank_count; i++) {
1794 int j, gpio_count = 16;
1795
1796 bank = &gpio_bank[i];
5e1c5ff4 1797 spin_lock_init(&bank->lock);
9f7065da
TL		 1798
1799 /* Static mapping, never released */
1800 bank->base = ioremap(bank->pbase, bank_size);
1801 if (!bank->base) {
1802 printk(KERN_ERR "Could not ioremap gpio bank%i\n", i);
1803 continue;
1804 }
1805
e5c56ed3 1806 if (bank_is_mpuio(bank))
7c7095aa 1807 __raw_writew(0xffff, bank->base + OMAP_MPUIO_GPIO_MASKIT);
d11ac979 1808 if (cpu_is_omap15xx() && bank->method == METHOD_GPIO_1510) {
5e1c5ff4
TL		 1809 __raw_writew(0xffff, bank->base + OMAP1510_GPIO_INT_MASK);
1810 __raw_writew(0x0000, bank->base + OMAP1510_GPIO_INT_STATUS);
1811 }
d11ac979 1812 if (cpu_is_omap16xx() && bank->method == METHOD_GPIO_1610) {
5e1c5ff4
TL		 1813 __raw_writew(0x0000, bank->base + OMAP1610_GPIO_IRQENABLE1);
1814 __raw_writew(0xffff, bank->base + OMAP1610_GPIO_IRQSTATUS1);
92105bb7 1815 __raw_writew(0x0014, bank->base + OMAP1610_GPIO_SYSCONFIG);
5e1c5ff4 1816 }
7c006926
AB		 1817 if (cpu_is_omap7xx() && bank->method == METHOD_GPIO_7XX) {
1818 __raw_writel(0xffffffff, bank->base + OMAP7XX_GPIO_INT_MASK);
1819 __raw_writel(0x00000000, bank->base + OMAP7XX_GPIO_INT_STATUS);
5e1c5ff4 1820
7c006926 1821 gpio_count = 32; /* 7xx has 32-bit GPIOs */
5e1c5ff4 1822 }
d11ac979 1823
140455fa 1824#ifdef CONFIG_ARCH_OMAP2PLUS
3f1686a9
TL		 1825 if ((bank->method == METHOD_GPIO_24XX) ||
1826 (bank->method == METHOD_GPIO_44XX)) {
3ac4fa99
JY		 1827 static const u32 non_wakeup_gpios[] = {
1828 0xe203ffc0, 0x08700040
1829 };
3f1686a9
TL		 1830
1831 if (cpu_is_omap44xx()) {
1832 __raw_writel(0xffffffff, bank->base +
78a1a6d3 1833 OMAP4_GPIO_IRQSTATUSCLR0);
3f1686a9 1834 __raw_writew(0x0015, bank->base +
78a1a6d3 1835 OMAP4_GPIO_SYSCONFIG);
3f1686a9 1836 __raw_writel(0x00000000, bank->base +
78a1a6d3 1837 OMAP4_GPIO_DEBOUNCENABLE);
3f1686a9
TL		 1838 /*
1839 * Initialize interface clock ungated,
1840 * module enabled
1841 */
1842 __raw_writel(0, bank->base + OMAP4_GPIO_CTRL);
1843 } else {
1844 __raw_writel(0x00000000, bank->base +
1845 OMAP24XX_GPIO_IRQENABLE1);
1846 __raw_writel(0xffffffff, bank->base +
1847 OMAP24XX_GPIO_IRQSTATUS1);
1848 __raw_writew(0x0015, bank->base +
1849 OMAP24XX_GPIO_SYSCONFIG);
1850 __raw_writel(0x00000000, bank->base +
1851 OMAP24XX_GPIO_DEBOUNCE_EN);
1852
1853 /*
1854 * Initialize interface clock ungated,
1855 * module enabled
1856 */
1857 __raw_writel(0, bank->base +
1858 OMAP24XX_GPIO_CTRL);
1859 }
a118b5f3
TK		 1860 if (cpu_is_omap24xx() &&
1861 i < ARRAY_SIZE(non_wakeup_gpios))
3ac4fa99 1862 bank->non_wakeup_gpios = non_wakeup_gpios[i];
92105bb7
TL		 1863 gpio_count = 32;
1864 }
5e1c5ff4 1865#endif
058af1ea
C		 1866
1867 bank->mod_usage = 0;
52e31344
DB		 1868 /* REVISIT eventually switch from OMAP-specific gpio structs
1869 * over to the generic ones
1870 */
3ff164e1
JN		 1871 bank->chip.request = omap_gpio_request;
1872 bank->chip.free = omap_gpio_free;
52e31344
DB		 1873 bank->chip.direction_input = gpio_input;
1874 bank->chip.get = gpio_get;
1875 bank->chip.direction_output = gpio_output;
1876 bank->chip.set = gpio_set;
a007b709 1877 bank->chip.to_irq = gpio_2irq;
52e31344
DB		 1878 if (bank_is_mpuio(bank)) {
1879 bank->chip.label = "mpuio";
69114a47 1880#ifdef CONFIG_ARCH_OMAP16XX
d8f388d8
DB		 1881 bank->chip.dev = &omap_mpuio_device.dev;
1882#endif
52e31344
DB		 1883 bank->chip.base = OMAP_MPUIO(0);
1884 } else {
1885 bank->chip.label = "gpio";
1886 bank->chip.base = gpio;
1887 gpio += gpio_count;
1888 }
1889 bank->chip.ngpio = gpio_count;
1890
1891 gpiochip_add(&bank->chip);
1892
5e1c5ff4
TL		 1893 for (j = bank->virtual_irq_start;
1894 j < bank->virtual_irq_start + gpio_count; j++) {
8ba55c5c 1895 lockdep_set_class(&irq_desc[j].lock, &gpio_lock_class);
58781016 1896 set_irq_chip_data(j, bank);
e5c56ed3 1897 if (bank_is_mpuio(bank))
5e1c5ff4
TL		 1898 set_irq_chip(j, &mpuio_irq_chip);
1899 else
1900 set_irq_chip(j, &gpio_irq_chip);
10dd5ce2 1901 set_irq_handler(j, handle_simple_irq);
5e1c5ff4
TL		 1902 set_irq_flags(j, IRQF_VALID);
1903 }
1904 set_irq_chained_handler(bank->irq, gpio_irq_handler);
1905 set_irq_data(bank->irq, bank);
89db9482 1906
44169075 1907 if (cpu_is_omap34xx() || cpu_is_omap44xx()) {
89db9482
JH		 1908 sprintf(clk_name, "gpio%d_dbck", i + 1);
1909 bank->dbck = clk_get(NULL, clk_name);
1910 if (IS_ERR(bank->dbck))
1911 printk(KERN_ERR "Could not get %s\n", clk_name);
1912 }
5e1c5ff4
TL		 1913 }
1914
1915 /* Enable system clock for GPIO module.
1916 * The CAM_CLK_CTRL *is* really the right place. */
92105bb7 1917 if (cpu_is_omap16xx())
5e1c5ff4
TL		 1918 omap_writel(omap_readl(ULPD_CAM_CLK_CTRL) | 0x04, ULPD_CAM_CLK_CTRL);
1919
14f1c3bf
JY		 1920 /* Enable autoidle for the OCP interface */
1921 if (cpu_is_omap24xx())
1922 omap_writel(1 << 0, 0x48019010);
5492fb1a
SMK		 1923 if (cpu_is_omap34xx())
1924 omap_writel(1 << 0, 0x48306814);
d11ac979 1925
9f7065da
TL		 1926 omap_gpio_show_rev();
1927
5e1c5ff4
TL		 1928 return 0;
1929}
1930
140455fa 1931#if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP2PLUS)
92105bb7
TL		 1932static int omap_gpio_suspend(struct sys_device *dev, pm_message_t mesg)
1933{
1934 int i;
1935
5492fb1a 1936 if (!cpu_class_is_omap2() && !cpu_is_omap16xx())
92105bb7
TL		 1937 return 0;
1938
1939 for (i = 0; i < gpio_bank_count; i++) {
1940 struct gpio_bank *bank = &gpio_bank[i];
1941 void __iomem *wake_status;
1942 void __iomem *wake_clear;
1943 void __iomem *wake_set;
a6472533 1944 unsigned long flags;
92105bb7
TL		 1945
1946 switch (bank->method) {
e5c56ed3 1947#ifdef CONFIG_ARCH_OMAP16XX
92105bb7
TL		 1948 case METHOD_GPIO_1610:
1949 wake_status = bank->base + OMAP1610_GPIO_WAKEUPENABLE;
1950 wake_clear = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
1951 wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA;
1952 break;
e5c56ed3 1953#endif
a8eb7ca0 1954#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
92105bb7 1955 case METHOD_GPIO_24XX:
723fdb78 1956 wake_status = bank->base + OMAP24XX_GPIO_WAKE_EN;
92105bb7
TL		 1957 wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
1958 wake_set = bank->base + OMAP24XX_GPIO_SETWKUENA;
1959 break;
78a1a6d3
SR		 1960#endif
1961#ifdef CONFIG_ARCH_OMAP4
3f1686a9 1962 case METHOD_GPIO_44XX:
78a1a6d3
SR		 1963 wake_status = bank->base + OMAP4_GPIO_IRQWAKEN0;
1964 wake_clear = bank->base + OMAP4_GPIO_IRQWAKEN0;
1965 wake_set = bank->base + OMAP4_GPIO_IRQWAKEN0;
1966 break;
e5c56ed3 1967#endif
92105bb7
TL		 1968 default:
1969 continue;
1970 }
1971
a6472533 1972 spin_lock_irqsave(&bank->lock, flags);
92105bb7
TL		 1973 bank->saved_wakeup = __raw_readl(wake_status);
1974 __raw_writel(0xffffffff, wake_clear);
1975 __raw_writel(bank->suspend_wakeup, wake_set);
a6472533 1976 spin_unlock_irqrestore(&bank->lock, flags);
92105bb7
TL		 1977 }
1978
1979 return 0;
1980}
1981
1982static int omap_gpio_resume(struct sys_device *dev)
1983{
1984 int i;
1985
723fdb78 1986 if (!cpu_class_is_omap2() && !cpu_is_omap16xx())
92105bb7
TL		 1987 return 0;
1988
1989 for (i = 0; i < gpio_bank_count; i++) {
1990 struct gpio_bank *bank = &gpio_bank[i];
1991 void __iomem *wake_clear;
1992 void __iomem *wake_set;
a6472533 1993 unsigned long flags;
92105bb7
TL		 1994
1995 switch (bank->method) {
e5c56ed3 1996#ifdef CONFIG_ARCH_OMAP16XX
92105bb7
TL		 1997 case METHOD_GPIO_1610:
1998 wake_clear = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
1999 wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA;
2000 break;
e5c56ed3 2001#endif
a8eb7ca0 2002#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
92105bb7 2003 case METHOD_GPIO_24XX:
0d9356cb
TL		 2004 wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
2005 wake_set = bank->base + OMAP24XX_GPIO_SETWKUENA;
92105bb7 2006 break;
78a1a6d3
SR		 2007#endif
2008#ifdef CONFIG_ARCH_OMAP4
3f1686a9 2009 case METHOD_GPIO_44XX:
78a1a6d3
SR		 2010 wake_clear = bank->base + OMAP4_GPIO_IRQWAKEN0;
2011 wake_set = bank->base + OMAP4_GPIO_IRQWAKEN0;
2012 break;
e5c56ed3 2013#endif
92105bb7
TL		 2014 default:
2015 continue;
2016 }
2017
a6472533 2018 spin_lock_irqsave(&bank->lock, flags);
92105bb7
TL		 2019 __raw_writel(0xffffffff, wake_clear);
2020 __raw_writel(bank->saved_wakeup, wake_set);
a6472533 2021 spin_unlock_irqrestore(&bank->lock, flags);
92105bb7
TL		 2022 }
2023
2024 return 0;
2025}
2026
2027static struct sysdev_class omap_gpio_sysclass = {
af5ca3f4 2028 .name = "gpio",
92105bb7
TL		 2029 .suspend = omap_gpio_suspend,
2030 .resume = omap_gpio_resume,
2031};
2032
2033static struct sys_device omap_gpio_device = {
2034 .id = 0,
2035 .cls = &omap_gpio_sysclass,
2036};
3ac4fa99
JY		 2037
2038#endif
2039
140455fa 2040#ifdef CONFIG_ARCH_OMAP2PLUS
3ac4fa99
JY		 2041
2042static int workaround_enabled;
2043
2044void omap2_gpio_prepare_for_retention(void)
2045{
2046 int i, c = 0;
a118b5f3 2047 int min = 0;
3ac4fa99 2048
a118b5f3
TK		 2049 if (cpu_is_omap34xx())
2050 min = 1;
3ac4fa99
JY		 2051 /* Remove triggering for all non-wakeup GPIOs. Otherwise spurious
2052 * IRQs will be generated. See OMAP2420 Errata item 1.101. */
a118b5f3 2053 for (i = min; i < gpio_bank_count; i++) {
3ac4fa99
JY		 2054 struct gpio_bank *bank = &gpio_bank[i];
2055 u32 l1, l2;
2056
2057 if (!(bank->enabled_non_wakeup_gpios))
2058 continue;
3f1686a9
TL		 2059
2060 if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
2061 bank->saved_datain = __raw_readl(bank->base +
2062 OMAP24XX_GPIO_DATAIN);
2063 l1 = __raw_readl(bank->base +
2064 OMAP24XX_GPIO_FALLINGDETECT);
2065 l2 = __raw_readl(bank->base +
2066 OMAP24XX_GPIO_RISINGDETECT);
2067 }
2068
2069 if (cpu_is_omap44xx()) {
2070 bank->saved_datain = __raw_readl(bank->base +
2071 OMAP4_GPIO_DATAIN);
2072 l1 = __raw_readl(bank->base +
2073 OMAP4_GPIO_FALLINGDETECT);
2074 l2 = __raw_readl(bank->base +
2075 OMAP4_GPIO_RISINGDETECT);
2076 }
2077
3ac4fa99
JY		 2078 bank->saved_fallingdetect = l1;
2079 bank->saved_risingdetect = l2;
2080 l1 &= ~bank->enabled_non_wakeup_gpios;
2081 l2 &= ~bank->enabled_non_wakeup_gpios;
3f1686a9
TL		 2082
2083 if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
2084 __raw_writel(l1, bank->base +
2085 OMAP24XX_GPIO_FALLINGDETECT);
2086 __raw_writel(l2, bank->base +
2087 OMAP24XX_GPIO_RISINGDETECT);
2088 }
2089
2090 if (cpu_is_omap44xx()) {
2091 __raw_writel(l1, bank->base + OMAP4_GPIO_FALLINGDETECT);
2092 __raw_writel(l2, bank->base + OMAP4_GPIO_RISINGDETECT);
2093 }
2094
3ac4fa99
JY		 2095 c++;
2096 }
2097 if (!c) {
2098 workaround_enabled = 0;
2099 return;
2100 }
2101 workaround_enabled = 1;
2102}
2103
2104void omap2_gpio_resume_after_retention(void)
2105{
2106 int i;
a118b5f3 2107 int min = 0;
3ac4fa99
JY		 2108
2109 if (!workaround_enabled)
2110 return;
a118b5f3
TK		 2111 if (cpu_is_omap34xx())
2112 min = 1;
2113 for (i = min; i < gpio_bank_count; i++) {
3ac4fa99 2114 struct gpio_bank *bank = &gpio_bank[i];
82dbb9d3 2115 u32 l, gen, gen0, gen1;
3ac4fa99
JY		 2116
2117 if (!(bank->enabled_non_wakeup_gpios))
2118 continue;
3f1686a9
TL		 2119
2120 if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
2121 __raw_writel(bank->saved_fallingdetect,
3ac4fa99 2122 bank->base + OMAP24XX_GPIO_FALLINGDETECT);
3f1686a9 2123 __raw_writel(bank->saved_risingdetect,
3ac4fa99 2124 bank->base + OMAP24XX_GPIO_RISINGDETECT);
3f1686a9
TL		 2125 l = __raw_readl(bank->base + OMAP24XX_GPIO_DATAIN);
2126 }
2127
2128 if (cpu_is_omap44xx()) {
2129 __raw_writel(bank->saved_fallingdetect,
78a1a6d3 2130 bank->base + OMAP4_GPIO_FALLINGDETECT);
3f1686a9 2131 __raw_writel(bank->saved_risingdetect,
78a1a6d3 2132 bank->base + OMAP4_GPIO_RISINGDETECT);
3f1686a9
TL		 2133 l = __raw_readl(bank->base + OMAP4_GPIO_DATAIN);
2134 }
2135
3ac4fa99
JY		 2136 /* Check if any of the non-wakeup interrupt GPIOs have changed
2137 * state. If so, generate an IRQ by software. This is
2138 * horribly racy, but it's the best we can do to work around
2139 * this silicon bug. */
3ac4fa99 2140 l ^= bank->saved_datain;
a118b5f3 2141 l &= bank->enabled_non_wakeup_gpios;
82dbb9d3
EN		 2142
2143 /*
2144 * No need to generate IRQs for the rising edge for gpio IRQs
2145 * configured with falling edge only; and vice versa.
2146 */
2147 gen0 = l & bank->saved_fallingdetect;
2148 gen0 &= bank->saved_datain;
2149
2150 gen1 = l & bank->saved_risingdetect;
2151 gen1 &= ~(bank->saved_datain);
2152
2153 /* FIXME: Consider GPIO IRQs with level detections properly! */
2154 gen = l & (~(bank->saved_fallingdetect) &
2155 ~(bank->saved_risingdetect));
2156 /* Consider all GPIO IRQs needed to be updated */
2157 gen |= gen0 | gen1;
2158
2159 if (gen) {
3ac4fa99 2160 u32 old0, old1;
3f1686a9 2161
f00d6497 2162 if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
3f1686a9
TL		 2163 old0 = __raw_readl(bank->base +
2164 OMAP24XX_GPIO_LEVELDETECT0);
2165 old1 = __raw_readl(bank->base +
2166 OMAP24XX_GPIO_LEVELDETECT1);
f00d6497 2167 __raw_writel(old0 | gen, bank->base +
82dbb9d3 2168 OMAP24XX_GPIO_LEVELDETECT0);
f00d6497 2169 __raw_writel(old1 | gen, bank->base +
82dbb9d3 2170 OMAP24XX_GPIO_LEVELDETECT1);
f00d6497 2171 __raw_writel(old0, bank->base +
3f1686a9 2172 OMAP24XX_GPIO_LEVELDETECT0);
f00d6497 2173 __raw_writel(old1, bank->base +
3f1686a9
TL		 2174 OMAP24XX_GPIO_LEVELDETECT1);
2175 }
2176
2177 if (cpu_is_omap44xx()) {
2178 old0 = __raw_readl(bank->base +
78a1a6d3 2179 OMAP4_GPIO_LEVELDETECT0);
3f1686a9 2180 old1 = __raw_readl(bank->base +
78a1a6d3 2181 OMAP4_GPIO_LEVELDETECT1);
3f1686a9 2182 __raw_writel(old0 | l, bank->base +
78a1a6d3 2183 OMAP4_GPIO_LEVELDETECT0);
3f1686a9 2184 __raw_writel(old1 | l, bank->base +
78a1a6d3 2185 OMAP4_GPIO_LEVELDETECT1);
3f1686a9 2186 __raw_writel(old0, bank->base +
78a1a6d3 2187 OMAP4_GPIO_LEVELDETECT0);
3f1686a9 2188 __raw_writel(old1, bank->base +
78a1a6d3 2189 OMAP4_GPIO_LEVELDETECT1);
3f1686a9 2190 }
3ac4fa99
JY		 2191 }
2192 }
2193
2194}
2195
92105bb7
TL		 2196#endif
2197
a8eb7ca0 2198#ifdef CONFIG_ARCH_OMAP3
40c670f0
RN		 2199/* save the registers of bank 2-6 */
2200void omap_gpio_save_context(void)
2201{
2202 int i;
2203
2204 /* saving banks from 2-6 only since GPIO1 is in WKUP */
2205 for (i = 1; i < gpio_bank_count; i++) {
2206 struct gpio_bank *bank = &gpio_bank[i];
2207 gpio_context[i].sysconfig =
2208 __raw_readl(bank->base + OMAP24XX_GPIO_SYSCONFIG);
2209 gpio_context[i].irqenable1 =
2210 __raw_readl(bank->base + OMAP24XX_GPIO_IRQENABLE1);
2211 gpio_context[i].irqenable2 =
2212 __raw_readl(bank->base + OMAP24XX_GPIO_IRQENABLE2);
2213 gpio_context[i].wake_en =
2214 __raw_readl(bank->base + OMAP24XX_GPIO_WAKE_EN);
2215 gpio_context[i].ctrl =
2216 __raw_readl(bank->base + OMAP24XX_GPIO_CTRL);
2217 gpio_context[i].oe =
2218 __raw_readl(bank->base + OMAP24XX_GPIO_OE);
2219 gpio_context[i].leveldetect0 =
2220 __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT0);
2221 gpio_context[i].leveldetect1 =
2222 __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT1);
2223 gpio_context[i].risingdetect =
2224 __raw_readl(bank->base + OMAP24XX_GPIO_RISINGDETECT);
2225 gpio_context[i].fallingdetect =
2226 __raw_readl(bank->base + OMAP24XX_GPIO_FALLINGDETECT);
2227 gpio_context[i].dataout =
2228 __raw_readl(bank->base + OMAP24XX_GPIO_DATAOUT);
2229 gpio_context[i].setwkuena =
2230 __raw_readl(bank->base + OMAP24XX_GPIO_SETWKUENA);
2231 gpio_context[i].setdataout =
2232 __raw_readl(bank->base + OMAP24XX_GPIO_SETDATAOUT);
2233 }
2234}
2235
2236/* restore the required registers of bank 2-6 */
2237void omap_gpio_restore_context(void)
2238{
2239 int i;
2240
2241 for (i = 1; i < gpio_bank_count; i++) {
2242 struct gpio_bank *bank = &gpio_bank[i];
2243 __raw_writel(gpio_context[i].sysconfig,
2244 bank->base + OMAP24XX_GPIO_SYSCONFIG);
2245 __raw_writel(gpio_context[i].irqenable1,
2246 bank->base + OMAP24XX_GPIO_IRQENABLE1);
2247 __raw_writel(gpio_context[i].irqenable2,
2248 bank->base + OMAP24XX_GPIO_IRQENABLE2);
2249 __raw_writel(gpio_context[i].wake_en,
2250 bank->base + OMAP24XX_GPIO_WAKE_EN);
2251 __raw_writel(gpio_context[i].ctrl,
2252 bank->base + OMAP24XX_GPIO_CTRL);
2253 __raw_writel(gpio_context[i].oe,
2254 bank->base + OMAP24XX_GPIO_OE);
2255 __raw_writel(gpio_context[i].leveldetect0,
2256 bank->base + OMAP24XX_GPIO_LEVELDETECT0);
2257 __raw_writel(gpio_context[i].leveldetect1,
2258 bank->base + OMAP24XX_GPIO_LEVELDETECT1);
2259 __raw_writel(gpio_context[i].risingdetect,
2260 bank->base + OMAP24XX_GPIO_RISINGDETECT);
2261 __raw_writel(gpio_context[i].fallingdetect,
2262 bank->base + OMAP24XX_GPIO_FALLINGDETECT);
2263 __raw_writel(gpio_context[i].dataout,
2264 bank->base + OMAP24XX_GPIO_DATAOUT);
2265 __raw_writel(gpio_context[i].setwkuena,
2266 bank->base + OMAP24XX_GPIO_SETWKUENA);
2267 __raw_writel(gpio_context[i].setdataout,
2268 bank->base + OMAP24XX_GPIO_SETDATAOUT);
2269 }
2270}
2271#endif
2272
5e1c5ff4
TL		 2273/*
2274 * This may get called early from board specific init
1a8bfa1e 2275 * for boards that have interrupts routed via FPGA.
5e1c5ff4 2276 */
277d58ef 2277int __init omap_gpio_init(void)
5e1c5ff4
TL		 2278{
2279 if (!initialized)
2280 return _omap_gpio_init();
2281 else
2282 return 0;
2283}
2284
92105bb7
TL		 2285static int __init omap_gpio_sysinit(void)
2286{
2287 int ret = 0;
2288
2289 if (!initialized)
2290 ret = _omap_gpio_init();
2291
11a78b79
DB		 2292 mpuio_init();
2293
140455fa 2294#if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP2PLUS)
5492fb1a 2295 if (cpu_is_omap16xx() || cpu_class_is_omap2()) {
92105bb7
TL		 2296 if (ret == 0) {
2297 ret = sysdev_class_register(&omap_gpio_sysclass);
2298 if (ret == 0)
2299 ret = sysdev_register(&omap_gpio_device);
2300 }
2301 }
2302#endif
2303
2304 return ret;
2305}
2306
92105bb7 2307arch_initcall(omap_gpio_sysinit);
b9772a22
DB		 2308
2309
2310#ifdef CONFIG_DEBUG_FS
2311
2312#include <linux/debugfs.h>
2313#include <linux/seq_file.h>
2314
b9772a22
DB		 2315static int dbg_gpio_show(struct seq_file *s, void *unused)
2316{
2317 unsigned i, j, gpio;
2318
2319 for (i = 0, gpio = 0; i < gpio_bank_count; i++) {
2320 struct gpio_bank *bank = gpio_bank + i;
2321 unsigned bankwidth = 16;
2322 u32 mask = 1;
2323
e5c56ed3 2324 if (bank_is_mpuio(bank))
b9772a22 2325 gpio = OMAP_MPUIO(0);
b718aa81 2326 else if (cpu_class_is_omap2() || cpu_is_omap7xx())
b9772a22
DB		 2327 bankwidth = 32;
2328
2329 for (j = 0; j < bankwidth; j++, gpio++, mask <<= 1) {
2330 unsigned irq, value, is_in, irqstat;
52e31344 2331 const char *label;
b9772a22 2332
52e31344
DB		 2333 label = gpiochip_is_requested(&bank->chip, j);
2334 if (!label)
b9772a22
DB		 2335 continue;
2336
2337 irq = bank->virtual_irq_start + j;
0b84b5ca 2338 value = gpio_get_value(gpio);
b9772a22
DB		 2339 is_in = gpio_is_input(bank, mask);
2340
e5c56ed3 2341 if (bank_is_mpuio(bank))
52e31344 2342 seq_printf(s, "MPUIO %2d ", j);
b9772a22 2343 else
52e31344 2344 seq_printf(s, "GPIO %3d ", gpio);
21c867f1 2345 seq_printf(s, "(%-20.20s): %s %s",
52e31344 2346 label,
b9772a22
DB		 2347 is_in ? "in " : "out",
2348 value ? "hi" : "lo");
2349
52e31344
DB		 2350/* FIXME for at least omap2, show pullup/pulldown state */
2351
b9772a22 2352 irqstat = irq_desc[irq].status;
140455fa 2353#if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP2PLUS)
b9772a22
DB		 2354 if (is_in && ((bank->suspend_wakeup & mask)
2355 || irqstat & IRQ_TYPE_SENSE_MASK)) {
2356 char *trigger = NULL;
2357
2358 switch (irqstat & IRQ_TYPE_SENSE_MASK) {
2359 case IRQ_TYPE_EDGE_FALLING:
2360 trigger = "falling";
2361 break;
2362 case IRQ_TYPE_EDGE_RISING:
2363 trigger = "rising";
2364 break;
2365 case IRQ_TYPE_EDGE_BOTH:
2366 trigger = "bothedge";
2367 break;
2368 case IRQ_TYPE_LEVEL_LOW:
2369 trigger = "low";
2370 break;
2371 case IRQ_TYPE_LEVEL_HIGH:
2372 trigger = "high";
2373 break;
2374 case IRQ_TYPE_NONE:
52e31344 2375 trigger = "(?)";
b9772a22
DB		 2376 break;
2377 }
52e31344 2378 seq_printf(s, ", irq-%d %-8s%s",
b9772a22
DB		 2379 irq, trigger,
2380 (bank->suspend_wakeup & mask)
2381 ? " wakeup" : "");
2382 }
3a26e331 2383#endif
b9772a22
DB		 2384 seq_printf(s, "\n");
2385 }
2386
e5c56ed3 2387 if (bank_is_mpuio(bank)) {
b9772a22
DB		 2388 seq_printf(s, "\n");
2389 gpio = 0;
2390 }
2391 }
2392 return 0;
2393}
2394
2395static int dbg_gpio_open(struct inode *inode, struct file *file)
2396{
e5c56ed3 2397 return single_open(file, dbg_gpio_show, &inode->i_private);
b9772a22
DB		 2398}
2399
2400static const struct file_operations debug_fops = {
2401 .open = dbg_gpio_open,
2402 .read = seq_read,
2403 .llseek = seq_lseek,
2404 .release = single_release,
2405};
2406
2407static int __init omap_gpio_debuginit(void)
2408{
e5c56ed3
DB		 2409 (void) debugfs_create_file("omap_gpio", S_IRUGO,
2410 NULL, NULL, &debug_fops);
b9772a22
DB		 2411 return 0;
2412}
2413late_initcall(omap_gpio_debuginit);
2414#endif
Linux 6.x block layer and io_uring tree(s)