Commit | Line | Data |
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5e1c5ff4 TL |
1 | /* |
2 | * linux/arch/arm/plat-omap/gpio.c | |
3 | * | |
4 | * Support functions for OMAP GPIO | |
5 | * | |
92105bb7 | 6 | * Copyright (C) 2003-2005 Nokia Corporation |
96de0e25 | 7 | * Written by Juha Yrjölä <juha.yrjola@nokia.com> |
5e1c5ff4 TL |
8 | * |
9 | * This program is free software; you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License version 2 as | |
11 | * published by the Free Software Foundation. | |
12 | */ | |
13 | ||
5e1c5ff4 TL |
14 | #include <linux/init.h> |
15 | #include <linux/module.h> | |
5e1c5ff4 | 16 | #include <linux/interrupt.h> |
92105bb7 TL |
17 | #include <linux/sysdev.h> |
18 | #include <linux/err.h> | |
f8ce2547 | 19 | #include <linux/clk.h> |
5e1c5ff4 TL |
20 | |
21 | #include <asm/hardware.h> | |
22 | #include <asm/irq.h> | |
23 | #include <asm/arch/irqs.h> | |
24 | #include <asm/arch/gpio.h> | |
25 | #include <asm/mach/irq.h> | |
26 | ||
27 | #include <asm/io.h> | |
28 | ||
29 | /* | |
30 | * OMAP1510 GPIO registers | |
31 | */ | |
92105bb7 | 32 | #define OMAP1510_GPIO_BASE (void __iomem *)0xfffce000 |
5e1c5ff4 TL |
33 | #define OMAP1510_GPIO_DATA_INPUT 0x00 |
34 | #define OMAP1510_GPIO_DATA_OUTPUT 0x04 | |
35 | #define OMAP1510_GPIO_DIR_CONTROL 0x08 | |
36 | #define OMAP1510_GPIO_INT_CONTROL 0x0c | |
37 | #define OMAP1510_GPIO_INT_MASK 0x10 | |
38 | #define OMAP1510_GPIO_INT_STATUS 0x14 | |
39 | #define OMAP1510_GPIO_PIN_CONTROL 0x18 | |
40 | ||
41 | #define OMAP1510_IH_GPIO_BASE 64 | |
42 | ||
43 | /* | |
44 | * OMAP1610 specific GPIO registers | |
45 | */ | |
92105bb7 TL |
46 | #define OMAP1610_GPIO1_BASE (void __iomem *)0xfffbe400 |
47 | #define OMAP1610_GPIO2_BASE (void __iomem *)0xfffbec00 | |
48 | #define OMAP1610_GPIO3_BASE (void __iomem *)0xfffbb400 | |
49 | #define OMAP1610_GPIO4_BASE (void __iomem *)0xfffbbc00 | |
5e1c5ff4 TL |
50 | #define OMAP1610_GPIO_REVISION 0x0000 |
51 | #define OMAP1610_GPIO_SYSCONFIG 0x0010 | |
52 | #define OMAP1610_GPIO_SYSSTATUS 0x0014 | |
53 | #define OMAP1610_GPIO_IRQSTATUS1 0x0018 | |
54 | #define OMAP1610_GPIO_IRQENABLE1 0x001c | |
92105bb7 | 55 | #define OMAP1610_GPIO_WAKEUPENABLE 0x0028 |
5e1c5ff4 TL |
56 | #define OMAP1610_GPIO_DATAIN 0x002c |
57 | #define OMAP1610_GPIO_DATAOUT 0x0030 | |
58 | #define OMAP1610_GPIO_DIRECTION 0x0034 | |
59 | #define OMAP1610_GPIO_EDGE_CTRL1 0x0038 | |
60 | #define OMAP1610_GPIO_EDGE_CTRL2 0x003c | |
61 | #define OMAP1610_GPIO_CLEAR_IRQENABLE1 0x009c | |
92105bb7 | 62 | #define OMAP1610_GPIO_CLEAR_WAKEUPENA 0x00a8 |
5e1c5ff4 TL |
63 | #define OMAP1610_GPIO_CLEAR_DATAOUT 0x00b0 |
64 | #define OMAP1610_GPIO_SET_IRQENABLE1 0x00dc | |
92105bb7 | 65 | #define OMAP1610_GPIO_SET_WAKEUPENA 0x00e8 |
5e1c5ff4 TL |
66 | #define OMAP1610_GPIO_SET_DATAOUT 0x00f0 |
67 | ||
68 | /* | |
69 | * OMAP730 specific GPIO registers | |
70 | */ | |
92105bb7 TL |
71 | #define OMAP730_GPIO1_BASE (void __iomem *)0xfffbc000 |
72 | #define OMAP730_GPIO2_BASE (void __iomem *)0xfffbc800 | |
73 | #define OMAP730_GPIO3_BASE (void __iomem *)0xfffbd000 | |
74 | #define OMAP730_GPIO4_BASE (void __iomem *)0xfffbd800 | |
75 | #define OMAP730_GPIO5_BASE (void __iomem *)0xfffbe000 | |
76 | #define OMAP730_GPIO6_BASE (void __iomem *)0xfffbe800 | |
5e1c5ff4 TL |
77 | #define OMAP730_GPIO_DATA_INPUT 0x00 |
78 | #define OMAP730_GPIO_DATA_OUTPUT 0x04 | |
79 | #define OMAP730_GPIO_DIR_CONTROL 0x08 | |
80 | #define OMAP730_GPIO_INT_CONTROL 0x0c | |
81 | #define OMAP730_GPIO_INT_MASK 0x10 | |
82 | #define OMAP730_GPIO_INT_STATUS 0x14 | |
83 | ||
92105bb7 TL |
84 | /* |
85 | * omap24xx specific GPIO registers | |
86 | */ | |
56a25641 SMK |
87 | #define OMAP242X_GPIO1_BASE (void __iomem *)0x48018000 |
88 | #define OMAP242X_GPIO2_BASE (void __iomem *)0x4801a000 | |
89 | #define OMAP242X_GPIO3_BASE (void __iomem *)0x4801c000 | |
90 | #define OMAP242X_GPIO4_BASE (void __iomem *)0x4801e000 | |
91 | ||
92 | #define OMAP243X_GPIO1_BASE (void __iomem *)0x4900C000 | |
93 | #define OMAP243X_GPIO2_BASE (void __iomem *)0x4900E000 | |
94 | #define OMAP243X_GPIO3_BASE (void __iomem *)0x49010000 | |
95 | #define OMAP243X_GPIO4_BASE (void __iomem *)0x49012000 | |
96 | #define OMAP243X_GPIO5_BASE (void __iomem *)0x480B6000 | |
97 | ||
92105bb7 TL |
98 | #define OMAP24XX_GPIO_REVISION 0x0000 |
99 | #define OMAP24XX_GPIO_SYSCONFIG 0x0010 | |
100 | #define OMAP24XX_GPIO_SYSSTATUS 0x0014 | |
101 | #define OMAP24XX_GPIO_IRQSTATUS1 0x0018 | |
bee7930f HD |
102 | #define OMAP24XX_GPIO_IRQSTATUS2 0x0028 |
103 | #define OMAP24XX_GPIO_IRQENABLE2 0x002c | |
92105bb7 TL |
104 | #define OMAP24XX_GPIO_IRQENABLE1 0x001c |
105 | #define OMAP24XX_GPIO_CTRL 0x0030 | |
106 | #define OMAP24XX_GPIO_OE 0x0034 | |
107 | #define OMAP24XX_GPIO_DATAIN 0x0038 | |
108 | #define OMAP24XX_GPIO_DATAOUT 0x003c | |
109 | #define OMAP24XX_GPIO_LEVELDETECT0 0x0040 | |
110 | #define OMAP24XX_GPIO_LEVELDETECT1 0x0044 | |
111 | #define OMAP24XX_GPIO_RISINGDETECT 0x0048 | |
112 | #define OMAP24XX_GPIO_FALLINGDETECT 0x004c | |
5eb3bb9c KH |
113 | #define OMAP24XX_GPIO_DEBOUNCE_EN 0x0050 |
114 | #define OMAP24XX_GPIO_DEBOUNCE_VAL 0x0054 | |
92105bb7 TL |
115 | #define OMAP24XX_GPIO_CLEARIRQENABLE1 0x0060 |
116 | #define OMAP24XX_GPIO_SETIRQENABLE1 0x0064 | |
117 | #define OMAP24XX_GPIO_CLEARWKUENA 0x0080 | |
118 | #define OMAP24XX_GPIO_SETWKUENA 0x0084 | |
119 | #define OMAP24XX_GPIO_CLEARDATAOUT 0x0090 | |
120 | #define OMAP24XX_GPIO_SETDATAOUT 0x0094 | |
121 | ||
5492fb1a SMK |
122 | /* |
123 | * omap34xx specific GPIO registers | |
124 | */ | |
125 | ||
126 | #define OMAP34XX_GPIO1_BASE (void __iomem *)0x48310000 | |
127 | #define OMAP34XX_GPIO2_BASE (void __iomem *)0x49050000 | |
128 | #define OMAP34XX_GPIO3_BASE (void __iomem *)0x49052000 | |
129 | #define OMAP34XX_GPIO4_BASE (void __iomem *)0x49054000 | |
130 | #define OMAP34XX_GPIO5_BASE (void __iomem *)0x49056000 | |
131 | #define OMAP34XX_GPIO6_BASE (void __iomem *)0x49058000 | |
132 | ||
133 | ||
5e1c5ff4 | 134 | struct gpio_bank { |
92105bb7 | 135 | void __iomem *base; |
5e1c5ff4 TL |
136 | u16 irq; |
137 | u16 virtual_irq_start; | |
92105bb7 | 138 | int method; |
5e1c5ff4 | 139 | u32 reserved_map; |
5492fb1a | 140 | #if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) |
92105bb7 TL |
141 | u32 suspend_wakeup; |
142 | u32 saved_wakeup; | |
3ac4fa99 | 143 | #endif |
5492fb1a | 144 | #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) |
3ac4fa99 JY |
145 | u32 non_wakeup_gpios; |
146 | u32 enabled_non_wakeup_gpios; | |
147 | ||
148 | u32 saved_datain; | |
149 | u32 saved_fallingdetect; | |
150 | u32 saved_risingdetect; | |
151 | #endif | |
5e1c5ff4 TL |
152 | spinlock_t lock; |
153 | }; | |
154 | ||
155 | #define METHOD_MPUIO 0 | |
156 | #define METHOD_GPIO_1510 1 | |
157 | #define METHOD_GPIO_1610 2 | |
158 | #define METHOD_GPIO_730 3 | |
92105bb7 | 159 | #define METHOD_GPIO_24XX 4 |
5e1c5ff4 | 160 | |
92105bb7 | 161 | #ifdef CONFIG_ARCH_OMAP16XX |
5e1c5ff4 TL |
162 | static struct gpio_bank gpio_bank_1610[5] = { |
163 | { OMAP_MPUIO_BASE, INT_MPUIO, IH_MPUIO_BASE, METHOD_MPUIO}, | |
164 | { OMAP1610_GPIO1_BASE, INT_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_1610 }, | |
165 | { OMAP1610_GPIO2_BASE, INT_1610_GPIO_BANK2, IH_GPIO_BASE + 16, METHOD_GPIO_1610 }, | |
166 | { OMAP1610_GPIO3_BASE, INT_1610_GPIO_BANK3, IH_GPIO_BASE + 32, METHOD_GPIO_1610 }, | |
167 | { OMAP1610_GPIO4_BASE, INT_1610_GPIO_BANK4, IH_GPIO_BASE + 48, METHOD_GPIO_1610 }, | |
168 | }; | |
169 | #endif | |
170 | ||
1a8bfa1e | 171 | #ifdef CONFIG_ARCH_OMAP15XX |
5e1c5ff4 TL |
172 | static struct gpio_bank gpio_bank_1510[2] = { |
173 | { OMAP_MPUIO_BASE, INT_MPUIO, IH_MPUIO_BASE, METHOD_MPUIO }, | |
174 | { OMAP1510_GPIO_BASE, INT_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_1510 } | |
175 | }; | |
176 | #endif | |
177 | ||
178 | #ifdef CONFIG_ARCH_OMAP730 | |
179 | static struct gpio_bank gpio_bank_730[7] = { | |
180 | { OMAP_MPUIO_BASE, INT_730_MPUIO, IH_MPUIO_BASE, METHOD_MPUIO }, | |
181 | { OMAP730_GPIO1_BASE, INT_730_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_730 }, | |
182 | { OMAP730_GPIO2_BASE, INT_730_GPIO_BANK2, IH_GPIO_BASE + 32, METHOD_GPIO_730 }, | |
183 | { OMAP730_GPIO3_BASE, INT_730_GPIO_BANK3, IH_GPIO_BASE + 64, METHOD_GPIO_730 }, | |
184 | { OMAP730_GPIO4_BASE, INT_730_GPIO_BANK4, IH_GPIO_BASE + 96, METHOD_GPIO_730 }, | |
185 | { OMAP730_GPIO5_BASE, INT_730_GPIO_BANK5, IH_GPIO_BASE + 128, METHOD_GPIO_730 }, | |
186 | { OMAP730_GPIO6_BASE, INT_730_GPIO_BANK6, IH_GPIO_BASE + 160, METHOD_GPIO_730 }, | |
187 | }; | |
188 | #endif | |
189 | ||
92105bb7 | 190 | #ifdef CONFIG_ARCH_OMAP24XX |
56a25641 SMK |
191 | |
192 | static struct gpio_bank gpio_bank_242x[4] = { | |
193 | { OMAP242X_GPIO1_BASE, INT_24XX_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_24XX }, | |
194 | { OMAP242X_GPIO2_BASE, INT_24XX_GPIO_BANK2, IH_GPIO_BASE + 32, METHOD_GPIO_24XX }, | |
195 | { OMAP242X_GPIO3_BASE, INT_24XX_GPIO_BANK3, IH_GPIO_BASE + 64, METHOD_GPIO_24XX }, | |
196 | { OMAP242X_GPIO4_BASE, INT_24XX_GPIO_BANK4, IH_GPIO_BASE + 96, METHOD_GPIO_24XX }, | |
92105bb7 | 197 | }; |
56a25641 SMK |
198 | |
199 | static struct gpio_bank gpio_bank_243x[5] = { | |
200 | { OMAP243X_GPIO1_BASE, INT_24XX_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_24XX }, | |
201 | { OMAP243X_GPIO2_BASE, INT_24XX_GPIO_BANK2, IH_GPIO_BASE + 32, METHOD_GPIO_24XX }, | |
202 | { OMAP243X_GPIO3_BASE, INT_24XX_GPIO_BANK3, IH_GPIO_BASE + 64, METHOD_GPIO_24XX }, | |
203 | { OMAP243X_GPIO4_BASE, INT_24XX_GPIO_BANK4, IH_GPIO_BASE + 96, METHOD_GPIO_24XX }, | |
204 | { OMAP243X_GPIO5_BASE, INT_24XX_GPIO_BANK5, IH_GPIO_BASE + 128, METHOD_GPIO_24XX }, | |
205 | }; | |
206 | ||
92105bb7 TL |
207 | #endif |
208 | ||
5492fb1a SMK |
209 | #ifdef CONFIG_ARCH_OMAP34XX |
210 | static struct gpio_bank gpio_bank_34xx[6] = { | |
211 | { OMAP34XX_GPIO1_BASE, INT_34XX_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_24XX }, | |
212 | { OMAP34XX_GPIO2_BASE, INT_34XX_GPIO_BANK2, IH_GPIO_BASE + 32, METHOD_GPIO_24XX }, | |
213 | { OMAP34XX_GPIO3_BASE, INT_34XX_GPIO_BANK3, IH_GPIO_BASE + 64, METHOD_GPIO_24XX }, | |
214 | { OMAP34XX_GPIO4_BASE, INT_34XX_GPIO_BANK4, IH_GPIO_BASE + 96, METHOD_GPIO_24XX }, | |
215 | { OMAP34XX_GPIO5_BASE, INT_34XX_GPIO_BANK5, IH_GPIO_BASE + 128, METHOD_GPIO_24XX }, | |
216 | { OMAP34XX_GPIO6_BASE, INT_34XX_GPIO_BANK6, IH_GPIO_BASE + 160, METHOD_GPIO_24XX }, | |
217 | }; | |
218 | ||
219 | #endif | |
220 | ||
5e1c5ff4 TL |
221 | static struct gpio_bank *gpio_bank; |
222 | static int gpio_bank_count; | |
223 | ||
224 | static inline struct gpio_bank *get_gpio_bank(int gpio) | |
225 | { | |
6e60e79a | 226 | if (cpu_is_omap15xx()) { |
5e1c5ff4 TL |
227 | if (OMAP_GPIO_IS_MPUIO(gpio)) |
228 | return &gpio_bank[0]; | |
229 | return &gpio_bank[1]; | |
230 | } | |
5e1c5ff4 TL |
231 | if (cpu_is_omap16xx()) { |
232 | if (OMAP_GPIO_IS_MPUIO(gpio)) | |
233 | return &gpio_bank[0]; | |
234 | return &gpio_bank[1 + (gpio >> 4)]; | |
235 | } | |
5e1c5ff4 TL |
236 | if (cpu_is_omap730()) { |
237 | if (OMAP_GPIO_IS_MPUIO(gpio)) | |
238 | return &gpio_bank[0]; | |
239 | return &gpio_bank[1 + (gpio >> 5)]; | |
240 | } | |
92105bb7 TL |
241 | if (cpu_is_omap24xx()) |
242 | return &gpio_bank[gpio >> 5]; | |
5492fb1a SMK |
243 | if (cpu_is_omap34xx()) |
244 | return &gpio_bank[gpio >> 5]; | |
5e1c5ff4 TL |
245 | } |
246 | ||
247 | static inline int get_gpio_index(int gpio) | |
248 | { | |
249 | if (cpu_is_omap730()) | |
250 | return gpio & 0x1f; | |
92105bb7 TL |
251 | if (cpu_is_omap24xx()) |
252 | return gpio & 0x1f; | |
5492fb1a SMK |
253 | if (cpu_is_omap34xx()) |
254 | return gpio & 0x1f; | |
92105bb7 | 255 | return gpio & 0x0f; |
5e1c5ff4 TL |
256 | } |
257 | ||
258 | static inline int gpio_valid(int gpio) | |
259 | { | |
260 | if (gpio < 0) | |
261 | return -1; | |
d11ac979 | 262 | if (cpu_class_is_omap1() && OMAP_GPIO_IS_MPUIO(gpio)) { |
193e68be | 263 | if (gpio >= OMAP_MAX_GPIO_LINES + 16) |
5e1c5ff4 TL |
264 | return -1; |
265 | return 0; | |
266 | } | |
6e60e79a | 267 | if (cpu_is_omap15xx() && gpio < 16) |
5e1c5ff4 | 268 | return 0; |
5e1c5ff4 TL |
269 | if ((cpu_is_omap16xx()) && gpio < 64) |
270 | return 0; | |
5e1c5ff4 TL |
271 | if (cpu_is_omap730() && gpio < 192) |
272 | return 0; | |
92105bb7 TL |
273 | if (cpu_is_omap24xx() && gpio < 128) |
274 | return 0; | |
5492fb1a SMK |
275 | if (cpu_is_omap34xx() && gpio < 160) |
276 | return 0; | |
5e1c5ff4 TL |
277 | return -1; |
278 | } | |
279 | ||
280 | static int check_gpio(int gpio) | |
281 | { | |
282 | if (unlikely(gpio_valid(gpio)) < 0) { | |
283 | printk(KERN_ERR "omap-gpio: invalid GPIO %d\n", gpio); | |
284 | dump_stack(); | |
285 | return -1; | |
286 | } | |
287 | return 0; | |
288 | } | |
289 | ||
290 | static void _set_gpio_direction(struct gpio_bank *bank, int gpio, int is_input) | |
291 | { | |
92105bb7 | 292 | void __iomem *reg = bank->base; |
5e1c5ff4 TL |
293 | u32 l; |
294 | ||
295 | switch (bank->method) { | |
e5c56ed3 | 296 | #ifdef CONFIG_ARCH_OMAP1 |
5e1c5ff4 TL |
297 | case METHOD_MPUIO: |
298 | reg += OMAP_MPUIO_IO_CNTL; | |
299 | break; | |
e5c56ed3 DB |
300 | #endif |
301 | #ifdef CONFIG_ARCH_OMAP15XX | |
5e1c5ff4 TL |
302 | case METHOD_GPIO_1510: |
303 | reg += OMAP1510_GPIO_DIR_CONTROL; | |
304 | break; | |
e5c56ed3 DB |
305 | #endif |
306 | #ifdef CONFIG_ARCH_OMAP16XX | |
5e1c5ff4 TL |
307 | case METHOD_GPIO_1610: |
308 | reg += OMAP1610_GPIO_DIRECTION; | |
309 | break; | |
e5c56ed3 DB |
310 | #endif |
311 | #ifdef CONFIG_ARCH_OMAP730 | |
5e1c5ff4 TL |
312 | case METHOD_GPIO_730: |
313 | reg += OMAP730_GPIO_DIR_CONTROL; | |
314 | break; | |
e5c56ed3 | 315 | #endif |
5492fb1a | 316 | #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) |
92105bb7 TL |
317 | case METHOD_GPIO_24XX: |
318 | reg += OMAP24XX_GPIO_OE; | |
319 | break; | |
e5c56ed3 DB |
320 | #endif |
321 | default: | |
322 | WARN_ON(1); | |
323 | return; | |
5e1c5ff4 TL |
324 | } |
325 | l = __raw_readl(reg); | |
326 | if (is_input) | |
327 | l |= 1 << gpio; | |
328 | else | |
329 | l &= ~(1 << gpio); | |
330 | __raw_writel(l, reg); | |
331 | } | |
332 | ||
333 | void omap_set_gpio_direction(int gpio, int is_input) | |
334 | { | |
335 | struct gpio_bank *bank; | |
a6472533 | 336 | unsigned long flags; |
5e1c5ff4 TL |
337 | |
338 | if (check_gpio(gpio) < 0) | |
339 | return; | |
340 | bank = get_gpio_bank(gpio); | |
a6472533 | 341 | spin_lock_irqsave(&bank->lock, flags); |
5e1c5ff4 | 342 | _set_gpio_direction(bank, get_gpio_index(gpio), is_input); |
a6472533 | 343 | spin_unlock_irqrestore(&bank->lock, flags); |
5e1c5ff4 TL |
344 | } |
345 | ||
346 | static void _set_gpio_dataout(struct gpio_bank *bank, int gpio, int enable) | |
347 | { | |
92105bb7 | 348 | void __iomem *reg = bank->base; |
5e1c5ff4 TL |
349 | u32 l = 0; |
350 | ||
351 | switch (bank->method) { | |
e5c56ed3 | 352 | #ifdef CONFIG_ARCH_OMAP1 |
5e1c5ff4 TL |
353 | case METHOD_MPUIO: |
354 | reg += OMAP_MPUIO_OUTPUT; | |
355 | l = __raw_readl(reg); | |
356 | if (enable) | |
357 | l |= 1 << gpio; | |
358 | else | |
359 | l &= ~(1 << gpio); | |
360 | break; | |
e5c56ed3 DB |
361 | #endif |
362 | #ifdef CONFIG_ARCH_OMAP15XX | |
5e1c5ff4 TL |
363 | case METHOD_GPIO_1510: |
364 | reg += OMAP1510_GPIO_DATA_OUTPUT; | |
365 | l = __raw_readl(reg); | |
366 | if (enable) | |
367 | l |= 1 << gpio; | |
368 | else | |
369 | l &= ~(1 << gpio); | |
370 | break; | |
e5c56ed3 DB |
371 | #endif |
372 | #ifdef CONFIG_ARCH_OMAP16XX | |
5e1c5ff4 TL |
373 | case METHOD_GPIO_1610: |
374 | if (enable) | |
375 | reg += OMAP1610_GPIO_SET_DATAOUT; | |
376 | else | |
377 | reg += OMAP1610_GPIO_CLEAR_DATAOUT; | |
378 | l = 1 << gpio; | |
379 | break; | |
e5c56ed3 DB |
380 | #endif |
381 | #ifdef CONFIG_ARCH_OMAP730 | |
5e1c5ff4 TL |
382 | case METHOD_GPIO_730: |
383 | reg += OMAP730_GPIO_DATA_OUTPUT; | |
384 | l = __raw_readl(reg); | |
385 | if (enable) | |
386 | l |= 1 << gpio; | |
387 | else | |
388 | l &= ~(1 << gpio); | |
389 | break; | |
e5c56ed3 | 390 | #endif |
5492fb1a | 391 | #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) |
92105bb7 TL |
392 | case METHOD_GPIO_24XX: |
393 | if (enable) | |
394 | reg += OMAP24XX_GPIO_SETDATAOUT; | |
395 | else | |
396 | reg += OMAP24XX_GPIO_CLEARDATAOUT; | |
397 | l = 1 << gpio; | |
398 | break; | |
e5c56ed3 | 399 | #endif |
5e1c5ff4 | 400 | default: |
e5c56ed3 | 401 | WARN_ON(1); |
5e1c5ff4 TL |
402 | return; |
403 | } | |
404 | __raw_writel(l, reg); | |
405 | } | |
406 | ||
407 | void omap_set_gpio_dataout(int gpio, int enable) | |
408 | { | |
409 | struct gpio_bank *bank; | |
a6472533 | 410 | unsigned long flags; |
5e1c5ff4 TL |
411 | |
412 | if (check_gpio(gpio) < 0) | |
413 | return; | |
414 | bank = get_gpio_bank(gpio); | |
a6472533 | 415 | spin_lock_irqsave(&bank->lock, flags); |
5e1c5ff4 | 416 | _set_gpio_dataout(bank, get_gpio_index(gpio), enable); |
a6472533 | 417 | spin_unlock_irqrestore(&bank->lock, flags); |
5e1c5ff4 TL |
418 | } |
419 | ||
420 | int omap_get_gpio_datain(int gpio) | |
421 | { | |
422 | struct gpio_bank *bank; | |
92105bb7 | 423 | void __iomem *reg; |
5e1c5ff4 TL |
424 | |
425 | if (check_gpio(gpio) < 0) | |
e5c56ed3 | 426 | return -EINVAL; |
5e1c5ff4 TL |
427 | bank = get_gpio_bank(gpio); |
428 | reg = bank->base; | |
429 | switch (bank->method) { | |
e5c56ed3 | 430 | #ifdef CONFIG_ARCH_OMAP1 |
5e1c5ff4 TL |
431 | case METHOD_MPUIO: |
432 | reg += OMAP_MPUIO_INPUT_LATCH; | |
433 | break; | |
e5c56ed3 DB |
434 | #endif |
435 | #ifdef CONFIG_ARCH_OMAP15XX | |
5e1c5ff4 TL |
436 | case METHOD_GPIO_1510: |
437 | reg += OMAP1510_GPIO_DATA_INPUT; | |
438 | break; | |
e5c56ed3 DB |
439 | #endif |
440 | #ifdef CONFIG_ARCH_OMAP16XX | |
5e1c5ff4 TL |
441 | case METHOD_GPIO_1610: |
442 | reg += OMAP1610_GPIO_DATAIN; | |
443 | break; | |
e5c56ed3 DB |
444 | #endif |
445 | #ifdef CONFIG_ARCH_OMAP730 | |
5e1c5ff4 TL |
446 | case METHOD_GPIO_730: |
447 | reg += OMAP730_GPIO_DATA_INPUT; | |
448 | break; | |
e5c56ed3 | 449 | #endif |
5492fb1a | 450 | #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) |
92105bb7 TL |
451 | case METHOD_GPIO_24XX: |
452 | reg += OMAP24XX_GPIO_DATAIN; | |
453 | break; | |
e5c56ed3 | 454 | #endif |
5e1c5ff4 | 455 | default: |
e5c56ed3 | 456 | return -EINVAL; |
5e1c5ff4 | 457 | } |
92105bb7 TL |
458 | return (__raw_readl(reg) |
459 | & (1 << get_gpio_index(gpio))) != 0; | |
5e1c5ff4 TL |
460 | } |
461 | ||
92105bb7 TL |
462 | #define MOD_REG_BIT(reg, bit_mask, set) \ |
463 | do { \ | |
464 | int l = __raw_readl(base + reg); \ | |
465 | if (set) l |= bit_mask; \ | |
466 | else l &= ~bit_mask; \ | |
467 | __raw_writel(l, base + reg); \ | |
468 | } while(0) | |
469 | ||
5eb3bb9c KH |
470 | void omap_set_gpio_debounce(int gpio, int enable) |
471 | { | |
472 | struct gpio_bank *bank; | |
473 | void __iomem *reg; | |
474 | u32 val, l = 1 << get_gpio_index(gpio); | |
475 | ||
476 | if (cpu_class_is_omap1()) | |
477 | return; | |
478 | ||
479 | bank = get_gpio_bank(gpio); | |
480 | reg = bank->base; | |
481 | ||
482 | reg += OMAP24XX_GPIO_DEBOUNCE_EN; | |
483 | val = __raw_readl(reg); | |
484 | ||
485 | if (enable) | |
486 | val |= l; | |
487 | else | |
488 | val &= ~l; | |
489 | ||
490 | __raw_writel(val, reg); | |
491 | } | |
492 | EXPORT_SYMBOL(omap_set_gpio_debounce); | |
493 | ||
494 | void omap_set_gpio_debounce_time(int gpio, int enc_time) | |
495 | { | |
496 | struct gpio_bank *bank; | |
497 | void __iomem *reg; | |
498 | ||
499 | if (cpu_class_is_omap1()) | |
500 | return; | |
501 | ||
502 | bank = get_gpio_bank(gpio); | |
503 | reg = bank->base; | |
504 | ||
505 | enc_time &= 0xff; | |
506 | reg += OMAP24XX_GPIO_DEBOUNCE_VAL; | |
507 | __raw_writel(enc_time, reg); | |
508 | } | |
509 | EXPORT_SYMBOL(omap_set_gpio_debounce_time); | |
510 | ||
5492fb1a | 511 | #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) |
5eb3bb9c KH |
512 | static inline void set_24xx_gpio_triggering(struct gpio_bank *bank, int gpio, |
513 | int trigger) | |
5e1c5ff4 | 514 | { |
3ac4fa99 | 515 | void __iomem *base = bank->base; |
92105bb7 TL |
516 | u32 gpio_bit = 1 << gpio; |
517 | ||
518 | MOD_REG_BIT(OMAP24XX_GPIO_LEVELDETECT0, gpio_bit, | |
6e60e79a | 519 | trigger & __IRQT_LOWLVL); |
92105bb7 | 520 | MOD_REG_BIT(OMAP24XX_GPIO_LEVELDETECT1, gpio_bit, |
6e60e79a | 521 | trigger & __IRQT_HIGHLVL); |
92105bb7 | 522 | MOD_REG_BIT(OMAP24XX_GPIO_RISINGDETECT, gpio_bit, |
6e60e79a | 523 | trigger & __IRQT_RISEDGE); |
92105bb7 | 524 | MOD_REG_BIT(OMAP24XX_GPIO_FALLINGDETECT, gpio_bit, |
6e60e79a | 525 | trigger & __IRQT_FALEDGE); |
5eb3bb9c | 526 | |
3ac4fa99 JY |
527 | if (likely(!(bank->non_wakeup_gpios & gpio_bit))) { |
528 | if (trigger != 0) | |
5eb3bb9c KH |
529 | __raw_writel(1 << gpio, bank->base |
530 | + OMAP24XX_GPIO_SETWKUENA); | |
3ac4fa99 | 531 | else |
5eb3bb9c KH |
532 | __raw_writel(1 << gpio, bank->base |
533 | + OMAP24XX_GPIO_CLEARWKUENA); | |
3ac4fa99 JY |
534 | } else { |
535 | if (trigger != 0) | |
536 | bank->enabled_non_wakeup_gpios |= gpio_bit; | |
537 | else | |
538 | bank->enabled_non_wakeup_gpios &= ~gpio_bit; | |
539 | } | |
5eb3bb9c KH |
540 | |
541 | /* | |
542 | * FIXME: Possibly do 'set_irq_handler(j, handle_level_irq)' if only | |
543 | * level triggering requested. | |
544 | */ | |
92105bb7 | 545 | } |
3ac4fa99 | 546 | #endif |
92105bb7 TL |
547 | |
548 | static int _set_gpio_triggering(struct gpio_bank *bank, int gpio, int trigger) | |
549 | { | |
550 | void __iomem *reg = bank->base; | |
551 | u32 l = 0; | |
5e1c5ff4 TL |
552 | |
553 | switch (bank->method) { | |
e5c56ed3 | 554 | #ifdef CONFIG_ARCH_OMAP1 |
5e1c5ff4 TL |
555 | case METHOD_MPUIO: |
556 | reg += OMAP_MPUIO_GPIO_INT_EDGE; | |
557 | l = __raw_readl(reg); | |
6e60e79a | 558 | if (trigger & __IRQT_RISEDGE) |
5e1c5ff4 | 559 | l |= 1 << gpio; |
6e60e79a | 560 | else if (trigger & __IRQT_FALEDGE) |
5e1c5ff4 | 561 | l &= ~(1 << gpio); |
92105bb7 TL |
562 | else |
563 | goto bad; | |
5e1c5ff4 | 564 | break; |
e5c56ed3 DB |
565 | #endif |
566 | #ifdef CONFIG_ARCH_OMAP15XX | |
5e1c5ff4 TL |
567 | case METHOD_GPIO_1510: |
568 | reg += OMAP1510_GPIO_INT_CONTROL; | |
569 | l = __raw_readl(reg); | |
6e60e79a | 570 | if (trigger & __IRQT_RISEDGE) |
5e1c5ff4 | 571 | l |= 1 << gpio; |
6e60e79a | 572 | else if (trigger & __IRQT_FALEDGE) |
5e1c5ff4 | 573 | l &= ~(1 << gpio); |
92105bb7 TL |
574 | else |
575 | goto bad; | |
5e1c5ff4 | 576 | break; |
e5c56ed3 | 577 | #endif |
3ac4fa99 | 578 | #ifdef CONFIG_ARCH_OMAP16XX |
5e1c5ff4 | 579 | case METHOD_GPIO_1610: |
5e1c5ff4 TL |
580 | if (gpio & 0x08) |
581 | reg += OMAP1610_GPIO_EDGE_CTRL2; | |
582 | else | |
583 | reg += OMAP1610_GPIO_EDGE_CTRL1; | |
584 | gpio &= 0x07; | |
585 | l = __raw_readl(reg); | |
586 | l &= ~(3 << (gpio << 1)); | |
6e60e79a TL |
587 | if (trigger & __IRQT_RISEDGE) |
588 | l |= 2 << (gpio << 1); | |
589 | if (trigger & __IRQT_FALEDGE) | |
590 | l |= 1 << (gpio << 1); | |
3ac4fa99 JY |
591 | if (trigger) |
592 | /* Enable wake-up during idle for dynamic tick */ | |
593 | __raw_writel(1 << gpio, bank->base + OMAP1610_GPIO_SET_WAKEUPENA); | |
594 | else | |
595 | __raw_writel(1 << gpio, bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA); | |
5e1c5ff4 | 596 | break; |
3ac4fa99 JY |
597 | #endif |
598 | #ifdef CONFIG_ARCH_OMAP730 | |
5e1c5ff4 TL |
599 | case METHOD_GPIO_730: |
600 | reg += OMAP730_GPIO_INT_CONTROL; | |
601 | l = __raw_readl(reg); | |
6e60e79a | 602 | if (trigger & __IRQT_RISEDGE) |
5e1c5ff4 | 603 | l |= 1 << gpio; |
6e60e79a | 604 | else if (trigger & __IRQT_FALEDGE) |
5e1c5ff4 | 605 | l &= ~(1 << gpio); |
92105bb7 TL |
606 | else |
607 | goto bad; | |
608 | break; | |
3ac4fa99 | 609 | #endif |
5492fb1a | 610 | #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) |
92105bb7 | 611 | case METHOD_GPIO_24XX: |
3ac4fa99 | 612 | set_24xx_gpio_triggering(bank, gpio, trigger); |
5e1c5ff4 | 613 | break; |
3ac4fa99 | 614 | #endif |
5e1c5ff4 | 615 | default: |
92105bb7 | 616 | goto bad; |
5e1c5ff4 | 617 | } |
92105bb7 TL |
618 | __raw_writel(l, reg); |
619 | return 0; | |
620 | bad: | |
621 | return -EINVAL; | |
5e1c5ff4 TL |
622 | } |
623 | ||
92105bb7 | 624 | static int gpio_irq_type(unsigned irq, unsigned type) |
5e1c5ff4 TL |
625 | { |
626 | struct gpio_bank *bank; | |
92105bb7 TL |
627 | unsigned gpio; |
628 | int retval; | |
a6472533 | 629 | unsigned long flags; |
92105bb7 | 630 | |
5492fb1a | 631 | if (!cpu_class_is_omap2() && irq > IH_MPUIO_BASE) |
92105bb7 TL |
632 | gpio = OMAP_MPUIO(irq - IH_MPUIO_BASE); |
633 | else | |
634 | gpio = irq - IH_GPIO_BASE; | |
5e1c5ff4 TL |
635 | |
636 | if (check_gpio(gpio) < 0) | |
92105bb7 TL |
637 | return -EINVAL; |
638 | ||
e5c56ed3 | 639 | if (type & ~IRQ_TYPE_SENSE_MASK) |
6e60e79a | 640 | return -EINVAL; |
e5c56ed3 DB |
641 | |
642 | /* OMAP1 allows only only edge triggering */ | |
5492fb1a | 643 | if (!cpu_class_is_omap2() |
e5c56ed3 | 644 | && (type & (IRQ_TYPE_LEVEL_LOW|IRQ_TYPE_LEVEL_HIGH))) |
92105bb7 TL |
645 | return -EINVAL; |
646 | ||
58781016 | 647 | bank = get_irq_chip_data(irq); |
a6472533 | 648 | spin_lock_irqsave(&bank->lock, flags); |
92105bb7 | 649 | retval = _set_gpio_triggering(bank, get_gpio_index(gpio), type); |
b9772a22 DB |
650 | if (retval == 0) { |
651 | irq_desc[irq].status &= ~IRQ_TYPE_SENSE_MASK; | |
652 | irq_desc[irq].status |= type; | |
653 | } | |
a6472533 | 654 | spin_unlock_irqrestore(&bank->lock, flags); |
92105bb7 | 655 | return retval; |
5e1c5ff4 TL |
656 | } |
657 | ||
658 | static void _clear_gpio_irqbank(struct gpio_bank *bank, int gpio_mask) | |
659 | { | |
92105bb7 | 660 | void __iomem *reg = bank->base; |
5e1c5ff4 TL |
661 | |
662 | switch (bank->method) { | |
e5c56ed3 | 663 | #ifdef CONFIG_ARCH_OMAP1 |
5e1c5ff4 TL |
664 | case METHOD_MPUIO: |
665 | /* MPUIO irqstatus is reset by reading the status register, | |
666 | * so do nothing here */ | |
667 | return; | |
e5c56ed3 DB |
668 | #endif |
669 | #ifdef CONFIG_ARCH_OMAP15XX | |
5e1c5ff4 TL |
670 | case METHOD_GPIO_1510: |
671 | reg += OMAP1510_GPIO_INT_STATUS; | |
672 | break; | |
e5c56ed3 DB |
673 | #endif |
674 | #ifdef CONFIG_ARCH_OMAP16XX | |
5e1c5ff4 TL |
675 | case METHOD_GPIO_1610: |
676 | reg += OMAP1610_GPIO_IRQSTATUS1; | |
677 | break; | |
e5c56ed3 DB |
678 | #endif |
679 | #ifdef CONFIG_ARCH_OMAP730 | |
5e1c5ff4 TL |
680 | case METHOD_GPIO_730: |
681 | reg += OMAP730_GPIO_INT_STATUS; | |
682 | break; | |
e5c56ed3 | 683 | #endif |
5492fb1a | 684 | #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) |
92105bb7 TL |
685 | case METHOD_GPIO_24XX: |
686 | reg += OMAP24XX_GPIO_IRQSTATUS1; | |
687 | break; | |
e5c56ed3 | 688 | #endif |
5e1c5ff4 | 689 | default: |
e5c56ed3 | 690 | WARN_ON(1); |
5e1c5ff4 TL |
691 | return; |
692 | } | |
693 | __raw_writel(gpio_mask, reg); | |
bee7930f HD |
694 | |
695 | /* Workaround for clearing DSP GPIO interrupts to allow retention */ | |
5492fb1a SMK |
696 | #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) |
697 | if (cpu_is_omap24xx() || cpu_is_omap34xx()) | |
bee7930f | 698 | __raw_writel(gpio_mask, bank->base + OMAP24XX_GPIO_IRQSTATUS2); |
5492fb1a | 699 | #endif |
5e1c5ff4 TL |
700 | } |
701 | ||
702 | static inline void _clear_gpio_irqstatus(struct gpio_bank *bank, int gpio) | |
703 | { | |
704 | _clear_gpio_irqbank(bank, 1 << get_gpio_index(gpio)); | |
705 | } | |
706 | ||
ea6dedd7 ID |
707 | static u32 _get_gpio_irqbank_mask(struct gpio_bank *bank) |
708 | { | |
709 | void __iomem *reg = bank->base; | |
99c47707 ID |
710 | int inv = 0; |
711 | u32 l; | |
712 | u32 mask; | |
ea6dedd7 ID |
713 | |
714 | switch (bank->method) { | |
e5c56ed3 | 715 | #ifdef CONFIG_ARCH_OMAP1 |
ea6dedd7 ID |
716 | case METHOD_MPUIO: |
717 | reg += OMAP_MPUIO_GPIO_MASKIT; | |
99c47707 ID |
718 | mask = 0xffff; |
719 | inv = 1; | |
ea6dedd7 | 720 | break; |
e5c56ed3 DB |
721 | #endif |
722 | #ifdef CONFIG_ARCH_OMAP15XX | |
ea6dedd7 ID |
723 | case METHOD_GPIO_1510: |
724 | reg += OMAP1510_GPIO_INT_MASK; | |
99c47707 ID |
725 | mask = 0xffff; |
726 | inv = 1; | |
ea6dedd7 | 727 | break; |
e5c56ed3 DB |
728 | #endif |
729 | #ifdef CONFIG_ARCH_OMAP16XX | |
ea6dedd7 ID |
730 | case METHOD_GPIO_1610: |
731 | reg += OMAP1610_GPIO_IRQENABLE1; | |
99c47707 | 732 | mask = 0xffff; |
ea6dedd7 | 733 | break; |
e5c56ed3 DB |
734 | #endif |
735 | #ifdef CONFIG_ARCH_OMAP730 | |
ea6dedd7 ID |
736 | case METHOD_GPIO_730: |
737 | reg += OMAP730_GPIO_INT_MASK; | |
99c47707 ID |
738 | mask = 0xffffffff; |
739 | inv = 1; | |
ea6dedd7 | 740 | break; |
e5c56ed3 | 741 | #endif |
5492fb1a | 742 | #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) |
ea6dedd7 ID |
743 | case METHOD_GPIO_24XX: |
744 | reg += OMAP24XX_GPIO_IRQENABLE1; | |
99c47707 | 745 | mask = 0xffffffff; |
ea6dedd7 | 746 | break; |
e5c56ed3 | 747 | #endif |
ea6dedd7 | 748 | default: |
e5c56ed3 | 749 | WARN_ON(1); |
ea6dedd7 ID |
750 | return 0; |
751 | } | |
752 | ||
99c47707 ID |
753 | l = __raw_readl(reg); |
754 | if (inv) | |
755 | l = ~l; | |
756 | l &= mask; | |
757 | return l; | |
ea6dedd7 ID |
758 | } |
759 | ||
5e1c5ff4 TL |
760 | static void _enable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask, int enable) |
761 | { | |
92105bb7 | 762 | void __iomem *reg = bank->base; |
5e1c5ff4 TL |
763 | u32 l; |
764 | ||
765 | switch (bank->method) { | |
e5c56ed3 | 766 | #ifdef CONFIG_ARCH_OMAP1 |
5e1c5ff4 TL |
767 | case METHOD_MPUIO: |
768 | reg += OMAP_MPUIO_GPIO_MASKIT; | |
769 | l = __raw_readl(reg); | |
770 | if (enable) | |
771 | l &= ~(gpio_mask); | |
772 | else | |
773 | l |= gpio_mask; | |
774 | break; | |
e5c56ed3 DB |
775 | #endif |
776 | #ifdef CONFIG_ARCH_OMAP15XX | |
5e1c5ff4 TL |
777 | case METHOD_GPIO_1510: |
778 | reg += OMAP1510_GPIO_INT_MASK; | |
779 | l = __raw_readl(reg); | |
780 | if (enable) | |
781 | l &= ~(gpio_mask); | |
782 | else | |
783 | l |= gpio_mask; | |
784 | break; | |
e5c56ed3 DB |
785 | #endif |
786 | #ifdef CONFIG_ARCH_OMAP16XX | |
5e1c5ff4 TL |
787 | case METHOD_GPIO_1610: |
788 | if (enable) | |
789 | reg += OMAP1610_GPIO_SET_IRQENABLE1; | |
790 | else | |
791 | reg += OMAP1610_GPIO_CLEAR_IRQENABLE1; | |
792 | l = gpio_mask; | |
793 | break; | |
e5c56ed3 DB |
794 | #endif |
795 | #ifdef CONFIG_ARCH_OMAP730 | |
5e1c5ff4 TL |
796 | case METHOD_GPIO_730: |
797 | reg += OMAP730_GPIO_INT_MASK; | |
798 | l = __raw_readl(reg); | |
799 | if (enable) | |
800 | l &= ~(gpio_mask); | |
801 | else | |
802 | l |= gpio_mask; | |
803 | break; | |
e5c56ed3 | 804 | #endif |
5492fb1a | 805 | #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) |
92105bb7 TL |
806 | case METHOD_GPIO_24XX: |
807 | if (enable) | |
808 | reg += OMAP24XX_GPIO_SETIRQENABLE1; | |
809 | else | |
810 | reg += OMAP24XX_GPIO_CLEARIRQENABLE1; | |
811 | l = gpio_mask; | |
812 | break; | |
e5c56ed3 | 813 | #endif |
5e1c5ff4 | 814 | default: |
e5c56ed3 | 815 | WARN_ON(1); |
5e1c5ff4 TL |
816 | return; |
817 | } | |
818 | __raw_writel(l, reg); | |
819 | } | |
820 | ||
821 | static inline void _set_gpio_irqenable(struct gpio_bank *bank, int gpio, int enable) | |
822 | { | |
823 | _enable_gpio_irqbank(bank, 1 << get_gpio_index(gpio), enable); | |
824 | } | |
825 | ||
92105bb7 TL |
826 | /* |
827 | * Note that ENAWAKEUP needs to be enabled in GPIO_SYSCONFIG register. | |
828 | * 1510 does not seem to have a wake-up register. If JTAG is connected | |
829 | * to the target, system will wake up always on GPIO events. While | |
830 | * system is running all registered GPIO interrupts need to have wake-up | |
831 | * enabled. When system is suspended, only selected GPIO interrupts need | |
832 | * to have wake-up enabled. | |
833 | */ | |
834 | static int _set_gpio_wakeup(struct gpio_bank *bank, int gpio, int enable) | |
835 | { | |
a6472533 DB |
836 | unsigned long flags; |
837 | ||
92105bb7 | 838 | switch (bank->method) { |
3ac4fa99 | 839 | #ifdef CONFIG_ARCH_OMAP16XX |
11a78b79 | 840 | case METHOD_MPUIO: |
92105bb7 | 841 | case METHOD_GPIO_1610: |
a6472533 | 842 | spin_lock_irqsave(&bank->lock, flags); |
11a78b79 | 843 | if (enable) { |
92105bb7 | 844 | bank->suspend_wakeup |= (1 << gpio); |
11a78b79 DB |
845 | enable_irq_wake(bank->irq); |
846 | } else { | |
847 | disable_irq_wake(bank->irq); | |
92105bb7 | 848 | bank->suspend_wakeup &= ~(1 << gpio); |
11a78b79 | 849 | } |
a6472533 | 850 | spin_unlock_irqrestore(&bank->lock, flags); |
92105bb7 | 851 | return 0; |
3ac4fa99 | 852 | #endif |
5492fb1a | 853 | #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) |
3ac4fa99 | 854 | case METHOD_GPIO_24XX: |
11a78b79 DB |
855 | if (bank->non_wakeup_gpios & (1 << gpio)) { |
856 | printk(KERN_ERR "Unable to modify wakeup on " | |
857 | "non-wakeup GPIO%d\n", | |
858 | (bank - gpio_bank) * 32 + gpio); | |
859 | return -EINVAL; | |
860 | } | |
a6472533 | 861 | spin_lock_irqsave(&bank->lock, flags); |
3ac4fa99 | 862 | if (enable) { |
3ac4fa99 | 863 | bank->suspend_wakeup |= (1 << gpio); |
11a78b79 DB |
864 | enable_irq_wake(bank->irq); |
865 | } else { | |
866 | disable_irq_wake(bank->irq); | |
3ac4fa99 | 867 | bank->suspend_wakeup &= ~(1 << gpio); |
11a78b79 | 868 | } |
a6472533 | 869 | spin_unlock_irqrestore(&bank->lock, flags); |
3ac4fa99 JY |
870 | return 0; |
871 | #endif | |
92105bb7 TL |
872 | default: |
873 | printk(KERN_ERR "Can't enable GPIO wakeup for method %i\n", | |
874 | bank->method); | |
875 | return -EINVAL; | |
876 | } | |
877 | } | |
878 | ||
4196dd6b TL |
879 | static void _reset_gpio(struct gpio_bank *bank, int gpio) |
880 | { | |
881 | _set_gpio_direction(bank, get_gpio_index(gpio), 1); | |
882 | _set_gpio_irqenable(bank, gpio, 0); | |
883 | _clear_gpio_irqstatus(bank, gpio); | |
884 | _set_gpio_triggering(bank, get_gpio_index(gpio), IRQT_NOEDGE); | |
885 | } | |
886 | ||
92105bb7 TL |
887 | /* Use disable_irq_wake() and enable_irq_wake() functions from drivers */ |
888 | static int gpio_wake_enable(unsigned int irq, unsigned int enable) | |
889 | { | |
890 | unsigned int gpio = irq - IH_GPIO_BASE; | |
891 | struct gpio_bank *bank; | |
892 | int retval; | |
893 | ||
894 | if (check_gpio(gpio) < 0) | |
895 | return -ENODEV; | |
58781016 | 896 | bank = get_irq_chip_data(irq); |
92105bb7 | 897 | retval = _set_gpio_wakeup(bank, get_gpio_index(gpio), enable); |
92105bb7 TL |
898 | |
899 | return retval; | |
900 | } | |
901 | ||
5e1c5ff4 TL |
902 | int omap_request_gpio(int gpio) |
903 | { | |
904 | struct gpio_bank *bank; | |
a6472533 | 905 | unsigned long flags; |
5e1c5ff4 TL |
906 | |
907 | if (check_gpio(gpio) < 0) | |
908 | return -EINVAL; | |
909 | ||
910 | bank = get_gpio_bank(gpio); | |
a6472533 | 911 | spin_lock_irqsave(&bank->lock, flags); |
5e1c5ff4 TL |
912 | if (unlikely(bank->reserved_map & (1 << get_gpio_index(gpio)))) { |
913 | printk(KERN_ERR "omap-gpio: GPIO %d is already reserved!\n", gpio); | |
914 | dump_stack(); | |
a6472533 | 915 | spin_unlock_irqrestore(&bank->lock, flags); |
5e1c5ff4 TL |
916 | return -1; |
917 | } | |
918 | bank->reserved_map |= (1 << get_gpio_index(gpio)); | |
92105bb7 | 919 | |
4196dd6b TL |
920 | /* Set trigger to none. You need to enable the desired trigger with |
921 | * request_irq() or set_irq_type(). | |
922 | */ | |
92105bb7 TL |
923 | _set_gpio_triggering(bank, get_gpio_index(gpio), IRQT_NOEDGE); |
924 | ||
1a8bfa1e | 925 | #ifdef CONFIG_ARCH_OMAP15XX |
5e1c5ff4 | 926 | if (bank->method == METHOD_GPIO_1510) { |
92105bb7 | 927 | void __iomem *reg; |
5e1c5ff4 | 928 | |
92105bb7 | 929 | /* Claim the pin for MPU */ |
5e1c5ff4 TL |
930 | reg = bank->base + OMAP1510_GPIO_PIN_CONTROL; |
931 | __raw_writel(__raw_readl(reg) | (1 << get_gpio_index(gpio)), reg); | |
932 | } | |
933 | #endif | |
a6472533 | 934 | spin_unlock_irqrestore(&bank->lock, flags); |
5e1c5ff4 TL |
935 | |
936 | return 0; | |
937 | } | |
938 | ||
939 | void omap_free_gpio(int gpio) | |
940 | { | |
941 | struct gpio_bank *bank; | |
a6472533 | 942 | unsigned long flags; |
5e1c5ff4 TL |
943 | |
944 | if (check_gpio(gpio) < 0) | |
945 | return; | |
946 | bank = get_gpio_bank(gpio); | |
a6472533 | 947 | spin_lock_irqsave(&bank->lock, flags); |
5e1c5ff4 TL |
948 | if (unlikely(!(bank->reserved_map & (1 << get_gpio_index(gpio))))) { |
949 | printk(KERN_ERR "omap-gpio: GPIO %d wasn't reserved!\n", gpio); | |
950 | dump_stack(); | |
a6472533 | 951 | spin_unlock_irqrestore(&bank->lock, flags); |
5e1c5ff4 TL |
952 | return; |
953 | } | |
92105bb7 TL |
954 | #ifdef CONFIG_ARCH_OMAP16XX |
955 | if (bank->method == METHOD_GPIO_1610) { | |
956 | /* Disable wake-up during idle for dynamic tick */ | |
957 | void __iomem *reg = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA; | |
958 | __raw_writel(1 << get_gpio_index(gpio), reg); | |
959 | } | |
960 | #endif | |
5492fb1a | 961 | #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) |
92105bb7 TL |
962 | if (bank->method == METHOD_GPIO_24XX) { |
963 | /* Disable wake-up during idle for dynamic tick */ | |
964 | void __iomem *reg = bank->base + OMAP24XX_GPIO_CLEARWKUENA; | |
965 | __raw_writel(1 << get_gpio_index(gpio), reg); | |
966 | } | |
967 | #endif | |
5e1c5ff4 | 968 | bank->reserved_map &= ~(1 << get_gpio_index(gpio)); |
4196dd6b | 969 | _reset_gpio(bank, gpio); |
a6472533 | 970 | spin_unlock_irqrestore(&bank->lock, flags); |
5e1c5ff4 TL |
971 | } |
972 | ||
973 | /* | |
974 | * We need to unmask the GPIO bank interrupt as soon as possible to | |
975 | * avoid missing GPIO interrupts for other lines in the bank. | |
976 | * Then we need to mask-read-clear-unmask the triggered GPIO lines | |
977 | * in the bank to avoid missing nested interrupts for a GPIO line. | |
978 | * If we wait to unmask individual GPIO lines in the bank after the | |
979 | * line's interrupt handler has been run, we may miss some nested | |
980 | * interrupts. | |
981 | */ | |
10dd5ce2 | 982 | static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc) |
5e1c5ff4 | 983 | { |
92105bb7 | 984 | void __iomem *isr_reg = NULL; |
5e1c5ff4 TL |
985 | u32 isr; |
986 | unsigned int gpio_irq; | |
987 | struct gpio_bank *bank; | |
ea6dedd7 ID |
988 | u32 retrigger = 0; |
989 | int unmasked = 0; | |
5e1c5ff4 TL |
990 | |
991 | desc->chip->ack(irq); | |
992 | ||
418ca1f0 | 993 | bank = get_irq_data(irq); |
e5c56ed3 | 994 | #ifdef CONFIG_ARCH_OMAP1 |
5e1c5ff4 TL |
995 | if (bank->method == METHOD_MPUIO) |
996 | isr_reg = bank->base + OMAP_MPUIO_GPIO_INT; | |
e5c56ed3 | 997 | #endif |
1a8bfa1e | 998 | #ifdef CONFIG_ARCH_OMAP15XX |
5e1c5ff4 TL |
999 | if (bank->method == METHOD_GPIO_1510) |
1000 | isr_reg = bank->base + OMAP1510_GPIO_INT_STATUS; | |
1001 | #endif | |
1002 | #if defined(CONFIG_ARCH_OMAP16XX) | |
1003 | if (bank->method == METHOD_GPIO_1610) | |
1004 | isr_reg = bank->base + OMAP1610_GPIO_IRQSTATUS1; | |
1005 | #endif | |
1006 | #ifdef CONFIG_ARCH_OMAP730 | |
1007 | if (bank->method == METHOD_GPIO_730) | |
1008 | isr_reg = bank->base + OMAP730_GPIO_INT_STATUS; | |
1009 | #endif | |
5492fb1a | 1010 | #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) |
92105bb7 TL |
1011 | if (bank->method == METHOD_GPIO_24XX) |
1012 | isr_reg = bank->base + OMAP24XX_GPIO_IRQSTATUS1; | |
1013 | #endif | |
92105bb7 | 1014 | while(1) { |
6e60e79a | 1015 | u32 isr_saved, level_mask = 0; |
ea6dedd7 | 1016 | u32 enabled; |
6e60e79a | 1017 | |
ea6dedd7 ID |
1018 | enabled = _get_gpio_irqbank_mask(bank); |
1019 | isr_saved = isr = __raw_readl(isr_reg) & enabled; | |
6e60e79a TL |
1020 | |
1021 | if (cpu_is_omap15xx() && (bank->method == METHOD_MPUIO)) | |
1022 | isr &= 0x0000ffff; | |
1023 | ||
5492fb1a | 1024 | if (cpu_class_is_omap2()) { |
6e60e79a TL |
1025 | level_mask = |
1026 | __raw_readl(bank->base + | |
1027 | OMAP24XX_GPIO_LEVELDETECT0) | | |
1028 | __raw_readl(bank->base + | |
1029 | OMAP24XX_GPIO_LEVELDETECT1); | |
ea6dedd7 ID |
1030 | level_mask &= enabled; |
1031 | } | |
6e60e79a TL |
1032 | |
1033 | /* clear edge sensitive interrupts before handler(s) are | |
1034 | called so that we don't miss any interrupt occurred while | |
1035 | executing them */ | |
1036 | _enable_gpio_irqbank(bank, isr_saved & ~level_mask, 0); | |
1037 | _clear_gpio_irqbank(bank, isr_saved & ~level_mask); | |
1038 | _enable_gpio_irqbank(bank, isr_saved & ~level_mask, 1); | |
1039 | ||
1040 | /* if there is only edge sensitive GPIO pin interrupts | |
1041 | configured, we could unmask GPIO bank interrupt immediately */ | |
ea6dedd7 ID |
1042 | if (!level_mask && !unmasked) { |
1043 | unmasked = 1; | |
6e60e79a | 1044 | desc->chip->unmask(irq); |
ea6dedd7 | 1045 | } |
92105bb7 | 1046 | |
ea6dedd7 ID |
1047 | isr |= retrigger; |
1048 | retrigger = 0; | |
92105bb7 TL |
1049 | if (!isr) |
1050 | break; | |
1051 | ||
1052 | gpio_irq = bank->virtual_irq_start; | |
1053 | for (; isr != 0; isr >>= 1, gpio_irq++) { | |
10dd5ce2 | 1054 | struct irq_desc *d; |
ea6dedd7 | 1055 | int irq_mask; |
92105bb7 TL |
1056 | if (!(isr & 1)) |
1057 | continue; | |
1058 | d = irq_desc + gpio_irq; | |
ea6dedd7 ID |
1059 | /* Don't run the handler if it's already running |
1060 | * or was disabled lazely. | |
1061 | */ | |
29454dde TG |
1062 | if (unlikely((d->depth || |
1063 | (d->status & IRQ_INPROGRESS)))) { | |
ea6dedd7 ID |
1064 | irq_mask = 1 << |
1065 | (gpio_irq - bank->virtual_irq_start); | |
1066 | /* The unmasking will be done by | |
1067 | * enable_irq in case it is disabled or | |
1068 | * after returning from the handler if | |
1069 | * it's already running. | |
1070 | */ | |
1071 | _enable_gpio_irqbank(bank, irq_mask, 0); | |
29454dde | 1072 | if (!d->depth) { |
ea6dedd7 ID |
1073 | /* Level triggered interrupts |
1074 | * won't ever be reentered | |
1075 | */ | |
1076 | BUG_ON(level_mask & irq_mask); | |
29454dde | 1077 | d->status |= IRQ_PENDING; |
ea6dedd7 ID |
1078 | } |
1079 | continue; | |
1080 | } | |
29454dde | 1081 | |
0cd61b68 | 1082 | desc_handle_irq(gpio_irq, d); |
29454dde TG |
1083 | |
1084 | if (unlikely((d->status & IRQ_PENDING) && !d->depth)) { | |
ea6dedd7 ID |
1085 | irq_mask = 1 << |
1086 | (gpio_irq - bank->virtual_irq_start); | |
29454dde | 1087 | d->status &= ~IRQ_PENDING; |
ea6dedd7 ID |
1088 | _enable_gpio_irqbank(bank, irq_mask, 1); |
1089 | retrigger |= irq_mask; | |
1090 | } | |
92105bb7 | 1091 | } |
6e60e79a | 1092 | |
5492fb1a | 1093 | if (cpu_class_is_omap2()) { |
6e60e79a TL |
1094 | /* clear level sensitive interrupts after handler(s) */ |
1095 | _enable_gpio_irqbank(bank, isr_saved & level_mask, 0); | |
1096 | _clear_gpio_irqbank(bank, isr_saved & level_mask); | |
1097 | _enable_gpio_irqbank(bank, isr_saved & level_mask, 1); | |
1098 | } | |
1099 | ||
1a8bfa1e | 1100 | } |
ea6dedd7 ID |
1101 | /* if bank has any level sensitive GPIO pin interrupt |
1102 | configured, we must unmask the bank interrupt only after | |
1103 | handler(s) are executed in order to avoid spurious bank | |
1104 | interrupt */ | |
1105 | if (!unmasked) | |
1106 | desc->chip->unmask(irq); | |
1107 | ||
5e1c5ff4 TL |
1108 | } |
1109 | ||
4196dd6b TL |
1110 | static void gpio_irq_shutdown(unsigned int irq) |
1111 | { | |
1112 | unsigned int gpio = irq - IH_GPIO_BASE; | |
58781016 | 1113 | struct gpio_bank *bank = get_irq_chip_data(irq); |
4196dd6b TL |
1114 | |
1115 | _reset_gpio(bank, gpio); | |
1116 | } | |
1117 | ||
5e1c5ff4 TL |
1118 | static void gpio_ack_irq(unsigned int irq) |
1119 | { | |
1120 | unsigned int gpio = irq - IH_GPIO_BASE; | |
58781016 | 1121 | struct gpio_bank *bank = get_irq_chip_data(irq); |
5e1c5ff4 TL |
1122 | |
1123 | _clear_gpio_irqstatus(bank, gpio); | |
1124 | } | |
1125 | ||
1126 | static void gpio_mask_irq(unsigned int irq) | |
1127 | { | |
1128 | unsigned int gpio = irq - IH_GPIO_BASE; | |
58781016 | 1129 | struct gpio_bank *bank = get_irq_chip_data(irq); |
5e1c5ff4 TL |
1130 | |
1131 | _set_gpio_irqenable(bank, gpio, 0); | |
1132 | } | |
1133 | ||
1134 | static void gpio_unmask_irq(unsigned int irq) | |
1135 | { | |
1136 | unsigned int gpio = irq - IH_GPIO_BASE; | |
58781016 | 1137 | struct gpio_bank *bank = get_irq_chip_data(irq); |
5e1c5ff4 | 1138 | |
4de8c75b | 1139 | _set_gpio_irqenable(bank, gpio, 1); |
5e1c5ff4 TL |
1140 | } |
1141 | ||
e5c56ed3 DB |
1142 | static struct irq_chip gpio_irq_chip = { |
1143 | .name = "GPIO", | |
1144 | .shutdown = gpio_irq_shutdown, | |
1145 | .ack = gpio_ack_irq, | |
1146 | .mask = gpio_mask_irq, | |
1147 | .unmask = gpio_unmask_irq, | |
1148 | .set_type = gpio_irq_type, | |
1149 | .set_wake = gpio_wake_enable, | |
1150 | }; | |
1151 | ||
1152 | /*---------------------------------------------------------------------*/ | |
1153 | ||
1154 | #ifdef CONFIG_ARCH_OMAP1 | |
1155 | ||
1156 | /* MPUIO uses the always-on 32k clock */ | |
1157 | ||
5e1c5ff4 TL |
1158 | static void mpuio_ack_irq(unsigned int irq) |
1159 | { | |
1160 | /* The ISR is reset automatically, so do nothing here. */ | |
1161 | } | |
1162 | ||
1163 | static void mpuio_mask_irq(unsigned int irq) | |
1164 | { | |
1165 | unsigned int gpio = OMAP_MPUIO(irq - IH_MPUIO_BASE); | |
58781016 | 1166 | struct gpio_bank *bank = get_irq_chip_data(irq); |
5e1c5ff4 TL |
1167 | |
1168 | _set_gpio_irqenable(bank, gpio, 0); | |
1169 | } | |
1170 | ||
1171 | static void mpuio_unmask_irq(unsigned int irq) | |
1172 | { | |
1173 | unsigned int gpio = OMAP_MPUIO(irq - IH_MPUIO_BASE); | |
58781016 | 1174 | struct gpio_bank *bank = get_irq_chip_data(irq); |
5e1c5ff4 TL |
1175 | |
1176 | _set_gpio_irqenable(bank, gpio, 1); | |
1177 | } | |
1178 | ||
e5c56ed3 DB |
1179 | static struct irq_chip mpuio_irq_chip = { |
1180 | .name = "MPUIO", | |
1181 | .ack = mpuio_ack_irq, | |
1182 | .mask = mpuio_mask_irq, | |
1183 | .unmask = mpuio_unmask_irq, | |
92105bb7 | 1184 | .set_type = gpio_irq_type, |
11a78b79 DB |
1185 | #ifdef CONFIG_ARCH_OMAP16XX |
1186 | /* REVISIT: assuming only 16xx supports MPUIO wake events */ | |
1187 | .set_wake = gpio_wake_enable, | |
1188 | #endif | |
5e1c5ff4 TL |
1189 | }; |
1190 | ||
e5c56ed3 DB |
1191 | |
1192 | #define bank_is_mpuio(bank) ((bank)->method == METHOD_MPUIO) | |
1193 | ||
11a78b79 DB |
1194 | |
1195 | #ifdef CONFIG_ARCH_OMAP16XX | |
1196 | ||
1197 | #include <linux/platform_device.h> | |
1198 | ||
1199 | static int omap_mpuio_suspend_late(struct platform_device *pdev, pm_message_t mesg) | |
1200 | { | |
1201 | struct gpio_bank *bank = platform_get_drvdata(pdev); | |
1202 | void __iomem *mask_reg = bank->base + OMAP_MPUIO_GPIO_MASKIT; | |
a6472533 | 1203 | unsigned long flags; |
11a78b79 | 1204 | |
a6472533 | 1205 | spin_lock_irqsave(&bank->lock, flags); |
11a78b79 DB |
1206 | bank->saved_wakeup = __raw_readl(mask_reg); |
1207 | __raw_writel(0xffff & ~bank->suspend_wakeup, mask_reg); | |
a6472533 | 1208 | spin_unlock_irqrestore(&bank->lock, flags); |
11a78b79 DB |
1209 | |
1210 | return 0; | |
1211 | } | |
1212 | ||
1213 | static int omap_mpuio_resume_early(struct platform_device *pdev) | |
1214 | { | |
1215 | struct gpio_bank *bank = platform_get_drvdata(pdev); | |
1216 | void __iomem *mask_reg = bank->base + OMAP_MPUIO_GPIO_MASKIT; | |
a6472533 | 1217 | unsigned long flags; |
11a78b79 | 1218 | |
a6472533 | 1219 | spin_lock_irqsave(&bank->lock, flags); |
11a78b79 | 1220 | __raw_writel(bank->saved_wakeup, mask_reg); |
a6472533 | 1221 | spin_unlock_irqrestore(&bank->lock, flags); |
11a78b79 DB |
1222 | |
1223 | return 0; | |
1224 | } | |
1225 | ||
1226 | /* use platform_driver for this, now that there's no longer any | |
1227 | * point to sys_device (other than not disturbing old code). | |
1228 | */ | |
1229 | static struct platform_driver omap_mpuio_driver = { | |
1230 | .suspend_late = omap_mpuio_suspend_late, | |
1231 | .resume_early = omap_mpuio_resume_early, | |
1232 | .driver = { | |
1233 | .name = "mpuio", | |
1234 | }, | |
1235 | }; | |
1236 | ||
1237 | static struct platform_device omap_mpuio_device = { | |
1238 | .name = "mpuio", | |
1239 | .id = -1, | |
1240 | .dev = { | |
1241 | .driver = &omap_mpuio_driver.driver, | |
1242 | } | |
1243 | /* could list the /proc/iomem resources */ | |
1244 | }; | |
1245 | ||
1246 | static inline void mpuio_init(void) | |
1247 | { | |
fcf126d8 DB |
1248 | platform_set_drvdata(&omap_mpuio_device, &gpio_bank_1610[0]); |
1249 | ||
11a78b79 DB |
1250 | if (platform_driver_register(&omap_mpuio_driver) == 0) |
1251 | (void) platform_device_register(&omap_mpuio_device); | |
1252 | } | |
1253 | ||
1254 | #else | |
1255 | static inline void mpuio_init(void) {} | |
1256 | #endif /* 16xx */ | |
1257 | ||
e5c56ed3 DB |
1258 | #else |
1259 | ||
1260 | extern struct irq_chip mpuio_irq_chip; | |
1261 | ||
1262 | #define bank_is_mpuio(bank) 0 | |
11a78b79 | 1263 | static inline void mpuio_init(void) {} |
e5c56ed3 DB |
1264 | |
1265 | #endif | |
1266 | ||
1267 | /*---------------------------------------------------------------------*/ | |
5e1c5ff4 | 1268 | |
1a8bfa1e | 1269 | static int initialized; |
5492fb1a | 1270 | #if !defined(CONFIG_ARCH_OMAP3) |
1a8bfa1e | 1271 | static struct clk * gpio_ick; |
5492fb1a SMK |
1272 | #endif |
1273 | ||
1274 | #if defined(CONFIG_ARCH_OMAP2) | |
1a8bfa1e | 1275 | static struct clk * gpio_fck; |
5492fb1a | 1276 | #endif |
5e1c5ff4 | 1277 | |
5492fb1a | 1278 | #if defined(CONFIG_ARCH_OMAP2430) |
56a25641 SMK |
1279 | static struct clk * gpio5_ick; |
1280 | static struct clk * gpio5_fck; | |
1281 | #endif | |
1282 | ||
5492fb1a SMK |
1283 | #if defined(CONFIG_ARCH_OMAP3) |
1284 | static struct clk *gpio_fclks[OMAP34XX_NR_GPIOS]; | |
1285 | static struct clk *gpio_iclks[OMAP34XX_NR_GPIOS]; | |
1286 | #endif | |
1287 | ||
8ba55c5c DB |
1288 | /* This lock class tells lockdep that GPIO irqs are in a different |
1289 | * category than their parents, so it won't report false recursion. | |
1290 | */ | |
1291 | static struct lock_class_key gpio_lock_class; | |
1292 | ||
5e1c5ff4 TL |
1293 | static int __init _omap_gpio_init(void) |
1294 | { | |
1295 | int i; | |
1296 | struct gpio_bank *bank; | |
5492fb1a SMK |
1297 | #if defined(CONFIG_ARCH_OMAP3) |
1298 | char clk_name[11]; | |
1299 | #endif | |
5e1c5ff4 TL |
1300 | |
1301 | initialized = 1; | |
1302 | ||
5492fb1a | 1303 | #if defined(CONFIG_ARCH_OMAP1) |
6e60e79a | 1304 | if (cpu_is_omap15xx()) { |
1a8bfa1e TL |
1305 | gpio_ick = clk_get(NULL, "arm_gpio_ck"); |
1306 | if (IS_ERR(gpio_ick)) | |
92105bb7 TL |
1307 | printk("Could not get arm_gpio_ck\n"); |
1308 | else | |
30ff720b | 1309 | clk_enable(gpio_ick); |
1a8bfa1e | 1310 | } |
5492fb1a SMK |
1311 | #endif |
1312 | #if defined(CONFIG_ARCH_OMAP2) | |
1313 | if (cpu_class_is_omap2()) { | |
1a8bfa1e TL |
1314 | gpio_ick = clk_get(NULL, "gpios_ick"); |
1315 | if (IS_ERR(gpio_ick)) | |
1316 | printk("Could not get gpios_ick\n"); | |
1317 | else | |
30ff720b | 1318 | clk_enable(gpio_ick); |
1a8bfa1e | 1319 | gpio_fck = clk_get(NULL, "gpios_fck"); |
1630b52d | 1320 | if (IS_ERR(gpio_fck)) |
1a8bfa1e TL |
1321 | printk("Could not get gpios_fck\n"); |
1322 | else | |
30ff720b | 1323 | clk_enable(gpio_fck); |
56a25641 SMK |
1324 | |
1325 | /* | |
5492fb1a | 1326 | * On 2430 & 3430 GPIO 5 uses CORE L4 ICLK |
56a25641 | 1327 | */ |
5492fb1a | 1328 | #if defined(CONFIG_ARCH_OMAP2430) |
56a25641 SMK |
1329 | if (cpu_is_omap2430()) { |
1330 | gpio5_ick = clk_get(NULL, "gpio5_ick"); | |
1331 | if (IS_ERR(gpio5_ick)) | |
1332 | printk("Could not get gpio5_ick\n"); | |
1333 | else | |
1334 | clk_enable(gpio5_ick); | |
1335 | gpio5_fck = clk_get(NULL, "gpio5_fck"); | |
1336 | if (IS_ERR(gpio5_fck)) | |
1337 | printk("Could not get gpio5_fck\n"); | |
1338 | else | |
1339 | clk_enable(gpio5_fck); | |
1340 | } | |
1341 | #endif | |
5492fb1a SMK |
1342 | } |
1343 | #endif | |
1344 | ||
1345 | #if defined(CONFIG_ARCH_OMAP3) | |
1346 | if (cpu_is_omap34xx()) { | |
1347 | for (i = 0; i < OMAP34XX_NR_GPIOS; i++) { | |
1348 | sprintf(clk_name, "gpio%d_ick", i + 1); | |
1349 | gpio_iclks[i] = clk_get(NULL, clk_name); | |
1350 | if (IS_ERR(gpio_iclks[i])) | |
1351 | printk(KERN_ERR "Could not get %s\n", clk_name); | |
1352 | else | |
1353 | clk_enable(gpio_iclks[i]); | |
1354 | sprintf(clk_name, "gpio%d_fck", i + 1); | |
1355 | gpio_fclks[i] = clk_get(NULL, clk_name); | |
1356 | if (IS_ERR(gpio_fclks[i])) | |
1357 | printk(KERN_ERR "Could not get %s\n", clk_name); | |
1358 | else | |
1359 | clk_enable(gpio_fclks[i]); | |
1360 | } | |
1361 | } | |
1362 | #endif | |
1363 | ||
92105bb7 | 1364 | |
1a8bfa1e | 1365 | #ifdef CONFIG_ARCH_OMAP15XX |
6e60e79a | 1366 | if (cpu_is_omap15xx()) { |
5e1c5ff4 TL |
1367 | printk(KERN_INFO "OMAP1510 GPIO hardware\n"); |
1368 | gpio_bank_count = 2; | |
1369 | gpio_bank = gpio_bank_1510; | |
1370 | } | |
1371 | #endif | |
1372 | #if defined(CONFIG_ARCH_OMAP16XX) | |
1373 | if (cpu_is_omap16xx()) { | |
92105bb7 | 1374 | u32 rev; |
5e1c5ff4 TL |
1375 | |
1376 | gpio_bank_count = 5; | |
1377 | gpio_bank = gpio_bank_1610; | |
1378 | rev = omap_readw(gpio_bank[1].base + OMAP1610_GPIO_REVISION); | |
1379 | printk(KERN_INFO "OMAP GPIO hardware version %d.%d\n", | |
1380 | (rev >> 4) & 0x0f, rev & 0x0f); | |
1381 | } | |
1382 | #endif | |
1383 | #ifdef CONFIG_ARCH_OMAP730 | |
1384 | if (cpu_is_omap730()) { | |
1385 | printk(KERN_INFO "OMAP730 GPIO hardware\n"); | |
1386 | gpio_bank_count = 7; | |
1387 | gpio_bank = gpio_bank_730; | |
1388 | } | |
92105bb7 | 1389 | #endif |
56a25641 | 1390 | |
92105bb7 | 1391 | #ifdef CONFIG_ARCH_OMAP24XX |
56a25641 | 1392 | if (cpu_is_omap242x()) { |
92105bb7 TL |
1393 | int rev; |
1394 | ||
1395 | gpio_bank_count = 4; | |
56a25641 SMK |
1396 | gpio_bank = gpio_bank_242x; |
1397 | rev = omap_readl(gpio_bank[0].base + OMAP24XX_GPIO_REVISION); | |
1398 | printk(KERN_INFO "OMAP242x GPIO hardware version %d.%d\n", | |
1399 | (rev >> 4) & 0x0f, rev & 0x0f); | |
1400 | } | |
1401 | if (cpu_is_omap243x()) { | |
1402 | int rev; | |
1403 | ||
1404 | gpio_bank_count = 5; | |
1405 | gpio_bank = gpio_bank_243x; | |
92105bb7 | 1406 | rev = omap_readl(gpio_bank[0].base + OMAP24XX_GPIO_REVISION); |
56a25641 | 1407 | printk(KERN_INFO "OMAP243x GPIO hardware version %d.%d\n", |
92105bb7 TL |
1408 | (rev >> 4) & 0x0f, rev & 0x0f); |
1409 | } | |
5492fb1a SMK |
1410 | #endif |
1411 | #ifdef CONFIG_ARCH_OMAP34XX | |
1412 | if (cpu_is_omap34xx()) { | |
1413 | int rev; | |
1414 | ||
1415 | gpio_bank_count = OMAP34XX_NR_GPIOS; | |
1416 | gpio_bank = gpio_bank_34xx; | |
1417 | rev = omap_readl(gpio_bank[0].base + OMAP24XX_GPIO_REVISION); | |
1418 | printk(KERN_INFO "OMAP34xx GPIO hardware version %d.%d\n", | |
1419 | (rev >> 4) & 0x0f, rev & 0x0f); | |
1420 | } | |
5e1c5ff4 TL |
1421 | #endif |
1422 | for (i = 0; i < gpio_bank_count; i++) { | |
1423 | int j, gpio_count = 16; | |
1424 | ||
1425 | bank = &gpio_bank[i]; | |
1426 | bank->reserved_map = 0; | |
1427 | bank->base = IO_ADDRESS(bank->base); | |
1428 | spin_lock_init(&bank->lock); | |
e5c56ed3 | 1429 | if (bank_is_mpuio(bank)) |
5e1c5ff4 | 1430 | omap_writew(0xFFFF, OMAP_MPUIO_BASE + OMAP_MPUIO_GPIO_MASKIT); |
d11ac979 | 1431 | if (cpu_is_omap15xx() && bank->method == METHOD_GPIO_1510) { |
5e1c5ff4 TL |
1432 | __raw_writew(0xffff, bank->base + OMAP1510_GPIO_INT_MASK); |
1433 | __raw_writew(0x0000, bank->base + OMAP1510_GPIO_INT_STATUS); | |
1434 | } | |
d11ac979 | 1435 | if (cpu_is_omap16xx() && bank->method == METHOD_GPIO_1610) { |
5e1c5ff4 TL |
1436 | __raw_writew(0x0000, bank->base + OMAP1610_GPIO_IRQENABLE1); |
1437 | __raw_writew(0xffff, bank->base + OMAP1610_GPIO_IRQSTATUS1); | |
92105bb7 | 1438 | __raw_writew(0x0014, bank->base + OMAP1610_GPIO_SYSCONFIG); |
5e1c5ff4 | 1439 | } |
d11ac979 | 1440 | if (cpu_is_omap730() && bank->method == METHOD_GPIO_730) { |
5e1c5ff4 TL |
1441 | __raw_writel(0xffffffff, bank->base + OMAP730_GPIO_INT_MASK); |
1442 | __raw_writel(0x00000000, bank->base + OMAP730_GPIO_INT_STATUS); | |
1443 | ||
1444 | gpio_count = 32; /* 730 has 32-bit GPIOs */ | |
1445 | } | |
d11ac979 | 1446 | |
5492fb1a | 1447 | #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) |
92105bb7 | 1448 | if (bank->method == METHOD_GPIO_24XX) { |
3ac4fa99 JY |
1449 | static const u32 non_wakeup_gpios[] = { |
1450 | 0xe203ffc0, 0x08700040 | |
1451 | }; | |
1452 | ||
92105bb7 TL |
1453 | __raw_writel(0x00000000, bank->base + OMAP24XX_GPIO_IRQENABLE1); |
1454 | __raw_writel(0xffffffff, bank->base + OMAP24XX_GPIO_IRQSTATUS1); | |
14f1c3bf JY |
1455 | __raw_writew(0x0015, bank->base + OMAP24XX_GPIO_SYSCONFIG); |
1456 | ||
1457 | /* Initialize interface clock ungated, module enabled */ | |
1458 | __raw_writel(0, bank->base + OMAP24XX_GPIO_CTRL); | |
3ac4fa99 JY |
1459 | if (i < ARRAY_SIZE(non_wakeup_gpios)) |
1460 | bank->non_wakeup_gpios = non_wakeup_gpios[i]; | |
92105bb7 TL |
1461 | gpio_count = 32; |
1462 | } | |
5e1c5ff4 TL |
1463 | #endif |
1464 | for (j = bank->virtual_irq_start; | |
1465 | j < bank->virtual_irq_start + gpio_count; j++) { | |
8ba55c5c | 1466 | lockdep_set_class(&irq_desc[j].lock, &gpio_lock_class); |
58781016 | 1467 | set_irq_chip_data(j, bank); |
e5c56ed3 | 1468 | if (bank_is_mpuio(bank)) |
5e1c5ff4 TL |
1469 | set_irq_chip(j, &mpuio_irq_chip); |
1470 | else | |
1471 | set_irq_chip(j, &gpio_irq_chip); | |
10dd5ce2 | 1472 | set_irq_handler(j, handle_simple_irq); |
5e1c5ff4 TL |
1473 | set_irq_flags(j, IRQF_VALID); |
1474 | } | |
1475 | set_irq_chained_handler(bank->irq, gpio_irq_handler); | |
1476 | set_irq_data(bank->irq, bank); | |
1477 | } | |
1478 | ||
1479 | /* Enable system clock for GPIO module. | |
1480 | * The CAM_CLK_CTRL *is* really the right place. */ | |
92105bb7 | 1481 | if (cpu_is_omap16xx()) |
5e1c5ff4 TL |
1482 | omap_writel(omap_readl(ULPD_CAM_CLK_CTRL) | 0x04, ULPD_CAM_CLK_CTRL); |
1483 | ||
14f1c3bf JY |
1484 | /* Enable autoidle for the OCP interface */ |
1485 | if (cpu_is_omap24xx()) | |
1486 | omap_writel(1 << 0, 0x48019010); | |
5492fb1a SMK |
1487 | if (cpu_is_omap34xx()) |
1488 | omap_writel(1 << 0, 0x48306814); | |
d11ac979 | 1489 | |
5e1c5ff4 TL |
1490 | return 0; |
1491 | } | |
1492 | ||
5492fb1a | 1493 | #if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) |
92105bb7 TL |
1494 | static int omap_gpio_suspend(struct sys_device *dev, pm_message_t mesg) |
1495 | { | |
1496 | int i; | |
1497 | ||
5492fb1a | 1498 | if (!cpu_class_is_omap2() && !cpu_is_omap16xx()) |
92105bb7 TL |
1499 | return 0; |
1500 | ||
1501 | for (i = 0; i < gpio_bank_count; i++) { | |
1502 | struct gpio_bank *bank = &gpio_bank[i]; | |
1503 | void __iomem *wake_status; | |
1504 | void __iomem *wake_clear; | |
1505 | void __iomem *wake_set; | |
a6472533 | 1506 | unsigned long flags; |
92105bb7 TL |
1507 | |
1508 | switch (bank->method) { | |
e5c56ed3 | 1509 | #ifdef CONFIG_ARCH_OMAP16XX |
92105bb7 TL |
1510 | case METHOD_GPIO_1610: |
1511 | wake_status = bank->base + OMAP1610_GPIO_WAKEUPENABLE; | |
1512 | wake_clear = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA; | |
1513 | wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA; | |
1514 | break; | |
e5c56ed3 | 1515 | #endif |
5492fb1a | 1516 | #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) |
92105bb7 TL |
1517 | case METHOD_GPIO_24XX: |
1518 | wake_status = bank->base + OMAP24XX_GPIO_SETWKUENA; | |
1519 | wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA; | |
1520 | wake_set = bank->base + OMAP24XX_GPIO_SETWKUENA; | |
1521 | break; | |
e5c56ed3 | 1522 | #endif |
92105bb7 TL |
1523 | default: |
1524 | continue; | |
1525 | } | |
1526 | ||
a6472533 | 1527 | spin_lock_irqsave(&bank->lock, flags); |
92105bb7 TL |
1528 | bank->saved_wakeup = __raw_readl(wake_status); |
1529 | __raw_writel(0xffffffff, wake_clear); | |
1530 | __raw_writel(bank->suspend_wakeup, wake_set); | |
a6472533 | 1531 | spin_unlock_irqrestore(&bank->lock, flags); |
92105bb7 TL |
1532 | } |
1533 | ||
1534 | return 0; | |
1535 | } | |
1536 | ||
1537 | static int omap_gpio_resume(struct sys_device *dev) | |
1538 | { | |
1539 | int i; | |
1540 | ||
1541 | if (!cpu_is_omap24xx() && !cpu_is_omap16xx()) | |
1542 | return 0; | |
1543 | ||
1544 | for (i = 0; i < gpio_bank_count; i++) { | |
1545 | struct gpio_bank *bank = &gpio_bank[i]; | |
1546 | void __iomem *wake_clear; | |
1547 | void __iomem *wake_set; | |
a6472533 | 1548 | unsigned long flags; |
92105bb7 TL |
1549 | |
1550 | switch (bank->method) { | |
e5c56ed3 | 1551 | #ifdef CONFIG_ARCH_OMAP16XX |
92105bb7 TL |
1552 | case METHOD_GPIO_1610: |
1553 | wake_clear = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA; | |
1554 | wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA; | |
1555 | break; | |
e5c56ed3 | 1556 | #endif |
5492fb1a | 1557 | #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) |
92105bb7 | 1558 | case METHOD_GPIO_24XX: |
0d9356cb TL |
1559 | wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA; |
1560 | wake_set = bank->base + OMAP24XX_GPIO_SETWKUENA; | |
92105bb7 | 1561 | break; |
e5c56ed3 | 1562 | #endif |
92105bb7 TL |
1563 | default: |
1564 | continue; | |
1565 | } | |
1566 | ||
a6472533 | 1567 | spin_lock_irqsave(&bank->lock, flags); |
92105bb7 TL |
1568 | __raw_writel(0xffffffff, wake_clear); |
1569 | __raw_writel(bank->saved_wakeup, wake_set); | |
a6472533 | 1570 | spin_unlock_irqrestore(&bank->lock, flags); |
92105bb7 TL |
1571 | } |
1572 | ||
1573 | return 0; | |
1574 | } | |
1575 | ||
1576 | static struct sysdev_class omap_gpio_sysclass = { | |
af5ca3f4 | 1577 | .name = "gpio", |
92105bb7 TL |
1578 | .suspend = omap_gpio_suspend, |
1579 | .resume = omap_gpio_resume, | |
1580 | }; | |
1581 | ||
1582 | static struct sys_device omap_gpio_device = { | |
1583 | .id = 0, | |
1584 | .cls = &omap_gpio_sysclass, | |
1585 | }; | |
3ac4fa99 JY |
1586 | |
1587 | #endif | |
1588 | ||
5492fb1a | 1589 | #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) |
3ac4fa99 JY |
1590 | |
1591 | static int workaround_enabled; | |
1592 | ||
1593 | void omap2_gpio_prepare_for_retention(void) | |
1594 | { | |
1595 | int i, c = 0; | |
1596 | ||
1597 | /* Remove triggering for all non-wakeup GPIOs. Otherwise spurious | |
1598 | * IRQs will be generated. See OMAP2420 Errata item 1.101. */ | |
1599 | for (i = 0; i < gpio_bank_count; i++) { | |
1600 | struct gpio_bank *bank = &gpio_bank[i]; | |
1601 | u32 l1, l2; | |
1602 | ||
1603 | if (!(bank->enabled_non_wakeup_gpios)) | |
1604 | continue; | |
5492fb1a | 1605 | #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) |
3ac4fa99 JY |
1606 | bank->saved_datain = __raw_readl(bank->base + OMAP24XX_GPIO_DATAIN); |
1607 | l1 = __raw_readl(bank->base + OMAP24XX_GPIO_FALLINGDETECT); | |
1608 | l2 = __raw_readl(bank->base + OMAP24XX_GPIO_RISINGDETECT); | |
5492fb1a | 1609 | #endif |
3ac4fa99 JY |
1610 | bank->saved_fallingdetect = l1; |
1611 | bank->saved_risingdetect = l2; | |
1612 | l1 &= ~bank->enabled_non_wakeup_gpios; | |
1613 | l2 &= ~bank->enabled_non_wakeup_gpios; | |
5492fb1a | 1614 | #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) |
3ac4fa99 JY |
1615 | __raw_writel(l1, bank->base + OMAP24XX_GPIO_FALLINGDETECT); |
1616 | __raw_writel(l2, bank->base + OMAP24XX_GPIO_RISINGDETECT); | |
5492fb1a | 1617 | #endif |
3ac4fa99 JY |
1618 | c++; |
1619 | } | |
1620 | if (!c) { | |
1621 | workaround_enabled = 0; | |
1622 | return; | |
1623 | } | |
1624 | workaround_enabled = 1; | |
1625 | } | |
1626 | ||
1627 | void omap2_gpio_resume_after_retention(void) | |
1628 | { | |
1629 | int i; | |
1630 | ||
1631 | if (!workaround_enabled) | |
1632 | return; | |
1633 | for (i = 0; i < gpio_bank_count; i++) { | |
1634 | struct gpio_bank *bank = &gpio_bank[i]; | |
1635 | u32 l; | |
1636 | ||
1637 | if (!(bank->enabled_non_wakeup_gpios)) | |
1638 | continue; | |
5492fb1a | 1639 | #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) |
3ac4fa99 JY |
1640 | __raw_writel(bank->saved_fallingdetect, |
1641 | bank->base + OMAP24XX_GPIO_FALLINGDETECT); | |
1642 | __raw_writel(bank->saved_risingdetect, | |
1643 | bank->base + OMAP24XX_GPIO_RISINGDETECT); | |
5492fb1a | 1644 | #endif |
3ac4fa99 JY |
1645 | /* Check if any of the non-wakeup interrupt GPIOs have changed |
1646 | * state. If so, generate an IRQ by software. This is | |
1647 | * horribly racy, but it's the best we can do to work around | |
1648 | * this silicon bug. */ | |
5492fb1a | 1649 | #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) |
3ac4fa99 | 1650 | l = __raw_readl(bank->base + OMAP24XX_GPIO_DATAIN); |
5492fb1a | 1651 | #endif |
3ac4fa99 JY |
1652 | l ^= bank->saved_datain; |
1653 | l &= bank->non_wakeup_gpios; | |
1654 | if (l) { | |
1655 | u32 old0, old1; | |
5492fb1a | 1656 | #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) |
3ac4fa99 JY |
1657 | old0 = __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT0); |
1658 | old1 = __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT1); | |
1659 | __raw_writel(old0 | l, bank->base + OMAP24XX_GPIO_LEVELDETECT0); | |
1660 | __raw_writel(old1 | l, bank->base + OMAP24XX_GPIO_LEVELDETECT1); | |
1661 | __raw_writel(old0, bank->base + OMAP24XX_GPIO_LEVELDETECT0); | |
1662 | __raw_writel(old1, bank->base + OMAP24XX_GPIO_LEVELDETECT1); | |
5492fb1a | 1663 | #endif |
3ac4fa99 JY |
1664 | } |
1665 | } | |
1666 | ||
1667 | } | |
1668 | ||
92105bb7 TL |
1669 | #endif |
1670 | ||
5e1c5ff4 TL |
1671 | /* |
1672 | * This may get called early from board specific init | |
1a8bfa1e | 1673 | * for boards that have interrupts routed via FPGA. |
5e1c5ff4 | 1674 | */ |
277d58ef | 1675 | int __init omap_gpio_init(void) |
5e1c5ff4 TL |
1676 | { |
1677 | if (!initialized) | |
1678 | return _omap_gpio_init(); | |
1679 | else | |
1680 | return 0; | |
1681 | } | |
1682 | ||
92105bb7 TL |
1683 | static int __init omap_gpio_sysinit(void) |
1684 | { | |
1685 | int ret = 0; | |
1686 | ||
1687 | if (!initialized) | |
1688 | ret = _omap_gpio_init(); | |
1689 | ||
11a78b79 DB |
1690 | mpuio_init(); |
1691 | ||
5492fb1a SMK |
1692 | #if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) |
1693 | if (cpu_is_omap16xx() || cpu_class_is_omap2()) { | |
92105bb7 TL |
1694 | if (ret == 0) { |
1695 | ret = sysdev_class_register(&omap_gpio_sysclass); | |
1696 | if (ret == 0) | |
1697 | ret = sysdev_register(&omap_gpio_device); | |
1698 | } | |
1699 | } | |
1700 | #endif | |
1701 | ||
1702 | return ret; | |
1703 | } | |
1704 | ||
5e1c5ff4 TL |
1705 | EXPORT_SYMBOL(omap_request_gpio); |
1706 | EXPORT_SYMBOL(omap_free_gpio); | |
1707 | EXPORT_SYMBOL(omap_set_gpio_direction); | |
1708 | EXPORT_SYMBOL(omap_set_gpio_dataout); | |
1709 | EXPORT_SYMBOL(omap_get_gpio_datain); | |
5e1c5ff4 | 1710 | |
92105bb7 | 1711 | arch_initcall(omap_gpio_sysinit); |
b9772a22 DB |
1712 | |
1713 | ||
1714 | #ifdef CONFIG_DEBUG_FS | |
1715 | ||
1716 | #include <linux/debugfs.h> | |
1717 | #include <linux/seq_file.h> | |
1718 | ||
1719 | static int gpio_is_input(struct gpio_bank *bank, int mask) | |
1720 | { | |
1721 | void __iomem *reg = bank->base; | |
1722 | ||
1723 | switch (bank->method) { | |
1724 | case METHOD_MPUIO: | |
1725 | reg += OMAP_MPUIO_IO_CNTL; | |
1726 | break; | |
1727 | case METHOD_GPIO_1510: | |
1728 | reg += OMAP1510_GPIO_DIR_CONTROL; | |
1729 | break; | |
1730 | case METHOD_GPIO_1610: | |
1731 | reg += OMAP1610_GPIO_DIRECTION; | |
1732 | break; | |
1733 | case METHOD_GPIO_730: | |
1734 | reg += OMAP730_GPIO_DIR_CONTROL; | |
1735 | break; | |
1736 | case METHOD_GPIO_24XX: | |
1737 | reg += OMAP24XX_GPIO_OE; | |
1738 | break; | |
1739 | } | |
1740 | return __raw_readl(reg) & mask; | |
1741 | } | |
1742 | ||
1743 | ||
1744 | static int dbg_gpio_show(struct seq_file *s, void *unused) | |
1745 | { | |
1746 | unsigned i, j, gpio; | |
1747 | ||
1748 | for (i = 0, gpio = 0; i < gpio_bank_count; i++) { | |
1749 | struct gpio_bank *bank = gpio_bank + i; | |
1750 | unsigned bankwidth = 16; | |
1751 | u32 mask = 1; | |
1752 | ||
e5c56ed3 | 1753 | if (bank_is_mpuio(bank)) |
b9772a22 | 1754 | gpio = OMAP_MPUIO(0); |
5492fb1a | 1755 | else if (cpu_class_is_omap2() || cpu_is_omap730()) |
b9772a22 DB |
1756 | bankwidth = 32; |
1757 | ||
1758 | for (j = 0; j < bankwidth; j++, gpio++, mask <<= 1) { | |
1759 | unsigned irq, value, is_in, irqstat; | |
1760 | ||
1761 | if (!(bank->reserved_map & mask)) | |
1762 | continue; | |
1763 | ||
1764 | irq = bank->virtual_irq_start + j; | |
1765 | value = omap_get_gpio_datain(gpio); | |
1766 | is_in = gpio_is_input(bank, mask); | |
1767 | ||
e5c56ed3 | 1768 | if (bank_is_mpuio(bank)) |
b9772a22 DB |
1769 | seq_printf(s, "MPUIO %2d: ", j); |
1770 | else | |
1771 | seq_printf(s, "GPIO %3d: ", gpio); | |
1772 | seq_printf(s, "%s %s", | |
1773 | is_in ? "in " : "out", | |
1774 | value ? "hi" : "lo"); | |
1775 | ||
1776 | irqstat = irq_desc[irq].status; | |
1777 | if (is_in && ((bank->suspend_wakeup & mask) | |
1778 | || irqstat & IRQ_TYPE_SENSE_MASK)) { | |
1779 | char *trigger = NULL; | |
1780 | ||
1781 | switch (irqstat & IRQ_TYPE_SENSE_MASK) { | |
1782 | case IRQ_TYPE_EDGE_FALLING: | |
1783 | trigger = "falling"; | |
1784 | break; | |
1785 | case IRQ_TYPE_EDGE_RISING: | |
1786 | trigger = "rising"; | |
1787 | break; | |
1788 | case IRQ_TYPE_EDGE_BOTH: | |
1789 | trigger = "bothedge"; | |
1790 | break; | |
1791 | case IRQ_TYPE_LEVEL_LOW: | |
1792 | trigger = "low"; | |
1793 | break; | |
1794 | case IRQ_TYPE_LEVEL_HIGH: | |
1795 | trigger = "high"; | |
1796 | break; | |
1797 | case IRQ_TYPE_NONE: | |
1798 | trigger = "(unspecified)"; | |
1799 | break; | |
1800 | } | |
1801 | seq_printf(s, ", irq-%d %s%s", | |
1802 | irq, trigger, | |
1803 | (bank->suspend_wakeup & mask) | |
1804 | ? " wakeup" : ""); | |
1805 | } | |
1806 | seq_printf(s, "\n"); | |
1807 | } | |
1808 | ||
e5c56ed3 | 1809 | if (bank_is_mpuio(bank)) { |
b9772a22 DB |
1810 | seq_printf(s, "\n"); |
1811 | gpio = 0; | |
1812 | } | |
1813 | } | |
1814 | return 0; | |
1815 | } | |
1816 | ||
1817 | static int dbg_gpio_open(struct inode *inode, struct file *file) | |
1818 | { | |
e5c56ed3 | 1819 | return single_open(file, dbg_gpio_show, &inode->i_private); |
b9772a22 DB |
1820 | } |
1821 | ||
1822 | static const struct file_operations debug_fops = { | |
1823 | .open = dbg_gpio_open, | |
1824 | .read = seq_read, | |
1825 | .llseek = seq_lseek, | |
1826 | .release = single_release, | |
1827 | }; | |
1828 | ||
1829 | static int __init omap_gpio_debuginit(void) | |
1830 | { | |
e5c56ed3 DB |
1831 | (void) debugfs_create_file("omap_gpio", S_IRUGO, |
1832 | NULL, NULL, &debug_fops); | |
b9772a22 DB |
1833 | return 0; |
1834 | } | |
1835 | late_initcall(omap_gpio_debuginit); | |
1836 | #endif |