Commit | Line | Data |
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5e1c5ff4 TL |
1 | /* |
2 | * linux/arch/arm/plat-omap/gpio.c | |
3 | * | |
4 | * Support functions for OMAP GPIO | |
5 | * | |
92105bb7 | 6 | * Copyright (C) 2003-2005 Nokia Corporation |
96de0e25 | 7 | * Written by Juha Yrjölä <juha.yrjola@nokia.com> |
5e1c5ff4 | 8 | * |
44169075 SS |
9 | * Copyright (C) 2009 Texas Instruments |
10 | * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com> | |
11 | * | |
5e1c5ff4 TL |
12 | * This program is free software; you can redistribute it and/or modify |
13 | * it under the terms of the GNU General Public License version 2 as | |
14 | * published by the Free Software Foundation. | |
15 | */ | |
16 | ||
5e1c5ff4 TL |
17 | #include <linux/init.h> |
18 | #include <linux/module.h> | |
5e1c5ff4 | 19 | #include <linux/interrupt.h> |
92105bb7 TL |
20 | #include <linux/sysdev.h> |
21 | #include <linux/err.h> | |
f8ce2547 | 22 | #include <linux/clk.h> |
fced80c7 | 23 | #include <linux/io.h> |
5e1c5ff4 | 24 | |
a09e64fb | 25 | #include <mach/hardware.h> |
5e1c5ff4 | 26 | #include <asm/irq.h> |
a09e64fb RK |
27 | #include <mach/irqs.h> |
28 | #include <mach/gpio.h> | |
5e1c5ff4 | 29 | #include <asm/mach/irq.h> |
43ffcd9a | 30 | #include <plat/powerdomain.h> |
5e1c5ff4 | 31 | |
5e1c5ff4 TL |
32 | /* |
33 | * OMAP1510 GPIO registers | |
34 | */ | |
9f7065da | 35 | #define OMAP1510_GPIO_BASE 0xfffce000 |
5e1c5ff4 TL |
36 | #define OMAP1510_GPIO_DATA_INPUT 0x00 |
37 | #define OMAP1510_GPIO_DATA_OUTPUT 0x04 | |
38 | #define OMAP1510_GPIO_DIR_CONTROL 0x08 | |
39 | #define OMAP1510_GPIO_INT_CONTROL 0x0c | |
40 | #define OMAP1510_GPIO_INT_MASK 0x10 | |
41 | #define OMAP1510_GPIO_INT_STATUS 0x14 | |
42 | #define OMAP1510_GPIO_PIN_CONTROL 0x18 | |
43 | ||
44 | #define OMAP1510_IH_GPIO_BASE 64 | |
45 | ||
46 | /* | |
47 | * OMAP1610 specific GPIO registers | |
48 | */ | |
9f7065da TL |
49 | #define OMAP1610_GPIO1_BASE 0xfffbe400 |
50 | #define OMAP1610_GPIO2_BASE 0xfffbec00 | |
51 | #define OMAP1610_GPIO3_BASE 0xfffbb400 | |
52 | #define OMAP1610_GPIO4_BASE 0xfffbbc00 | |
5e1c5ff4 TL |
53 | #define OMAP1610_GPIO_REVISION 0x0000 |
54 | #define OMAP1610_GPIO_SYSCONFIG 0x0010 | |
55 | #define OMAP1610_GPIO_SYSSTATUS 0x0014 | |
56 | #define OMAP1610_GPIO_IRQSTATUS1 0x0018 | |
57 | #define OMAP1610_GPIO_IRQENABLE1 0x001c | |
92105bb7 | 58 | #define OMAP1610_GPIO_WAKEUPENABLE 0x0028 |
5e1c5ff4 TL |
59 | #define OMAP1610_GPIO_DATAIN 0x002c |
60 | #define OMAP1610_GPIO_DATAOUT 0x0030 | |
61 | #define OMAP1610_GPIO_DIRECTION 0x0034 | |
62 | #define OMAP1610_GPIO_EDGE_CTRL1 0x0038 | |
63 | #define OMAP1610_GPIO_EDGE_CTRL2 0x003c | |
64 | #define OMAP1610_GPIO_CLEAR_IRQENABLE1 0x009c | |
92105bb7 | 65 | #define OMAP1610_GPIO_CLEAR_WAKEUPENA 0x00a8 |
5e1c5ff4 TL |
66 | #define OMAP1610_GPIO_CLEAR_DATAOUT 0x00b0 |
67 | #define OMAP1610_GPIO_SET_IRQENABLE1 0x00dc | |
92105bb7 | 68 | #define OMAP1610_GPIO_SET_WAKEUPENA 0x00e8 |
5e1c5ff4 TL |
69 | #define OMAP1610_GPIO_SET_DATAOUT 0x00f0 |
70 | ||
71 | /* | |
7c006926 | 72 | * OMAP7XX specific GPIO registers |
5e1c5ff4 | 73 | */ |
9f7065da TL |
74 | #define OMAP7XX_GPIO1_BASE 0xfffbc000 |
75 | #define OMAP7XX_GPIO2_BASE 0xfffbc800 | |
76 | #define OMAP7XX_GPIO3_BASE 0xfffbd000 | |
77 | #define OMAP7XX_GPIO4_BASE 0xfffbd800 | |
78 | #define OMAP7XX_GPIO5_BASE 0xfffbe000 | |
79 | #define OMAP7XX_GPIO6_BASE 0xfffbe800 | |
7c006926 AB |
80 | #define OMAP7XX_GPIO_DATA_INPUT 0x00 |
81 | #define OMAP7XX_GPIO_DATA_OUTPUT 0x04 | |
82 | #define OMAP7XX_GPIO_DIR_CONTROL 0x08 | |
83 | #define OMAP7XX_GPIO_INT_CONTROL 0x0c | |
84 | #define OMAP7XX_GPIO_INT_MASK 0x10 | |
85 | #define OMAP7XX_GPIO_INT_STATUS 0x14 | |
5e1c5ff4 | 86 | |
9f7065da | 87 | #define OMAP1_MPUIO_VBASE OMAP1_MPUIO_BASE |
94113260 | 88 | |
92105bb7 TL |
89 | /* |
90 | * omap24xx specific GPIO registers | |
91 | */ | |
9f7065da TL |
92 | #define OMAP242X_GPIO1_BASE 0x48018000 |
93 | #define OMAP242X_GPIO2_BASE 0x4801a000 | |
94 | #define OMAP242X_GPIO3_BASE 0x4801c000 | |
95 | #define OMAP242X_GPIO4_BASE 0x4801e000 | |
56a25641 | 96 | |
9f7065da TL |
97 | #define OMAP243X_GPIO1_BASE 0x4900C000 |
98 | #define OMAP243X_GPIO2_BASE 0x4900E000 | |
99 | #define OMAP243X_GPIO3_BASE 0x49010000 | |
100 | #define OMAP243X_GPIO4_BASE 0x49012000 | |
101 | #define OMAP243X_GPIO5_BASE 0x480B6000 | |
56a25641 | 102 | |
92105bb7 TL |
103 | #define OMAP24XX_GPIO_REVISION 0x0000 |
104 | #define OMAP24XX_GPIO_SYSCONFIG 0x0010 | |
105 | #define OMAP24XX_GPIO_SYSSTATUS 0x0014 | |
106 | #define OMAP24XX_GPIO_IRQSTATUS1 0x0018 | |
bee7930f HD |
107 | #define OMAP24XX_GPIO_IRQSTATUS2 0x0028 |
108 | #define OMAP24XX_GPIO_IRQENABLE2 0x002c | |
92105bb7 | 109 | #define OMAP24XX_GPIO_IRQENABLE1 0x001c |
723fdb78 | 110 | #define OMAP24XX_GPIO_WAKE_EN 0x0020 |
92105bb7 TL |
111 | #define OMAP24XX_GPIO_CTRL 0x0030 |
112 | #define OMAP24XX_GPIO_OE 0x0034 | |
113 | #define OMAP24XX_GPIO_DATAIN 0x0038 | |
114 | #define OMAP24XX_GPIO_DATAOUT 0x003c | |
115 | #define OMAP24XX_GPIO_LEVELDETECT0 0x0040 | |
116 | #define OMAP24XX_GPIO_LEVELDETECT1 0x0044 | |
117 | #define OMAP24XX_GPIO_RISINGDETECT 0x0048 | |
118 | #define OMAP24XX_GPIO_FALLINGDETECT 0x004c | |
5eb3bb9c KH |
119 | #define OMAP24XX_GPIO_DEBOUNCE_EN 0x0050 |
120 | #define OMAP24XX_GPIO_DEBOUNCE_VAL 0x0054 | |
92105bb7 TL |
121 | #define OMAP24XX_GPIO_CLEARIRQENABLE1 0x0060 |
122 | #define OMAP24XX_GPIO_SETIRQENABLE1 0x0064 | |
123 | #define OMAP24XX_GPIO_CLEARWKUENA 0x0080 | |
124 | #define OMAP24XX_GPIO_SETWKUENA 0x0084 | |
125 | #define OMAP24XX_GPIO_CLEARDATAOUT 0x0090 | |
126 | #define OMAP24XX_GPIO_SETDATAOUT 0x0094 | |
127 | ||
78a1a6d3 SR |
128 | #define OMAP4_GPIO_REVISION 0x0000 |
129 | #define OMAP4_GPIO_SYSCONFIG 0x0010 | |
130 | #define OMAP4_GPIO_EOI 0x0020 | |
131 | #define OMAP4_GPIO_IRQSTATUSRAW0 0x0024 | |
132 | #define OMAP4_GPIO_IRQSTATUSRAW1 0x0028 | |
133 | #define OMAP4_GPIO_IRQSTATUS0 0x002c | |
134 | #define OMAP4_GPIO_IRQSTATUS1 0x0030 | |
135 | #define OMAP4_GPIO_IRQSTATUSSET0 0x0034 | |
136 | #define OMAP4_GPIO_IRQSTATUSSET1 0x0038 | |
137 | #define OMAP4_GPIO_IRQSTATUSCLR0 0x003c | |
138 | #define OMAP4_GPIO_IRQSTATUSCLR1 0x0040 | |
139 | #define OMAP4_GPIO_IRQWAKEN0 0x0044 | |
140 | #define OMAP4_GPIO_IRQWAKEN1 0x0048 | |
9f096868 C |
141 | #define OMAP4_GPIO_SYSSTATUS 0x0114 |
142 | #define OMAP4_GPIO_IRQENABLE1 0x011c | |
143 | #define OMAP4_GPIO_WAKE_EN 0x0120 | |
144 | #define OMAP4_GPIO_IRQSTATUS2 0x0128 | |
145 | #define OMAP4_GPIO_IRQENABLE2 0x012c | |
78a1a6d3 SR |
146 | #define OMAP4_GPIO_CTRL 0x0130 |
147 | #define OMAP4_GPIO_OE 0x0134 | |
148 | #define OMAP4_GPIO_DATAIN 0x0138 | |
149 | #define OMAP4_GPIO_DATAOUT 0x013c | |
150 | #define OMAP4_GPIO_LEVELDETECT0 0x0140 | |
151 | #define OMAP4_GPIO_LEVELDETECT1 0x0144 | |
152 | #define OMAP4_GPIO_RISINGDETECT 0x0148 | |
153 | #define OMAP4_GPIO_FALLINGDETECT 0x014c | |
154 | #define OMAP4_GPIO_DEBOUNCENABLE 0x0150 | |
155 | #define OMAP4_GPIO_DEBOUNCINGTIME 0x0154 | |
9f096868 C |
156 | #define OMAP4_GPIO_CLEARIRQENABLE1 0x0160 |
157 | #define OMAP4_GPIO_SETIRQENABLE1 0x0164 | |
158 | #define OMAP4_GPIO_CLEARWKUENA 0x0180 | |
159 | #define OMAP4_GPIO_SETWKUENA 0x0184 | |
78a1a6d3 SR |
160 | #define OMAP4_GPIO_CLEARDATAOUT 0x0190 |
161 | #define OMAP4_GPIO_SETDATAOUT 0x0194 | |
5492fb1a SMK |
162 | /* |
163 | * omap34xx specific GPIO registers | |
164 | */ | |
165 | ||
9f7065da TL |
166 | #define OMAP34XX_GPIO1_BASE 0x48310000 |
167 | #define OMAP34XX_GPIO2_BASE 0x49050000 | |
168 | #define OMAP34XX_GPIO3_BASE 0x49052000 | |
169 | #define OMAP34XX_GPIO4_BASE 0x49054000 | |
170 | #define OMAP34XX_GPIO5_BASE 0x49056000 | |
171 | #define OMAP34XX_GPIO6_BASE 0x49058000 | |
5492fb1a | 172 | |
44169075 SS |
173 | /* |
174 | * OMAP44XX specific GPIO registers | |
175 | */ | |
9f7065da TL |
176 | #define OMAP44XX_GPIO1_BASE 0x4a310000 |
177 | #define OMAP44XX_GPIO2_BASE 0x48055000 | |
178 | #define OMAP44XX_GPIO3_BASE 0x48057000 | |
179 | #define OMAP44XX_GPIO4_BASE 0x48059000 | |
180 | #define OMAP44XX_GPIO5_BASE 0x4805B000 | |
181 | #define OMAP44XX_GPIO6_BASE 0x4805D000 | |
5492fb1a | 182 | |
5e1c5ff4 | 183 | struct gpio_bank { |
9f7065da | 184 | unsigned long pbase; |
92105bb7 | 185 | void __iomem *base; |
5e1c5ff4 TL |
186 | u16 irq; |
187 | u16 virtual_irq_start; | |
92105bb7 | 188 | int method; |
140455fa | 189 | #if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP2PLUS) |
92105bb7 TL |
190 | u32 suspend_wakeup; |
191 | u32 saved_wakeup; | |
3ac4fa99 | 192 | #endif |
140455fa | 193 | #ifdef CONFIG_ARCH_OMAP2PLUS |
3ac4fa99 JY |
194 | u32 non_wakeup_gpios; |
195 | u32 enabled_non_wakeup_gpios; | |
196 | ||
197 | u32 saved_datain; | |
198 | u32 saved_fallingdetect; | |
199 | u32 saved_risingdetect; | |
200 | #endif | |
b144ff6f | 201 | u32 level_mask; |
4318f36b | 202 | u32 toggle_mask; |
5e1c5ff4 | 203 | spinlock_t lock; |
52e31344 | 204 | struct gpio_chip chip; |
89db9482 | 205 | struct clk *dbck; |
058af1ea | 206 | u32 mod_usage; |
8865b9b6 | 207 | u32 dbck_enable_mask; |
5e1c5ff4 TL |
208 | }; |
209 | ||
210 | #define METHOD_MPUIO 0 | |
211 | #define METHOD_GPIO_1510 1 | |
212 | #define METHOD_GPIO_1610 2 | |
7c006926 | 213 | #define METHOD_GPIO_7XX 3 |
56739a69 | 214 | #define METHOD_GPIO_24XX 5 |
3f1686a9 | 215 | #define METHOD_GPIO_44XX 6 |
5e1c5ff4 | 216 | |
92105bb7 | 217 | #ifdef CONFIG_ARCH_OMAP16XX |
5e1c5ff4 | 218 | static struct gpio_bank gpio_bank_1610[5] = { |
9f7065da TL |
219 | { OMAP1_MPUIO_VBASE, NULL, INT_MPUIO, IH_MPUIO_BASE, |
220 | METHOD_MPUIO }, | |
221 | { OMAP1610_GPIO1_BASE, NULL, INT_GPIO_BANK1, IH_GPIO_BASE, | |
222 | METHOD_GPIO_1610 }, | |
223 | { OMAP1610_GPIO2_BASE, NULL, INT_1610_GPIO_BANK2, IH_GPIO_BASE + 16, | |
224 | METHOD_GPIO_1610 }, | |
225 | { OMAP1610_GPIO3_BASE, NULL, INT_1610_GPIO_BANK3, IH_GPIO_BASE + 32, | |
226 | METHOD_GPIO_1610 }, | |
227 | { OMAP1610_GPIO4_BASE, NULL, INT_1610_GPIO_BANK4, IH_GPIO_BASE + 48, | |
228 | METHOD_GPIO_1610 }, | |
5e1c5ff4 TL |
229 | }; |
230 | #endif | |
231 | ||
1a8bfa1e | 232 | #ifdef CONFIG_ARCH_OMAP15XX |
5e1c5ff4 | 233 | static struct gpio_bank gpio_bank_1510[2] = { |
9f7065da TL |
234 | { OMAP1_MPUIO_VBASE, NULL, INT_MPUIO, IH_MPUIO_BASE, |
235 | METHOD_MPUIO }, | |
236 | { OMAP1510_GPIO_BASE, NULL, INT_GPIO_BANK1, IH_GPIO_BASE, | |
237 | METHOD_GPIO_1510 } | |
5e1c5ff4 TL |
238 | }; |
239 | #endif | |
240 | ||
b718aa81 | 241 | #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850) |
7c006926 | 242 | static struct gpio_bank gpio_bank_7xx[7] = { |
9f7065da TL |
243 | { OMAP1_MPUIO_VBASE, NULL, INT_7XX_MPUIO, IH_MPUIO_BASE, |
244 | METHOD_MPUIO }, | |
245 | { OMAP7XX_GPIO1_BASE, NULL, INT_7XX_GPIO_BANK1, IH_GPIO_BASE, | |
246 | METHOD_GPIO_7XX }, | |
247 | { OMAP7XX_GPIO2_BASE, NULL, INT_7XX_GPIO_BANK2, IH_GPIO_BASE + 32, | |
248 | METHOD_GPIO_7XX }, | |
249 | { OMAP7XX_GPIO3_BASE, NULL, INT_7XX_GPIO_BANK3, IH_GPIO_BASE + 64, | |
250 | METHOD_GPIO_7XX }, | |
251 | { OMAP7XX_GPIO4_BASE, NULL, INT_7XX_GPIO_BANK4, IH_GPIO_BASE + 96, | |
252 | METHOD_GPIO_7XX }, | |
253 | { OMAP7XX_GPIO5_BASE, NULL, INT_7XX_GPIO_BANK5, IH_GPIO_BASE + 128, | |
254 | METHOD_GPIO_7XX }, | |
255 | { OMAP7XX_GPIO6_BASE, NULL, INT_7XX_GPIO_BANK6, IH_GPIO_BASE + 160, | |
256 | METHOD_GPIO_7XX }, | |
5e1c5ff4 TL |
257 | }; |
258 | #endif | |
259 | ||
088ef950 | 260 | #ifdef CONFIG_ARCH_OMAP2 |
56a25641 SMK |
261 | |
262 | static struct gpio_bank gpio_bank_242x[4] = { | |
9f7065da TL |
263 | { OMAP242X_GPIO1_BASE, NULL, INT_24XX_GPIO_BANK1, IH_GPIO_BASE, |
264 | METHOD_GPIO_24XX }, | |
265 | { OMAP242X_GPIO2_BASE, NULL, INT_24XX_GPIO_BANK2, IH_GPIO_BASE + 32, | |
266 | METHOD_GPIO_24XX }, | |
267 | { OMAP242X_GPIO3_BASE, NULL, INT_24XX_GPIO_BANK3, IH_GPIO_BASE + 64, | |
268 | METHOD_GPIO_24XX }, | |
269 | { OMAP242X_GPIO4_BASE, NULL, INT_24XX_GPIO_BANK4, IH_GPIO_BASE + 96, | |
270 | METHOD_GPIO_24XX }, | |
92105bb7 | 271 | }; |
56a25641 SMK |
272 | |
273 | static struct gpio_bank gpio_bank_243x[5] = { | |
9f7065da TL |
274 | { OMAP243X_GPIO1_BASE, NULL, INT_24XX_GPIO_BANK1, IH_GPIO_BASE, |
275 | METHOD_GPIO_24XX }, | |
276 | { OMAP243X_GPIO2_BASE, NULL, INT_24XX_GPIO_BANK2, IH_GPIO_BASE + 32, | |
277 | METHOD_GPIO_24XX }, | |
278 | { OMAP243X_GPIO3_BASE, NULL, INT_24XX_GPIO_BANK3, IH_GPIO_BASE + 64, | |
279 | METHOD_GPIO_24XX }, | |
280 | { OMAP243X_GPIO4_BASE, NULL, INT_24XX_GPIO_BANK4, IH_GPIO_BASE + 96, | |
281 | METHOD_GPIO_24XX }, | |
282 | { OMAP243X_GPIO5_BASE, NULL, INT_24XX_GPIO_BANK5, IH_GPIO_BASE + 128, | |
283 | METHOD_GPIO_24XX }, | |
56a25641 SMK |
284 | }; |
285 | ||
92105bb7 TL |
286 | #endif |
287 | ||
a8eb7ca0 | 288 | #ifdef CONFIG_ARCH_OMAP3 |
5492fb1a | 289 | static struct gpio_bank gpio_bank_34xx[6] = { |
9f7065da TL |
290 | { OMAP34XX_GPIO1_BASE, NULL, INT_34XX_GPIO_BANK1, IH_GPIO_BASE, |
291 | METHOD_GPIO_24XX }, | |
292 | { OMAP34XX_GPIO2_BASE, NULL, INT_34XX_GPIO_BANK2, IH_GPIO_BASE + 32, | |
293 | METHOD_GPIO_24XX }, | |
294 | { OMAP34XX_GPIO3_BASE, NULL, INT_34XX_GPIO_BANK3, IH_GPIO_BASE + 64, | |
295 | METHOD_GPIO_24XX }, | |
296 | { OMAP34XX_GPIO4_BASE, NULL, INT_34XX_GPIO_BANK4, IH_GPIO_BASE + 96, | |
297 | METHOD_GPIO_24XX }, | |
298 | { OMAP34XX_GPIO5_BASE, NULL, INT_34XX_GPIO_BANK5, IH_GPIO_BASE + 128, | |
299 | METHOD_GPIO_24XX }, | |
300 | { OMAP34XX_GPIO6_BASE, NULL, INT_34XX_GPIO_BANK6, IH_GPIO_BASE + 160, | |
301 | METHOD_GPIO_24XX }, | |
5492fb1a SMK |
302 | }; |
303 | ||
40c670f0 RN |
304 | struct omap3_gpio_regs { |
305 | u32 sysconfig; | |
306 | u32 irqenable1; | |
307 | u32 irqenable2; | |
308 | u32 wake_en; | |
309 | u32 ctrl; | |
310 | u32 oe; | |
311 | u32 leveldetect0; | |
312 | u32 leveldetect1; | |
313 | u32 risingdetect; | |
314 | u32 fallingdetect; | |
315 | u32 dataout; | |
5492fb1a SMK |
316 | }; |
317 | ||
40c670f0 | 318 | static struct omap3_gpio_regs gpio_context[OMAP34XX_NR_GPIOS]; |
5492fb1a SMK |
319 | #endif |
320 | ||
44169075 SS |
321 | #ifdef CONFIG_ARCH_OMAP4 |
322 | static struct gpio_bank gpio_bank_44xx[6] = { | |
5772ca7d | 323 | { OMAP44XX_GPIO1_BASE, NULL, OMAP44XX_IRQ_GPIO1, IH_GPIO_BASE, |
3f1686a9 | 324 | METHOD_GPIO_44XX }, |
5772ca7d | 325 | { OMAP44XX_GPIO2_BASE, NULL, OMAP44XX_IRQ_GPIO2, IH_GPIO_BASE + 32, |
3f1686a9 | 326 | METHOD_GPIO_44XX }, |
5772ca7d | 327 | { OMAP44XX_GPIO3_BASE, NULL, OMAP44XX_IRQ_GPIO3, IH_GPIO_BASE + 64, |
3f1686a9 | 328 | METHOD_GPIO_44XX }, |
5772ca7d | 329 | { OMAP44XX_GPIO4_BASE, NULL, OMAP44XX_IRQ_GPIO4, IH_GPIO_BASE + 96, |
3f1686a9 | 330 | METHOD_GPIO_44XX }, |
5772ca7d | 331 | { OMAP44XX_GPIO5_BASE, NULL, OMAP44XX_IRQ_GPIO5, IH_GPIO_BASE + 128, |
3f1686a9 | 332 | METHOD_GPIO_44XX }, |
5772ca7d | 333 | { OMAP44XX_GPIO6_BASE, NULL, OMAP44XX_IRQ_GPIO6, IH_GPIO_BASE + 160, |
3f1686a9 | 334 | METHOD_GPIO_44XX }, |
44169075 SS |
335 | }; |
336 | ||
337 | #endif | |
338 | ||
5e1c5ff4 TL |
339 | static struct gpio_bank *gpio_bank; |
340 | static int gpio_bank_count; | |
341 | ||
342 | static inline struct gpio_bank *get_gpio_bank(int gpio) | |
343 | { | |
6e60e79a | 344 | if (cpu_is_omap15xx()) { |
5e1c5ff4 TL |
345 | if (OMAP_GPIO_IS_MPUIO(gpio)) |
346 | return &gpio_bank[0]; | |
347 | return &gpio_bank[1]; | |
348 | } | |
5e1c5ff4 TL |
349 | if (cpu_is_omap16xx()) { |
350 | if (OMAP_GPIO_IS_MPUIO(gpio)) | |
351 | return &gpio_bank[0]; | |
352 | return &gpio_bank[1 + (gpio >> 4)]; | |
353 | } | |
56739a69 | 354 | if (cpu_is_omap7xx()) { |
5e1c5ff4 TL |
355 | if (OMAP_GPIO_IS_MPUIO(gpio)) |
356 | return &gpio_bank[0]; | |
357 | return &gpio_bank[1 + (gpio >> 5)]; | |
358 | } | |
92105bb7 TL |
359 | if (cpu_is_omap24xx()) |
360 | return &gpio_bank[gpio >> 5]; | |
44169075 | 361 | if (cpu_is_omap34xx() || cpu_is_omap44xx()) |
5492fb1a | 362 | return &gpio_bank[gpio >> 5]; |
e031ab23 DB |
363 | BUG(); |
364 | return NULL; | |
5e1c5ff4 TL |
365 | } |
366 | ||
367 | static inline int get_gpio_index(int gpio) | |
368 | { | |
56739a69 | 369 | if (cpu_is_omap7xx()) |
5e1c5ff4 | 370 | return gpio & 0x1f; |
92105bb7 TL |
371 | if (cpu_is_omap24xx()) |
372 | return gpio & 0x1f; | |
44169075 | 373 | if (cpu_is_omap34xx() || cpu_is_omap44xx()) |
5492fb1a | 374 | return gpio & 0x1f; |
92105bb7 | 375 | return gpio & 0x0f; |
5e1c5ff4 TL |
376 | } |
377 | ||
378 | static inline int gpio_valid(int gpio) | |
379 | { | |
380 | if (gpio < 0) | |
381 | return -1; | |
d11ac979 | 382 | if (cpu_class_is_omap1() && OMAP_GPIO_IS_MPUIO(gpio)) { |
193e68be | 383 | if (gpio >= OMAP_MAX_GPIO_LINES + 16) |
5e1c5ff4 TL |
384 | return -1; |
385 | return 0; | |
386 | } | |
6e60e79a | 387 | if (cpu_is_omap15xx() && gpio < 16) |
5e1c5ff4 | 388 | return 0; |
5e1c5ff4 TL |
389 | if ((cpu_is_omap16xx()) && gpio < 64) |
390 | return 0; | |
56739a69 | 391 | if (cpu_is_omap7xx() && gpio < 192) |
5e1c5ff4 | 392 | return 0; |
92105bb7 TL |
393 | if (cpu_is_omap24xx() && gpio < 128) |
394 | return 0; | |
44169075 | 395 | if ((cpu_is_omap34xx() || cpu_is_omap44xx()) && gpio < 192) |
5492fb1a | 396 | return 0; |
5e1c5ff4 TL |
397 | return -1; |
398 | } | |
399 | ||
400 | static int check_gpio(int gpio) | |
401 | { | |
d32b20fc | 402 | if (unlikely(gpio_valid(gpio) < 0)) { |
5e1c5ff4 TL |
403 | printk(KERN_ERR "omap-gpio: invalid GPIO %d\n", gpio); |
404 | dump_stack(); | |
405 | return -1; | |
406 | } | |
407 | return 0; | |
408 | } | |
409 | ||
410 | static void _set_gpio_direction(struct gpio_bank *bank, int gpio, int is_input) | |
411 | { | |
92105bb7 | 412 | void __iomem *reg = bank->base; |
5e1c5ff4 TL |
413 | u32 l; |
414 | ||
415 | switch (bank->method) { | |
e5c56ed3 | 416 | #ifdef CONFIG_ARCH_OMAP1 |
5e1c5ff4 TL |
417 | case METHOD_MPUIO: |
418 | reg += OMAP_MPUIO_IO_CNTL; | |
419 | break; | |
e5c56ed3 DB |
420 | #endif |
421 | #ifdef CONFIG_ARCH_OMAP15XX | |
5e1c5ff4 TL |
422 | case METHOD_GPIO_1510: |
423 | reg += OMAP1510_GPIO_DIR_CONTROL; | |
424 | break; | |
e5c56ed3 DB |
425 | #endif |
426 | #ifdef CONFIG_ARCH_OMAP16XX | |
5e1c5ff4 TL |
427 | case METHOD_GPIO_1610: |
428 | reg += OMAP1610_GPIO_DIRECTION; | |
429 | break; | |
e5c56ed3 | 430 | #endif |
b718aa81 | 431 | #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850) |
7c006926 AB |
432 | case METHOD_GPIO_7XX: |
433 | reg += OMAP7XX_GPIO_DIR_CONTROL; | |
56739a69 ZM |
434 | break; |
435 | #endif | |
a8eb7ca0 | 436 | #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) |
92105bb7 TL |
437 | case METHOD_GPIO_24XX: |
438 | reg += OMAP24XX_GPIO_OE; | |
439 | break; | |
78a1a6d3 SR |
440 | #endif |
441 | #if defined(CONFIG_ARCH_OMAP4) | |
3f1686a9 | 442 | case METHOD_GPIO_44XX: |
78a1a6d3 SR |
443 | reg += OMAP4_GPIO_OE; |
444 | break; | |
e5c56ed3 DB |
445 | #endif |
446 | default: | |
447 | WARN_ON(1); | |
448 | return; | |
5e1c5ff4 TL |
449 | } |
450 | l = __raw_readl(reg); | |
451 | if (is_input) | |
452 | l |= 1 << gpio; | |
453 | else | |
454 | l &= ~(1 << gpio); | |
455 | __raw_writel(l, reg); | |
456 | } | |
457 | ||
5e1c5ff4 TL |
458 | static void _set_gpio_dataout(struct gpio_bank *bank, int gpio, int enable) |
459 | { | |
92105bb7 | 460 | void __iomem *reg = bank->base; |
5e1c5ff4 TL |
461 | u32 l = 0; |
462 | ||
463 | switch (bank->method) { | |
e5c56ed3 | 464 | #ifdef CONFIG_ARCH_OMAP1 |
5e1c5ff4 TL |
465 | case METHOD_MPUIO: |
466 | reg += OMAP_MPUIO_OUTPUT; | |
467 | l = __raw_readl(reg); | |
468 | if (enable) | |
469 | l |= 1 << gpio; | |
470 | else | |
471 | l &= ~(1 << gpio); | |
472 | break; | |
e5c56ed3 DB |
473 | #endif |
474 | #ifdef CONFIG_ARCH_OMAP15XX | |
5e1c5ff4 TL |
475 | case METHOD_GPIO_1510: |
476 | reg += OMAP1510_GPIO_DATA_OUTPUT; | |
477 | l = __raw_readl(reg); | |
478 | if (enable) | |
479 | l |= 1 << gpio; | |
480 | else | |
481 | l &= ~(1 << gpio); | |
482 | break; | |
e5c56ed3 DB |
483 | #endif |
484 | #ifdef CONFIG_ARCH_OMAP16XX | |
5e1c5ff4 TL |
485 | case METHOD_GPIO_1610: |
486 | if (enable) | |
487 | reg += OMAP1610_GPIO_SET_DATAOUT; | |
488 | else | |
489 | reg += OMAP1610_GPIO_CLEAR_DATAOUT; | |
490 | l = 1 << gpio; | |
491 | break; | |
e5c56ed3 | 492 | #endif |
b718aa81 | 493 | #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850) |
7c006926 AB |
494 | case METHOD_GPIO_7XX: |
495 | reg += OMAP7XX_GPIO_DATA_OUTPUT; | |
56739a69 ZM |
496 | l = __raw_readl(reg); |
497 | if (enable) | |
498 | l |= 1 << gpio; | |
499 | else | |
500 | l &= ~(1 << gpio); | |
501 | break; | |
502 | #endif | |
a8eb7ca0 | 503 | #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) |
92105bb7 TL |
504 | case METHOD_GPIO_24XX: |
505 | if (enable) | |
506 | reg += OMAP24XX_GPIO_SETDATAOUT; | |
507 | else | |
508 | reg += OMAP24XX_GPIO_CLEARDATAOUT; | |
509 | l = 1 << gpio; | |
510 | break; | |
78a1a6d3 SR |
511 | #endif |
512 | #ifdef CONFIG_ARCH_OMAP4 | |
3f1686a9 | 513 | case METHOD_GPIO_44XX: |
78a1a6d3 SR |
514 | if (enable) |
515 | reg += OMAP4_GPIO_SETDATAOUT; | |
516 | else | |
517 | reg += OMAP4_GPIO_CLEARDATAOUT; | |
518 | l = 1 << gpio; | |
519 | break; | |
e5c56ed3 | 520 | #endif |
5e1c5ff4 | 521 | default: |
e5c56ed3 | 522 | WARN_ON(1); |
5e1c5ff4 TL |
523 | return; |
524 | } | |
525 | __raw_writel(l, reg); | |
526 | } | |
527 | ||
b37c45b8 | 528 | static int _get_gpio_datain(struct gpio_bank *bank, int gpio) |
5e1c5ff4 | 529 | { |
92105bb7 | 530 | void __iomem *reg; |
5e1c5ff4 TL |
531 | |
532 | if (check_gpio(gpio) < 0) | |
e5c56ed3 | 533 | return -EINVAL; |
5e1c5ff4 TL |
534 | reg = bank->base; |
535 | switch (bank->method) { | |
e5c56ed3 | 536 | #ifdef CONFIG_ARCH_OMAP1 |
5e1c5ff4 TL |
537 | case METHOD_MPUIO: |
538 | reg += OMAP_MPUIO_INPUT_LATCH; | |
539 | break; | |
e5c56ed3 DB |
540 | #endif |
541 | #ifdef CONFIG_ARCH_OMAP15XX | |
5e1c5ff4 TL |
542 | case METHOD_GPIO_1510: |
543 | reg += OMAP1510_GPIO_DATA_INPUT; | |
544 | break; | |
e5c56ed3 DB |
545 | #endif |
546 | #ifdef CONFIG_ARCH_OMAP16XX | |
5e1c5ff4 TL |
547 | case METHOD_GPIO_1610: |
548 | reg += OMAP1610_GPIO_DATAIN; | |
549 | break; | |
e5c56ed3 | 550 | #endif |
b718aa81 | 551 | #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850) |
7c006926 AB |
552 | case METHOD_GPIO_7XX: |
553 | reg += OMAP7XX_GPIO_DATA_INPUT; | |
56739a69 ZM |
554 | break; |
555 | #endif | |
a8eb7ca0 | 556 | #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) |
92105bb7 TL |
557 | case METHOD_GPIO_24XX: |
558 | reg += OMAP24XX_GPIO_DATAIN; | |
559 | break; | |
78a1a6d3 SR |
560 | #endif |
561 | #ifdef CONFIG_ARCH_OMAP4 | |
3f1686a9 | 562 | case METHOD_GPIO_44XX: |
78a1a6d3 SR |
563 | reg += OMAP4_GPIO_DATAIN; |
564 | break; | |
e5c56ed3 | 565 | #endif |
5e1c5ff4 | 566 | default: |
e5c56ed3 | 567 | return -EINVAL; |
5e1c5ff4 | 568 | } |
92105bb7 TL |
569 | return (__raw_readl(reg) |
570 | & (1 << get_gpio_index(gpio))) != 0; | |
5e1c5ff4 TL |
571 | } |
572 | ||
b37c45b8 RQ |
573 | static int _get_gpio_dataout(struct gpio_bank *bank, int gpio) |
574 | { | |
575 | void __iomem *reg; | |
576 | ||
577 | if (check_gpio(gpio) < 0) | |
578 | return -EINVAL; | |
579 | reg = bank->base; | |
580 | ||
581 | switch (bank->method) { | |
582 | #ifdef CONFIG_ARCH_OMAP1 | |
583 | case METHOD_MPUIO: | |
584 | reg += OMAP_MPUIO_OUTPUT; | |
585 | break; | |
586 | #endif | |
587 | #ifdef CONFIG_ARCH_OMAP15XX | |
588 | case METHOD_GPIO_1510: | |
589 | reg += OMAP1510_GPIO_DATA_OUTPUT; | |
590 | break; | |
591 | #endif | |
592 | #ifdef CONFIG_ARCH_OMAP16XX | |
593 | case METHOD_GPIO_1610: | |
594 | reg += OMAP1610_GPIO_DATAOUT; | |
595 | break; | |
596 | #endif | |
b718aa81 | 597 | #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850) |
7c006926 AB |
598 | case METHOD_GPIO_7XX: |
599 | reg += OMAP7XX_GPIO_DATA_OUTPUT; | |
b37c45b8 RQ |
600 | break; |
601 | #endif | |
9f096868 | 602 | #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) |
b37c45b8 RQ |
603 | case METHOD_GPIO_24XX: |
604 | reg += OMAP24XX_GPIO_DATAOUT; | |
605 | break; | |
9f096868 C |
606 | #endif |
607 | #ifdef CONFIG_ARCH_OMAP4 | |
608 | case METHOD_GPIO_44XX: | |
609 | reg += OMAP4_GPIO_DATAOUT; | |
610 | break; | |
b37c45b8 RQ |
611 | #endif |
612 | default: | |
613 | return -EINVAL; | |
614 | } | |
615 | ||
616 | return (__raw_readl(reg) & (1 << get_gpio_index(gpio))) != 0; | |
617 | } | |
618 | ||
92105bb7 TL |
619 | #define MOD_REG_BIT(reg, bit_mask, set) \ |
620 | do { \ | |
621 | int l = __raw_readl(base + reg); \ | |
622 | if (set) l |= bit_mask; \ | |
623 | else l &= ~bit_mask; \ | |
624 | __raw_writel(l, base + reg); \ | |
625 | } while(0) | |
626 | ||
168ef3d9 FB |
627 | /** |
628 | * _set_gpio_debounce - low level gpio debounce time | |
629 | * @bank: the gpio bank we're acting upon | |
630 | * @gpio: the gpio number on this @gpio | |
631 | * @debounce: debounce time to use | |
632 | * | |
633 | * OMAP's debounce time is in 31us steps so we need | |
634 | * to convert and round up to the closest unit. | |
635 | */ | |
636 | static void _set_gpio_debounce(struct gpio_bank *bank, unsigned gpio, | |
637 | unsigned debounce) | |
638 | { | |
639 | void __iomem *reg = bank->base; | |
640 | u32 val; | |
641 | u32 l; | |
642 | ||
643 | if (debounce < 32) | |
644 | debounce = 0x01; | |
645 | else if (debounce > 7936) | |
646 | debounce = 0xff; | |
647 | else | |
648 | debounce = (debounce / 0x1f) - 1; | |
649 | ||
650 | l = 1 << get_gpio_index(gpio); | |
651 | ||
652 | if (cpu_is_omap44xx()) | |
653 | reg += OMAP4_GPIO_DEBOUNCINGTIME; | |
654 | else | |
655 | reg += OMAP24XX_GPIO_DEBOUNCE_VAL; | |
656 | ||
657 | __raw_writel(debounce, reg); | |
658 | ||
659 | reg = bank->base; | |
660 | if (cpu_is_omap44xx()) | |
661 | reg += OMAP4_GPIO_DEBOUNCENABLE; | |
662 | else | |
663 | reg += OMAP24XX_GPIO_DEBOUNCE_EN; | |
664 | ||
665 | val = __raw_readl(reg); | |
666 | ||
667 | if (debounce) { | |
668 | val |= l; | |
669 | if (cpu_is_omap34xx() || cpu_is_omap44xx()) | |
670 | clk_enable(bank->dbck); | |
671 | } else { | |
672 | val &= ~l; | |
673 | if (cpu_is_omap34xx() || cpu_is_omap44xx()) | |
674 | clk_disable(bank->dbck); | |
675 | } | |
f7ec0b0b | 676 | bank->dbck_enable_mask = val; |
168ef3d9 FB |
677 | |
678 | __raw_writel(val, reg); | |
679 | } | |
680 | ||
140455fa | 681 | #ifdef CONFIG_ARCH_OMAP2PLUS |
5eb3bb9c KH |
682 | static inline void set_24xx_gpio_triggering(struct gpio_bank *bank, int gpio, |
683 | int trigger) | |
5e1c5ff4 | 684 | { |
3ac4fa99 | 685 | void __iomem *base = bank->base; |
92105bb7 | 686 | u32 gpio_bit = 1 << gpio; |
78a1a6d3 | 687 | u32 val; |
92105bb7 | 688 | |
78a1a6d3 SR |
689 | if (cpu_is_omap44xx()) { |
690 | MOD_REG_BIT(OMAP4_GPIO_LEVELDETECT0, gpio_bit, | |
691 | trigger & IRQ_TYPE_LEVEL_LOW); | |
692 | MOD_REG_BIT(OMAP4_GPIO_LEVELDETECT1, gpio_bit, | |
693 | trigger & IRQ_TYPE_LEVEL_HIGH); | |
694 | MOD_REG_BIT(OMAP4_GPIO_RISINGDETECT, gpio_bit, | |
695 | trigger & IRQ_TYPE_EDGE_RISING); | |
696 | MOD_REG_BIT(OMAP4_GPIO_FALLINGDETECT, gpio_bit, | |
697 | trigger & IRQ_TYPE_EDGE_FALLING); | |
698 | } else { | |
699 | MOD_REG_BIT(OMAP24XX_GPIO_LEVELDETECT0, gpio_bit, | |
700 | trigger & IRQ_TYPE_LEVEL_LOW); | |
701 | MOD_REG_BIT(OMAP24XX_GPIO_LEVELDETECT1, gpio_bit, | |
702 | trigger & IRQ_TYPE_LEVEL_HIGH); | |
703 | MOD_REG_BIT(OMAP24XX_GPIO_RISINGDETECT, gpio_bit, | |
704 | trigger & IRQ_TYPE_EDGE_RISING); | |
705 | MOD_REG_BIT(OMAP24XX_GPIO_FALLINGDETECT, gpio_bit, | |
706 | trigger & IRQ_TYPE_EDGE_FALLING); | |
707 | } | |
3ac4fa99 | 708 | if (likely(!(bank->non_wakeup_gpios & gpio_bit))) { |
78a1a6d3 SR |
709 | if (cpu_is_omap44xx()) { |
710 | if (trigger != 0) | |
711 | __raw_writel(1 << gpio, bank->base+ | |
712 | OMAP4_GPIO_IRQWAKEN0); | |
713 | else { | |
714 | val = __raw_readl(bank->base + | |
715 | OMAP4_GPIO_IRQWAKEN0); | |
716 | __raw_writel(val & (~(1 << gpio)), bank->base + | |
717 | OMAP4_GPIO_IRQWAKEN0); | |
718 | } | |
719 | } else { | |
699117a6 CW |
720 | /* |
721 | * GPIO wakeup request can only be generated on edge | |
722 | * transitions | |
723 | */ | |
724 | if (trigger & IRQ_TYPE_EDGE_BOTH) | |
78a1a6d3 | 725 | __raw_writel(1 << gpio, bank->base |
5eb3bb9c | 726 | + OMAP24XX_GPIO_SETWKUENA); |
78a1a6d3 SR |
727 | else |
728 | __raw_writel(1 << gpio, bank->base | |
5eb3bb9c | 729 | + OMAP24XX_GPIO_CLEARWKUENA); |
78a1a6d3 | 730 | } |
a118b5f3 TK |
731 | } |
732 | /* This part needs to be executed always for OMAP34xx */ | |
733 | if (cpu_is_omap34xx() || (bank->non_wakeup_gpios & gpio_bit)) { | |
699117a6 CW |
734 | /* |
735 | * Log the edge gpio and manually trigger the IRQ | |
736 | * after resume if the input level changes | |
737 | * to avoid irq lost during PER RET/OFF mode | |
738 | * Applies for omap2 non-wakeup gpio and all omap3 gpios | |
739 | */ | |
740 | if (trigger & IRQ_TYPE_EDGE_BOTH) | |
3ac4fa99 JY |
741 | bank->enabled_non_wakeup_gpios |= gpio_bit; |
742 | else | |
743 | bank->enabled_non_wakeup_gpios &= ~gpio_bit; | |
744 | } | |
5eb3bb9c | 745 | |
78a1a6d3 SR |
746 | if (cpu_is_omap44xx()) { |
747 | bank->level_mask = | |
748 | __raw_readl(bank->base + OMAP4_GPIO_LEVELDETECT0) | | |
749 | __raw_readl(bank->base + OMAP4_GPIO_LEVELDETECT1); | |
750 | } else { | |
751 | bank->level_mask = | |
752 | __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT0) | | |
753 | __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT1); | |
754 | } | |
92105bb7 | 755 | } |
3ac4fa99 | 756 | #endif |
92105bb7 | 757 | |
9198bcd3 | 758 | #ifdef CONFIG_ARCH_OMAP1 |
4318f36b CM |
759 | /* |
760 | * This only applies to chips that can't do both rising and falling edge | |
761 | * detection at once. For all other chips, this function is a noop. | |
762 | */ | |
763 | static void _toggle_gpio_edge_triggering(struct gpio_bank *bank, int gpio) | |
764 | { | |
765 | void __iomem *reg = bank->base; | |
766 | u32 l = 0; | |
767 | ||
768 | switch (bank->method) { | |
4318f36b CM |
769 | case METHOD_MPUIO: |
770 | reg += OMAP_MPUIO_GPIO_INT_EDGE; | |
771 | break; | |
4318f36b CM |
772 | #ifdef CONFIG_ARCH_OMAP15XX |
773 | case METHOD_GPIO_1510: | |
774 | reg += OMAP1510_GPIO_INT_CONTROL; | |
775 | break; | |
776 | #endif | |
777 | #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850) | |
778 | case METHOD_GPIO_7XX: | |
779 | reg += OMAP7XX_GPIO_INT_CONTROL; | |
780 | break; | |
781 | #endif | |
782 | default: | |
783 | return; | |
784 | } | |
785 | ||
786 | l = __raw_readl(reg); | |
787 | if ((l >> gpio) & 1) | |
788 | l &= ~(1 << gpio); | |
789 | else | |
790 | l |= 1 << gpio; | |
791 | ||
792 | __raw_writel(l, reg); | |
793 | } | |
9198bcd3 | 794 | #endif |
4318f36b | 795 | |
92105bb7 TL |
796 | static int _set_gpio_triggering(struct gpio_bank *bank, int gpio, int trigger) |
797 | { | |
798 | void __iomem *reg = bank->base; | |
799 | u32 l = 0; | |
5e1c5ff4 TL |
800 | |
801 | switch (bank->method) { | |
e5c56ed3 | 802 | #ifdef CONFIG_ARCH_OMAP1 |
5e1c5ff4 TL |
803 | case METHOD_MPUIO: |
804 | reg += OMAP_MPUIO_GPIO_INT_EDGE; | |
805 | l = __raw_readl(reg); | |
29501577 | 806 | if ((trigger & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) |
4318f36b | 807 | bank->toggle_mask |= 1 << gpio; |
6cab4860 | 808 | if (trigger & IRQ_TYPE_EDGE_RISING) |
5e1c5ff4 | 809 | l |= 1 << gpio; |
6cab4860 | 810 | else if (trigger & IRQ_TYPE_EDGE_FALLING) |
5e1c5ff4 | 811 | l &= ~(1 << gpio); |
92105bb7 TL |
812 | else |
813 | goto bad; | |
5e1c5ff4 | 814 | break; |
e5c56ed3 DB |
815 | #endif |
816 | #ifdef CONFIG_ARCH_OMAP15XX | |
5e1c5ff4 TL |
817 | case METHOD_GPIO_1510: |
818 | reg += OMAP1510_GPIO_INT_CONTROL; | |
819 | l = __raw_readl(reg); | |
29501577 | 820 | if ((trigger & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) |
4318f36b | 821 | bank->toggle_mask |= 1 << gpio; |
6cab4860 | 822 | if (trigger & IRQ_TYPE_EDGE_RISING) |
5e1c5ff4 | 823 | l |= 1 << gpio; |
6cab4860 | 824 | else if (trigger & IRQ_TYPE_EDGE_FALLING) |
5e1c5ff4 | 825 | l &= ~(1 << gpio); |
92105bb7 TL |
826 | else |
827 | goto bad; | |
5e1c5ff4 | 828 | break; |
e5c56ed3 | 829 | #endif |
3ac4fa99 | 830 | #ifdef CONFIG_ARCH_OMAP16XX |
5e1c5ff4 | 831 | case METHOD_GPIO_1610: |
5e1c5ff4 TL |
832 | if (gpio & 0x08) |
833 | reg += OMAP1610_GPIO_EDGE_CTRL2; | |
834 | else | |
835 | reg += OMAP1610_GPIO_EDGE_CTRL1; | |
836 | gpio &= 0x07; | |
837 | l = __raw_readl(reg); | |
838 | l &= ~(3 << (gpio << 1)); | |
6cab4860 | 839 | if (trigger & IRQ_TYPE_EDGE_RISING) |
6e60e79a | 840 | l |= 2 << (gpio << 1); |
6cab4860 | 841 | if (trigger & IRQ_TYPE_EDGE_FALLING) |
6e60e79a | 842 | l |= 1 << (gpio << 1); |
3ac4fa99 JY |
843 | if (trigger) |
844 | /* Enable wake-up during idle for dynamic tick */ | |
845 | __raw_writel(1 << gpio, bank->base + OMAP1610_GPIO_SET_WAKEUPENA); | |
846 | else | |
847 | __raw_writel(1 << gpio, bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA); | |
5e1c5ff4 | 848 | break; |
3ac4fa99 | 849 | #endif |
b718aa81 | 850 | #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850) |
7c006926 AB |
851 | case METHOD_GPIO_7XX: |
852 | reg += OMAP7XX_GPIO_INT_CONTROL; | |
56739a69 | 853 | l = __raw_readl(reg); |
29501577 | 854 | if ((trigger & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) |
4318f36b | 855 | bank->toggle_mask |= 1 << gpio; |
56739a69 ZM |
856 | if (trigger & IRQ_TYPE_EDGE_RISING) |
857 | l |= 1 << gpio; | |
858 | else if (trigger & IRQ_TYPE_EDGE_FALLING) | |
859 | l &= ~(1 << gpio); | |
860 | else | |
861 | goto bad; | |
862 | break; | |
863 | #endif | |
140455fa | 864 | #ifdef CONFIG_ARCH_OMAP2PLUS |
92105bb7 | 865 | case METHOD_GPIO_24XX: |
3f1686a9 | 866 | case METHOD_GPIO_44XX: |
3ac4fa99 | 867 | set_24xx_gpio_triggering(bank, gpio, trigger); |
5e1c5ff4 | 868 | break; |
3ac4fa99 | 869 | #endif |
5e1c5ff4 | 870 | default: |
92105bb7 | 871 | goto bad; |
5e1c5ff4 | 872 | } |
92105bb7 TL |
873 | __raw_writel(l, reg); |
874 | return 0; | |
875 | bad: | |
876 | return -EINVAL; | |
5e1c5ff4 TL |
877 | } |
878 | ||
92105bb7 | 879 | static int gpio_irq_type(unsigned irq, unsigned type) |
5e1c5ff4 TL |
880 | { |
881 | struct gpio_bank *bank; | |
92105bb7 TL |
882 | unsigned gpio; |
883 | int retval; | |
a6472533 | 884 | unsigned long flags; |
92105bb7 | 885 | |
5492fb1a | 886 | if (!cpu_class_is_omap2() && irq > IH_MPUIO_BASE) |
92105bb7 TL |
887 | gpio = OMAP_MPUIO(irq - IH_MPUIO_BASE); |
888 | else | |
889 | gpio = irq - IH_GPIO_BASE; | |
5e1c5ff4 TL |
890 | |
891 | if (check_gpio(gpio) < 0) | |
92105bb7 TL |
892 | return -EINVAL; |
893 | ||
e5c56ed3 | 894 | if (type & ~IRQ_TYPE_SENSE_MASK) |
6e60e79a | 895 | return -EINVAL; |
e5c56ed3 DB |
896 | |
897 | /* OMAP1 allows only only edge triggering */ | |
5492fb1a | 898 | if (!cpu_class_is_omap2() |
e5c56ed3 | 899 | && (type & (IRQ_TYPE_LEVEL_LOW|IRQ_TYPE_LEVEL_HIGH))) |
92105bb7 TL |
900 | return -EINVAL; |
901 | ||
58781016 | 902 | bank = get_irq_chip_data(irq); |
a6472533 | 903 | spin_lock_irqsave(&bank->lock, flags); |
92105bb7 | 904 | retval = _set_gpio_triggering(bank, get_gpio_index(gpio), type); |
b9772a22 DB |
905 | if (retval == 0) { |
906 | irq_desc[irq].status &= ~IRQ_TYPE_SENSE_MASK; | |
907 | irq_desc[irq].status |= type; | |
908 | } | |
a6472533 | 909 | spin_unlock_irqrestore(&bank->lock, flags); |
672e302e KH |
910 | |
911 | if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH)) | |
912 | __set_irq_handler_unlocked(irq, handle_level_irq); | |
913 | else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)) | |
914 | __set_irq_handler_unlocked(irq, handle_edge_irq); | |
915 | ||
92105bb7 | 916 | return retval; |
5e1c5ff4 TL |
917 | } |
918 | ||
919 | static void _clear_gpio_irqbank(struct gpio_bank *bank, int gpio_mask) | |
920 | { | |
92105bb7 | 921 | void __iomem *reg = bank->base; |
5e1c5ff4 TL |
922 | |
923 | switch (bank->method) { | |
e5c56ed3 | 924 | #ifdef CONFIG_ARCH_OMAP1 |
5e1c5ff4 TL |
925 | case METHOD_MPUIO: |
926 | /* MPUIO irqstatus is reset by reading the status register, | |
927 | * so do nothing here */ | |
928 | return; | |
e5c56ed3 DB |
929 | #endif |
930 | #ifdef CONFIG_ARCH_OMAP15XX | |
5e1c5ff4 TL |
931 | case METHOD_GPIO_1510: |
932 | reg += OMAP1510_GPIO_INT_STATUS; | |
933 | break; | |
e5c56ed3 DB |
934 | #endif |
935 | #ifdef CONFIG_ARCH_OMAP16XX | |
5e1c5ff4 TL |
936 | case METHOD_GPIO_1610: |
937 | reg += OMAP1610_GPIO_IRQSTATUS1; | |
938 | break; | |
e5c56ed3 | 939 | #endif |
b718aa81 | 940 | #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850) |
7c006926 AB |
941 | case METHOD_GPIO_7XX: |
942 | reg += OMAP7XX_GPIO_INT_STATUS; | |
56739a69 ZM |
943 | break; |
944 | #endif | |
a8eb7ca0 | 945 | #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) |
92105bb7 TL |
946 | case METHOD_GPIO_24XX: |
947 | reg += OMAP24XX_GPIO_IRQSTATUS1; | |
948 | break; | |
78a1a6d3 SR |
949 | #endif |
950 | #if defined(CONFIG_ARCH_OMAP4) | |
3f1686a9 | 951 | case METHOD_GPIO_44XX: |
78a1a6d3 SR |
952 | reg += OMAP4_GPIO_IRQSTATUS0; |
953 | break; | |
e5c56ed3 | 954 | #endif |
5e1c5ff4 | 955 | default: |
e5c56ed3 | 956 | WARN_ON(1); |
5e1c5ff4 TL |
957 | return; |
958 | } | |
959 | __raw_writel(gpio_mask, reg); | |
bee7930f HD |
960 | |
961 | /* Workaround for clearing DSP GPIO interrupts to allow retention */ | |
3f1686a9 TL |
962 | if (cpu_is_omap24xx() || cpu_is_omap34xx()) |
963 | reg = bank->base + OMAP24XX_GPIO_IRQSTATUS2; | |
964 | else if (cpu_is_omap44xx()) | |
965 | reg = bank->base + OMAP4_GPIO_IRQSTATUS1; | |
966 | ||
78a1a6d3 | 967 | if (cpu_is_omap24xx() || cpu_is_omap34xx() || cpu_is_omap44xx()) { |
bedfd154 RQ |
968 | __raw_writel(gpio_mask, reg); |
969 | ||
970 | /* Flush posted write for the irq status to avoid spurious interrupts */ | |
971 | __raw_readl(reg); | |
78a1a6d3 | 972 | } |
5e1c5ff4 TL |
973 | } |
974 | ||
975 | static inline void _clear_gpio_irqstatus(struct gpio_bank *bank, int gpio) | |
976 | { | |
977 | _clear_gpio_irqbank(bank, 1 << get_gpio_index(gpio)); | |
978 | } | |
979 | ||
ea6dedd7 ID |
980 | static u32 _get_gpio_irqbank_mask(struct gpio_bank *bank) |
981 | { | |
982 | void __iomem *reg = bank->base; | |
99c47707 ID |
983 | int inv = 0; |
984 | u32 l; | |
985 | u32 mask; | |
ea6dedd7 ID |
986 | |
987 | switch (bank->method) { | |
e5c56ed3 | 988 | #ifdef CONFIG_ARCH_OMAP1 |
ea6dedd7 ID |
989 | case METHOD_MPUIO: |
990 | reg += OMAP_MPUIO_GPIO_MASKIT; | |
99c47707 ID |
991 | mask = 0xffff; |
992 | inv = 1; | |
ea6dedd7 | 993 | break; |
e5c56ed3 DB |
994 | #endif |
995 | #ifdef CONFIG_ARCH_OMAP15XX | |
ea6dedd7 ID |
996 | case METHOD_GPIO_1510: |
997 | reg += OMAP1510_GPIO_INT_MASK; | |
99c47707 ID |
998 | mask = 0xffff; |
999 | inv = 1; | |
ea6dedd7 | 1000 | break; |
e5c56ed3 DB |
1001 | #endif |
1002 | #ifdef CONFIG_ARCH_OMAP16XX | |
ea6dedd7 ID |
1003 | case METHOD_GPIO_1610: |
1004 | reg += OMAP1610_GPIO_IRQENABLE1; | |
99c47707 | 1005 | mask = 0xffff; |
ea6dedd7 | 1006 | break; |
e5c56ed3 | 1007 | #endif |
b718aa81 | 1008 | #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850) |
7c006926 AB |
1009 | case METHOD_GPIO_7XX: |
1010 | reg += OMAP7XX_GPIO_INT_MASK; | |
56739a69 ZM |
1011 | mask = 0xffffffff; |
1012 | inv = 1; | |
1013 | break; | |
1014 | #endif | |
a8eb7ca0 | 1015 | #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) |
ea6dedd7 ID |
1016 | case METHOD_GPIO_24XX: |
1017 | reg += OMAP24XX_GPIO_IRQENABLE1; | |
99c47707 | 1018 | mask = 0xffffffff; |
ea6dedd7 | 1019 | break; |
78a1a6d3 SR |
1020 | #endif |
1021 | #if defined(CONFIG_ARCH_OMAP4) | |
3f1686a9 | 1022 | case METHOD_GPIO_44XX: |
78a1a6d3 SR |
1023 | reg += OMAP4_GPIO_IRQSTATUSSET0; |
1024 | mask = 0xffffffff; | |
1025 | break; | |
e5c56ed3 | 1026 | #endif |
ea6dedd7 | 1027 | default: |
e5c56ed3 | 1028 | WARN_ON(1); |
ea6dedd7 ID |
1029 | return 0; |
1030 | } | |
1031 | ||
99c47707 ID |
1032 | l = __raw_readl(reg); |
1033 | if (inv) | |
1034 | l = ~l; | |
1035 | l &= mask; | |
1036 | return l; | |
ea6dedd7 ID |
1037 | } |
1038 | ||
5e1c5ff4 TL |
1039 | static void _enable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask, int enable) |
1040 | { | |
92105bb7 | 1041 | void __iomem *reg = bank->base; |
5e1c5ff4 TL |
1042 | u32 l; |
1043 | ||
1044 | switch (bank->method) { | |
e5c56ed3 | 1045 | #ifdef CONFIG_ARCH_OMAP1 |
5e1c5ff4 TL |
1046 | case METHOD_MPUIO: |
1047 | reg += OMAP_MPUIO_GPIO_MASKIT; | |
1048 | l = __raw_readl(reg); | |
1049 | if (enable) | |
1050 | l &= ~(gpio_mask); | |
1051 | else | |
1052 | l |= gpio_mask; | |
1053 | break; | |
e5c56ed3 DB |
1054 | #endif |
1055 | #ifdef CONFIG_ARCH_OMAP15XX | |
5e1c5ff4 TL |
1056 | case METHOD_GPIO_1510: |
1057 | reg += OMAP1510_GPIO_INT_MASK; | |
1058 | l = __raw_readl(reg); | |
1059 | if (enable) | |
1060 | l &= ~(gpio_mask); | |
1061 | else | |
1062 | l |= gpio_mask; | |
1063 | break; | |
e5c56ed3 DB |
1064 | #endif |
1065 | #ifdef CONFIG_ARCH_OMAP16XX | |
5e1c5ff4 TL |
1066 | case METHOD_GPIO_1610: |
1067 | if (enable) | |
1068 | reg += OMAP1610_GPIO_SET_IRQENABLE1; | |
1069 | else | |
1070 | reg += OMAP1610_GPIO_CLEAR_IRQENABLE1; | |
1071 | l = gpio_mask; | |
1072 | break; | |
e5c56ed3 | 1073 | #endif |
b718aa81 | 1074 | #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850) |
7c006926 AB |
1075 | case METHOD_GPIO_7XX: |
1076 | reg += OMAP7XX_GPIO_INT_MASK; | |
56739a69 ZM |
1077 | l = __raw_readl(reg); |
1078 | if (enable) | |
1079 | l &= ~(gpio_mask); | |
1080 | else | |
1081 | l |= gpio_mask; | |
1082 | break; | |
1083 | #endif | |
a8eb7ca0 | 1084 | #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) |
92105bb7 TL |
1085 | case METHOD_GPIO_24XX: |
1086 | if (enable) | |
1087 | reg += OMAP24XX_GPIO_SETIRQENABLE1; | |
1088 | else | |
1089 | reg += OMAP24XX_GPIO_CLEARIRQENABLE1; | |
1090 | l = gpio_mask; | |
1091 | break; | |
78a1a6d3 SR |
1092 | #endif |
1093 | #ifdef CONFIG_ARCH_OMAP4 | |
3f1686a9 | 1094 | case METHOD_GPIO_44XX: |
78a1a6d3 SR |
1095 | if (enable) |
1096 | reg += OMAP4_GPIO_IRQSTATUSSET0; | |
1097 | else | |
1098 | reg += OMAP4_GPIO_IRQSTATUSCLR0; | |
1099 | l = gpio_mask; | |
1100 | break; | |
e5c56ed3 | 1101 | #endif |
5e1c5ff4 | 1102 | default: |
e5c56ed3 | 1103 | WARN_ON(1); |
5e1c5ff4 TL |
1104 | return; |
1105 | } | |
1106 | __raw_writel(l, reg); | |
1107 | } | |
1108 | ||
1109 | static inline void _set_gpio_irqenable(struct gpio_bank *bank, int gpio, int enable) | |
1110 | { | |
1111 | _enable_gpio_irqbank(bank, 1 << get_gpio_index(gpio), enable); | |
1112 | } | |
1113 | ||
92105bb7 TL |
1114 | /* |
1115 | * Note that ENAWAKEUP needs to be enabled in GPIO_SYSCONFIG register. | |
1116 | * 1510 does not seem to have a wake-up register. If JTAG is connected | |
1117 | * to the target, system will wake up always on GPIO events. While | |
1118 | * system is running all registered GPIO interrupts need to have wake-up | |
1119 | * enabled. When system is suspended, only selected GPIO interrupts need | |
1120 | * to have wake-up enabled. | |
1121 | */ | |
1122 | static int _set_gpio_wakeup(struct gpio_bank *bank, int gpio, int enable) | |
1123 | { | |
4cc6420c | 1124 | unsigned long uninitialized_var(flags); |
a6472533 | 1125 | |
92105bb7 | 1126 | switch (bank->method) { |
3ac4fa99 | 1127 | #ifdef CONFIG_ARCH_OMAP16XX |
11a78b79 | 1128 | case METHOD_MPUIO: |
92105bb7 | 1129 | case METHOD_GPIO_1610: |
a6472533 | 1130 | spin_lock_irqsave(&bank->lock, flags); |
b3bb4f68 | 1131 | if (enable) |
92105bb7 | 1132 | bank->suspend_wakeup |= (1 << gpio); |
b3bb4f68 | 1133 | else |
92105bb7 | 1134 | bank->suspend_wakeup &= ~(1 << gpio); |
a6472533 | 1135 | spin_unlock_irqrestore(&bank->lock, flags); |
92105bb7 | 1136 | return 0; |
3ac4fa99 | 1137 | #endif |
140455fa | 1138 | #ifdef CONFIG_ARCH_OMAP2PLUS |
3ac4fa99 | 1139 | case METHOD_GPIO_24XX: |
3f1686a9 | 1140 | case METHOD_GPIO_44XX: |
11a78b79 DB |
1141 | if (bank->non_wakeup_gpios & (1 << gpio)) { |
1142 | printk(KERN_ERR "Unable to modify wakeup on " | |
1143 | "non-wakeup GPIO%d\n", | |
1144 | (bank - gpio_bank) * 32 + gpio); | |
1145 | return -EINVAL; | |
1146 | } | |
a6472533 | 1147 | spin_lock_irqsave(&bank->lock, flags); |
b3bb4f68 | 1148 | if (enable) |
3ac4fa99 | 1149 | bank->suspend_wakeup |= (1 << gpio); |
b3bb4f68 | 1150 | else |
3ac4fa99 | 1151 | bank->suspend_wakeup &= ~(1 << gpio); |
a6472533 | 1152 | spin_unlock_irqrestore(&bank->lock, flags); |
3ac4fa99 JY |
1153 | return 0; |
1154 | #endif | |
92105bb7 TL |
1155 | default: |
1156 | printk(KERN_ERR "Can't enable GPIO wakeup for method %i\n", | |
1157 | bank->method); | |
1158 | return -EINVAL; | |
1159 | } | |
1160 | } | |
1161 | ||
4196dd6b TL |
1162 | static void _reset_gpio(struct gpio_bank *bank, int gpio) |
1163 | { | |
1164 | _set_gpio_direction(bank, get_gpio_index(gpio), 1); | |
1165 | _set_gpio_irqenable(bank, gpio, 0); | |
1166 | _clear_gpio_irqstatus(bank, gpio); | |
6cab4860 | 1167 | _set_gpio_triggering(bank, get_gpio_index(gpio), IRQ_TYPE_NONE); |
4196dd6b TL |
1168 | } |
1169 | ||
92105bb7 TL |
1170 | /* Use disable_irq_wake() and enable_irq_wake() functions from drivers */ |
1171 | static int gpio_wake_enable(unsigned int irq, unsigned int enable) | |
1172 | { | |
1173 | unsigned int gpio = irq - IH_GPIO_BASE; | |
1174 | struct gpio_bank *bank; | |
1175 | int retval; | |
1176 | ||
1177 | if (check_gpio(gpio) < 0) | |
1178 | return -ENODEV; | |
58781016 | 1179 | bank = get_irq_chip_data(irq); |
92105bb7 | 1180 | retval = _set_gpio_wakeup(bank, get_gpio_index(gpio), enable); |
92105bb7 TL |
1181 | |
1182 | return retval; | |
1183 | } | |
1184 | ||
3ff164e1 | 1185 | static int omap_gpio_request(struct gpio_chip *chip, unsigned offset) |
5e1c5ff4 | 1186 | { |
3ff164e1 | 1187 | struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip); |
a6472533 | 1188 | unsigned long flags; |
52e31344 | 1189 | |
a6472533 | 1190 | spin_lock_irqsave(&bank->lock, flags); |
92105bb7 | 1191 | |
4196dd6b TL |
1192 | /* Set trigger to none. You need to enable the desired trigger with |
1193 | * request_irq() or set_irq_type(). | |
1194 | */ | |
3ff164e1 | 1195 | _set_gpio_triggering(bank, offset, IRQ_TYPE_NONE); |
92105bb7 | 1196 | |
1a8bfa1e | 1197 | #ifdef CONFIG_ARCH_OMAP15XX |
5e1c5ff4 | 1198 | if (bank->method == METHOD_GPIO_1510) { |
92105bb7 | 1199 | void __iomem *reg; |
5e1c5ff4 | 1200 | |
92105bb7 | 1201 | /* Claim the pin for MPU */ |
5e1c5ff4 | 1202 | reg = bank->base + OMAP1510_GPIO_PIN_CONTROL; |
3ff164e1 | 1203 | __raw_writel(__raw_readl(reg) | (1 << offset), reg); |
5e1c5ff4 TL |
1204 | } |
1205 | #endif | |
058af1ea C |
1206 | if (!cpu_class_is_omap1()) { |
1207 | if (!bank->mod_usage) { | |
9f096868 | 1208 | void __iomem *reg = bank->base; |
058af1ea | 1209 | u32 ctrl; |
9f096868 C |
1210 | |
1211 | if (cpu_is_omap24xx() || cpu_is_omap34xx()) | |
1212 | reg += OMAP24XX_GPIO_CTRL; | |
1213 | else if (cpu_is_omap44xx()) | |
1214 | reg += OMAP4_GPIO_CTRL; | |
1215 | ctrl = __raw_readl(reg); | |
058af1ea | 1216 | /* Module is enabled, clocks are not gated */ |
9f096868 C |
1217 | ctrl &= 0xFFFFFFFE; |
1218 | __raw_writel(ctrl, reg); | |
058af1ea C |
1219 | } |
1220 | bank->mod_usage |= 1 << offset; | |
1221 | } | |
a6472533 | 1222 | spin_unlock_irqrestore(&bank->lock, flags); |
5e1c5ff4 TL |
1223 | |
1224 | return 0; | |
1225 | } | |
1226 | ||
3ff164e1 | 1227 | static void omap_gpio_free(struct gpio_chip *chip, unsigned offset) |
5e1c5ff4 | 1228 | { |
3ff164e1 | 1229 | struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip); |
a6472533 | 1230 | unsigned long flags; |
5e1c5ff4 | 1231 | |
a6472533 | 1232 | spin_lock_irqsave(&bank->lock, flags); |
92105bb7 TL |
1233 | #ifdef CONFIG_ARCH_OMAP16XX |
1234 | if (bank->method == METHOD_GPIO_1610) { | |
1235 | /* Disable wake-up during idle for dynamic tick */ | |
1236 | void __iomem *reg = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA; | |
3ff164e1 | 1237 | __raw_writel(1 << offset, reg); |
92105bb7 TL |
1238 | } |
1239 | #endif | |
9f096868 C |
1240 | #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) |
1241 | if (bank->method == METHOD_GPIO_24XX) { | |
92105bb7 TL |
1242 | /* Disable wake-up during idle for dynamic tick */ |
1243 | void __iomem *reg = bank->base + OMAP24XX_GPIO_CLEARWKUENA; | |
3ff164e1 | 1244 | __raw_writel(1 << offset, reg); |
92105bb7 | 1245 | } |
9f096868 C |
1246 | #endif |
1247 | #ifdef CONFIG_ARCH_OMAP4 | |
1248 | if (bank->method == METHOD_GPIO_44XX) { | |
1249 | /* Disable wake-up during idle for dynamic tick */ | |
1250 | void __iomem *reg = bank->base + OMAP4_GPIO_IRQWAKEN0; | |
1251 | __raw_writel(1 << offset, reg); | |
1252 | } | |
92105bb7 | 1253 | #endif |
058af1ea C |
1254 | if (!cpu_class_is_omap1()) { |
1255 | bank->mod_usage &= ~(1 << offset); | |
1256 | if (!bank->mod_usage) { | |
9f096868 | 1257 | void __iomem *reg = bank->base; |
058af1ea | 1258 | u32 ctrl; |
9f096868 C |
1259 | |
1260 | if (cpu_is_omap24xx() || cpu_is_omap34xx()) | |
1261 | reg += OMAP24XX_GPIO_CTRL; | |
1262 | else if (cpu_is_omap44xx()) | |
1263 | reg += OMAP4_GPIO_CTRL; | |
1264 | ctrl = __raw_readl(reg); | |
058af1ea C |
1265 | /* Module is disabled, clocks are gated */ |
1266 | ctrl |= 1; | |
9f096868 | 1267 | __raw_writel(ctrl, reg); |
058af1ea C |
1268 | } |
1269 | } | |
3ff164e1 | 1270 | _reset_gpio(bank, bank->chip.base + offset); |
a6472533 | 1271 | spin_unlock_irqrestore(&bank->lock, flags); |
5e1c5ff4 TL |
1272 | } |
1273 | ||
1274 | /* | |
1275 | * We need to unmask the GPIO bank interrupt as soon as possible to | |
1276 | * avoid missing GPIO interrupts for other lines in the bank. | |
1277 | * Then we need to mask-read-clear-unmask the triggered GPIO lines | |
1278 | * in the bank to avoid missing nested interrupts for a GPIO line. | |
1279 | * If we wait to unmask individual GPIO lines in the bank after the | |
1280 | * line's interrupt handler has been run, we may miss some nested | |
1281 | * interrupts. | |
1282 | */ | |
10dd5ce2 | 1283 | static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc) |
5e1c5ff4 | 1284 | { |
92105bb7 | 1285 | void __iomem *isr_reg = NULL; |
5e1c5ff4 | 1286 | u32 isr; |
4318f36b | 1287 | unsigned int gpio_irq, gpio_index; |
5e1c5ff4 | 1288 | struct gpio_bank *bank; |
ea6dedd7 ID |
1289 | u32 retrigger = 0; |
1290 | int unmasked = 0; | |
5e1c5ff4 TL |
1291 | |
1292 | desc->chip->ack(irq); | |
1293 | ||
418ca1f0 | 1294 | bank = get_irq_data(irq); |
e5c56ed3 | 1295 | #ifdef CONFIG_ARCH_OMAP1 |
5e1c5ff4 TL |
1296 | if (bank->method == METHOD_MPUIO) |
1297 | isr_reg = bank->base + OMAP_MPUIO_GPIO_INT; | |
e5c56ed3 | 1298 | #endif |
1a8bfa1e | 1299 | #ifdef CONFIG_ARCH_OMAP15XX |
5e1c5ff4 TL |
1300 | if (bank->method == METHOD_GPIO_1510) |
1301 | isr_reg = bank->base + OMAP1510_GPIO_INT_STATUS; | |
1302 | #endif | |
1303 | #if defined(CONFIG_ARCH_OMAP16XX) | |
1304 | if (bank->method == METHOD_GPIO_1610) | |
1305 | isr_reg = bank->base + OMAP1610_GPIO_IRQSTATUS1; | |
1306 | #endif | |
b718aa81 | 1307 | #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850) |
7c006926 AB |
1308 | if (bank->method == METHOD_GPIO_7XX) |
1309 | isr_reg = bank->base + OMAP7XX_GPIO_INT_STATUS; | |
56739a69 | 1310 | #endif |
a8eb7ca0 | 1311 | #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) |
92105bb7 TL |
1312 | if (bank->method == METHOD_GPIO_24XX) |
1313 | isr_reg = bank->base + OMAP24XX_GPIO_IRQSTATUS1; | |
78a1a6d3 SR |
1314 | #endif |
1315 | #if defined(CONFIG_ARCH_OMAP4) | |
3f1686a9 | 1316 | if (bank->method == METHOD_GPIO_44XX) |
78a1a6d3 | 1317 | isr_reg = bank->base + OMAP4_GPIO_IRQSTATUS0; |
92105bb7 | 1318 | #endif |
92105bb7 | 1319 | while(1) { |
6e60e79a | 1320 | u32 isr_saved, level_mask = 0; |
ea6dedd7 | 1321 | u32 enabled; |
6e60e79a | 1322 | |
ea6dedd7 ID |
1323 | enabled = _get_gpio_irqbank_mask(bank); |
1324 | isr_saved = isr = __raw_readl(isr_reg) & enabled; | |
6e60e79a TL |
1325 | |
1326 | if (cpu_is_omap15xx() && (bank->method == METHOD_MPUIO)) | |
1327 | isr &= 0x0000ffff; | |
1328 | ||
5492fb1a | 1329 | if (cpu_class_is_omap2()) { |
b144ff6f | 1330 | level_mask = bank->level_mask & enabled; |
ea6dedd7 | 1331 | } |
6e60e79a TL |
1332 | |
1333 | /* clear edge sensitive interrupts before handler(s) are | |
1334 | called so that we don't miss any interrupt occurred while | |
1335 | executing them */ | |
1336 | _enable_gpio_irqbank(bank, isr_saved & ~level_mask, 0); | |
1337 | _clear_gpio_irqbank(bank, isr_saved & ~level_mask); | |
1338 | _enable_gpio_irqbank(bank, isr_saved & ~level_mask, 1); | |
1339 | ||
1340 | /* if there is only edge sensitive GPIO pin interrupts | |
1341 | configured, we could unmask GPIO bank interrupt immediately */ | |
ea6dedd7 ID |
1342 | if (!level_mask && !unmasked) { |
1343 | unmasked = 1; | |
6e60e79a | 1344 | desc->chip->unmask(irq); |
ea6dedd7 | 1345 | } |
92105bb7 | 1346 | |
ea6dedd7 ID |
1347 | isr |= retrigger; |
1348 | retrigger = 0; | |
92105bb7 TL |
1349 | if (!isr) |
1350 | break; | |
1351 | ||
1352 | gpio_irq = bank->virtual_irq_start; | |
1353 | for (; isr != 0; isr >>= 1, gpio_irq++) { | |
4318f36b CM |
1354 | gpio_index = get_gpio_index(irq_to_gpio(gpio_irq)); |
1355 | ||
92105bb7 TL |
1356 | if (!(isr & 1)) |
1357 | continue; | |
29454dde | 1358 | |
4318f36b CM |
1359 | #ifdef CONFIG_ARCH_OMAP1 |
1360 | /* | |
1361 | * Some chips can't respond to both rising and falling | |
1362 | * at the same time. If this irq was requested with | |
1363 | * both flags, we need to flip the ICR data for the IRQ | |
1364 | * to respond to the IRQ for the opposite direction. | |
1365 | * This will be indicated in the bank toggle_mask. | |
1366 | */ | |
1367 | if (bank->toggle_mask & (1 << gpio_index)) | |
1368 | _toggle_gpio_edge_triggering(bank, gpio_index); | |
1369 | #endif | |
1370 | ||
d8aa0251 | 1371 | generic_handle_irq(gpio_irq); |
92105bb7 | 1372 | } |
1a8bfa1e | 1373 | } |
ea6dedd7 ID |
1374 | /* if bank has any level sensitive GPIO pin interrupt |
1375 | configured, we must unmask the bank interrupt only after | |
1376 | handler(s) are executed in order to avoid spurious bank | |
1377 | interrupt */ | |
1378 | if (!unmasked) | |
1379 | desc->chip->unmask(irq); | |
1380 | ||
5e1c5ff4 TL |
1381 | } |
1382 | ||
4196dd6b TL |
1383 | static void gpio_irq_shutdown(unsigned int irq) |
1384 | { | |
1385 | unsigned int gpio = irq - IH_GPIO_BASE; | |
58781016 | 1386 | struct gpio_bank *bank = get_irq_chip_data(irq); |
4196dd6b TL |
1387 | |
1388 | _reset_gpio(bank, gpio); | |
1389 | } | |
1390 | ||
5e1c5ff4 TL |
1391 | static void gpio_ack_irq(unsigned int irq) |
1392 | { | |
1393 | unsigned int gpio = irq - IH_GPIO_BASE; | |
58781016 | 1394 | struct gpio_bank *bank = get_irq_chip_data(irq); |
5e1c5ff4 TL |
1395 | |
1396 | _clear_gpio_irqstatus(bank, gpio); | |
1397 | } | |
1398 | ||
1399 | static void gpio_mask_irq(unsigned int irq) | |
1400 | { | |
1401 | unsigned int gpio = irq - IH_GPIO_BASE; | |
58781016 | 1402 | struct gpio_bank *bank = get_irq_chip_data(irq); |
5e1c5ff4 TL |
1403 | |
1404 | _set_gpio_irqenable(bank, gpio, 0); | |
55b6019a | 1405 | _set_gpio_triggering(bank, get_gpio_index(gpio), IRQ_TYPE_NONE); |
5e1c5ff4 TL |
1406 | } |
1407 | ||
1408 | static void gpio_unmask_irq(unsigned int irq) | |
1409 | { | |
1410 | unsigned int gpio = irq - IH_GPIO_BASE; | |
58781016 | 1411 | struct gpio_bank *bank = get_irq_chip_data(irq); |
b144ff6f | 1412 | unsigned int irq_mask = 1 << get_gpio_index(gpio); |
55b6019a KH |
1413 | struct irq_desc *desc = irq_to_desc(irq); |
1414 | u32 trigger = desc->status & IRQ_TYPE_SENSE_MASK; | |
1415 | ||
1416 | if (trigger) | |
1417 | _set_gpio_triggering(bank, get_gpio_index(gpio), trigger); | |
b144ff6f KH |
1418 | |
1419 | /* For level-triggered GPIOs, the clearing must be done after | |
1420 | * the HW source is cleared, thus after the handler has run */ | |
1421 | if (bank->level_mask & irq_mask) { | |
1422 | _set_gpio_irqenable(bank, gpio, 0); | |
1423 | _clear_gpio_irqstatus(bank, gpio); | |
1424 | } | |
5e1c5ff4 | 1425 | |
4de8c75b | 1426 | _set_gpio_irqenable(bank, gpio, 1); |
5e1c5ff4 TL |
1427 | } |
1428 | ||
e5c56ed3 DB |
1429 | static struct irq_chip gpio_irq_chip = { |
1430 | .name = "GPIO", | |
1431 | .shutdown = gpio_irq_shutdown, | |
1432 | .ack = gpio_ack_irq, | |
1433 | .mask = gpio_mask_irq, | |
1434 | .unmask = gpio_unmask_irq, | |
1435 | .set_type = gpio_irq_type, | |
1436 | .set_wake = gpio_wake_enable, | |
1437 | }; | |
1438 | ||
1439 | /*---------------------------------------------------------------------*/ | |
1440 | ||
1441 | #ifdef CONFIG_ARCH_OMAP1 | |
1442 | ||
1443 | /* MPUIO uses the always-on 32k clock */ | |
1444 | ||
5e1c5ff4 TL |
1445 | static void mpuio_ack_irq(unsigned int irq) |
1446 | { | |
1447 | /* The ISR is reset automatically, so do nothing here. */ | |
1448 | } | |
1449 | ||
1450 | static void mpuio_mask_irq(unsigned int irq) | |
1451 | { | |
1452 | unsigned int gpio = OMAP_MPUIO(irq - IH_MPUIO_BASE); | |
58781016 | 1453 | struct gpio_bank *bank = get_irq_chip_data(irq); |
5e1c5ff4 TL |
1454 | |
1455 | _set_gpio_irqenable(bank, gpio, 0); | |
1456 | } | |
1457 | ||
1458 | static void mpuio_unmask_irq(unsigned int irq) | |
1459 | { | |
1460 | unsigned int gpio = OMAP_MPUIO(irq - IH_MPUIO_BASE); | |
58781016 | 1461 | struct gpio_bank *bank = get_irq_chip_data(irq); |
5e1c5ff4 TL |
1462 | |
1463 | _set_gpio_irqenable(bank, gpio, 1); | |
1464 | } | |
1465 | ||
e5c56ed3 DB |
1466 | static struct irq_chip mpuio_irq_chip = { |
1467 | .name = "MPUIO", | |
1468 | .ack = mpuio_ack_irq, | |
1469 | .mask = mpuio_mask_irq, | |
1470 | .unmask = mpuio_unmask_irq, | |
92105bb7 | 1471 | .set_type = gpio_irq_type, |
11a78b79 DB |
1472 | #ifdef CONFIG_ARCH_OMAP16XX |
1473 | /* REVISIT: assuming only 16xx supports MPUIO wake events */ | |
1474 | .set_wake = gpio_wake_enable, | |
1475 | #endif | |
5e1c5ff4 TL |
1476 | }; |
1477 | ||
e5c56ed3 DB |
1478 | |
1479 | #define bank_is_mpuio(bank) ((bank)->method == METHOD_MPUIO) | |
1480 | ||
11a78b79 DB |
1481 | |
1482 | #ifdef CONFIG_ARCH_OMAP16XX | |
1483 | ||
1484 | #include <linux/platform_device.h> | |
1485 | ||
79ee031f | 1486 | static int omap_mpuio_suspend_noirq(struct device *dev) |
11a78b79 | 1487 | { |
79ee031f | 1488 | struct platform_device *pdev = to_platform_device(dev); |
11a78b79 DB |
1489 | struct gpio_bank *bank = platform_get_drvdata(pdev); |
1490 | void __iomem *mask_reg = bank->base + OMAP_MPUIO_GPIO_MASKIT; | |
a6472533 | 1491 | unsigned long flags; |
11a78b79 | 1492 | |
a6472533 | 1493 | spin_lock_irqsave(&bank->lock, flags); |
11a78b79 DB |
1494 | bank->saved_wakeup = __raw_readl(mask_reg); |
1495 | __raw_writel(0xffff & ~bank->suspend_wakeup, mask_reg); | |
a6472533 | 1496 | spin_unlock_irqrestore(&bank->lock, flags); |
11a78b79 DB |
1497 | |
1498 | return 0; | |
1499 | } | |
1500 | ||
79ee031f | 1501 | static int omap_mpuio_resume_noirq(struct device *dev) |
11a78b79 | 1502 | { |
79ee031f | 1503 | struct platform_device *pdev = to_platform_device(dev); |
11a78b79 DB |
1504 | struct gpio_bank *bank = platform_get_drvdata(pdev); |
1505 | void __iomem *mask_reg = bank->base + OMAP_MPUIO_GPIO_MASKIT; | |
a6472533 | 1506 | unsigned long flags; |
11a78b79 | 1507 | |
a6472533 | 1508 | spin_lock_irqsave(&bank->lock, flags); |
11a78b79 | 1509 | __raw_writel(bank->saved_wakeup, mask_reg); |
a6472533 | 1510 | spin_unlock_irqrestore(&bank->lock, flags); |
11a78b79 DB |
1511 | |
1512 | return 0; | |
1513 | } | |
1514 | ||
47145210 | 1515 | static const struct dev_pm_ops omap_mpuio_dev_pm_ops = { |
79ee031f MD |
1516 | .suspend_noirq = omap_mpuio_suspend_noirq, |
1517 | .resume_noirq = omap_mpuio_resume_noirq, | |
1518 | }; | |
1519 | ||
11a78b79 DB |
1520 | /* use platform_driver for this, now that there's no longer any |
1521 | * point to sys_device (other than not disturbing old code). | |
1522 | */ | |
1523 | static struct platform_driver omap_mpuio_driver = { | |
11a78b79 DB |
1524 | .driver = { |
1525 | .name = "mpuio", | |
79ee031f | 1526 | .pm = &omap_mpuio_dev_pm_ops, |
11a78b79 DB |
1527 | }, |
1528 | }; | |
1529 | ||
1530 | static struct platform_device omap_mpuio_device = { | |
1531 | .name = "mpuio", | |
1532 | .id = -1, | |
1533 | .dev = { | |
1534 | .driver = &omap_mpuio_driver.driver, | |
1535 | } | |
1536 | /* could list the /proc/iomem resources */ | |
1537 | }; | |
1538 | ||
1539 | static inline void mpuio_init(void) | |
1540 | { | |
fcf126d8 DB |
1541 | platform_set_drvdata(&omap_mpuio_device, &gpio_bank_1610[0]); |
1542 | ||
11a78b79 DB |
1543 | if (platform_driver_register(&omap_mpuio_driver) == 0) |
1544 | (void) platform_device_register(&omap_mpuio_device); | |
1545 | } | |
1546 | ||
1547 | #else | |
1548 | static inline void mpuio_init(void) {} | |
1549 | #endif /* 16xx */ | |
1550 | ||
e5c56ed3 DB |
1551 | #else |
1552 | ||
1553 | extern struct irq_chip mpuio_irq_chip; | |
1554 | ||
1555 | #define bank_is_mpuio(bank) 0 | |
11a78b79 | 1556 | static inline void mpuio_init(void) {} |
e5c56ed3 DB |
1557 | |
1558 | #endif | |
1559 | ||
1560 | /*---------------------------------------------------------------------*/ | |
5e1c5ff4 | 1561 | |
52e31344 DB |
1562 | /* REVISIT these are stupid implementations! replace by ones that |
1563 | * don't switch on METHOD_* and which mostly avoid spinlocks | |
1564 | */ | |
1565 | ||
1566 | static int gpio_input(struct gpio_chip *chip, unsigned offset) | |
1567 | { | |
1568 | struct gpio_bank *bank; | |
1569 | unsigned long flags; | |
1570 | ||
1571 | bank = container_of(chip, struct gpio_bank, chip); | |
1572 | spin_lock_irqsave(&bank->lock, flags); | |
1573 | _set_gpio_direction(bank, offset, 1); | |
1574 | spin_unlock_irqrestore(&bank->lock, flags); | |
1575 | return 0; | |
1576 | } | |
1577 | ||
b37c45b8 RQ |
1578 | static int gpio_is_input(struct gpio_bank *bank, int mask) |
1579 | { | |
1580 | void __iomem *reg = bank->base; | |
1581 | ||
1582 | switch (bank->method) { | |
1583 | case METHOD_MPUIO: | |
1584 | reg += OMAP_MPUIO_IO_CNTL; | |
1585 | break; | |
1586 | case METHOD_GPIO_1510: | |
1587 | reg += OMAP1510_GPIO_DIR_CONTROL; | |
1588 | break; | |
1589 | case METHOD_GPIO_1610: | |
1590 | reg += OMAP1610_GPIO_DIRECTION; | |
1591 | break; | |
7c006926 AB |
1592 | case METHOD_GPIO_7XX: |
1593 | reg += OMAP7XX_GPIO_DIR_CONTROL; | |
b37c45b8 RQ |
1594 | break; |
1595 | case METHOD_GPIO_24XX: | |
1596 | reg += OMAP24XX_GPIO_OE; | |
1597 | break; | |
9f096868 C |
1598 | case METHOD_GPIO_44XX: |
1599 | reg += OMAP4_GPIO_OE; | |
1600 | break; | |
1601 | default: | |
1602 | WARN_ONCE(1, "gpio_is_input: incorrect OMAP GPIO method"); | |
1603 | return -EINVAL; | |
b37c45b8 RQ |
1604 | } |
1605 | return __raw_readl(reg) & mask; | |
1606 | } | |
1607 | ||
52e31344 DB |
1608 | static int gpio_get(struct gpio_chip *chip, unsigned offset) |
1609 | { | |
b37c45b8 RQ |
1610 | struct gpio_bank *bank; |
1611 | void __iomem *reg; | |
1612 | int gpio; | |
1613 | u32 mask; | |
1614 | ||
1615 | gpio = chip->base + offset; | |
1616 | bank = get_gpio_bank(gpio); | |
1617 | reg = bank->base; | |
1618 | mask = 1 << get_gpio_index(gpio); | |
1619 | ||
1620 | if (gpio_is_input(bank, mask)) | |
1621 | return _get_gpio_datain(bank, gpio); | |
1622 | else | |
1623 | return _get_gpio_dataout(bank, gpio); | |
52e31344 DB |
1624 | } |
1625 | ||
1626 | static int gpio_output(struct gpio_chip *chip, unsigned offset, int value) | |
1627 | { | |
1628 | struct gpio_bank *bank; | |
1629 | unsigned long flags; | |
1630 | ||
1631 | bank = container_of(chip, struct gpio_bank, chip); | |
1632 | spin_lock_irqsave(&bank->lock, flags); | |
1633 | _set_gpio_dataout(bank, offset, value); | |
1634 | _set_gpio_direction(bank, offset, 0); | |
1635 | spin_unlock_irqrestore(&bank->lock, flags); | |
1636 | return 0; | |
1637 | } | |
1638 | ||
168ef3d9 FB |
1639 | static int gpio_debounce(struct gpio_chip *chip, unsigned offset, |
1640 | unsigned debounce) | |
1641 | { | |
1642 | struct gpio_bank *bank; | |
1643 | unsigned long flags; | |
1644 | ||
1645 | bank = container_of(chip, struct gpio_bank, chip); | |
1646 | spin_lock_irqsave(&bank->lock, flags); | |
1647 | _set_gpio_debounce(bank, offset, debounce); | |
1648 | spin_unlock_irqrestore(&bank->lock, flags); | |
1649 | ||
1650 | return 0; | |
1651 | } | |
1652 | ||
52e31344 DB |
1653 | static void gpio_set(struct gpio_chip *chip, unsigned offset, int value) |
1654 | { | |
1655 | struct gpio_bank *bank; | |
1656 | unsigned long flags; | |
1657 | ||
1658 | bank = container_of(chip, struct gpio_bank, chip); | |
1659 | spin_lock_irqsave(&bank->lock, flags); | |
1660 | _set_gpio_dataout(bank, offset, value); | |
1661 | spin_unlock_irqrestore(&bank->lock, flags); | |
1662 | } | |
1663 | ||
a007b709 DB |
1664 | static int gpio_2irq(struct gpio_chip *chip, unsigned offset) |
1665 | { | |
1666 | struct gpio_bank *bank; | |
1667 | ||
1668 | bank = container_of(chip, struct gpio_bank, chip); | |
1669 | return bank->virtual_irq_start + offset; | |
1670 | } | |
1671 | ||
52e31344 DB |
1672 | /*---------------------------------------------------------------------*/ |
1673 | ||
1a8bfa1e | 1674 | static int initialized; |
56213ca4 | 1675 | #if defined(CONFIG_ARCH_OMAP1) || defined(CONFIG_ARCH_OMAP2) |
1a8bfa1e | 1676 | static struct clk * gpio_ick; |
5492fb1a SMK |
1677 | #endif |
1678 | ||
1679 | #if defined(CONFIG_ARCH_OMAP2) | |
1a8bfa1e | 1680 | static struct clk * gpio_fck; |
5492fb1a | 1681 | #endif |
5e1c5ff4 | 1682 | |
5492fb1a | 1683 | #if defined(CONFIG_ARCH_OMAP2430) |
56a25641 SMK |
1684 | static struct clk * gpio5_ick; |
1685 | static struct clk * gpio5_fck; | |
1686 | #endif | |
1687 | ||
44169075 | 1688 | #if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4) |
5492fb1a SMK |
1689 | static struct clk *gpio_iclks[OMAP34XX_NR_GPIOS]; |
1690 | #endif | |
1691 | ||
9f7065da TL |
1692 | static void __init omap_gpio_show_rev(void) |
1693 | { | |
1694 | u32 rev; | |
1695 | ||
1696 | if (cpu_is_omap16xx()) | |
1697 | rev = __raw_readw(gpio_bank[1].base + OMAP1610_GPIO_REVISION); | |
1698 | else if (cpu_is_omap24xx() || cpu_is_omap34xx()) | |
1699 | rev = __raw_readl(gpio_bank[0].base + OMAP24XX_GPIO_REVISION); | |
1700 | else if (cpu_is_omap44xx()) | |
1701 | rev = __raw_readl(gpio_bank[0].base + OMAP4_GPIO_REVISION); | |
1702 | else | |
1703 | return; | |
1704 | ||
1705 | printk(KERN_INFO "OMAP GPIO hardware version %d.%d\n", | |
1706 | (rev >> 4) & 0x0f, rev & 0x0f); | |
1707 | } | |
1708 | ||
8ba55c5c DB |
1709 | /* This lock class tells lockdep that GPIO irqs are in a different |
1710 | * category than their parents, so it won't report false recursion. | |
1711 | */ | |
1712 | static struct lock_class_key gpio_lock_class; | |
1713 | ||
5e1c5ff4 TL |
1714 | static int __init _omap_gpio_init(void) |
1715 | { | |
1716 | int i; | |
52e31344 | 1717 | int gpio = 0; |
5e1c5ff4 | 1718 | struct gpio_bank *bank; |
9f7065da | 1719 | int bank_size = SZ_8K; /* Module 4KB + L4 4KB except on omap1 */ |
5492fb1a | 1720 | char clk_name[11]; |
5e1c5ff4 TL |
1721 | |
1722 | initialized = 1; | |
1723 | ||
5492fb1a | 1724 | #if defined(CONFIG_ARCH_OMAP1) |
6e60e79a | 1725 | if (cpu_is_omap15xx()) { |
1a8bfa1e TL |
1726 | gpio_ick = clk_get(NULL, "arm_gpio_ck"); |
1727 | if (IS_ERR(gpio_ick)) | |
92105bb7 TL |
1728 | printk("Could not get arm_gpio_ck\n"); |
1729 | else | |
30ff720b | 1730 | clk_enable(gpio_ick); |
1a8bfa1e | 1731 | } |
5492fb1a SMK |
1732 | #endif |
1733 | #if defined(CONFIG_ARCH_OMAP2) | |
1734 | if (cpu_class_is_omap2()) { | |
1a8bfa1e TL |
1735 | gpio_ick = clk_get(NULL, "gpios_ick"); |
1736 | if (IS_ERR(gpio_ick)) | |
1737 | printk("Could not get gpios_ick\n"); | |
1738 | else | |
30ff720b | 1739 | clk_enable(gpio_ick); |
1a8bfa1e | 1740 | gpio_fck = clk_get(NULL, "gpios_fck"); |
1630b52d | 1741 | if (IS_ERR(gpio_fck)) |
1a8bfa1e TL |
1742 | printk("Could not get gpios_fck\n"); |
1743 | else | |
30ff720b | 1744 | clk_enable(gpio_fck); |
56a25641 SMK |
1745 | |
1746 | /* | |
5492fb1a | 1747 | * On 2430 & 3430 GPIO 5 uses CORE L4 ICLK |
56a25641 | 1748 | */ |
5492fb1a | 1749 | #if defined(CONFIG_ARCH_OMAP2430) |
56a25641 SMK |
1750 | if (cpu_is_omap2430()) { |
1751 | gpio5_ick = clk_get(NULL, "gpio5_ick"); | |
1752 | if (IS_ERR(gpio5_ick)) | |
1753 | printk("Could not get gpio5_ick\n"); | |
1754 | else | |
1755 | clk_enable(gpio5_ick); | |
1756 | gpio5_fck = clk_get(NULL, "gpio5_fck"); | |
1757 | if (IS_ERR(gpio5_fck)) | |
1758 | printk("Could not get gpio5_fck\n"); | |
1759 | else | |
1760 | clk_enable(gpio5_fck); | |
1761 | } | |
1762 | #endif | |
5492fb1a SMK |
1763 | } |
1764 | #endif | |
1765 | ||
44169075 SS |
1766 | #if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4) |
1767 | if (cpu_is_omap34xx() || cpu_is_omap44xx()) { | |
5492fb1a SMK |
1768 | for (i = 0; i < OMAP34XX_NR_GPIOS; i++) { |
1769 | sprintf(clk_name, "gpio%d_ick", i + 1); | |
1770 | gpio_iclks[i] = clk_get(NULL, clk_name); | |
1771 | if (IS_ERR(gpio_iclks[i])) | |
1772 | printk(KERN_ERR "Could not get %s\n", clk_name); | |
1773 | else | |
1774 | clk_enable(gpio_iclks[i]); | |
5492fb1a SMK |
1775 | } |
1776 | } | |
1777 | #endif | |
1778 | ||
92105bb7 | 1779 | |
1a8bfa1e | 1780 | #ifdef CONFIG_ARCH_OMAP15XX |
6e60e79a | 1781 | if (cpu_is_omap15xx()) { |
5e1c5ff4 TL |
1782 | gpio_bank_count = 2; |
1783 | gpio_bank = gpio_bank_1510; | |
9f7065da | 1784 | bank_size = SZ_2K; |
5e1c5ff4 TL |
1785 | } |
1786 | #endif | |
1787 | #if defined(CONFIG_ARCH_OMAP16XX) | |
1788 | if (cpu_is_omap16xx()) { | |
5e1c5ff4 TL |
1789 | gpio_bank_count = 5; |
1790 | gpio_bank = gpio_bank_1610; | |
9f7065da | 1791 | bank_size = SZ_2K; |
5e1c5ff4 TL |
1792 | } |
1793 | #endif | |
b718aa81 AB |
1794 | #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850) |
1795 | if (cpu_is_omap7xx()) { | |
56739a69 | 1796 | gpio_bank_count = 7; |
7c006926 | 1797 | gpio_bank = gpio_bank_7xx; |
9f7065da | 1798 | bank_size = SZ_2K; |
56739a69 ZM |
1799 | } |
1800 | #endif | |
088ef950 | 1801 | #ifdef CONFIG_ARCH_OMAP2 |
56a25641 | 1802 | if (cpu_is_omap242x()) { |
92105bb7 | 1803 | gpio_bank_count = 4; |
56a25641 | 1804 | gpio_bank = gpio_bank_242x; |
56a25641 SMK |
1805 | } |
1806 | if (cpu_is_omap243x()) { | |
56a25641 SMK |
1807 | gpio_bank_count = 5; |
1808 | gpio_bank = gpio_bank_243x; | |
92105bb7 | 1809 | } |
5492fb1a | 1810 | #endif |
a8eb7ca0 | 1811 | #ifdef CONFIG_ARCH_OMAP3 |
5492fb1a | 1812 | if (cpu_is_omap34xx()) { |
5492fb1a SMK |
1813 | gpio_bank_count = OMAP34XX_NR_GPIOS; |
1814 | gpio_bank = gpio_bank_34xx; | |
5492fb1a | 1815 | } |
44169075 SS |
1816 | #endif |
1817 | #ifdef CONFIG_ARCH_OMAP4 | |
1818 | if (cpu_is_omap44xx()) { | |
44169075 SS |
1819 | gpio_bank_count = OMAP34XX_NR_GPIOS; |
1820 | gpio_bank = gpio_bank_44xx; | |
44169075 | 1821 | } |
5e1c5ff4 TL |
1822 | #endif |
1823 | for (i = 0; i < gpio_bank_count; i++) { | |
1824 | int j, gpio_count = 16; | |
1825 | ||
1826 | bank = &gpio_bank[i]; | |
5e1c5ff4 | 1827 | spin_lock_init(&bank->lock); |
9f7065da TL |
1828 | |
1829 | /* Static mapping, never released */ | |
1830 | bank->base = ioremap(bank->pbase, bank_size); | |
1831 | if (!bank->base) { | |
1832 | printk(KERN_ERR "Could not ioremap gpio bank%i\n", i); | |
1833 | continue; | |
1834 | } | |
1835 | ||
e5c56ed3 | 1836 | if (bank_is_mpuio(bank)) |
7c7095aa | 1837 | __raw_writew(0xffff, bank->base + OMAP_MPUIO_GPIO_MASKIT); |
d11ac979 | 1838 | if (cpu_is_omap15xx() && bank->method == METHOD_GPIO_1510) { |
5e1c5ff4 TL |
1839 | __raw_writew(0xffff, bank->base + OMAP1510_GPIO_INT_MASK); |
1840 | __raw_writew(0x0000, bank->base + OMAP1510_GPIO_INT_STATUS); | |
1841 | } | |
d11ac979 | 1842 | if (cpu_is_omap16xx() && bank->method == METHOD_GPIO_1610) { |
5e1c5ff4 TL |
1843 | __raw_writew(0x0000, bank->base + OMAP1610_GPIO_IRQENABLE1); |
1844 | __raw_writew(0xffff, bank->base + OMAP1610_GPIO_IRQSTATUS1); | |
92105bb7 | 1845 | __raw_writew(0x0014, bank->base + OMAP1610_GPIO_SYSCONFIG); |
5e1c5ff4 | 1846 | } |
7c006926 AB |
1847 | if (cpu_is_omap7xx() && bank->method == METHOD_GPIO_7XX) { |
1848 | __raw_writel(0xffffffff, bank->base + OMAP7XX_GPIO_INT_MASK); | |
1849 | __raw_writel(0x00000000, bank->base + OMAP7XX_GPIO_INT_STATUS); | |
5e1c5ff4 | 1850 | |
7c006926 | 1851 | gpio_count = 32; /* 7xx has 32-bit GPIOs */ |
5e1c5ff4 | 1852 | } |
d11ac979 | 1853 | |
140455fa | 1854 | #ifdef CONFIG_ARCH_OMAP2PLUS |
3f1686a9 TL |
1855 | if ((bank->method == METHOD_GPIO_24XX) || |
1856 | (bank->method == METHOD_GPIO_44XX)) { | |
3ac4fa99 JY |
1857 | static const u32 non_wakeup_gpios[] = { |
1858 | 0xe203ffc0, 0x08700040 | |
1859 | }; | |
3f1686a9 TL |
1860 | |
1861 | if (cpu_is_omap44xx()) { | |
1862 | __raw_writel(0xffffffff, bank->base + | |
78a1a6d3 | 1863 | OMAP4_GPIO_IRQSTATUSCLR0); |
3f1686a9 | 1864 | __raw_writew(0x0015, bank->base + |
78a1a6d3 | 1865 | OMAP4_GPIO_SYSCONFIG); |
3f1686a9 | 1866 | __raw_writel(0x00000000, bank->base + |
78a1a6d3 | 1867 | OMAP4_GPIO_DEBOUNCENABLE); |
3f1686a9 TL |
1868 | /* |
1869 | * Initialize interface clock ungated, | |
1870 | * module enabled | |
1871 | */ | |
1872 | __raw_writel(0, bank->base + OMAP4_GPIO_CTRL); | |
1873 | } else { | |
1874 | __raw_writel(0x00000000, bank->base + | |
1875 | OMAP24XX_GPIO_IRQENABLE1); | |
1876 | __raw_writel(0xffffffff, bank->base + | |
1877 | OMAP24XX_GPIO_IRQSTATUS1); | |
1878 | __raw_writew(0x0015, bank->base + | |
1879 | OMAP24XX_GPIO_SYSCONFIG); | |
1880 | __raw_writel(0x00000000, bank->base + | |
1881 | OMAP24XX_GPIO_DEBOUNCE_EN); | |
1882 | ||
1883 | /* | |
1884 | * Initialize interface clock ungated, | |
1885 | * module enabled | |
1886 | */ | |
1887 | __raw_writel(0, bank->base + | |
1888 | OMAP24XX_GPIO_CTRL); | |
1889 | } | |
a118b5f3 TK |
1890 | if (cpu_is_omap24xx() && |
1891 | i < ARRAY_SIZE(non_wakeup_gpios)) | |
3ac4fa99 | 1892 | bank->non_wakeup_gpios = non_wakeup_gpios[i]; |
92105bb7 TL |
1893 | gpio_count = 32; |
1894 | } | |
5e1c5ff4 | 1895 | #endif |
058af1ea C |
1896 | |
1897 | bank->mod_usage = 0; | |
52e31344 DB |
1898 | /* REVISIT eventually switch from OMAP-specific gpio structs |
1899 | * over to the generic ones | |
1900 | */ | |
3ff164e1 JN |
1901 | bank->chip.request = omap_gpio_request; |
1902 | bank->chip.free = omap_gpio_free; | |
52e31344 DB |
1903 | bank->chip.direction_input = gpio_input; |
1904 | bank->chip.get = gpio_get; | |
1905 | bank->chip.direction_output = gpio_output; | |
168ef3d9 | 1906 | bank->chip.set_debounce = gpio_debounce; |
52e31344 | 1907 | bank->chip.set = gpio_set; |
a007b709 | 1908 | bank->chip.to_irq = gpio_2irq; |
52e31344 DB |
1909 | if (bank_is_mpuio(bank)) { |
1910 | bank->chip.label = "mpuio"; | |
69114a47 | 1911 | #ifdef CONFIG_ARCH_OMAP16XX |
d8f388d8 DB |
1912 | bank->chip.dev = &omap_mpuio_device.dev; |
1913 | #endif | |
52e31344 DB |
1914 | bank->chip.base = OMAP_MPUIO(0); |
1915 | } else { | |
1916 | bank->chip.label = "gpio"; | |
1917 | bank->chip.base = gpio; | |
1918 | gpio += gpio_count; | |
1919 | } | |
1920 | bank->chip.ngpio = gpio_count; | |
1921 | ||
1922 | gpiochip_add(&bank->chip); | |
1923 | ||
5e1c5ff4 TL |
1924 | for (j = bank->virtual_irq_start; |
1925 | j < bank->virtual_irq_start + gpio_count; j++) { | |
8ba55c5c | 1926 | lockdep_set_class(&irq_desc[j].lock, &gpio_lock_class); |
58781016 | 1927 | set_irq_chip_data(j, bank); |
e5c56ed3 | 1928 | if (bank_is_mpuio(bank)) |
5e1c5ff4 TL |
1929 | set_irq_chip(j, &mpuio_irq_chip); |
1930 | else | |
1931 | set_irq_chip(j, &gpio_irq_chip); | |
10dd5ce2 | 1932 | set_irq_handler(j, handle_simple_irq); |
5e1c5ff4 TL |
1933 | set_irq_flags(j, IRQF_VALID); |
1934 | } | |
1935 | set_irq_chained_handler(bank->irq, gpio_irq_handler); | |
1936 | set_irq_data(bank->irq, bank); | |
89db9482 | 1937 | |
44169075 | 1938 | if (cpu_is_omap34xx() || cpu_is_omap44xx()) { |
89db9482 JH |
1939 | sprintf(clk_name, "gpio%d_dbck", i + 1); |
1940 | bank->dbck = clk_get(NULL, clk_name); | |
1941 | if (IS_ERR(bank->dbck)) | |
1942 | printk(KERN_ERR "Could not get %s\n", clk_name); | |
1943 | } | |
5e1c5ff4 TL |
1944 | } |
1945 | ||
1946 | /* Enable system clock for GPIO module. | |
1947 | * The CAM_CLK_CTRL *is* really the right place. */ | |
92105bb7 | 1948 | if (cpu_is_omap16xx()) |
5e1c5ff4 TL |
1949 | omap_writel(omap_readl(ULPD_CAM_CLK_CTRL) | 0x04, ULPD_CAM_CLK_CTRL); |
1950 | ||
14f1c3bf JY |
1951 | /* Enable autoidle for the OCP interface */ |
1952 | if (cpu_is_omap24xx()) | |
1953 | omap_writel(1 << 0, 0x48019010); | |
5492fb1a SMK |
1954 | if (cpu_is_omap34xx()) |
1955 | omap_writel(1 << 0, 0x48306814); | |
d11ac979 | 1956 | |
9f7065da TL |
1957 | omap_gpio_show_rev(); |
1958 | ||
5e1c5ff4 TL |
1959 | return 0; |
1960 | } | |
1961 | ||
140455fa | 1962 | #if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP2PLUS) |
92105bb7 TL |
1963 | static int omap_gpio_suspend(struct sys_device *dev, pm_message_t mesg) |
1964 | { | |
1965 | int i; | |
1966 | ||
5492fb1a | 1967 | if (!cpu_class_is_omap2() && !cpu_is_omap16xx()) |
92105bb7 TL |
1968 | return 0; |
1969 | ||
1970 | for (i = 0; i < gpio_bank_count; i++) { | |
1971 | struct gpio_bank *bank = &gpio_bank[i]; | |
1972 | void __iomem *wake_status; | |
1973 | void __iomem *wake_clear; | |
1974 | void __iomem *wake_set; | |
a6472533 | 1975 | unsigned long flags; |
92105bb7 TL |
1976 | |
1977 | switch (bank->method) { | |
e5c56ed3 | 1978 | #ifdef CONFIG_ARCH_OMAP16XX |
92105bb7 TL |
1979 | case METHOD_GPIO_1610: |
1980 | wake_status = bank->base + OMAP1610_GPIO_WAKEUPENABLE; | |
1981 | wake_clear = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA; | |
1982 | wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA; | |
1983 | break; | |
e5c56ed3 | 1984 | #endif |
a8eb7ca0 | 1985 | #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) |
92105bb7 | 1986 | case METHOD_GPIO_24XX: |
723fdb78 | 1987 | wake_status = bank->base + OMAP24XX_GPIO_WAKE_EN; |
92105bb7 TL |
1988 | wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA; |
1989 | wake_set = bank->base + OMAP24XX_GPIO_SETWKUENA; | |
1990 | break; | |
78a1a6d3 SR |
1991 | #endif |
1992 | #ifdef CONFIG_ARCH_OMAP4 | |
3f1686a9 | 1993 | case METHOD_GPIO_44XX: |
78a1a6d3 SR |
1994 | wake_status = bank->base + OMAP4_GPIO_IRQWAKEN0; |
1995 | wake_clear = bank->base + OMAP4_GPIO_IRQWAKEN0; | |
1996 | wake_set = bank->base + OMAP4_GPIO_IRQWAKEN0; | |
1997 | break; | |
e5c56ed3 | 1998 | #endif |
92105bb7 TL |
1999 | default: |
2000 | continue; | |
2001 | } | |
2002 | ||
a6472533 | 2003 | spin_lock_irqsave(&bank->lock, flags); |
92105bb7 TL |
2004 | bank->saved_wakeup = __raw_readl(wake_status); |
2005 | __raw_writel(0xffffffff, wake_clear); | |
2006 | __raw_writel(bank->suspend_wakeup, wake_set); | |
a6472533 | 2007 | spin_unlock_irqrestore(&bank->lock, flags); |
92105bb7 TL |
2008 | } |
2009 | ||
2010 | return 0; | |
2011 | } | |
2012 | ||
2013 | static int omap_gpio_resume(struct sys_device *dev) | |
2014 | { | |
2015 | int i; | |
2016 | ||
723fdb78 | 2017 | if (!cpu_class_is_omap2() && !cpu_is_omap16xx()) |
92105bb7 TL |
2018 | return 0; |
2019 | ||
2020 | for (i = 0; i < gpio_bank_count; i++) { | |
2021 | struct gpio_bank *bank = &gpio_bank[i]; | |
2022 | void __iomem *wake_clear; | |
2023 | void __iomem *wake_set; | |
a6472533 | 2024 | unsigned long flags; |
92105bb7 TL |
2025 | |
2026 | switch (bank->method) { | |
e5c56ed3 | 2027 | #ifdef CONFIG_ARCH_OMAP16XX |
92105bb7 TL |
2028 | case METHOD_GPIO_1610: |
2029 | wake_clear = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA; | |
2030 | wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA; | |
2031 | break; | |
e5c56ed3 | 2032 | #endif |
a8eb7ca0 | 2033 | #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) |
92105bb7 | 2034 | case METHOD_GPIO_24XX: |
0d9356cb TL |
2035 | wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA; |
2036 | wake_set = bank->base + OMAP24XX_GPIO_SETWKUENA; | |
92105bb7 | 2037 | break; |
78a1a6d3 SR |
2038 | #endif |
2039 | #ifdef CONFIG_ARCH_OMAP4 | |
3f1686a9 | 2040 | case METHOD_GPIO_44XX: |
78a1a6d3 SR |
2041 | wake_clear = bank->base + OMAP4_GPIO_IRQWAKEN0; |
2042 | wake_set = bank->base + OMAP4_GPIO_IRQWAKEN0; | |
2043 | break; | |
e5c56ed3 | 2044 | #endif |
92105bb7 TL |
2045 | default: |
2046 | continue; | |
2047 | } | |
2048 | ||
a6472533 | 2049 | spin_lock_irqsave(&bank->lock, flags); |
92105bb7 TL |
2050 | __raw_writel(0xffffffff, wake_clear); |
2051 | __raw_writel(bank->saved_wakeup, wake_set); | |
a6472533 | 2052 | spin_unlock_irqrestore(&bank->lock, flags); |
92105bb7 TL |
2053 | } |
2054 | ||
2055 | return 0; | |
2056 | } | |
2057 | ||
2058 | static struct sysdev_class omap_gpio_sysclass = { | |
af5ca3f4 | 2059 | .name = "gpio", |
92105bb7 TL |
2060 | .suspend = omap_gpio_suspend, |
2061 | .resume = omap_gpio_resume, | |
2062 | }; | |
2063 | ||
2064 | static struct sys_device omap_gpio_device = { | |
2065 | .id = 0, | |
2066 | .cls = &omap_gpio_sysclass, | |
2067 | }; | |
3ac4fa99 JY |
2068 | |
2069 | #endif | |
2070 | ||
140455fa | 2071 | #ifdef CONFIG_ARCH_OMAP2PLUS |
3ac4fa99 JY |
2072 | |
2073 | static int workaround_enabled; | |
2074 | ||
43ffcd9a | 2075 | void omap2_gpio_prepare_for_idle(int power_state) |
3ac4fa99 JY |
2076 | { |
2077 | int i, c = 0; | |
a118b5f3 | 2078 | int min = 0; |
3ac4fa99 | 2079 | |
a118b5f3 TK |
2080 | if (cpu_is_omap34xx()) |
2081 | min = 1; | |
43ffcd9a | 2082 | |
a118b5f3 | 2083 | for (i = min; i < gpio_bank_count; i++) { |
3ac4fa99 JY |
2084 | struct gpio_bank *bank = &gpio_bank[i]; |
2085 | u32 l1, l2; | |
2086 | ||
8865b9b6 KH |
2087 | if (bank->dbck_enable_mask) |
2088 | clk_disable(bank->dbck); | |
2089 | ||
43ffcd9a KH |
2090 | if (power_state > PWRDM_POWER_OFF) |
2091 | continue; | |
2092 | ||
2093 | /* If going to OFF, remove triggering for all | |
2094 | * non-wakeup GPIOs. Otherwise spurious IRQs will be | |
2095 | * generated. See OMAP2420 Errata item 1.101. */ | |
3ac4fa99 JY |
2096 | if (!(bank->enabled_non_wakeup_gpios)) |
2097 | continue; | |
3f1686a9 TL |
2098 | |
2099 | if (cpu_is_omap24xx() || cpu_is_omap34xx()) { | |
2100 | bank->saved_datain = __raw_readl(bank->base + | |
2101 | OMAP24XX_GPIO_DATAIN); | |
2102 | l1 = __raw_readl(bank->base + | |
2103 | OMAP24XX_GPIO_FALLINGDETECT); | |
2104 | l2 = __raw_readl(bank->base + | |
2105 | OMAP24XX_GPIO_RISINGDETECT); | |
2106 | } | |
2107 | ||
2108 | if (cpu_is_omap44xx()) { | |
2109 | bank->saved_datain = __raw_readl(bank->base + | |
2110 | OMAP4_GPIO_DATAIN); | |
2111 | l1 = __raw_readl(bank->base + | |
2112 | OMAP4_GPIO_FALLINGDETECT); | |
2113 | l2 = __raw_readl(bank->base + | |
2114 | OMAP4_GPIO_RISINGDETECT); | |
2115 | } | |
2116 | ||
3ac4fa99 JY |
2117 | bank->saved_fallingdetect = l1; |
2118 | bank->saved_risingdetect = l2; | |
2119 | l1 &= ~bank->enabled_non_wakeup_gpios; | |
2120 | l2 &= ~bank->enabled_non_wakeup_gpios; | |
3f1686a9 TL |
2121 | |
2122 | if (cpu_is_omap24xx() || cpu_is_omap34xx()) { | |
2123 | __raw_writel(l1, bank->base + | |
2124 | OMAP24XX_GPIO_FALLINGDETECT); | |
2125 | __raw_writel(l2, bank->base + | |
2126 | OMAP24XX_GPIO_RISINGDETECT); | |
2127 | } | |
2128 | ||
2129 | if (cpu_is_omap44xx()) { | |
2130 | __raw_writel(l1, bank->base + OMAP4_GPIO_FALLINGDETECT); | |
2131 | __raw_writel(l2, bank->base + OMAP4_GPIO_RISINGDETECT); | |
2132 | } | |
2133 | ||
3ac4fa99 JY |
2134 | c++; |
2135 | } | |
2136 | if (!c) { | |
2137 | workaround_enabled = 0; | |
2138 | return; | |
2139 | } | |
2140 | workaround_enabled = 1; | |
2141 | } | |
2142 | ||
43ffcd9a | 2143 | void omap2_gpio_resume_after_idle(void) |
3ac4fa99 JY |
2144 | { |
2145 | int i; | |
a118b5f3 | 2146 | int min = 0; |
3ac4fa99 | 2147 | |
a118b5f3 TK |
2148 | if (cpu_is_omap34xx()) |
2149 | min = 1; | |
2150 | for (i = min; i < gpio_bank_count; i++) { | |
3ac4fa99 | 2151 | struct gpio_bank *bank = &gpio_bank[i]; |
82dbb9d3 | 2152 | u32 l, gen, gen0, gen1; |
3ac4fa99 | 2153 | |
8865b9b6 KH |
2154 | if (bank->dbck_enable_mask) |
2155 | clk_enable(bank->dbck); | |
2156 | ||
43ffcd9a KH |
2157 | if (!workaround_enabled) |
2158 | continue; | |
2159 | ||
3ac4fa99 JY |
2160 | if (!(bank->enabled_non_wakeup_gpios)) |
2161 | continue; | |
3f1686a9 TL |
2162 | |
2163 | if (cpu_is_omap24xx() || cpu_is_omap34xx()) { | |
2164 | __raw_writel(bank->saved_fallingdetect, | |
3ac4fa99 | 2165 | bank->base + OMAP24XX_GPIO_FALLINGDETECT); |
3f1686a9 | 2166 | __raw_writel(bank->saved_risingdetect, |
3ac4fa99 | 2167 | bank->base + OMAP24XX_GPIO_RISINGDETECT); |
3f1686a9 TL |
2168 | l = __raw_readl(bank->base + OMAP24XX_GPIO_DATAIN); |
2169 | } | |
2170 | ||
2171 | if (cpu_is_omap44xx()) { | |
2172 | __raw_writel(bank->saved_fallingdetect, | |
78a1a6d3 | 2173 | bank->base + OMAP4_GPIO_FALLINGDETECT); |
3f1686a9 | 2174 | __raw_writel(bank->saved_risingdetect, |
78a1a6d3 | 2175 | bank->base + OMAP4_GPIO_RISINGDETECT); |
3f1686a9 TL |
2176 | l = __raw_readl(bank->base + OMAP4_GPIO_DATAIN); |
2177 | } | |
2178 | ||
3ac4fa99 JY |
2179 | /* Check if any of the non-wakeup interrupt GPIOs have changed |
2180 | * state. If so, generate an IRQ by software. This is | |
2181 | * horribly racy, but it's the best we can do to work around | |
2182 | * this silicon bug. */ | |
3ac4fa99 | 2183 | l ^= bank->saved_datain; |
a118b5f3 | 2184 | l &= bank->enabled_non_wakeup_gpios; |
82dbb9d3 EN |
2185 | |
2186 | /* | |
2187 | * No need to generate IRQs for the rising edge for gpio IRQs | |
2188 | * configured with falling edge only; and vice versa. | |
2189 | */ | |
2190 | gen0 = l & bank->saved_fallingdetect; | |
2191 | gen0 &= bank->saved_datain; | |
2192 | ||
2193 | gen1 = l & bank->saved_risingdetect; | |
2194 | gen1 &= ~(bank->saved_datain); | |
2195 | ||
2196 | /* FIXME: Consider GPIO IRQs with level detections properly! */ | |
2197 | gen = l & (~(bank->saved_fallingdetect) & | |
2198 | ~(bank->saved_risingdetect)); | |
2199 | /* Consider all GPIO IRQs needed to be updated */ | |
2200 | gen |= gen0 | gen1; | |
2201 | ||
2202 | if (gen) { | |
3ac4fa99 | 2203 | u32 old0, old1; |
3f1686a9 | 2204 | |
f00d6497 | 2205 | if (cpu_is_omap24xx() || cpu_is_omap34xx()) { |
3f1686a9 TL |
2206 | old0 = __raw_readl(bank->base + |
2207 | OMAP24XX_GPIO_LEVELDETECT0); | |
2208 | old1 = __raw_readl(bank->base + | |
2209 | OMAP24XX_GPIO_LEVELDETECT1); | |
f00d6497 | 2210 | __raw_writel(old0 | gen, bank->base + |
82dbb9d3 | 2211 | OMAP24XX_GPIO_LEVELDETECT0); |
f00d6497 | 2212 | __raw_writel(old1 | gen, bank->base + |
82dbb9d3 | 2213 | OMAP24XX_GPIO_LEVELDETECT1); |
f00d6497 | 2214 | __raw_writel(old0, bank->base + |
3f1686a9 | 2215 | OMAP24XX_GPIO_LEVELDETECT0); |
f00d6497 | 2216 | __raw_writel(old1, bank->base + |
3f1686a9 TL |
2217 | OMAP24XX_GPIO_LEVELDETECT1); |
2218 | } | |
2219 | ||
2220 | if (cpu_is_omap44xx()) { | |
2221 | old0 = __raw_readl(bank->base + | |
78a1a6d3 | 2222 | OMAP4_GPIO_LEVELDETECT0); |
3f1686a9 | 2223 | old1 = __raw_readl(bank->base + |
78a1a6d3 | 2224 | OMAP4_GPIO_LEVELDETECT1); |
3f1686a9 | 2225 | __raw_writel(old0 | l, bank->base + |
78a1a6d3 | 2226 | OMAP4_GPIO_LEVELDETECT0); |
3f1686a9 | 2227 | __raw_writel(old1 | l, bank->base + |
78a1a6d3 | 2228 | OMAP4_GPIO_LEVELDETECT1); |
3f1686a9 | 2229 | __raw_writel(old0, bank->base + |
78a1a6d3 | 2230 | OMAP4_GPIO_LEVELDETECT0); |
3f1686a9 | 2231 | __raw_writel(old1, bank->base + |
78a1a6d3 | 2232 | OMAP4_GPIO_LEVELDETECT1); |
3f1686a9 | 2233 | } |
3ac4fa99 JY |
2234 | } |
2235 | } | |
2236 | ||
2237 | } | |
2238 | ||
92105bb7 TL |
2239 | #endif |
2240 | ||
a8eb7ca0 | 2241 | #ifdef CONFIG_ARCH_OMAP3 |
40c670f0 RN |
2242 | /* save the registers of bank 2-6 */ |
2243 | void omap_gpio_save_context(void) | |
2244 | { | |
2245 | int i; | |
2246 | ||
2247 | /* saving banks from 2-6 only since GPIO1 is in WKUP */ | |
2248 | for (i = 1; i < gpio_bank_count; i++) { | |
2249 | struct gpio_bank *bank = &gpio_bank[i]; | |
2250 | gpio_context[i].sysconfig = | |
2251 | __raw_readl(bank->base + OMAP24XX_GPIO_SYSCONFIG); | |
2252 | gpio_context[i].irqenable1 = | |
2253 | __raw_readl(bank->base + OMAP24XX_GPIO_IRQENABLE1); | |
2254 | gpio_context[i].irqenable2 = | |
2255 | __raw_readl(bank->base + OMAP24XX_GPIO_IRQENABLE2); | |
2256 | gpio_context[i].wake_en = | |
2257 | __raw_readl(bank->base + OMAP24XX_GPIO_WAKE_EN); | |
2258 | gpio_context[i].ctrl = | |
2259 | __raw_readl(bank->base + OMAP24XX_GPIO_CTRL); | |
2260 | gpio_context[i].oe = | |
2261 | __raw_readl(bank->base + OMAP24XX_GPIO_OE); | |
2262 | gpio_context[i].leveldetect0 = | |
2263 | __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT0); | |
2264 | gpio_context[i].leveldetect1 = | |
2265 | __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT1); | |
2266 | gpio_context[i].risingdetect = | |
2267 | __raw_readl(bank->base + OMAP24XX_GPIO_RISINGDETECT); | |
2268 | gpio_context[i].fallingdetect = | |
2269 | __raw_readl(bank->base + OMAP24XX_GPIO_FALLINGDETECT); | |
2270 | gpio_context[i].dataout = | |
2271 | __raw_readl(bank->base + OMAP24XX_GPIO_DATAOUT); | |
40c670f0 RN |
2272 | } |
2273 | } | |
2274 | ||
2275 | /* restore the required registers of bank 2-6 */ | |
2276 | void omap_gpio_restore_context(void) | |
2277 | { | |
2278 | int i; | |
2279 | ||
2280 | for (i = 1; i < gpio_bank_count; i++) { | |
2281 | struct gpio_bank *bank = &gpio_bank[i]; | |
2282 | __raw_writel(gpio_context[i].sysconfig, | |
2283 | bank->base + OMAP24XX_GPIO_SYSCONFIG); | |
2284 | __raw_writel(gpio_context[i].irqenable1, | |
2285 | bank->base + OMAP24XX_GPIO_IRQENABLE1); | |
2286 | __raw_writel(gpio_context[i].irqenable2, | |
2287 | bank->base + OMAP24XX_GPIO_IRQENABLE2); | |
2288 | __raw_writel(gpio_context[i].wake_en, | |
2289 | bank->base + OMAP24XX_GPIO_WAKE_EN); | |
2290 | __raw_writel(gpio_context[i].ctrl, | |
2291 | bank->base + OMAP24XX_GPIO_CTRL); | |
2292 | __raw_writel(gpio_context[i].oe, | |
2293 | bank->base + OMAP24XX_GPIO_OE); | |
2294 | __raw_writel(gpio_context[i].leveldetect0, | |
2295 | bank->base + OMAP24XX_GPIO_LEVELDETECT0); | |
2296 | __raw_writel(gpio_context[i].leveldetect1, | |
2297 | bank->base + OMAP24XX_GPIO_LEVELDETECT1); | |
2298 | __raw_writel(gpio_context[i].risingdetect, | |
2299 | bank->base + OMAP24XX_GPIO_RISINGDETECT); | |
2300 | __raw_writel(gpio_context[i].fallingdetect, | |
2301 | bank->base + OMAP24XX_GPIO_FALLINGDETECT); | |
2302 | __raw_writel(gpio_context[i].dataout, | |
2303 | bank->base + OMAP24XX_GPIO_DATAOUT); | |
40c670f0 RN |
2304 | } |
2305 | } | |
2306 | #endif | |
2307 | ||
5e1c5ff4 TL |
2308 | /* |
2309 | * This may get called early from board specific init | |
1a8bfa1e | 2310 | * for boards that have interrupts routed via FPGA. |
5e1c5ff4 | 2311 | */ |
277d58ef | 2312 | int __init omap_gpio_init(void) |
5e1c5ff4 TL |
2313 | { |
2314 | if (!initialized) | |
2315 | return _omap_gpio_init(); | |
2316 | else | |
2317 | return 0; | |
2318 | } | |
2319 | ||
92105bb7 TL |
2320 | static int __init omap_gpio_sysinit(void) |
2321 | { | |
2322 | int ret = 0; | |
2323 | ||
2324 | if (!initialized) | |
2325 | ret = _omap_gpio_init(); | |
2326 | ||
11a78b79 DB |
2327 | mpuio_init(); |
2328 | ||
140455fa | 2329 | #if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP2PLUS) |
5492fb1a | 2330 | if (cpu_is_omap16xx() || cpu_class_is_omap2()) { |
92105bb7 TL |
2331 | if (ret == 0) { |
2332 | ret = sysdev_class_register(&omap_gpio_sysclass); | |
2333 | if (ret == 0) | |
2334 | ret = sysdev_register(&omap_gpio_device); | |
2335 | } | |
2336 | } | |
2337 | #endif | |
2338 | ||
2339 | return ret; | |
2340 | } | |
2341 | ||
92105bb7 | 2342 | arch_initcall(omap_gpio_sysinit); |