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4c98dc6b TL |
1 | /* |
2 | * arch/arm/plat-omap/include/mach/fpga.h | |
3 | * | |
4 | * Interrupt handler for OMAP-1510 FPGA | |
5 | * | |
6 | * Copyright (C) 2001 RidgeRun, Inc. | |
7 | * Author: Greg Lonnon <glonnon@ridgerun.com> | |
8 | * | |
9 | * Copyright (C) 2002 MontaVista Software, Inc. | |
10 | * | |
11 | * Separated FPGA interrupts from innovator1510.c and cleaned up for 2.6 | |
12 | * Copyright (C) 2004 Nokia Corporation by Tony Lindrgen <tony@atomide.com> | |
13 | * | |
14 | * This program is free software; you can redistribute it and/or modify | |
15 | * it under the terms of the GNU General Public License version 2 as | |
16 | * published by the Free Software Foundation. | |
17 | */ | |
18 | ||
19 | #ifndef __ASM_ARCH_OMAP_FPGA_H | |
20 | #define __ASM_ARCH_OMAP_FPGA_H | |
21 | ||
22 | /* | |
23 | * --------------------------------------------------------------------------- | |
24 | * H2/P2 Debug board FPGA | |
25 | * --------------------------------------------------------------------------- | |
26 | */ | |
27 | /* maps in the FPGA registers and the ETHR registers */ | |
28 | #define H2P2_DBG_FPGA_BASE 0xE8000000 /* VA */ | |
29 | #define H2P2_DBG_FPGA_SIZE SZ_4K /* SIZE */ | |
30 | #define H2P2_DBG_FPGA_START 0x04000000 /* PA */ | |
31 | ||
32 | #define H2P2_DBG_FPGA_ETHR_START (H2P2_DBG_FPGA_START + 0x300) | |
33 | #define H2P2_DBG_FPGA_FPGA_REV IOMEM(H2P2_DBG_FPGA_BASE + 0x10) /* FPGA Revision */ | |
34 | #define H2P2_DBG_FPGA_BOARD_REV IOMEM(H2P2_DBG_FPGA_BASE + 0x12) /* Board Revision */ | |
35 | #define H2P2_DBG_FPGA_GPIO IOMEM(H2P2_DBG_FPGA_BASE + 0x14) /* GPIO outputs */ | |
36 | #define H2P2_DBG_FPGA_LEDS IOMEM(H2P2_DBG_FPGA_BASE + 0x16) /* LEDs outputs */ | |
37 | #define H2P2_DBG_FPGA_MISC_INPUTS IOMEM(H2P2_DBG_FPGA_BASE + 0x18) /* Misc inputs */ | |
38 | #define H2P2_DBG_FPGA_LAN_STATUS IOMEM(H2P2_DBG_FPGA_BASE + 0x1A) /* LAN Status line */ | |
39 | #define H2P2_DBG_FPGA_LAN_RESET IOMEM(H2P2_DBG_FPGA_BASE + 0x1C) /* LAN Reset line */ | |
40 | ||
41 | /* NOTE: most boards don't have a static mapping for the FPGA ... */ | |
42 | struct h2p2_dbg_fpga { | |
43 | /* offset 0x00 */ | |
44 | u16 smc91x[8]; | |
45 | /* offset 0x10 */ | |
46 | u16 fpga_rev; | |
47 | u16 board_rev; | |
48 | u16 gpio_outputs; | |
49 | u16 leds; | |
50 | /* offset 0x18 */ | |
51 | u16 misc_inputs; | |
52 | u16 lan_status; | |
53 | u16 lan_reset; | |
54 | u16 reserved0; | |
55 | /* offset 0x20 */ | |
56 | u16 ps2_data; | |
57 | u16 ps2_ctrl; | |
58 | /* plus also 4 rs232 ports ... */ | |
59 | }; | |
60 | ||
61 | /* LEDs definition on debug board (16 LEDs, all physically green) */ | |
62 | #define H2P2_DBG_FPGA_LED_GREEN (1 << 15) | |
63 | #define H2P2_DBG_FPGA_LED_AMBER (1 << 14) | |
64 | #define H2P2_DBG_FPGA_LED_RED (1 << 13) | |
65 | #define H2P2_DBG_FPGA_LED_BLUE (1 << 12) | |
66 | /* cpu0 load-meter LEDs */ | |
67 | #define H2P2_DBG_FPGA_LOAD_METER (1 << 0) // A bit of fun on our board ... | |
68 | #define H2P2_DBG_FPGA_LOAD_METER_SIZE 11 | |
69 | #define H2P2_DBG_FPGA_LOAD_METER_MASK ((1 << H2P2_DBG_FPGA_LOAD_METER_SIZE) - 1) | |
70 | ||
71 | #define H2P2_DBG_FPGA_P2_LED_TIMER (1 << 0) | |
72 | #define H2P2_DBG_FPGA_P2_LED_IDLE (1 << 1) | |
73 | ||
74 | #endif |