Commit | Line | Data |
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d2912cb1 | 1 | // SPDX-License-Identifier: GPL-2.0-only |
5e1c5ff4 TL |
2 | /* |
3 | * linux/arch/arm/plat-omap/dma.c | |
4 | * | |
97b7f715 | 5 | * Copyright (C) 2003 - 2008 Nokia Corporation |
96de0e25 | 6 | * Author: Juha Yrjölä <juha.yrjola@nokia.com> |
5e1c5ff4 TL |
7 | * DMA channel linking for 1610 by Samuel Ortiz <samuel.ortiz@nokia.com> |
8 | * Graphics DMA and LCD DMA graphics tranformations | |
9 | * by Imre Deak <imre.deak@nokia.com> | |
f8151e5c | 10 | * OMAP2/3 support Copyright (C) 2004-2007 Texas Instruments, Inc. |
1a8bfa1e | 11 | * Merged to support both OMAP1 and OMAP2 by Tony Lindgren <tony@atomide.com> |
5e1c5ff4 TL |
12 | * Some functions based on earlier dma-omap.c Copyright (C) 2001 RidgeRun, Inc. |
13 | * | |
44169075 SS |
14 | * Copyright (C) 2009 Texas Instruments |
15 | * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com> | |
16 | * | |
5e1c5ff4 TL |
17 | * Support functions for the OMAP internal DMA channels. |
18 | * | |
f31cc962 MK |
19 | * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/ |
20 | * Converted DMA library into DMA platform driver. | |
21 | * - G, Manjunath Kondaiah <manjugk@ti.com> | |
5e1c5ff4 TL |
22 | */ |
23 | ||
24 | #include <linux/module.h> | |
25 | #include <linux/init.h> | |
26 | #include <linux/sched.h> | |
27 | #include <linux/spinlock.h> | |
28 | #include <linux/errno.h> | |
29 | #include <linux/interrupt.h> | |
418ca1f0 | 30 | #include <linux/irq.h> |
97b7f715 | 31 | #include <linux/io.h> |
5a0e3ad6 | 32 | #include <linux/slab.h> |
0e4905c0 | 33 | #include <linux/delay.h> |
5e1c5ff4 | 34 | |
45c3eb7d | 35 | #include <linux/omap-dma.h> |
5e1c5ff4 | 36 | |
685e2d08 TL |
37 | #ifdef CONFIG_ARCH_OMAP1 |
38 | #include <mach/soc.h> | |
39 | #endif | |
40 | ||
bc4d8b5f PW |
41 | /* |
42 | * MAX_LOGICAL_DMA_CH_COUNT: the maximum number of logical DMA | |
43 | * channels that an instance of the SDMA IP block can support. Used | |
44 | * to size arrays. (The actual maximum on a particular SoC may be less | |
45 | * than this -- for example, OMAP1 SDMA instances only support 17 logical | |
46 | * DMA channels.) | |
47 | */ | |
48 | #define MAX_LOGICAL_DMA_CH_COUNT 32 | |
49 | ||
f8151e5c AG |
50 | #undef DEBUG |
51 | ||
52 | #ifndef CONFIG_ARCH_OMAP1 | |
53 | enum { DMA_CH_ALLOC_DONE, DMA_CH_PARAMS_SET_DONE, DMA_CH_STARTED, | |
54 | DMA_CH_QUEUED, DMA_CH_NOTSTARTED, DMA_CH_PAUSED, DMA_CH_LINK_ENABLED | |
55 | }; | |
56 | ||
57 | enum { DMA_CHAIN_STARTED, DMA_CHAIN_NOTSTARTED }; | |
1a8bfa1e | 58 | #endif |
5e1c5ff4 | 59 | |
97b7f715 | 60 | #define OMAP_DMA_ACTIVE 0x01 |
4fb699b4 | 61 | #define OMAP2_DMA_CSR_CLEAR_MASK 0xffffffff |
5e1c5ff4 | 62 | |
97b7f715 | 63 | #define OMAP_FUNC_MUX_ARM_BASE (0xfffe1000 + 0xec) |
5e1c5ff4 | 64 | |
f31cc962 MK |
65 | static struct omap_system_dma_plat_info *p; |
66 | static struct omap_dma_dev_attr *d; | |
175655bd TL |
67 | static void omap_clear_dma(int lch); |
68 | static int omap_dma_set_prio_lch(int lch, unsigned char read_prio, | |
69 | unsigned char write_prio); | |
97b7f715 | 70 | static int enable_1510_mode; |
d3c9be2f | 71 | static u32 errata; |
5e1c5ff4 | 72 | |
f2d11858 TK |
73 | static struct omap_dma_global_context_registers { |
74 | u32 dma_irqenable_l0; | |
9ce2482f | 75 | u32 dma_irqenable_l1; |
f2d11858 TK |
76 | u32 dma_ocp_sysconfig; |
77 | u32 dma_gcr; | |
78 | } omap_dma_global_context; | |
79 | ||
f8151e5c AG |
80 | struct dma_link_info { |
81 | int *linked_dmach_q; | |
82 | int no_of_lchs_linked; | |
83 | ||
84 | int q_count; | |
85 | int q_tail; | |
86 | int q_head; | |
87 | ||
88 | int chain_state; | |
89 | int chain_mode; | |
90 | ||
91 | }; | |
92 | ||
4d96372e TL |
93 | static struct dma_link_info *dma_linked_lch; |
94 | ||
95 | #ifndef CONFIG_ARCH_OMAP1 | |
f8151e5c AG |
96 | |
97 | /* Chain handling macros */ | |
98 | #define OMAP_DMA_CHAIN_QINIT(chain_id) \ | |
99 | do { \ | |
100 | dma_linked_lch[chain_id].q_head = \ | |
101 | dma_linked_lch[chain_id].q_tail = \ | |
102 | dma_linked_lch[chain_id].q_count = 0; \ | |
103 | } while (0) | |
104 | #define OMAP_DMA_CHAIN_QFULL(chain_id) \ | |
105 | (dma_linked_lch[chain_id].no_of_lchs_linked == \ | |
106 | dma_linked_lch[chain_id].q_count) | |
107 | #define OMAP_DMA_CHAIN_QLAST(chain_id) \ | |
108 | do { \ | |
109 | ((dma_linked_lch[chain_id].no_of_lchs_linked-1) == \ | |
110 | dma_linked_lch[chain_id].q_count) \ | |
111 | } while (0) | |
112 | #define OMAP_DMA_CHAIN_QEMPTY(chain_id) \ | |
113 | (0 == dma_linked_lch[chain_id].q_count) | |
114 | #define __OMAP_DMA_CHAIN_INCQ(end) \ | |
115 | ((end) = ((end)+1) % dma_linked_lch[chain_id].no_of_lchs_linked) | |
116 | #define OMAP_DMA_CHAIN_INCQHEAD(chain_id) \ | |
117 | do { \ | |
118 | __OMAP_DMA_CHAIN_INCQ(dma_linked_lch[chain_id].q_head); \ | |
119 | dma_linked_lch[chain_id].q_count--; \ | |
120 | } while (0) | |
121 | ||
122 | #define OMAP_DMA_CHAIN_INCQTAIL(chain_id) \ | |
123 | do { \ | |
124 | __OMAP_DMA_CHAIN_INCQ(dma_linked_lch[chain_id].q_tail); \ | |
125 | dma_linked_lch[chain_id].q_count++; \ | |
126 | } while (0) | |
127 | #endif | |
4d96372e TL |
128 | |
129 | static int dma_lch_count; | |
5e1c5ff4 | 130 | static int dma_chan_count; |
2263f022 | 131 | static int omap_dma_reserve_channels; |
5e1c5ff4 TL |
132 | |
133 | static spinlock_t dma_chan_lock; | |
4d96372e | 134 | static struct omap_dma_lch *dma_chan; |
5e1c5ff4 | 135 | |
f8151e5c AG |
136 | static inline void disable_lnk(int lch); |
137 | static void omap_disable_channel_irq(int lch); | |
138 | static inline void omap_enable_channel_irq(int lch); | |
139 | ||
1a8bfa1e | 140 | #define REVISIT_24XX() printk(KERN_ERR "FIXME: no %s on 24xx\n", \ |
8e86f427 | 141 | __func__); |
1a8bfa1e TL |
142 | |
143 | #ifdef CONFIG_ARCH_OMAP15XX | |
144 | /* Returns 1 if the DMA module is in OMAP1510-compatible mode, 0 otherwise */ | |
c7767582 | 145 | static int omap_dma_in_1510_mode(void) |
1a8bfa1e TL |
146 | { |
147 | return enable_1510_mode; | |
148 | } | |
149 | #else | |
150 | #define omap_dma_in_1510_mode() 0 | |
151 | #endif | |
152 | ||
153 | #ifdef CONFIG_ARCH_OMAP1 | |
5e1c5ff4 TL |
154 | static inline void set_gdma_dev(int req, int dev) |
155 | { | |
156 | u32 reg = OMAP_FUNC_MUX_ARM_BASE + ((req - 1) / 5) * 4; | |
157 | int shift = ((req - 1) % 5) * 6; | |
158 | u32 l; | |
159 | ||
160 | l = omap_readl(reg); | |
161 | l &= ~(0x3f << shift); | |
162 | l |= (dev - 1) << shift; | |
163 | omap_writel(l, reg); | |
164 | } | |
1a8bfa1e TL |
165 | #else |
166 | #define set_gdma_dev(req, dev) do {} while (0) | |
2c799cef TL |
167 | #define omap_readl(reg) 0 |
168 | #define omap_writel(val, reg) do {} while (0) | |
1a8bfa1e | 169 | #endif |
5e1c5ff4 | 170 | |
54b693d4 | 171 | #ifdef CONFIG_ARCH_OMAP1 |
709eb3e5 | 172 | void omap_set_dma_priority(int lch, int dst_port, int priority) |
5e1c5ff4 TL |
173 | { |
174 | unsigned long reg; | |
175 | u32 l; | |
176 | ||
82809601 | 177 | if (dma_omap1()) { |
709eb3e5 TL |
178 | switch (dst_port) { |
179 | case OMAP_DMA_PORT_OCP_T1: /* FFFECC00 */ | |
180 | reg = OMAP_TC_OCPT1_PRIOR; | |
181 | break; | |
182 | case OMAP_DMA_PORT_OCP_T2: /* FFFECCD0 */ | |
183 | reg = OMAP_TC_OCPT2_PRIOR; | |
184 | break; | |
185 | case OMAP_DMA_PORT_EMIFF: /* FFFECC08 */ | |
186 | reg = OMAP_TC_EMIFF_PRIOR; | |
187 | break; | |
188 | case OMAP_DMA_PORT_EMIFS: /* FFFECC04 */ | |
189 | reg = OMAP_TC_EMIFS_PRIOR; | |
190 | break; | |
191 | default: | |
192 | BUG(); | |
193 | return; | |
194 | } | |
195 | l = omap_readl(reg); | |
196 | l &= ~(0xf << 8); | |
197 | l |= (priority & 0xf) << 8; | |
198 | omap_writel(l, reg); | |
199 | } | |
54b693d4 TL |
200 | } |
201 | #endif | |
709eb3e5 | 202 | |
54b693d4 TL |
203 | #ifdef CONFIG_ARCH_OMAP2PLUS |
204 | void omap_set_dma_priority(int lch, int dst_port, int priority) | |
205 | { | |
206 | u32 ccr; | |
207 | ||
208 | ccr = p->dma_read(CCR, lch); | |
209 | if (priority) | |
210 | ccr |= (1 << 6); | |
211 | else | |
212 | ccr &= ~(1 << 6); | |
213 | p->dma_write(ccr, CCR, lch); | |
5e1c5ff4 | 214 | } |
54b693d4 | 215 | #endif |
97b7f715 | 216 | EXPORT_SYMBOL(omap_set_dma_priority); |
5e1c5ff4 TL |
217 | |
218 | void omap_set_dma_transfer_params(int lch, int data_type, int elem_count, | |
1a8bfa1e TL |
219 | int frame_count, int sync_mode, |
220 | int dma_trigger, int src_or_dst_synch) | |
5e1c5ff4 | 221 | { |
0499bdeb TL |
222 | u32 l; |
223 | ||
f31cc962 | 224 | l = p->dma_read(CSDP, lch); |
0499bdeb TL |
225 | l &= ~0x03; |
226 | l |= data_type; | |
f31cc962 | 227 | p->dma_write(l, CSDP, lch); |
5e1c5ff4 | 228 | |
82809601 | 229 | if (dma_omap1()) { |
0499bdeb TL |
230 | u16 ccr; |
231 | ||
f31cc962 | 232 | ccr = p->dma_read(CCR, lch); |
0499bdeb | 233 | ccr &= ~(1 << 5); |
1a8bfa1e | 234 | if (sync_mode == OMAP_DMA_SYNC_FRAME) |
0499bdeb | 235 | ccr |= 1 << 5; |
f31cc962 | 236 | p->dma_write(ccr, CCR, lch); |
1a8bfa1e | 237 | |
f31cc962 | 238 | ccr = p->dma_read(CCR2, lch); |
0499bdeb | 239 | ccr &= ~(1 << 2); |
1a8bfa1e | 240 | if (sync_mode == OMAP_DMA_SYNC_BLOCK) |
0499bdeb | 241 | ccr |= 1 << 2; |
f31cc962 | 242 | p->dma_write(ccr, CCR2, lch); |
1a8bfa1e TL |
243 | } |
244 | ||
82809601 | 245 | if (dma_omap2plus() && dma_trigger) { |
0499bdeb | 246 | u32 val; |
1a8bfa1e | 247 | |
f31cc962 | 248 | val = p->dma_read(CCR, lch); |
4b3cf448 AG |
249 | |
250 | /* DMA_SYNCHRO_CONTROL_UPPER depends on the channel number */ | |
72a1179e | 251 | val &= ~((1 << 23) | (3 << 19) | 0x1f); |
4b3cf448 AG |
252 | val |= (dma_trigger & ~0x1f) << 14; |
253 | val |= dma_trigger & 0x1f; | |
5e1c5ff4 | 254 | |
1a8bfa1e TL |
255 | if (sync_mode & OMAP_DMA_SYNC_FRAME) |
256 | val |= 1 << 5; | |
eca9e56e PU |
257 | else |
258 | val &= ~(1 << 5); | |
5e1c5ff4 | 259 | |
1a8bfa1e TL |
260 | if (sync_mode & OMAP_DMA_SYNC_BLOCK) |
261 | val |= 1 << 18; | |
eca9e56e PU |
262 | else |
263 | val &= ~(1 << 18); | |
5e1c5ff4 | 264 | |
72a1179e SO |
265 | if (src_or_dst_synch == OMAP_DMA_DST_SYNC_PREFETCH) { |
266 | val &= ~(1 << 24); /* dest synch */ | |
267 | val |= (1 << 23); /* Prefetch */ | |
268 | } else if (src_or_dst_synch) { | |
1a8bfa1e | 269 | val |= 1 << 24; /* source synch */ |
72a1179e | 270 | } else { |
1a8bfa1e | 271 | val &= ~(1 << 24); /* dest synch */ |
72a1179e | 272 | } |
f31cc962 | 273 | p->dma_write(val, CCR, lch); |
1a8bfa1e TL |
274 | } |
275 | ||
f31cc962 MK |
276 | p->dma_write(elem_count, CEN, lch); |
277 | p->dma_write(frame_count, CFN, lch); | |
5e1c5ff4 | 278 | } |
97b7f715 | 279 | EXPORT_SYMBOL(omap_set_dma_transfer_params); |
1a8bfa1e | 280 | |
709eb3e5 TL |
281 | void omap_set_dma_write_mode(int lch, enum omap_dma_write_mode mode) |
282 | { | |
82809601 | 283 | if (dma_omap2plus()) { |
0499bdeb TL |
284 | u32 csdp; |
285 | ||
f31cc962 | 286 | csdp = p->dma_read(CSDP, lch); |
0499bdeb TL |
287 | csdp &= ~(0x3 << 16); |
288 | csdp |= (mode << 16); | |
f31cc962 | 289 | p->dma_write(csdp, CSDP, lch); |
709eb3e5 TL |
290 | } |
291 | } | |
97b7f715 | 292 | EXPORT_SYMBOL(omap_set_dma_write_mode); |
709eb3e5 | 293 | |
0499bdeb TL |
294 | void omap_set_dma_channel_mode(int lch, enum omap_dma_channel_mode mode) |
295 | { | |
82809601 | 296 | if (dma_omap1() && !dma_omap15xx()) { |
0499bdeb TL |
297 | u32 l; |
298 | ||
f31cc962 | 299 | l = p->dma_read(LCH_CTRL, lch); |
0499bdeb TL |
300 | l &= ~0x7; |
301 | l |= mode; | |
f31cc962 | 302 | p->dma_write(l, LCH_CTRL, lch); |
0499bdeb TL |
303 | } |
304 | } | |
305 | EXPORT_SYMBOL(omap_set_dma_channel_mode); | |
306 | ||
1a8bfa1e | 307 | /* Note that src_port is only for omap1 */ |
5e1c5ff4 | 308 | void omap_set_dma_src_params(int lch, int src_port, int src_amode, |
1a8bfa1e TL |
309 | unsigned long src_start, |
310 | int src_ei, int src_fi) | |
5e1c5ff4 | 311 | { |
97b7f715 TL |
312 | u32 l; |
313 | ||
82809601 | 314 | if (dma_omap1()) { |
0499bdeb | 315 | u16 w; |
1a8bfa1e | 316 | |
f31cc962 | 317 | w = p->dma_read(CSDP, lch); |
0499bdeb TL |
318 | w &= ~(0x1f << 2); |
319 | w |= src_port << 2; | |
f31cc962 | 320 | p->dma_write(w, CSDP, lch); |
97b7f715 | 321 | } |
1a8bfa1e | 322 | |
f31cc962 | 323 | l = p->dma_read(CCR, lch); |
97b7f715 TL |
324 | l &= ~(0x03 << 12); |
325 | l |= src_amode << 12; | |
f31cc962 | 326 | p->dma_write(l, CCR, lch); |
0499bdeb | 327 | |
f31cc962 | 328 | p->dma_write(src_start, CSSA, lch); |
5e1c5ff4 | 329 | |
f31cc962 MK |
330 | p->dma_write(src_ei, CSEI, lch); |
331 | p->dma_write(src_fi, CSFI, lch); | |
1a8bfa1e | 332 | } |
97b7f715 | 333 | EXPORT_SYMBOL(omap_set_dma_src_params); |
5e1c5ff4 | 334 | |
97b7f715 | 335 | void omap_set_dma_params(int lch, struct omap_dma_channel_params *params) |
1a8bfa1e TL |
336 | { |
337 | omap_set_dma_transfer_params(lch, params->data_type, | |
338 | params->elem_count, params->frame_count, | |
339 | params->sync_mode, params->trigger, | |
340 | params->src_or_dst_synch); | |
341 | omap_set_dma_src_params(lch, params->src_port, | |
342 | params->src_amode, params->src_start, | |
343 | params->src_ei, params->src_fi); | |
344 | ||
345 | omap_set_dma_dest_params(lch, params->dst_port, | |
346 | params->dst_amode, params->dst_start, | |
347 | params->dst_ei, params->dst_fi); | |
f8151e5c AG |
348 | if (params->read_prio || params->write_prio) |
349 | omap_dma_set_prio_lch(lch, params->read_prio, | |
350 | params->write_prio); | |
5e1c5ff4 | 351 | } |
97b7f715 | 352 | EXPORT_SYMBOL(omap_set_dma_params); |
5e1c5ff4 | 353 | |
5e1c5ff4 TL |
354 | void omap_set_dma_src_data_pack(int lch, int enable) |
355 | { | |
0499bdeb TL |
356 | u32 l; |
357 | ||
f31cc962 | 358 | l = p->dma_read(CSDP, lch); |
0499bdeb | 359 | l &= ~(1 << 6); |
1a8bfa1e | 360 | if (enable) |
0499bdeb | 361 | l |= (1 << 6); |
f31cc962 | 362 | p->dma_write(l, CSDP, lch); |
5e1c5ff4 | 363 | } |
97b7f715 | 364 | EXPORT_SYMBOL(omap_set_dma_src_data_pack); |
5e1c5ff4 TL |
365 | |
366 | void omap_set_dma_src_burst_mode(int lch, enum omap_dma_burst_mode burst_mode) | |
367 | { | |
6dc3c8f2 | 368 | unsigned int burst = 0; |
0499bdeb TL |
369 | u32 l; |
370 | ||
f31cc962 | 371 | l = p->dma_read(CSDP, lch); |
0499bdeb | 372 | l &= ~(0x03 << 7); |
5e1c5ff4 | 373 | |
5e1c5ff4 TL |
374 | switch (burst_mode) { |
375 | case OMAP_DMA_DATA_BURST_DIS: | |
376 | break; | |
377 | case OMAP_DMA_DATA_BURST_4: | |
82809601 | 378 | if (dma_omap2plus()) |
6dc3c8f2 KP |
379 | burst = 0x1; |
380 | else | |
381 | burst = 0x2; | |
5e1c5ff4 TL |
382 | break; |
383 | case OMAP_DMA_DATA_BURST_8: | |
82809601 | 384 | if (dma_omap2plus()) { |
6dc3c8f2 KP |
385 | burst = 0x2; |
386 | break; | |
387 | } | |
ea221a6a | 388 | /* |
389 | * not supported by current hardware on OMAP1 | |
5e1c5ff4 TL |
390 | * w |= (0x03 << 7); |
391 | * fall through | |
392 | */ | |
6dc3c8f2 | 393 | case OMAP_DMA_DATA_BURST_16: |
82809601 | 394 | if (dma_omap2plus()) { |
6dc3c8f2 KP |
395 | burst = 0x3; |
396 | break; | |
397 | } | |
ea221a6a | 398 | /* |
399 | * OMAP1 don't support burst 16 | |
6dc3c8f2 KP |
400 | * fall through |
401 | */ | |
5e1c5ff4 TL |
402 | default: |
403 | BUG(); | |
404 | } | |
0499bdeb TL |
405 | |
406 | l |= (burst << 7); | |
f31cc962 | 407 | p->dma_write(l, CSDP, lch); |
5e1c5ff4 | 408 | } |
97b7f715 | 409 | EXPORT_SYMBOL(omap_set_dma_src_burst_mode); |
5e1c5ff4 | 410 | |
1a8bfa1e | 411 | /* Note that dest_port is only for OMAP1 */ |
5e1c5ff4 | 412 | void omap_set_dma_dest_params(int lch, int dest_port, int dest_amode, |
1a8bfa1e TL |
413 | unsigned long dest_start, |
414 | int dst_ei, int dst_fi) | |
5e1c5ff4 | 415 | { |
0499bdeb TL |
416 | u32 l; |
417 | ||
82809601 | 418 | if (dma_omap1()) { |
f31cc962 | 419 | l = p->dma_read(CSDP, lch); |
0499bdeb TL |
420 | l &= ~(0x1f << 9); |
421 | l |= dest_port << 9; | |
f31cc962 | 422 | p->dma_write(l, CSDP, lch); |
1a8bfa1e | 423 | } |
5e1c5ff4 | 424 | |
f31cc962 | 425 | l = p->dma_read(CCR, lch); |
0499bdeb TL |
426 | l &= ~(0x03 << 14); |
427 | l |= dest_amode << 14; | |
f31cc962 | 428 | p->dma_write(l, CCR, lch); |
5e1c5ff4 | 429 | |
f31cc962 | 430 | p->dma_write(dest_start, CDSA, lch); |
5e1c5ff4 | 431 | |
f31cc962 MK |
432 | p->dma_write(dst_ei, CDEI, lch); |
433 | p->dma_write(dst_fi, CDFI, lch); | |
5e1c5ff4 | 434 | } |
97b7f715 | 435 | EXPORT_SYMBOL(omap_set_dma_dest_params); |
5e1c5ff4 | 436 | |
5e1c5ff4 TL |
437 | void omap_set_dma_dest_data_pack(int lch, int enable) |
438 | { | |
0499bdeb TL |
439 | u32 l; |
440 | ||
f31cc962 | 441 | l = p->dma_read(CSDP, lch); |
0499bdeb | 442 | l &= ~(1 << 13); |
1a8bfa1e | 443 | if (enable) |
0499bdeb | 444 | l |= 1 << 13; |
f31cc962 | 445 | p->dma_write(l, CSDP, lch); |
5e1c5ff4 | 446 | } |
97b7f715 | 447 | EXPORT_SYMBOL(omap_set_dma_dest_data_pack); |
5e1c5ff4 TL |
448 | |
449 | void omap_set_dma_dest_burst_mode(int lch, enum omap_dma_burst_mode burst_mode) | |
450 | { | |
6dc3c8f2 | 451 | unsigned int burst = 0; |
0499bdeb TL |
452 | u32 l; |
453 | ||
f31cc962 | 454 | l = p->dma_read(CSDP, lch); |
0499bdeb | 455 | l &= ~(0x03 << 14); |
5e1c5ff4 | 456 | |
5e1c5ff4 TL |
457 | switch (burst_mode) { |
458 | case OMAP_DMA_DATA_BURST_DIS: | |
459 | break; | |
460 | case OMAP_DMA_DATA_BURST_4: | |
82809601 | 461 | if (dma_omap2plus()) |
6dc3c8f2 KP |
462 | burst = 0x1; |
463 | else | |
464 | burst = 0x2; | |
5e1c5ff4 TL |
465 | break; |
466 | case OMAP_DMA_DATA_BURST_8: | |
82809601 | 467 | if (dma_omap2plus()) |
6dc3c8f2 KP |
468 | burst = 0x2; |
469 | else | |
470 | burst = 0x3; | |
5e1c5ff4 | 471 | break; |
6dc3c8f2 | 472 | case OMAP_DMA_DATA_BURST_16: |
82809601 | 473 | if (dma_omap2plus()) { |
6dc3c8f2 KP |
474 | burst = 0x3; |
475 | break; | |
476 | } | |
ea221a6a | 477 | /* |
478 | * OMAP1 don't support burst 16 | |
6dc3c8f2 KP |
479 | * fall through |
480 | */ | |
5e1c5ff4 TL |
481 | default: |
482 | printk(KERN_ERR "Invalid DMA burst mode\n"); | |
483 | BUG(); | |
484 | return; | |
485 | } | |
0499bdeb | 486 | l |= (burst << 14); |
f31cc962 | 487 | p->dma_write(l, CSDP, lch); |
5e1c5ff4 | 488 | } |
97b7f715 | 489 | EXPORT_SYMBOL(omap_set_dma_dest_burst_mode); |
5e1c5ff4 | 490 | |
1a8bfa1e | 491 | static inline void omap_enable_channel_irq(int lch) |
5e1c5ff4 | 492 | { |
7ff879db | 493 | /* Clear CSR */ |
82809601 | 494 | if (dma_omap1()) |
bedfb7ad OM |
495 | p->dma_read(CSR, lch); |
496 | else | |
f31cc962 | 497 | p->dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR, lch); |
1a8bfa1e | 498 | |
5e1c5ff4 | 499 | /* Enable some nice interrupts. */ |
f31cc962 | 500 | p->dma_write(dma_chan[lch].enabled_irqs, CICR, lch); |
5e1c5ff4 TL |
501 | } |
502 | ||
bedfb7ad | 503 | static inline void omap_disable_channel_irq(int lch) |
5e1c5ff4 | 504 | { |
bedfb7ad OM |
505 | /* disable channel interrupts */ |
506 | p->dma_write(0, CICR, lch); | |
507 | /* Clear CSR */ | |
82809601 | 508 | if (dma_omap1()) |
bedfb7ad OM |
509 | p->dma_read(CSR, lch); |
510 | else | |
511 | p->dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR, lch); | |
1a8bfa1e TL |
512 | } |
513 | ||
514 | void omap_enable_dma_irq(int lch, u16 bits) | |
515 | { | |
516 | dma_chan[lch].enabled_irqs |= bits; | |
517 | } | |
97b7f715 | 518 | EXPORT_SYMBOL(omap_enable_dma_irq); |
5e1c5ff4 | 519 | |
1a8bfa1e TL |
520 | void omap_disable_dma_irq(int lch, u16 bits) |
521 | { | |
522 | dma_chan[lch].enabled_irqs &= ~bits; | |
523 | } | |
97b7f715 | 524 | EXPORT_SYMBOL(omap_disable_dma_irq); |
1a8bfa1e TL |
525 | |
526 | static inline void enable_lnk(int lch) | |
527 | { | |
0499bdeb TL |
528 | u32 l; |
529 | ||
f31cc962 | 530 | l = p->dma_read(CLNK_CTRL, lch); |
0499bdeb | 531 | |
82809601 | 532 | if (dma_omap1()) |
0499bdeb | 533 | l &= ~(1 << 14); |
5e1c5ff4 | 534 | |
1a8bfa1e | 535 | /* Set the ENABLE_LNK bits */ |
5e1c5ff4 | 536 | if (dma_chan[lch].next_lch != -1) |
0499bdeb | 537 | l = dma_chan[lch].next_lch | (1 << 15); |
f8151e5c AG |
538 | |
539 | #ifndef CONFIG_ARCH_OMAP1 | |
82809601 | 540 | if (dma_omap2plus()) |
97b7f715 TL |
541 | if (dma_chan[lch].next_linked_ch != -1) |
542 | l = dma_chan[lch].next_linked_ch | (1 << 15); | |
f8151e5c | 543 | #endif |
0499bdeb | 544 | |
f31cc962 | 545 | p->dma_write(l, CLNK_CTRL, lch); |
5e1c5ff4 TL |
546 | } |
547 | ||
548 | static inline void disable_lnk(int lch) | |
549 | { | |
0499bdeb TL |
550 | u32 l; |
551 | ||
f31cc962 | 552 | l = p->dma_read(CLNK_CTRL, lch); |
0499bdeb | 553 | |
5e1c5ff4 | 554 | /* Disable interrupts */ |
bedfb7ad OM |
555 | omap_disable_channel_irq(lch); |
556 | ||
82809601 | 557 | if (dma_omap1()) { |
1a8bfa1e | 558 | /* Set the STOP_LNK bit */ |
0499bdeb | 559 | l |= 1 << 14; |
1a8bfa1e | 560 | } |
5e1c5ff4 | 561 | |
82809601 | 562 | if (dma_omap2plus()) { |
1a8bfa1e | 563 | /* Clear the ENABLE_LNK bit */ |
0499bdeb | 564 | l &= ~(1 << 15); |
1a8bfa1e | 565 | } |
5e1c5ff4 | 566 | |
f31cc962 | 567 | p->dma_write(l, CLNK_CTRL, lch); |
5e1c5ff4 TL |
568 | dma_chan[lch].flags &= ~OMAP_DMA_ACTIVE; |
569 | } | |
570 | ||
1a8bfa1e | 571 | static inline void omap2_enable_irq_lch(int lch) |
5e1c5ff4 | 572 | { |
1a8bfa1e | 573 | u32 val; |
ee907324 | 574 | unsigned long flags; |
1a8bfa1e | 575 | |
82809601 | 576 | if (dma_omap1()) |
1a8bfa1e TL |
577 | return; |
578 | ||
ee907324 | 579 | spin_lock_irqsave(&dma_chan_lock, flags); |
bedfb7ad OM |
580 | /* clear IRQ STATUS */ |
581 | p->dma_write(1 << lch, IRQSTATUS_L0, lch); | |
582 | /* Enable interrupt */ | |
f31cc962 | 583 | val = p->dma_read(IRQENABLE_L0, lch); |
1a8bfa1e | 584 | val |= 1 << lch; |
f31cc962 | 585 | p->dma_write(val, IRQENABLE_L0, lch); |
ee907324 | 586 | spin_unlock_irqrestore(&dma_chan_lock, flags); |
1a8bfa1e TL |
587 | } |
588 | ||
ada8d4a5 MW |
589 | static inline void omap2_disable_irq_lch(int lch) |
590 | { | |
591 | u32 val; | |
592 | unsigned long flags; | |
593 | ||
82809601 | 594 | if (dma_omap1()) |
ada8d4a5 MW |
595 | return; |
596 | ||
597 | spin_lock_irqsave(&dma_chan_lock, flags); | |
bedfb7ad | 598 | /* Disable interrupt */ |
f31cc962 | 599 | val = p->dma_read(IRQENABLE_L0, lch); |
ada8d4a5 | 600 | val &= ~(1 << lch); |
f31cc962 | 601 | p->dma_write(val, IRQENABLE_L0, lch); |
bedfb7ad OM |
602 | /* clear IRQ STATUS */ |
603 | p->dma_write(1 << lch, IRQSTATUS_L0, lch); | |
ada8d4a5 MW |
604 | spin_unlock_irqrestore(&dma_chan_lock, flags); |
605 | } | |
606 | ||
1a8bfa1e | 607 | int omap_request_dma(int dev_id, const char *dev_name, |
97b7f715 | 608 | void (*callback)(int lch, u16 ch_status, void *data), |
1a8bfa1e TL |
609 | void *data, int *dma_ch_out) |
610 | { | |
611 | int ch, free_ch = -1; | |
612 | unsigned long flags; | |
613 | struct omap_dma_lch *chan; | |
614 | ||
5c65c360 RK |
615 | WARN(strcmp(dev_name, "DMA engine"), "Using deprecated platform DMA API - please update to DMA engine"); |
616 | ||
1a8bfa1e TL |
617 | spin_lock_irqsave(&dma_chan_lock, flags); |
618 | for (ch = 0; ch < dma_chan_count; ch++) { | |
619 | if (free_ch == -1 && dma_chan[ch].dev_id == -1) { | |
620 | free_ch = ch; | |
03a6d4a0 S |
621 | /* Exit after first free channel found */ |
622 | break; | |
1a8bfa1e TL |
623 | } |
624 | } | |
625 | if (free_ch == -1) { | |
626 | spin_unlock_irqrestore(&dma_chan_lock, flags); | |
627 | return -EBUSY; | |
628 | } | |
629 | chan = dma_chan + free_ch; | |
630 | chan->dev_id = dev_id; | |
631 | ||
f31cc962 MK |
632 | if (p->clear_lch_regs) |
633 | p->clear_lch_regs(free_ch); | |
5e1c5ff4 | 634 | |
82809601 | 635 | if (dma_omap2plus()) |
1a8bfa1e TL |
636 | omap_clear_dma(free_ch); |
637 | ||
638 | spin_unlock_irqrestore(&dma_chan_lock, flags); | |
639 | ||
640 | chan->dev_name = dev_name; | |
641 | chan->callback = callback; | |
642 | chan->data = data; | |
a92fda19 | 643 | chan->flags = 0; |
97b7f715 | 644 | |
f8151e5c | 645 | #ifndef CONFIG_ARCH_OMAP1 |
82809601 | 646 | if (dma_omap2plus()) { |
97b7f715 TL |
647 | chan->chain_id = -1; |
648 | chan->next_linked_ch = -1; | |
649 | } | |
f8151e5c | 650 | #endif |
97b7f715 | 651 | |
7ff879db | 652 | chan->enabled_irqs = OMAP_DMA_DROP_IRQ | OMAP_DMA_BLOCK_IRQ; |
1a8bfa1e | 653 | |
82809601 | 654 | if (dma_omap1()) |
7ff879db | 655 | chan->enabled_irqs |= OMAP1_DMA_TOUT_IRQ; |
82809601 | 656 | else if (dma_omap2plus()) |
7ff879db TL |
657 | chan->enabled_irqs |= OMAP2_DMA_MISALIGNED_ERR_IRQ | |
658 | OMAP2_DMA_TRANS_ERR_IRQ; | |
1a8bfa1e | 659 | |
82809601 | 660 | if (dma_omap16xx()) { |
1a8bfa1e TL |
661 | /* If the sync device is set, configure it dynamically. */ |
662 | if (dev_id != 0) { | |
663 | set_gdma_dev(free_ch + 1, dev_id); | |
664 | dev_id = free_ch + 1; | |
665 | } | |
97b7f715 TL |
666 | /* |
667 | * Disable the 1510 compatibility mode and set the sync device | |
668 | * id. | |
669 | */ | |
f31cc962 | 670 | p->dma_write(dev_id | (1 << 10), CCR, free_ch); |
82809601 | 671 | } else if (dma_omap1()) { |
f31cc962 | 672 | p->dma_write(dev_id, CCR, free_ch); |
1a8bfa1e TL |
673 | } |
674 | ||
82809601 | 675 | if (dma_omap2plus()) { |
1a8bfa1e | 676 | omap_enable_channel_irq(free_ch); |
bedfb7ad | 677 | omap2_enable_irq_lch(free_ch); |
1a8bfa1e TL |
678 | } |
679 | ||
680 | *dma_ch_out = free_ch; | |
681 | ||
682 | return 0; | |
683 | } | |
97b7f715 | 684 | EXPORT_SYMBOL(omap_request_dma); |
1a8bfa1e TL |
685 | |
686 | void omap_free_dma(int lch) | |
687 | { | |
688 | unsigned long flags; | |
689 | ||
1a8bfa1e | 690 | if (dma_chan[lch].dev_id == -1) { |
97b7f715 | 691 | pr_err("omap_dma: trying to free unallocated DMA channel %d\n", |
1a8bfa1e | 692 | lch); |
1a8bfa1e TL |
693 | return; |
694 | } | |
97b7f715 | 695 | |
bedfb7ad | 696 | /* Disable interrupt for logical channel */ |
82809601 | 697 | if (dma_omap2plus()) |
ada8d4a5 | 698 | omap2_disable_irq_lch(lch); |
1a8bfa1e | 699 | |
bedfb7ad OM |
700 | /* Disable all DMA interrupts for the channel. */ |
701 | omap_disable_channel_irq(lch); | |
1a8bfa1e | 702 | |
bedfb7ad OM |
703 | /* Make sure the DMA transfer is stopped. */ |
704 | p->dma_write(0, CCR, lch); | |
1a8bfa1e | 705 | |
bedfb7ad | 706 | /* Clear registers */ |
82809601 | 707 | if (dma_omap2plus()) |
1a8bfa1e | 708 | omap_clear_dma(lch); |
da1b94e6 SS |
709 | |
710 | spin_lock_irqsave(&dma_chan_lock, flags); | |
711 | dma_chan[lch].dev_id = -1; | |
712 | dma_chan[lch].next_lch = -1; | |
713 | dma_chan[lch].callback = NULL; | |
714 | spin_unlock_irqrestore(&dma_chan_lock, flags); | |
1a8bfa1e | 715 | } |
97b7f715 | 716 | EXPORT_SYMBOL(omap_free_dma); |
1a8bfa1e | 717 | |
f8151e5c AG |
718 | /** |
719 | * @brief omap_dma_set_global_params : Set global priority settings for dma | |
720 | * | |
721 | * @param arb_rate | |
722 | * @param max_fifo_depth | |
70cf644c AA |
723 | * @param tparams - Number of threads to reserve : DMA_THREAD_RESERVE_NORM |
724 | * DMA_THREAD_RESERVE_ONET | |
725 | * DMA_THREAD_RESERVE_TWOT | |
726 | * DMA_THREAD_RESERVE_THREET | |
f8151e5c AG |
727 | */ |
728 | void | |
729 | omap_dma_set_global_params(int arb_rate, int max_fifo_depth, int tparams) | |
730 | { | |
731 | u32 reg; | |
732 | ||
82809601 | 733 | if (dma_omap1()) { |
8e86f427 | 734 | printk(KERN_ERR "FIXME: no %s on 15xx/16xx\n", __func__); |
f8151e5c AG |
735 | return; |
736 | } | |
737 | ||
70cf644c AA |
738 | if (max_fifo_depth == 0) |
739 | max_fifo_depth = 1; | |
f8151e5c AG |
740 | if (arb_rate == 0) |
741 | arb_rate = 1; | |
742 | ||
70cf644c AA |
743 | reg = 0xff & max_fifo_depth; |
744 | reg |= (0x3 & tparams) << 12; | |
745 | reg |= (arb_rate & 0xff) << 16; | |
f8151e5c | 746 | |
f31cc962 | 747 | p->dma_write(reg, GCR, 0); |
f8151e5c AG |
748 | } |
749 | EXPORT_SYMBOL(omap_dma_set_global_params); | |
750 | ||
751 | /** | |
752 | * @brief omap_dma_set_prio_lch : Set channel wise priority settings | |
753 | * | |
754 | * @param lch | |
755 | * @param read_prio - Read priority | |
756 | * @param write_prio - Write priority | |
757 | * Both of the above can be set with one of the following values : | |
758 | * DMA_CH_PRIO_HIGH/DMA_CH_PRIO_LOW | |
759 | */ | |
175655bd | 760 | static int |
f8151e5c AG |
761 | omap_dma_set_prio_lch(int lch, unsigned char read_prio, |
762 | unsigned char write_prio) | |
763 | { | |
0499bdeb | 764 | u32 l; |
f8151e5c | 765 | |
4d96372e | 766 | if (unlikely((lch < 0 || lch >= dma_lch_count))) { |
f8151e5c AG |
767 | printk(KERN_ERR "Invalid channel id\n"); |
768 | return -EINVAL; | |
769 | } | |
f31cc962 | 770 | l = p->dma_read(CCR, lch); |
0499bdeb | 771 | l &= ~((1 << 6) | (1 << 26)); |
82809601 | 772 | if (d->dev_caps & IS_RW_PRIORITY) |
0499bdeb | 773 | l |= ((read_prio & 0x1) << 6) | ((write_prio & 0x1) << 26); |
f8151e5c | 774 | else |
0499bdeb TL |
775 | l |= ((read_prio & 0x1) << 6); |
776 | ||
f31cc962 | 777 | p->dma_write(l, CCR, lch); |
f8151e5c | 778 | |
f8151e5c AG |
779 | return 0; |
780 | } | |
175655bd | 781 | |
f8151e5c | 782 | |
1a8bfa1e TL |
783 | /* |
784 | * Clears any DMA state so the DMA engine is ready to restart with new buffers | |
785 | * through omap_start_dma(). Any buffers in flight are discarded. | |
786 | */ | |
175655bd | 787 | static void omap_clear_dma(int lch) |
1a8bfa1e TL |
788 | { |
789 | unsigned long flags; | |
790 | ||
791 | local_irq_save(flags); | |
f31cc962 | 792 | p->clear_dma(lch); |
1a8bfa1e TL |
793 | local_irq_restore(flags); |
794 | } | |
795 | ||
796 | void omap_start_dma(int lch) | |
797 | { | |
0499bdeb TL |
798 | u32 l; |
799 | ||
519e6166 | 800 | /* |
801 | * The CPC/CDAC register needs to be initialized to zero | |
802 | * before starting dma transfer. | |
803 | */ | |
82809601 | 804 | if (dma_omap15xx()) |
f31cc962 | 805 | p->dma_write(0, CPC, lch); |
519e6166 | 806 | else |
f31cc962 | 807 | p->dma_write(0, CDAC, lch); |
519e6166 | 808 | |
5e1c5ff4 TL |
809 | if (!omap_dma_in_1510_mode() && dma_chan[lch].next_lch != -1) { |
810 | int next_lch, cur_lch; | |
bc4d8b5f | 811 | char dma_chan_link_map[MAX_LOGICAL_DMA_CH_COUNT]; |
5e1c5ff4 | 812 | |
5e1c5ff4 TL |
813 | /* Set the link register of the first channel */ |
814 | enable_lnk(lch); | |
815 | ||
816 | memset(dma_chan_link_map, 0, sizeof(dma_chan_link_map)); | |
f0a3ff27 S |
817 | dma_chan_link_map[lch] = 1; |
818 | ||
5e1c5ff4 TL |
819 | cur_lch = dma_chan[lch].next_lch; |
820 | do { | |
821 | next_lch = dma_chan[cur_lch].next_lch; | |
822 | ||
1a8bfa1e | 823 | /* The loop case: we've been here already */ |
5e1c5ff4 TL |
824 | if (dma_chan_link_map[cur_lch]) |
825 | break; | |
826 | /* Mark the current channel */ | |
827 | dma_chan_link_map[cur_lch] = 1; | |
828 | ||
829 | enable_lnk(cur_lch); | |
1a8bfa1e | 830 | omap_enable_channel_irq(cur_lch); |
5e1c5ff4 TL |
831 | |
832 | cur_lch = next_lch; | |
833 | } while (next_lch != -1); | |
d3c9be2f | 834 | } else if (IS_DMA_ERRATA(DMA_ERRATA_PARALLEL_CHANNELS)) |
f31cc962 | 835 | p->dma_write(lch, CLNK_CTRL, lch); |
5e1c5ff4 | 836 | |
1a8bfa1e TL |
837 | omap_enable_channel_irq(lch); |
838 | ||
f31cc962 | 839 | l = p->dma_read(CCR, lch); |
0499bdeb | 840 | |
d3c9be2f MK |
841 | if (IS_DMA_ERRATA(DMA_ERRATA_IFRAME_BUFFERING)) |
842 | l |= OMAP_DMA_CCR_BUFFERING_DISABLE; | |
0499bdeb | 843 | l |= OMAP_DMA_CCR_EN; |
d3c9be2f | 844 | |
35453584 RK |
845 | /* |
846 | * As dma_write() uses IO accessors which are weakly ordered, there | |
847 | * is no guarantee that data in coherent DMA memory will be visible | |
848 | * to the DMA device. Add a memory barrier here to ensure that any | |
849 | * such data is visible prior to enabling DMA. | |
850 | */ | |
851 | mb(); | |
f31cc962 | 852 | p->dma_write(l, CCR, lch); |
5e1c5ff4 | 853 | |
5e1c5ff4 TL |
854 | dma_chan[lch].flags |= OMAP_DMA_ACTIVE; |
855 | } | |
97b7f715 | 856 | EXPORT_SYMBOL(omap_start_dma); |
5e1c5ff4 TL |
857 | |
858 | void omap_stop_dma(int lch) | |
859 | { | |
0499bdeb TL |
860 | u32 l; |
861 | ||
9da65a99 | 862 | /* Disable all interrupts on the channel */ |
bedfb7ad | 863 | omap_disable_channel_irq(lch); |
9da65a99 | 864 | |
f31cc962 | 865 | l = p->dma_read(CCR, lch); |
d3c9be2f MK |
866 | if (IS_DMA_ERRATA(DMA_ERRATA_i541) && |
867 | (l & OMAP_DMA_CCR_SEL_SRC_DST_SYNC)) { | |
0e4905c0 PU |
868 | int i = 0; |
869 | u32 sys_cf; | |
870 | ||
871 | /* Configure No-Standby */ | |
f31cc962 | 872 | l = p->dma_read(OCP_SYSCONFIG, lch); |
0e4905c0 PU |
873 | sys_cf = l; |
874 | l &= ~DMA_SYSCONFIG_MIDLEMODE_MASK; | |
875 | l |= DMA_SYSCONFIG_MIDLEMODE(DMA_IDLEMODE_NO_IDLE); | |
f31cc962 | 876 | p->dma_write(l , OCP_SYSCONFIG, 0); |
0e4905c0 | 877 | |
f31cc962 | 878 | l = p->dma_read(CCR, lch); |
0e4905c0 | 879 | l &= ~OMAP_DMA_CCR_EN; |
f31cc962 | 880 | p->dma_write(l, CCR, lch); |
0e4905c0 PU |
881 | |
882 | /* Wait for sDMA FIFO drain */ | |
f31cc962 | 883 | l = p->dma_read(CCR, lch); |
0e4905c0 PU |
884 | while (i < 100 && (l & (OMAP_DMA_CCR_RD_ACTIVE | |
885 | OMAP_DMA_CCR_WR_ACTIVE))) { | |
886 | udelay(5); | |
887 | i++; | |
f31cc962 | 888 | l = p->dma_read(CCR, lch); |
0e4905c0 PU |
889 | } |
890 | if (i >= 100) | |
7852ec05 | 891 | pr_err("DMA drain did not complete on lch %d\n", lch); |
0e4905c0 | 892 | /* Restore OCP_SYSCONFIG */ |
f31cc962 | 893 | p->dma_write(sys_cf, OCP_SYSCONFIG, lch); |
0e4905c0 PU |
894 | } else { |
895 | l &= ~OMAP_DMA_CCR_EN; | |
f31cc962 | 896 | p->dma_write(l, CCR, lch); |
0e4905c0 | 897 | } |
9da65a99 | 898 | |
35453584 RK |
899 | /* |
900 | * Ensure that data transferred by DMA is visible to any access | |
901 | * after DMA has been disabled. This is important for coherent | |
902 | * DMA regions. | |
903 | */ | |
904 | mb(); | |
905 | ||
5e1c5ff4 TL |
906 | if (!omap_dma_in_1510_mode() && dma_chan[lch].next_lch != -1) { |
907 | int next_lch, cur_lch = lch; | |
bc4d8b5f | 908 | char dma_chan_link_map[MAX_LOGICAL_DMA_CH_COUNT]; |
5e1c5ff4 TL |
909 | |
910 | memset(dma_chan_link_map, 0, sizeof(dma_chan_link_map)); | |
911 | do { | |
912 | /* The loop case: we've been here already */ | |
913 | if (dma_chan_link_map[cur_lch]) | |
914 | break; | |
915 | /* Mark the current channel */ | |
916 | dma_chan_link_map[cur_lch] = 1; | |
917 | ||
918 | disable_lnk(cur_lch); | |
919 | ||
920 | next_lch = dma_chan[cur_lch].next_lch; | |
921 | cur_lch = next_lch; | |
922 | } while (next_lch != -1); | |
5e1c5ff4 | 923 | } |
1a8bfa1e | 924 | |
5e1c5ff4 TL |
925 | dma_chan[lch].flags &= ~OMAP_DMA_ACTIVE; |
926 | } | |
97b7f715 | 927 | EXPORT_SYMBOL(omap_stop_dma); |
5e1c5ff4 | 928 | |
709eb3e5 TL |
929 | /* |
930 | * Allows changing the DMA callback function or data. This may be needed if | |
931 | * the driver shares a single DMA channel for multiple dma triggers. | |
932 | */ | |
933 | int omap_set_dma_callback(int lch, | |
97b7f715 | 934 | void (*callback)(int lch, u16 ch_status, void *data), |
709eb3e5 TL |
935 | void *data) |
936 | { | |
937 | unsigned long flags; | |
938 | ||
939 | if (lch < 0) | |
940 | return -ENODEV; | |
941 | ||
942 | spin_lock_irqsave(&dma_chan_lock, flags); | |
943 | if (dma_chan[lch].dev_id == -1) { | |
944 | printk(KERN_ERR "DMA callback for not set for free channel\n"); | |
945 | spin_unlock_irqrestore(&dma_chan_lock, flags); | |
946 | return -EINVAL; | |
947 | } | |
948 | dma_chan[lch].callback = callback; | |
949 | dma_chan[lch].data = data; | |
950 | spin_unlock_irqrestore(&dma_chan_lock, flags); | |
951 | ||
952 | return 0; | |
953 | } | |
97b7f715 | 954 | EXPORT_SYMBOL(omap_set_dma_callback); |
709eb3e5 | 955 | |
1a8bfa1e TL |
956 | /* |
957 | * Returns current physical source address for the given DMA channel. | |
958 | * If the channel is running the caller must disable interrupts prior calling | |
959 | * this function and process the returned value before re-enabling interrupt to | |
960 | * prevent races with the interrupt handler. Note that in continuous mode there | |
25985edc | 961 | * is a chance for CSSA_L register overflow between the two reads resulting |
1a8bfa1e TL |
962 | * in incorrect return value. |
963 | */ | |
964 | dma_addr_t omap_get_dma_src_pos(int lch) | |
5e1c5ff4 | 965 | { |
0695de32 | 966 | dma_addr_t offset = 0; |
5e1c5ff4 | 967 | |
82809601 | 968 | if (dma_omap15xx()) |
f31cc962 | 969 | offset = p->dma_read(CPC, lch); |
0499bdeb | 970 | else |
f31cc962 | 971 | offset = p->dma_read(CSAC, lch); |
5e1c5ff4 | 972 | |
d3c9be2f | 973 | if (IS_DMA_ERRATA(DMA_ERRATA_3_3) && offset == 0) |
f31cc962 | 974 | offset = p->dma_read(CSAC, lch); |
0499bdeb | 975 | |
82809601 | 976 | if (!dma_omap15xx()) { |
7ba96680 PU |
977 | /* |
978 | * CDAC == 0 indicates that the DMA transfer on the channel has | |
979 | * not been started (no data has been transferred so far). | |
980 | * Return the programmed source start address in this case. | |
981 | */ | |
982 | if (likely(p->dma_read(CDAC, lch))) | |
983 | offset = p->dma_read(CSAC, lch); | |
984 | else | |
985 | offset = p->dma_read(CSSA, lch); | |
986 | } | |
987 | ||
82809601 | 988 | if (dma_omap1()) |
f31cc962 | 989 | offset |= (p->dma_read(CSSA, lch) & 0xFFFF0000); |
5e1c5ff4 | 990 | |
1a8bfa1e | 991 | return offset; |
5e1c5ff4 | 992 | } |
97b7f715 | 993 | EXPORT_SYMBOL(omap_get_dma_src_pos); |
5e1c5ff4 | 994 | |
1a8bfa1e TL |
995 | /* |
996 | * Returns current physical destination address for the given DMA channel. | |
997 | * If the channel is running the caller must disable interrupts prior calling | |
998 | * this function and process the returned value before re-enabling interrupt to | |
999 | * prevent races with the interrupt handler. Note that in continuous mode there | |
25985edc | 1000 | * is a chance for CDSA_L register overflow between the two reads resulting |
1a8bfa1e TL |
1001 | * in incorrect return value. |
1002 | */ | |
1003 | dma_addr_t omap_get_dma_dst_pos(int lch) | |
5e1c5ff4 | 1004 | { |
0695de32 | 1005 | dma_addr_t offset = 0; |
5e1c5ff4 | 1006 | |
82809601 | 1007 | if (dma_omap15xx()) |
f31cc962 | 1008 | offset = p->dma_read(CPC, lch); |
0499bdeb | 1009 | else |
f31cc962 | 1010 | offset = p->dma_read(CDAC, lch); |
5e1c5ff4 | 1011 | |
0499bdeb TL |
1012 | /* |
1013 | * omap 3.2/3.3 erratum: sometimes 0 is returned if CSAC/CDAC is | |
1014 | * read before the DMA controller finished disabling the channel. | |
1015 | */ | |
82809601 | 1016 | if (!dma_omap15xx() && offset == 0) { |
f31cc962 | 1017 | offset = p->dma_read(CDAC, lch); |
06e8077b PU |
1018 | /* |
1019 | * CDAC == 0 indicates that the DMA transfer on the channel has | |
1020 | * not been started (no data has been transferred so far). | |
1021 | * Return the programmed destination start address in this case. | |
1022 | */ | |
1023 | if (unlikely(!offset)) | |
1024 | offset = p->dma_read(CDSA, lch); | |
1025 | } | |
0499bdeb | 1026 | |
82809601 | 1027 | if (dma_omap1()) |
f31cc962 | 1028 | offset |= (p->dma_read(CDSA, lch) & 0xFFFF0000); |
5e1c5ff4 | 1029 | |
1a8bfa1e | 1030 | return offset; |
5e1c5ff4 | 1031 | } |
97b7f715 | 1032 | EXPORT_SYMBOL(omap_get_dma_dst_pos); |
0499bdeb TL |
1033 | |
1034 | int omap_get_dma_active_status(int lch) | |
1035 | { | |
f31cc962 | 1036 | return (p->dma_read(CCR, lch) & OMAP_DMA_CCR_EN) != 0; |
5e1c5ff4 | 1037 | } |
0499bdeb | 1038 | EXPORT_SYMBOL(omap_get_dma_active_status); |
5e1c5ff4 | 1039 | |
1a8bfa1e | 1040 | int omap_dma_running(void) |
5e1c5ff4 | 1041 | { |
1a8bfa1e | 1042 | int lch; |
5e1c5ff4 | 1043 | |
82809601 | 1044 | if (dma_omap1()) |
f8e9e984 | 1045 | if (omap_lcd_dma_running()) |
1a8bfa1e | 1046 | return 1; |
5e1c5ff4 | 1047 | |
1a8bfa1e | 1048 | for (lch = 0; lch < dma_chan_count; lch++) |
f31cc962 | 1049 | if (p->dma_read(CCR, lch) & OMAP_DMA_CCR_EN) |
1a8bfa1e | 1050 | return 1; |
5e1c5ff4 | 1051 | |
1a8bfa1e | 1052 | return 0; |
5e1c5ff4 TL |
1053 | } |
1054 | ||
1055 | /* | |
1056 | * lch_queue DMA will start right after lch_head one is finished. | |
1057 | * For this DMA link to start, you still need to start (see omap_start_dma) | |
1058 | * the first one. That will fire up the entire queue. | |
1059 | */ | |
97b7f715 | 1060 | void omap_dma_link_lch(int lch_head, int lch_queue) |
5e1c5ff4 TL |
1061 | { |
1062 | if (omap_dma_in_1510_mode()) { | |
9f0f4ae5 | 1063 | if (lch_head == lch_queue) { |
f31cc962 | 1064 | p->dma_write(p->dma_read(CCR, lch_head) | (3 << 8), |
a4c537c7 | 1065 | CCR, lch_head); |
9f0f4ae5 JK |
1066 | return; |
1067 | } | |
5e1c5ff4 TL |
1068 | printk(KERN_ERR "DMA linking is not supported in 1510 mode\n"); |
1069 | BUG(); | |
1070 | return; | |
1071 | } | |
1072 | ||
1073 | if ((dma_chan[lch_head].dev_id == -1) || | |
1074 | (dma_chan[lch_queue].dev_id == -1)) { | |
7852ec05 | 1075 | pr_err("omap_dma: trying to link non requested channels\n"); |
5e1c5ff4 TL |
1076 | dump_stack(); |
1077 | } | |
1078 | ||
1079 | dma_chan[lch_head].next_lch = lch_queue; | |
1080 | } | |
97b7f715 | 1081 | EXPORT_SYMBOL(omap_dma_link_lch); |
5e1c5ff4 | 1082 | |
1a8bfa1e TL |
1083 | /*----------------------------------------------------------------------------*/ |
1084 | ||
1085 | #ifdef CONFIG_ARCH_OMAP1 | |
1086 | ||
1087 | static int omap1_dma_handle_ch(int ch) | |
1088 | { | |
0499bdeb | 1089 | u32 csr; |
1a8bfa1e TL |
1090 | |
1091 | if (enable_1510_mode && ch >= 6) { | |
1092 | csr = dma_chan[ch].saved_csr; | |
1093 | dma_chan[ch].saved_csr = 0; | |
1094 | } else | |
f31cc962 | 1095 | csr = p->dma_read(CSR, ch); |
1a8bfa1e TL |
1096 | if (enable_1510_mode && ch <= 2 && (csr >> 7) != 0) { |
1097 | dma_chan[ch + 6].saved_csr = csr >> 7; | |
1098 | csr &= 0x7f; | |
1099 | } | |
1100 | if ((csr & 0x3f) == 0) | |
1101 | return 0; | |
1102 | if (unlikely(dma_chan[ch].dev_id == -1)) { | |
7852ec05 PW |
1103 | pr_warn("Spurious interrupt from DMA channel %d (CSR %04x)\n", |
1104 | ch, csr); | |
1a8bfa1e TL |
1105 | return 0; |
1106 | } | |
7ff879db | 1107 | if (unlikely(csr & OMAP1_DMA_TOUT_IRQ)) |
7852ec05 | 1108 | pr_warn("DMA timeout with device %d\n", dma_chan[ch].dev_id); |
1a8bfa1e | 1109 | if (unlikely(csr & OMAP_DMA_DROP_IRQ)) |
7852ec05 PW |
1110 | pr_warn("DMA synchronization event drop occurred with device %d\n", |
1111 | dma_chan[ch].dev_id); | |
1a8bfa1e TL |
1112 | if (likely(csr & OMAP_DMA_BLOCK_IRQ)) |
1113 | dma_chan[ch].flags &= ~OMAP_DMA_ACTIVE; | |
1114 | if (likely(dma_chan[ch].callback != NULL)) | |
1115 | dma_chan[ch].callback(ch, csr, dma_chan[ch].data); | |
97b7f715 | 1116 | |
1a8bfa1e TL |
1117 | return 1; |
1118 | } | |
1119 | ||
0cd61b68 | 1120 | static irqreturn_t omap1_dma_irq_handler(int irq, void *dev_id) |
1a8bfa1e TL |
1121 | { |
1122 | int ch = ((int) dev_id) - 1; | |
1123 | int handled = 0; | |
1124 | ||
1125 | for (;;) { | |
1126 | int handled_now = 0; | |
1127 | ||
1128 | handled_now += omap1_dma_handle_ch(ch); | |
1129 | if (enable_1510_mode && dma_chan[ch + 6].saved_csr) | |
1130 | handled_now += omap1_dma_handle_ch(ch + 6); | |
1131 | if (!handled_now) | |
1132 | break; | |
1133 | handled += handled_now; | |
1134 | } | |
1135 | ||
1136 | return handled ? IRQ_HANDLED : IRQ_NONE; | |
1137 | } | |
1138 | ||
1139 | #else | |
1140 | #define omap1_dma_irq_handler NULL | |
1141 | #endif | |
1142 | ||
140455fa | 1143 | #ifdef CONFIG_ARCH_OMAP2PLUS |
1a8bfa1e TL |
1144 | |
1145 | static int omap2_dma_handle_ch(int ch) | |
1146 | { | |
f31cc962 | 1147 | u32 status = p->dma_read(CSR, ch); |
1a8bfa1e | 1148 | |
3151369d JY |
1149 | if (!status) { |
1150 | if (printk_ratelimit()) | |
7852ec05 | 1151 | pr_warn("Spurious DMA IRQ for lch %d\n", ch); |
f31cc962 | 1152 | p->dma_write(1 << ch, IRQSTATUS_L0, ch); |
1a8bfa1e | 1153 | return 0; |
3151369d JY |
1154 | } |
1155 | if (unlikely(dma_chan[ch].dev_id == -1)) { | |
1156 | if (printk_ratelimit()) | |
7852ec05 PW |
1157 | pr_warn("IRQ %04x for non-allocated DMA channel %d\n", |
1158 | status, ch); | |
1a8bfa1e | 1159 | return 0; |
3151369d | 1160 | } |
1a8bfa1e | 1161 | if (unlikely(status & OMAP_DMA_DROP_IRQ)) |
7852ec05 PW |
1162 | pr_info("DMA synchronization event drop occurred with device %d\n", |
1163 | dma_chan[ch].dev_id); | |
a50f18c7 | 1164 | if (unlikely(status & OMAP2_DMA_TRANS_ERR_IRQ)) { |
1a8bfa1e TL |
1165 | printk(KERN_INFO "DMA transaction error with device %d\n", |
1166 | dma_chan[ch].dev_id); | |
d3c9be2f | 1167 | if (IS_DMA_ERRATA(DMA_ERRATA_i378)) { |
a50f18c7 SS |
1168 | u32 ccr; |
1169 | ||
f31cc962 | 1170 | ccr = p->dma_read(CCR, ch); |
a50f18c7 | 1171 | ccr &= ~OMAP_DMA_CCR_EN; |
f31cc962 | 1172 | p->dma_write(ccr, CCR, ch); |
a50f18c7 SS |
1173 | dma_chan[ch].flags &= ~OMAP_DMA_ACTIVE; |
1174 | } | |
1175 | } | |
7ff879db TL |
1176 | if (unlikely(status & OMAP2_DMA_SECURE_ERR_IRQ)) |
1177 | printk(KERN_INFO "DMA secure error with device %d\n", | |
1178 | dma_chan[ch].dev_id); | |
1179 | if (unlikely(status & OMAP2_DMA_MISALIGNED_ERR_IRQ)) | |
1180 | printk(KERN_INFO "DMA misaligned error with device %d\n", | |
1181 | dma_chan[ch].dev_id); | |
1a8bfa1e | 1182 | |
4fb699b4 | 1183 | p->dma_write(status, CSR, ch); |
f31cc962 | 1184 | p->dma_write(1 << ch, IRQSTATUS_L0, ch); |
e860e6da | 1185 | /* read back the register to flush the write */ |
f31cc962 | 1186 | p->dma_read(IRQSTATUS_L0, ch); |
1a8bfa1e | 1187 | |
f8151e5c AG |
1188 | /* If the ch is not chained then chain_id will be -1 */ |
1189 | if (dma_chan[ch].chain_id != -1) { | |
1190 | int chain_id = dma_chan[ch].chain_id; | |
1191 | dma_chan[ch].state = DMA_CH_NOTSTARTED; | |
f31cc962 | 1192 | if (p->dma_read(CLNK_CTRL, ch) & (1 << 15)) |
f8151e5c AG |
1193 | dma_chan[dma_chan[ch].next_linked_ch].state = |
1194 | DMA_CH_STARTED; | |
1195 | if (dma_linked_lch[chain_id].chain_mode == | |
1196 | OMAP_DMA_DYNAMIC_CHAIN) | |
1197 | disable_lnk(ch); | |
1198 | ||
1199 | if (!OMAP_DMA_CHAIN_QEMPTY(chain_id)) | |
1200 | OMAP_DMA_CHAIN_INCQHEAD(chain_id); | |
1201 | ||
f31cc962 | 1202 | status = p->dma_read(CSR, ch); |
4fb699b4 | 1203 | p->dma_write(status, CSR, ch); |
f8151e5c AG |
1204 | } |
1205 | ||
538528de JN |
1206 | if (likely(dma_chan[ch].callback != NULL)) |
1207 | dma_chan[ch].callback(ch, status, dma_chan[ch].data); | |
f8151e5c | 1208 | |
1a8bfa1e TL |
1209 | return 0; |
1210 | } | |
1211 | ||
1212 | /* STATUS register count is from 1-32 while our is 0-31 */ | |
0cd61b68 | 1213 | static irqreturn_t omap2_dma_irq_handler(int irq, void *dev_id) |
1a8bfa1e | 1214 | { |
52176e70 | 1215 | u32 val, enable_reg; |
1a8bfa1e TL |
1216 | int i; |
1217 | ||
f31cc962 | 1218 | val = p->dma_read(IRQSTATUS_L0, 0); |
3151369d JY |
1219 | if (val == 0) { |
1220 | if (printk_ratelimit()) | |
1221 | printk(KERN_WARNING "Spurious DMA IRQ\n"); | |
1222 | return IRQ_HANDLED; | |
1223 | } | |
f31cc962 | 1224 | enable_reg = p->dma_read(IRQENABLE_L0, 0); |
52176e70 | 1225 | val &= enable_reg; /* Dispatch only relevant interrupts */ |
4d96372e | 1226 | for (i = 0; i < dma_lch_count && val != 0; i++) { |
3151369d JY |
1227 | if (val & 1) |
1228 | omap2_dma_handle_ch(i); | |
1229 | val >>= 1; | |
1a8bfa1e TL |
1230 | } |
1231 | ||
1232 | return IRQ_HANDLED; | |
1233 | } | |
1234 | ||
1235 | static struct irqaction omap24xx_dma_irq = { | |
1236 | .name = "DMA", | |
1237 | .handler = omap2_dma_irq_handler, | |
1a8bfa1e TL |
1238 | }; |
1239 | ||
1240 | #else | |
1241 | static struct irqaction omap24xx_dma_irq; | |
1242 | #endif | |
1243 | ||
1244 | /*----------------------------------------------------------------------------*/ | |
5e1c5ff4 | 1245 | |
9ce2482f TL |
1246 | /* |
1247 | * Note that we are currently using only IRQENABLE_L0 and L1. | |
1248 | * As the DSP may be using IRQENABLE_L2 and L3, let's not | |
1249 | * touch those for now. | |
1250 | */ | |
f2d11858 TK |
1251 | void omap_dma_global_context_save(void) |
1252 | { | |
1253 | omap_dma_global_context.dma_irqenable_l0 = | |
f31cc962 | 1254 | p->dma_read(IRQENABLE_L0, 0); |
9ce2482f TL |
1255 | omap_dma_global_context.dma_irqenable_l1 = |
1256 | p->dma_read(IRQENABLE_L1, 0); | |
f2d11858 | 1257 | omap_dma_global_context.dma_ocp_sysconfig = |
f31cc962 MK |
1258 | p->dma_read(OCP_SYSCONFIG, 0); |
1259 | omap_dma_global_context.dma_gcr = p->dma_read(GCR, 0); | |
f2d11858 TK |
1260 | } |
1261 | ||
1262 | void omap_dma_global_context_restore(void) | |
1263 | { | |
bf07c9f2 AK |
1264 | int ch; |
1265 | ||
f31cc962 MK |
1266 | p->dma_write(omap_dma_global_context.dma_gcr, GCR, 0); |
1267 | p->dma_write(omap_dma_global_context.dma_ocp_sysconfig, | |
a4c537c7 | 1268 | OCP_SYSCONFIG, 0); |
f31cc962 | 1269 | p->dma_write(omap_dma_global_context.dma_irqenable_l0, |
a4c537c7 | 1270 | IRQENABLE_L0, 0); |
9ce2482f TL |
1271 | p->dma_write(omap_dma_global_context.dma_irqenable_l1, |
1272 | IRQENABLE_L1, 0); | |
f2d11858 | 1273 | |
d3c9be2f | 1274 | if (IS_DMA_ERRATA(DMA_ROMCODE_BUG)) |
f31cc962 | 1275 | p->dma_write(0x3 , IRQSTATUS_L0, 0); |
bf07c9f2 AK |
1276 | |
1277 | for (ch = 0; ch < dma_chan_count; ch++) | |
1278 | if (dma_chan[ch].dev_id != -1) | |
1279 | omap_clear_dma(ch); | |
f2d11858 TK |
1280 | } |
1281 | ||
1b416c4b RK |
1282 | struct omap_system_dma_plat_info *omap_get_plat_info(void) |
1283 | { | |
1284 | return p; | |
1285 | } | |
1286 | EXPORT_SYMBOL_GPL(omap_get_plat_info); | |
1287 | ||
351a102d | 1288 | static int omap_system_dma_probe(struct platform_device *pdev) |
d3c9be2f | 1289 | { |
f31cc962 MK |
1290 | int ch, ret = 0; |
1291 | int dma_irq; | |
1292 | char irq_name[4]; | |
1293 | int irq_rel; | |
1294 | ||
1295 | p = pdev->dev.platform_data; | |
1296 | if (!p) { | |
7852ec05 PW |
1297 | dev_err(&pdev->dev, |
1298 | "%s: System DMA initialized without platform data\n", | |
1299 | __func__); | |
f31cc962 | 1300 | return -EINVAL; |
0499bdeb | 1301 | } |
4d96372e | 1302 | |
f31cc962 MK |
1303 | d = p->dma_attr; |
1304 | errata = p->errata; | |
a4c537c7 | 1305 | |
f31cc962 | 1306 | if ((d->dev_caps & RESERVE_CHANNEL) && omap_dma_reserve_channels |
e78f9606 | 1307 | && (omap_dma_reserve_channels < d->lch_count)) |
f31cc962 | 1308 | d->lch_count = omap_dma_reserve_channels; |
2263f022 | 1309 | |
f31cc962 MK |
1310 | dma_lch_count = d->lch_count; |
1311 | dma_chan_count = dma_lch_count; | |
f31cc962 | 1312 | enable_1510_mode = d->dev_caps & ENABLE_1510_MODE; |
4d96372e | 1313 | |
9834f813 | 1314 | dma_chan = devm_kcalloc(&pdev->dev, dma_lch_count, |
16e7ea53 | 1315 | sizeof(*dma_chan), GFP_KERNEL); |
d679950c | 1316 | if (!dma_chan) |
9834f813 | 1317 | return -ENOMEM; |
9834f813 | 1318 | |
82809601 | 1319 | if (dma_omap2plus()) { |
738c985d ME |
1320 | dma_linked_lch = kcalloc(dma_lch_count, |
1321 | sizeof(*dma_linked_lch), | |
1322 | GFP_KERNEL); | |
4d96372e | 1323 | if (!dma_linked_lch) { |
f31cc962 MK |
1324 | ret = -ENOMEM; |
1325 | goto exit_dma_lch_fail; | |
4d96372e TL |
1326 | } |
1327 | } | |
1328 | ||
5e1c5ff4 | 1329 | spin_lock_init(&dma_chan_lock); |
5e1c5ff4 | 1330 | for (ch = 0; ch < dma_chan_count; ch++) { |
1a8bfa1e | 1331 | omap_clear_dma(ch); |
82809601 | 1332 | if (dma_omap2plus()) |
ada8d4a5 MW |
1333 | omap2_disable_irq_lch(ch); |
1334 | ||
5e1c5ff4 TL |
1335 | dma_chan[ch].dev_id = -1; |
1336 | dma_chan[ch].next_lch = -1; | |
1337 | ||
1338 | if (ch >= 6 && enable_1510_mode) | |
1339 | continue; | |
1340 | ||
82809601 | 1341 | if (dma_omap1()) { |
97b7f715 TL |
1342 | /* |
1343 | * request_irq() doesn't like dev_id (ie. ch) being | |
1344 | * zero, so we have to kludge around this. | |
1345 | */ | |
f31cc962 MK |
1346 | sprintf(&irq_name[0], "%d", ch); |
1347 | dma_irq = platform_get_irq_byname(pdev, irq_name); | |
1348 | ||
1349 | if (dma_irq < 0) { | |
1350 | ret = dma_irq; | |
1351 | goto exit_dma_irq_fail; | |
1352 | } | |
1353 | ||
1354 | /* INT_DMA_LCD is handled in lcd_dma.c */ | |
1355 | if (dma_irq == INT_DMA_LCD) | |
1356 | continue; | |
1357 | ||
1358 | ret = request_irq(dma_irq, | |
1a8bfa1e TL |
1359 | omap1_dma_irq_handler, 0, "DMA", |
1360 | (void *) (ch + 1)); | |
f31cc962 MK |
1361 | if (ret != 0) |
1362 | goto exit_dma_irq_fail; | |
1a8bfa1e TL |
1363 | } |
1364 | } | |
1365 | ||
82809601 | 1366 | if (d->dev_caps & IS_RW_PRIORITY) |
f8151e5c AG |
1367 | omap_dma_set_global_params(DMA_DEFAULT_ARB_RATE, |
1368 | DMA_DEFAULT_FIFO_DEPTH, 0); | |
1369 | ||
76be4a54 | 1370 | if (dma_omap2plus() && !(d->dev_caps & DMA_ENGINE_HANDLE_IRQ)) { |
f31cc962 MK |
1371 | strcpy(irq_name, "0"); |
1372 | dma_irq = platform_get_irq_byname(pdev, irq_name); | |
1373 | if (dma_irq < 0) { | |
1374 | dev_err(&pdev->dev, "failed: request IRQ %d", dma_irq); | |
94b1d617 | 1375 | ret = dma_irq; |
f31cc962 MK |
1376 | goto exit_dma_lch_fail; |
1377 | } | |
1378 | ret = setup_irq(dma_irq, &omap24xx_dma_irq); | |
1379 | if (ret) { | |
7852ec05 PW |
1380 | dev_err(&pdev->dev, "set_up failed for IRQ %d for DMA (error %d)\n", |
1381 | dma_irq, ret); | |
f31cc962 | 1382 | goto exit_dma_lch_fail; |
ba50ea7e | 1383 | } |
aecedb94 KJ |
1384 | } |
1385 | ||
82809601 TL |
1386 | /* reserve dma channels 0 and 1 in high security devices on 34xx */ |
1387 | if (d->dev_caps & HS_CHANNELS_RESERVED) { | |
7852ec05 | 1388 | pr_info("Reserving DMA channels 0 and 1 for HS ROM code\n"); |
f31cc962 MK |
1389 | dma_chan[0].dev_id = 0; |
1390 | dma_chan[1].dev_id = 1; | |
1391 | } | |
1392 | p->show_dma_caps(); | |
5e1c5ff4 | 1393 | return 0; |
7e9bf847 | 1394 | |
f31cc962 | 1395 | exit_dma_irq_fail: |
7852ec05 PW |
1396 | dev_err(&pdev->dev, "unable to request IRQ %d for DMA (error %d)\n", |
1397 | dma_irq, ret); | |
f31cc962 MK |
1398 | for (irq_rel = 0; irq_rel < ch; irq_rel++) { |
1399 | dma_irq = platform_get_irq(pdev, irq_rel); | |
1400 | free_irq(dma_irq, (void *)(irq_rel + 1)); | |
1401 | } | |
1402 | ||
1403 | exit_dma_lch_fail: | |
f31cc962 MK |
1404 | return ret; |
1405 | } | |
7e9bf847 | 1406 | |
351a102d | 1407 | static int omap_system_dma_remove(struct platform_device *pdev) |
f31cc962 MK |
1408 | { |
1409 | int dma_irq; | |
7e9bf847 | 1410 | |
82809601 | 1411 | if (dma_omap2plus()) { |
f31cc962 MK |
1412 | char irq_name[4]; |
1413 | strcpy(irq_name, "0"); | |
1414 | dma_irq = platform_get_irq_byname(pdev, irq_name); | |
76be4a54 NM |
1415 | if (dma_irq >= 0) |
1416 | remove_irq(dma_irq, &omap24xx_dma_irq); | |
f31cc962 MK |
1417 | } else { |
1418 | int irq_rel = 0; | |
1419 | for ( ; irq_rel < dma_chan_count; irq_rel++) { | |
1420 | dma_irq = platform_get_irq(pdev, irq_rel); | |
1421 | free_irq(dma_irq, (void *)(irq_rel + 1)); | |
1422 | } | |
1423 | } | |
f31cc962 MK |
1424 | return 0; |
1425 | } | |
1426 | ||
1427 | static struct platform_driver omap_system_dma_driver = { | |
1428 | .probe = omap_system_dma_probe, | |
351a102d | 1429 | .remove = omap_system_dma_remove, |
f31cc962 MK |
1430 | .driver = { |
1431 | .name = "omap_dma_system" | |
1432 | }, | |
1433 | }; | |
1434 | ||
1435 | static int __init omap_system_dma_init(void) | |
1436 | { | |
1437 | return platform_driver_register(&omap_system_dma_driver); | |
1438 | } | |
1439 | arch_initcall(omap_system_dma_init); | |
1440 | ||
1441 | static void __exit omap_system_dma_exit(void) | |
1442 | { | |
1443 | platform_driver_unregister(&omap_system_dma_driver); | |
5e1c5ff4 TL |
1444 | } |
1445 | ||
f31cc962 MK |
1446 | MODULE_DESCRIPTION("OMAP SYSTEM DMA DRIVER"); |
1447 | MODULE_LICENSE("GPL"); | |
f31cc962 | 1448 | MODULE_AUTHOR("Texas Instruments Inc"); |
5e1c5ff4 | 1449 | |
2263f022 SS |
1450 | /* |
1451 | * Reserve the omap SDMA channels using cmdline bootarg | |
1452 | * "omap_dma_reserve_ch=". The valid range is 1 to 32 | |
1453 | */ | |
1454 | static int __init omap_dma_cmdline_reserve_ch(char *str) | |
1455 | { | |
1456 | if (get_option(&str, &omap_dma_reserve_channels) != 1) | |
1457 | omap_dma_reserve_channels = 0; | |
1458 | return 1; | |
1459 | } | |
1460 | ||
1461 | __setup("omap_dma_reserve_ch=", omap_dma_cmdline_reserve_ch); | |
1462 | ||
5e1c5ff4 | 1463 |