Commit | Line | Data |
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5e1c5ff4 TL |
1 | /* |
2 | * linux/arch/arm/plat-omap/dma.c | |
3 | * | |
97b7f715 | 4 | * Copyright (C) 2003 - 2008 Nokia Corporation |
96de0e25 | 5 | * Author: Juha Yrjölä <juha.yrjola@nokia.com> |
5e1c5ff4 TL |
6 | * DMA channel linking for 1610 by Samuel Ortiz <samuel.ortiz@nokia.com> |
7 | * Graphics DMA and LCD DMA graphics tranformations | |
8 | * by Imre Deak <imre.deak@nokia.com> | |
f8151e5c | 9 | * OMAP2/3 support Copyright (C) 2004-2007 Texas Instruments, Inc. |
1a8bfa1e | 10 | * Merged to support both OMAP1 and OMAP2 by Tony Lindgren <tony@atomide.com> |
5e1c5ff4 TL |
11 | * Some functions based on earlier dma-omap.c Copyright (C) 2001 RidgeRun, Inc. |
12 | * | |
44169075 SS |
13 | * Copyright (C) 2009 Texas Instruments |
14 | * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com> | |
15 | * | |
5e1c5ff4 TL |
16 | * Support functions for the OMAP internal DMA channels. |
17 | * | |
f31cc962 MK |
18 | * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/ |
19 | * Converted DMA library into DMA platform driver. | |
20 | * - G, Manjunath Kondaiah <manjugk@ti.com> | |
21 | * | |
5e1c5ff4 TL |
22 | * This program is free software; you can redistribute it and/or modify |
23 | * it under the terms of the GNU General Public License version 2 as | |
24 | * published by the Free Software Foundation. | |
25 | * | |
26 | */ | |
27 | ||
28 | #include <linux/module.h> | |
29 | #include <linux/init.h> | |
30 | #include <linux/sched.h> | |
31 | #include <linux/spinlock.h> | |
32 | #include <linux/errno.h> | |
33 | #include <linux/interrupt.h> | |
418ca1f0 | 34 | #include <linux/irq.h> |
97b7f715 | 35 | #include <linux/io.h> |
5a0e3ad6 | 36 | #include <linux/slab.h> |
0e4905c0 | 37 | #include <linux/delay.h> |
5e1c5ff4 | 38 | |
a09e64fb | 39 | #include <mach/hardware.h> |
ce491cf8 | 40 | #include <plat/dma.h> |
5e1c5ff4 | 41 | |
ce491cf8 | 42 | #include <plat/tc.h> |
5e1c5ff4 | 43 | |
f8151e5c AG |
44 | #undef DEBUG |
45 | ||
46 | #ifndef CONFIG_ARCH_OMAP1 | |
47 | enum { DMA_CH_ALLOC_DONE, DMA_CH_PARAMS_SET_DONE, DMA_CH_STARTED, | |
48 | DMA_CH_QUEUED, DMA_CH_NOTSTARTED, DMA_CH_PAUSED, DMA_CH_LINK_ENABLED | |
49 | }; | |
50 | ||
51 | enum { DMA_CHAIN_STARTED, DMA_CHAIN_NOTSTARTED }; | |
1a8bfa1e | 52 | #endif |
5e1c5ff4 | 53 | |
97b7f715 | 54 | #define OMAP_DMA_ACTIVE 0x01 |
4fb699b4 | 55 | #define OMAP2_DMA_CSR_CLEAR_MASK 0xffffffff |
5e1c5ff4 | 56 | |
97b7f715 | 57 | #define OMAP_FUNC_MUX_ARM_BASE (0xfffe1000 + 0xec) |
5e1c5ff4 | 58 | |
f31cc962 MK |
59 | static struct omap_system_dma_plat_info *p; |
60 | static struct omap_dma_dev_attr *d; | |
61 | ||
97b7f715 | 62 | static int enable_1510_mode; |
d3c9be2f | 63 | static u32 errata; |
5e1c5ff4 | 64 | |
f2d11858 TK |
65 | static struct omap_dma_global_context_registers { |
66 | u32 dma_irqenable_l0; | |
67 | u32 dma_ocp_sysconfig; | |
68 | u32 dma_gcr; | |
69 | } omap_dma_global_context; | |
70 | ||
f8151e5c AG |
71 | struct dma_link_info { |
72 | int *linked_dmach_q; | |
73 | int no_of_lchs_linked; | |
74 | ||
75 | int q_count; | |
76 | int q_tail; | |
77 | int q_head; | |
78 | ||
79 | int chain_state; | |
80 | int chain_mode; | |
81 | ||
82 | }; | |
83 | ||
4d96372e TL |
84 | static struct dma_link_info *dma_linked_lch; |
85 | ||
86 | #ifndef CONFIG_ARCH_OMAP1 | |
f8151e5c AG |
87 | |
88 | /* Chain handling macros */ | |
89 | #define OMAP_DMA_CHAIN_QINIT(chain_id) \ | |
90 | do { \ | |
91 | dma_linked_lch[chain_id].q_head = \ | |
92 | dma_linked_lch[chain_id].q_tail = \ | |
93 | dma_linked_lch[chain_id].q_count = 0; \ | |
94 | } while (0) | |
95 | #define OMAP_DMA_CHAIN_QFULL(chain_id) \ | |
96 | (dma_linked_lch[chain_id].no_of_lchs_linked == \ | |
97 | dma_linked_lch[chain_id].q_count) | |
98 | #define OMAP_DMA_CHAIN_QLAST(chain_id) \ | |
99 | do { \ | |
100 | ((dma_linked_lch[chain_id].no_of_lchs_linked-1) == \ | |
101 | dma_linked_lch[chain_id].q_count) \ | |
102 | } while (0) | |
103 | #define OMAP_DMA_CHAIN_QEMPTY(chain_id) \ | |
104 | (0 == dma_linked_lch[chain_id].q_count) | |
105 | #define __OMAP_DMA_CHAIN_INCQ(end) \ | |
106 | ((end) = ((end)+1) % dma_linked_lch[chain_id].no_of_lchs_linked) | |
107 | #define OMAP_DMA_CHAIN_INCQHEAD(chain_id) \ | |
108 | do { \ | |
109 | __OMAP_DMA_CHAIN_INCQ(dma_linked_lch[chain_id].q_head); \ | |
110 | dma_linked_lch[chain_id].q_count--; \ | |
111 | } while (0) | |
112 | ||
113 | #define OMAP_DMA_CHAIN_INCQTAIL(chain_id) \ | |
114 | do { \ | |
115 | __OMAP_DMA_CHAIN_INCQ(dma_linked_lch[chain_id].q_tail); \ | |
116 | dma_linked_lch[chain_id].q_count++; \ | |
117 | } while (0) | |
118 | #endif | |
4d96372e TL |
119 | |
120 | static int dma_lch_count; | |
5e1c5ff4 | 121 | static int dma_chan_count; |
2263f022 | 122 | static int omap_dma_reserve_channels; |
5e1c5ff4 TL |
123 | |
124 | static spinlock_t dma_chan_lock; | |
4d96372e | 125 | static struct omap_dma_lch *dma_chan; |
5e1c5ff4 | 126 | |
f8151e5c AG |
127 | static inline void disable_lnk(int lch); |
128 | static void omap_disable_channel_irq(int lch); | |
129 | static inline void omap_enable_channel_irq(int lch); | |
130 | ||
1a8bfa1e | 131 | #define REVISIT_24XX() printk(KERN_ERR "FIXME: no %s on 24xx\n", \ |
8e86f427 | 132 | __func__); |
1a8bfa1e TL |
133 | |
134 | #ifdef CONFIG_ARCH_OMAP15XX | |
135 | /* Returns 1 if the DMA module is in OMAP1510-compatible mode, 0 otherwise */ | |
c7767582 | 136 | static int omap_dma_in_1510_mode(void) |
1a8bfa1e TL |
137 | { |
138 | return enable_1510_mode; | |
139 | } | |
140 | #else | |
141 | #define omap_dma_in_1510_mode() 0 | |
142 | #endif | |
143 | ||
144 | #ifdef CONFIG_ARCH_OMAP1 | |
5e1c5ff4 TL |
145 | static inline int get_gdma_dev(int req) |
146 | { | |
147 | u32 reg = OMAP_FUNC_MUX_ARM_BASE + ((req - 1) / 5) * 4; | |
148 | int shift = ((req - 1) % 5) * 6; | |
149 | ||
150 | return ((omap_readl(reg) >> shift) & 0x3f) + 1; | |
151 | } | |
152 | ||
153 | static inline void set_gdma_dev(int req, int dev) | |
154 | { | |
155 | u32 reg = OMAP_FUNC_MUX_ARM_BASE + ((req - 1) / 5) * 4; | |
156 | int shift = ((req - 1) % 5) * 6; | |
157 | u32 l; | |
158 | ||
159 | l = omap_readl(reg); | |
160 | l &= ~(0x3f << shift); | |
161 | l |= (dev - 1) << shift; | |
162 | omap_writel(l, reg); | |
163 | } | |
1a8bfa1e TL |
164 | #else |
165 | #define set_gdma_dev(req, dev) do {} while (0) | |
2c799cef TL |
166 | #define omap_readl(reg) 0 |
167 | #define omap_writel(val, reg) do {} while (0) | |
1a8bfa1e | 168 | #endif |
5e1c5ff4 | 169 | |
709eb3e5 | 170 | void omap_set_dma_priority(int lch, int dst_port, int priority) |
5e1c5ff4 TL |
171 | { |
172 | unsigned long reg; | |
173 | u32 l; | |
174 | ||
709eb3e5 TL |
175 | if (cpu_class_is_omap1()) { |
176 | switch (dst_port) { | |
177 | case OMAP_DMA_PORT_OCP_T1: /* FFFECC00 */ | |
178 | reg = OMAP_TC_OCPT1_PRIOR; | |
179 | break; | |
180 | case OMAP_DMA_PORT_OCP_T2: /* FFFECCD0 */ | |
181 | reg = OMAP_TC_OCPT2_PRIOR; | |
182 | break; | |
183 | case OMAP_DMA_PORT_EMIFF: /* FFFECC08 */ | |
184 | reg = OMAP_TC_EMIFF_PRIOR; | |
185 | break; | |
186 | case OMAP_DMA_PORT_EMIFS: /* FFFECC04 */ | |
187 | reg = OMAP_TC_EMIFS_PRIOR; | |
188 | break; | |
189 | default: | |
190 | BUG(); | |
191 | return; | |
192 | } | |
193 | l = omap_readl(reg); | |
194 | l &= ~(0xf << 8); | |
195 | l |= (priority & 0xf) << 8; | |
196 | omap_writel(l, reg); | |
197 | } | |
198 | ||
f8151e5c | 199 | if (cpu_class_is_omap2()) { |
0499bdeb TL |
200 | u32 ccr; |
201 | ||
f31cc962 | 202 | ccr = p->dma_read(CCR, lch); |
709eb3e5 | 203 | if (priority) |
0499bdeb | 204 | ccr |= (1 << 6); |
709eb3e5 | 205 | else |
0499bdeb | 206 | ccr &= ~(1 << 6); |
f31cc962 | 207 | p->dma_write(ccr, CCR, lch); |
5e1c5ff4 | 208 | } |
5e1c5ff4 | 209 | } |
97b7f715 | 210 | EXPORT_SYMBOL(omap_set_dma_priority); |
5e1c5ff4 TL |
211 | |
212 | void omap_set_dma_transfer_params(int lch, int data_type, int elem_count, | |
1a8bfa1e TL |
213 | int frame_count, int sync_mode, |
214 | int dma_trigger, int src_or_dst_synch) | |
5e1c5ff4 | 215 | { |
0499bdeb TL |
216 | u32 l; |
217 | ||
f31cc962 | 218 | l = p->dma_read(CSDP, lch); |
0499bdeb TL |
219 | l &= ~0x03; |
220 | l |= data_type; | |
f31cc962 | 221 | p->dma_write(l, CSDP, lch); |
5e1c5ff4 | 222 | |
1a8bfa1e | 223 | if (cpu_class_is_omap1()) { |
0499bdeb TL |
224 | u16 ccr; |
225 | ||
f31cc962 | 226 | ccr = p->dma_read(CCR, lch); |
0499bdeb | 227 | ccr &= ~(1 << 5); |
1a8bfa1e | 228 | if (sync_mode == OMAP_DMA_SYNC_FRAME) |
0499bdeb | 229 | ccr |= 1 << 5; |
f31cc962 | 230 | p->dma_write(ccr, CCR, lch); |
1a8bfa1e | 231 | |
f31cc962 | 232 | ccr = p->dma_read(CCR2, lch); |
0499bdeb | 233 | ccr &= ~(1 << 2); |
1a8bfa1e | 234 | if (sync_mode == OMAP_DMA_SYNC_BLOCK) |
0499bdeb | 235 | ccr |= 1 << 2; |
f31cc962 | 236 | p->dma_write(ccr, CCR2, lch); |
1a8bfa1e TL |
237 | } |
238 | ||
f8151e5c | 239 | if (cpu_class_is_omap2() && dma_trigger) { |
0499bdeb | 240 | u32 val; |
1a8bfa1e | 241 | |
f31cc962 | 242 | val = p->dma_read(CCR, lch); |
4b3cf448 AG |
243 | |
244 | /* DMA_SYNCHRO_CONTROL_UPPER depends on the channel number */ | |
72a1179e | 245 | val &= ~((1 << 23) | (3 << 19) | 0x1f); |
4b3cf448 AG |
246 | val |= (dma_trigger & ~0x1f) << 14; |
247 | val |= dma_trigger & 0x1f; | |
5e1c5ff4 | 248 | |
1a8bfa1e TL |
249 | if (sync_mode & OMAP_DMA_SYNC_FRAME) |
250 | val |= 1 << 5; | |
eca9e56e PU |
251 | else |
252 | val &= ~(1 << 5); | |
5e1c5ff4 | 253 | |
1a8bfa1e TL |
254 | if (sync_mode & OMAP_DMA_SYNC_BLOCK) |
255 | val |= 1 << 18; | |
eca9e56e PU |
256 | else |
257 | val &= ~(1 << 18); | |
5e1c5ff4 | 258 | |
72a1179e SO |
259 | if (src_or_dst_synch == OMAP_DMA_DST_SYNC_PREFETCH) { |
260 | val &= ~(1 << 24); /* dest synch */ | |
261 | val |= (1 << 23); /* Prefetch */ | |
262 | } else if (src_or_dst_synch) { | |
1a8bfa1e | 263 | val |= 1 << 24; /* source synch */ |
72a1179e | 264 | } else { |
1a8bfa1e | 265 | val &= ~(1 << 24); /* dest synch */ |
72a1179e | 266 | } |
f31cc962 | 267 | p->dma_write(val, CCR, lch); |
1a8bfa1e TL |
268 | } |
269 | ||
f31cc962 MK |
270 | p->dma_write(elem_count, CEN, lch); |
271 | p->dma_write(frame_count, CFN, lch); | |
5e1c5ff4 | 272 | } |
97b7f715 | 273 | EXPORT_SYMBOL(omap_set_dma_transfer_params); |
1a8bfa1e | 274 | |
5e1c5ff4 TL |
275 | void omap_set_dma_color_mode(int lch, enum omap_dma_color_mode mode, u32 color) |
276 | { | |
5e1c5ff4 TL |
277 | BUG_ON(omap_dma_in_1510_mode()); |
278 | ||
0815f8ea TV |
279 | if (cpu_class_is_omap1()) { |
280 | u16 w; | |
1a8bfa1e | 281 | |
f31cc962 | 282 | w = p->dma_read(CCR2, lch); |
0815f8ea TV |
283 | w &= ~0x03; |
284 | ||
285 | switch (mode) { | |
286 | case OMAP_DMA_CONSTANT_FILL: | |
287 | w |= 0x01; | |
288 | break; | |
289 | case OMAP_DMA_TRANSPARENT_COPY: | |
290 | w |= 0x02; | |
291 | break; | |
292 | case OMAP_DMA_COLOR_DIS: | |
293 | break; | |
294 | default: | |
295 | BUG(); | |
296 | } | |
f31cc962 | 297 | p->dma_write(w, CCR2, lch); |
0815f8ea | 298 | |
f31cc962 | 299 | w = p->dma_read(LCH_CTRL, lch); |
0815f8ea TV |
300 | w &= ~0x0f; |
301 | /* Default is channel type 2D */ | |
302 | if (mode) { | |
f31cc962 | 303 | p->dma_write(color, COLOR, lch); |
0815f8ea TV |
304 | w |= 1; /* Channel type G */ |
305 | } | |
f31cc962 | 306 | p->dma_write(w, LCH_CTRL, lch); |
5e1c5ff4 | 307 | } |
0815f8ea TV |
308 | |
309 | if (cpu_class_is_omap2()) { | |
310 | u32 val; | |
311 | ||
f31cc962 | 312 | val = p->dma_read(CCR, lch); |
0815f8ea TV |
313 | val &= ~((1 << 17) | (1 << 16)); |
314 | ||
315 | switch (mode) { | |
316 | case OMAP_DMA_CONSTANT_FILL: | |
317 | val |= 1 << 16; | |
318 | break; | |
319 | case OMAP_DMA_TRANSPARENT_COPY: | |
320 | val |= 1 << 17; | |
321 | break; | |
322 | case OMAP_DMA_COLOR_DIS: | |
323 | break; | |
324 | default: | |
325 | BUG(); | |
326 | } | |
f31cc962 | 327 | p->dma_write(val, CCR, lch); |
0815f8ea TV |
328 | |
329 | color &= 0xffffff; | |
f31cc962 | 330 | p->dma_write(color, COLOR, lch); |
5e1c5ff4 | 331 | } |
5e1c5ff4 | 332 | } |
97b7f715 | 333 | EXPORT_SYMBOL(omap_set_dma_color_mode); |
5e1c5ff4 | 334 | |
709eb3e5 TL |
335 | void omap_set_dma_write_mode(int lch, enum omap_dma_write_mode mode) |
336 | { | |
f8151e5c | 337 | if (cpu_class_is_omap2()) { |
0499bdeb TL |
338 | u32 csdp; |
339 | ||
f31cc962 | 340 | csdp = p->dma_read(CSDP, lch); |
0499bdeb TL |
341 | csdp &= ~(0x3 << 16); |
342 | csdp |= (mode << 16); | |
f31cc962 | 343 | p->dma_write(csdp, CSDP, lch); |
709eb3e5 TL |
344 | } |
345 | } | |
97b7f715 | 346 | EXPORT_SYMBOL(omap_set_dma_write_mode); |
709eb3e5 | 347 | |
0499bdeb TL |
348 | void omap_set_dma_channel_mode(int lch, enum omap_dma_channel_mode mode) |
349 | { | |
350 | if (cpu_class_is_omap1() && !cpu_is_omap15xx()) { | |
351 | u32 l; | |
352 | ||
f31cc962 | 353 | l = p->dma_read(LCH_CTRL, lch); |
0499bdeb TL |
354 | l &= ~0x7; |
355 | l |= mode; | |
f31cc962 | 356 | p->dma_write(l, LCH_CTRL, lch); |
0499bdeb TL |
357 | } |
358 | } | |
359 | EXPORT_SYMBOL(omap_set_dma_channel_mode); | |
360 | ||
1a8bfa1e | 361 | /* Note that src_port is only for omap1 */ |
5e1c5ff4 | 362 | void omap_set_dma_src_params(int lch, int src_port, int src_amode, |
1a8bfa1e TL |
363 | unsigned long src_start, |
364 | int src_ei, int src_fi) | |
5e1c5ff4 | 365 | { |
97b7f715 TL |
366 | u32 l; |
367 | ||
1a8bfa1e | 368 | if (cpu_class_is_omap1()) { |
0499bdeb | 369 | u16 w; |
1a8bfa1e | 370 | |
f31cc962 | 371 | w = p->dma_read(CSDP, lch); |
0499bdeb TL |
372 | w &= ~(0x1f << 2); |
373 | w |= src_port << 2; | |
f31cc962 | 374 | p->dma_write(w, CSDP, lch); |
97b7f715 | 375 | } |
1a8bfa1e | 376 | |
f31cc962 | 377 | l = p->dma_read(CCR, lch); |
97b7f715 TL |
378 | l &= ~(0x03 << 12); |
379 | l |= src_amode << 12; | |
f31cc962 | 380 | p->dma_write(l, CCR, lch); |
0499bdeb | 381 | |
f31cc962 | 382 | p->dma_write(src_start, CSSA, lch); |
5e1c5ff4 | 383 | |
f31cc962 MK |
384 | p->dma_write(src_ei, CSEI, lch); |
385 | p->dma_write(src_fi, CSFI, lch); | |
1a8bfa1e | 386 | } |
97b7f715 | 387 | EXPORT_SYMBOL(omap_set_dma_src_params); |
5e1c5ff4 | 388 | |
97b7f715 | 389 | void omap_set_dma_params(int lch, struct omap_dma_channel_params *params) |
1a8bfa1e TL |
390 | { |
391 | omap_set_dma_transfer_params(lch, params->data_type, | |
392 | params->elem_count, params->frame_count, | |
393 | params->sync_mode, params->trigger, | |
394 | params->src_or_dst_synch); | |
395 | omap_set_dma_src_params(lch, params->src_port, | |
396 | params->src_amode, params->src_start, | |
397 | params->src_ei, params->src_fi); | |
398 | ||
399 | omap_set_dma_dest_params(lch, params->dst_port, | |
400 | params->dst_amode, params->dst_start, | |
401 | params->dst_ei, params->dst_fi); | |
f8151e5c AG |
402 | if (params->read_prio || params->write_prio) |
403 | omap_dma_set_prio_lch(lch, params->read_prio, | |
404 | params->write_prio); | |
5e1c5ff4 | 405 | } |
97b7f715 | 406 | EXPORT_SYMBOL(omap_set_dma_params); |
5e1c5ff4 TL |
407 | |
408 | void omap_set_dma_src_index(int lch, int eidx, int fidx) | |
409 | { | |
97b7f715 | 410 | if (cpu_class_is_omap2()) |
1a8bfa1e | 411 | return; |
97b7f715 | 412 | |
f31cc962 MK |
413 | p->dma_write(eidx, CSEI, lch); |
414 | p->dma_write(fidx, CSFI, lch); | |
5e1c5ff4 | 415 | } |
97b7f715 | 416 | EXPORT_SYMBOL(omap_set_dma_src_index); |
5e1c5ff4 TL |
417 | |
418 | void omap_set_dma_src_data_pack(int lch, int enable) | |
419 | { | |
0499bdeb TL |
420 | u32 l; |
421 | ||
f31cc962 | 422 | l = p->dma_read(CSDP, lch); |
0499bdeb | 423 | l &= ~(1 << 6); |
1a8bfa1e | 424 | if (enable) |
0499bdeb | 425 | l |= (1 << 6); |
f31cc962 | 426 | p->dma_write(l, CSDP, lch); |
5e1c5ff4 | 427 | } |
97b7f715 | 428 | EXPORT_SYMBOL(omap_set_dma_src_data_pack); |
5e1c5ff4 TL |
429 | |
430 | void omap_set_dma_src_burst_mode(int lch, enum omap_dma_burst_mode burst_mode) | |
431 | { | |
6dc3c8f2 | 432 | unsigned int burst = 0; |
0499bdeb TL |
433 | u32 l; |
434 | ||
f31cc962 | 435 | l = p->dma_read(CSDP, lch); |
0499bdeb | 436 | l &= ~(0x03 << 7); |
5e1c5ff4 | 437 | |
5e1c5ff4 TL |
438 | switch (burst_mode) { |
439 | case OMAP_DMA_DATA_BURST_DIS: | |
440 | break; | |
441 | case OMAP_DMA_DATA_BURST_4: | |
f8151e5c | 442 | if (cpu_class_is_omap2()) |
6dc3c8f2 KP |
443 | burst = 0x1; |
444 | else | |
445 | burst = 0x2; | |
5e1c5ff4 TL |
446 | break; |
447 | case OMAP_DMA_DATA_BURST_8: | |
f8151e5c | 448 | if (cpu_class_is_omap2()) { |
6dc3c8f2 KP |
449 | burst = 0x2; |
450 | break; | |
451 | } | |
ea221a6a | 452 | /* |
453 | * not supported by current hardware on OMAP1 | |
5e1c5ff4 TL |
454 | * w |= (0x03 << 7); |
455 | * fall through | |
456 | */ | |
6dc3c8f2 | 457 | case OMAP_DMA_DATA_BURST_16: |
f8151e5c | 458 | if (cpu_class_is_omap2()) { |
6dc3c8f2 KP |
459 | burst = 0x3; |
460 | break; | |
461 | } | |
ea221a6a | 462 | /* |
463 | * OMAP1 don't support burst 16 | |
6dc3c8f2 KP |
464 | * fall through |
465 | */ | |
5e1c5ff4 TL |
466 | default: |
467 | BUG(); | |
468 | } | |
0499bdeb TL |
469 | |
470 | l |= (burst << 7); | |
f31cc962 | 471 | p->dma_write(l, CSDP, lch); |
5e1c5ff4 | 472 | } |
97b7f715 | 473 | EXPORT_SYMBOL(omap_set_dma_src_burst_mode); |
5e1c5ff4 | 474 | |
1a8bfa1e | 475 | /* Note that dest_port is only for OMAP1 */ |
5e1c5ff4 | 476 | void omap_set_dma_dest_params(int lch, int dest_port, int dest_amode, |
1a8bfa1e TL |
477 | unsigned long dest_start, |
478 | int dst_ei, int dst_fi) | |
5e1c5ff4 | 479 | { |
0499bdeb TL |
480 | u32 l; |
481 | ||
1a8bfa1e | 482 | if (cpu_class_is_omap1()) { |
f31cc962 | 483 | l = p->dma_read(CSDP, lch); |
0499bdeb TL |
484 | l &= ~(0x1f << 9); |
485 | l |= dest_port << 9; | |
f31cc962 | 486 | p->dma_write(l, CSDP, lch); |
1a8bfa1e | 487 | } |
5e1c5ff4 | 488 | |
f31cc962 | 489 | l = p->dma_read(CCR, lch); |
0499bdeb TL |
490 | l &= ~(0x03 << 14); |
491 | l |= dest_amode << 14; | |
f31cc962 | 492 | p->dma_write(l, CCR, lch); |
5e1c5ff4 | 493 | |
f31cc962 | 494 | p->dma_write(dest_start, CDSA, lch); |
5e1c5ff4 | 495 | |
f31cc962 MK |
496 | p->dma_write(dst_ei, CDEI, lch); |
497 | p->dma_write(dst_fi, CDFI, lch); | |
5e1c5ff4 | 498 | } |
97b7f715 | 499 | EXPORT_SYMBOL(omap_set_dma_dest_params); |
5e1c5ff4 TL |
500 | |
501 | void omap_set_dma_dest_index(int lch, int eidx, int fidx) | |
502 | { | |
97b7f715 | 503 | if (cpu_class_is_omap2()) |
1a8bfa1e | 504 | return; |
97b7f715 | 505 | |
f31cc962 MK |
506 | p->dma_write(eidx, CDEI, lch); |
507 | p->dma_write(fidx, CDFI, lch); | |
5e1c5ff4 | 508 | } |
97b7f715 | 509 | EXPORT_SYMBOL(omap_set_dma_dest_index); |
5e1c5ff4 TL |
510 | |
511 | void omap_set_dma_dest_data_pack(int lch, int enable) | |
512 | { | |
0499bdeb TL |
513 | u32 l; |
514 | ||
f31cc962 | 515 | l = p->dma_read(CSDP, lch); |
0499bdeb | 516 | l &= ~(1 << 13); |
1a8bfa1e | 517 | if (enable) |
0499bdeb | 518 | l |= 1 << 13; |
f31cc962 | 519 | p->dma_write(l, CSDP, lch); |
5e1c5ff4 | 520 | } |
97b7f715 | 521 | EXPORT_SYMBOL(omap_set_dma_dest_data_pack); |
5e1c5ff4 TL |
522 | |
523 | void omap_set_dma_dest_burst_mode(int lch, enum omap_dma_burst_mode burst_mode) | |
524 | { | |
6dc3c8f2 | 525 | unsigned int burst = 0; |
0499bdeb TL |
526 | u32 l; |
527 | ||
f31cc962 | 528 | l = p->dma_read(CSDP, lch); |
0499bdeb | 529 | l &= ~(0x03 << 14); |
5e1c5ff4 | 530 | |
5e1c5ff4 TL |
531 | switch (burst_mode) { |
532 | case OMAP_DMA_DATA_BURST_DIS: | |
533 | break; | |
534 | case OMAP_DMA_DATA_BURST_4: | |
f8151e5c | 535 | if (cpu_class_is_omap2()) |
6dc3c8f2 KP |
536 | burst = 0x1; |
537 | else | |
538 | burst = 0x2; | |
5e1c5ff4 TL |
539 | break; |
540 | case OMAP_DMA_DATA_BURST_8: | |
f8151e5c | 541 | if (cpu_class_is_omap2()) |
6dc3c8f2 KP |
542 | burst = 0x2; |
543 | else | |
544 | burst = 0x3; | |
5e1c5ff4 | 545 | break; |
6dc3c8f2 | 546 | case OMAP_DMA_DATA_BURST_16: |
f8151e5c | 547 | if (cpu_class_is_omap2()) { |
6dc3c8f2 KP |
548 | burst = 0x3; |
549 | break; | |
550 | } | |
ea221a6a | 551 | /* |
552 | * OMAP1 don't support burst 16 | |
6dc3c8f2 KP |
553 | * fall through |
554 | */ | |
5e1c5ff4 TL |
555 | default: |
556 | printk(KERN_ERR "Invalid DMA burst mode\n"); | |
557 | BUG(); | |
558 | return; | |
559 | } | |
0499bdeb | 560 | l |= (burst << 14); |
f31cc962 | 561 | p->dma_write(l, CSDP, lch); |
5e1c5ff4 | 562 | } |
97b7f715 | 563 | EXPORT_SYMBOL(omap_set_dma_dest_burst_mode); |
5e1c5ff4 | 564 | |
1a8bfa1e | 565 | static inline void omap_enable_channel_irq(int lch) |
5e1c5ff4 | 566 | { |
1a8bfa1e | 567 | u32 status; |
5e1c5ff4 | 568 | |
7ff879db TL |
569 | /* Clear CSR */ |
570 | if (cpu_class_is_omap1()) | |
f31cc962 | 571 | status = p->dma_read(CSR, lch); |
f8151e5c | 572 | else if (cpu_class_is_omap2()) |
f31cc962 | 573 | p->dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR, lch); |
1a8bfa1e | 574 | |
5e1c5ff4 | 575 | /* Enable some nice interrupts. */ |
f31cc962 | 576 | p->dma_write(dma_chan[lch].enabled_irqs, CICR, lch); |
5e1c5ff4 TL |
577 | } |
578 | ||
1a8bfa1e | 579 | static void omap_disable_channel_irq(int lch) |
5e1c5ff4 | 580 | { |
f8151e5c | 581 | if (cpu_class_is_omap2()) |
f31cc962 | 582 | p->dma_write(0, CICR, lch); |
1a8bfa1e TL |
583 | } |
584 | ||
585 | void omap_enable_dma_irq(int lch, u16 bits) | |
586 | { | |
587 | dma_chan[lch].enabled_irqs |= bits; | |
588 | } | |
97b7f715 | 589 | EXPORT_SYMBOL(omap_enable_dma_irq); |
5e1c5ff4 | 590 | |
1a8bfa1e TL |
591 | void omap_disable_dma_irq(int lch, u16 bits) |
592 | { | |
593 | dma_chan[lch].enabled_irqs &= ~bits; | |
594 | } | |
97b7f715 | 595 | EXPORT_SYMBOL(omap_disable_dma_irq); |
1a8bfa1e TL |
596 | |
597 | static inline void enable_lnk(int lch) | |
598 | { | |
0499bdeb TL |
599 | u32 l; |
600 | ||
f31cc962 | 601 | l = p->dma_read(CLNK_CTRL, lch); |
0499bdeb | 602 | |
1a8bfa1e | 603 | if (cpu_class_is_omap1()) |
0499bdeb | 604 | l &= ~(1 << 14); |
5e1c5ff4 | 605 | |
1a8bfa1e | 606 | /* Set the ENABLE_LNK bits */ |
5e1c5ff4 | 607 | if (dma_chan[lch].next_lch != -1) |
0499bdeb | 608 | l = dma_chan[lch].next_lch | (1 << 15); |
f8151e5c AG |
609 | |
610 | #ifndef CONFIG_ARCH_OMAP1 | |
97b7f715 TL |
611 | if (cpu_class_is_omap2()) |
612 | if (dma_chan[lch].next_linked_ch != -1) | |
613 | l = dma_chan[lch].next_linked_ch | (1 << 15); | |
f8151e5c | 614 | #endif |
0499bdeb | 615 | |
f31cc962 | 616 | p->dma_write(l, CLNK_CTRL, lch); |
5e1c5ff4 TL |
617 | } |
618 | ||
619 | static inline void disable_lnk(int lch) | |
620 | { | |
0499bdeb TL |
621 | u32 l; |
622 | ||
f31cc962 | 623 | l = p->dma_read(CLNK_CTRL, lch); |
0499bdeb | 624 | |
5e1c5ff4 | 625 | /* Disable interrupts */ |
1a8bfa1e | 626 | if (cpu_class_is_omap1()) { |
f31cc962 | 627 | p->dma_write(0, CICR, lch); |
1a8bfa1e | 628 | /* Set the STOP_LNK bit */ |
0499bdeb | 629 | l |= 1 << 14; |
1a8bfa1e | 630 | } |
5e1c5ff4 | 631 | |
f8151e5c | 632 | if (cpu_class_is_omap2()) { |
1a8bfa1e TL |
633 | omap_disable_channel_irq(lch); |
634 | /* Clear the ENABLE_LNK bit */ | |
0499bdeb | 635 | l &= ~(1 << 15); |
1a8bfa1e | 636 | } |
5e1c5ff4 | 637 | |
f31cc962 | 638 | p->dma_write(l, CLNK_CTRL, lch); |
5e1c5ff4 TL |
639 | dma_chan[lch].flags &= ~OMAP_DMA_ACTIVE; |
640 | } | |
641 | ||
1a8bfa1e | 642 | static inline void omap2_enable_irq_lch(int lch) |
5e1c5ff4 | 643 | { |
1a8bfa1e | 644 | u32 val; |
ee907324 | 645 | unsigned long flags; |
1a8bfa1e | 646 | |
f8151e5c | 647 | if (!cpu_class_is_omap2()) |
1a8bfa1e TL |
648 | return; |
649 | ||
ee907324 | 650 | spin_lock_irqsave(&dma_chan_lock, flags); |
f31cc962 | 651 | val = p->dma_read(IRQENABLE_L0, lch); |
1a8bfa1e | 652 | val |= 1 << lch; |
f31cc962 | 653 | p->dma_write(val, IRQENABLE_L0, lch); |
ee907324 | 654 | spin_unlock_irqrestore(&dma_chan_lock, flags); |
1a8bfa1e TL |
655 | } |
656 | ||
ada8d4a5 MW |
657 | static inline void omap2_disable_irq_lch(int lch) |
658 | { | |
659 | u32 val; | |
660 | unsigned long flags; | |
661 | ||
662 | if (!cpu_class_is_omap2()) | |
663 | return; | |
664 | ||
665 | spin_lock_irqsave(&dma_chan_lock, flags); | |
f31cc962 | 666 | val = p->dma_read(IRQENABLE_L0, lch); |
ada8d4a5 | 667 | val &= ~(1 << lch); |
f31cc962 | 668 | p->dma_write(val, IRQENABLE_L0, lch); |
ada8d4a5 MW |
669 | spin_unlock_irqrestore(&dma_chan_lock, flags); |
670 | } | |
671 | ||
1a8bfa1e | 672 | int omap_request_dma(int dev_id, const char *dev_name, |
97b7f715 | 673 | void (*callback)(int lch, u16 ch_status, void *data), |
1a8bfa1e TL |
674 | void *data, int *dma_ch_out) |
675 | { | |
676 | int ch, free_ch = -1; | |
677 | unsigned long flags; | |
678 | struct omap_dma_lch *chan; | |
679 | ||
680 | spin_lock_irqsave(&dma_chan_lock, flags); | |
681 | for (ch = 0; ch < dma_chan_count; ch++) { | |
682 | if (free_ch == -1 && dma_chan[ch].dev_id == -1) { | |
683 | free_ch = ch; | |
684 | if (dev_id == 0) | |
685 | break; | |
686 | } | |
687 | } | |
688 | if (free_ch == -1) { | |
689 | spin_unlock_irqrestore(&dma_chan_lock, flags); | |
690 | return -EBUSY; | |
691 | } | |
692 | chan = dma_chan + free_ch; | |
693 | chan->dev_id = dev_id; | |
694 | ||
f31cc962 MK |
695 | if (p->clear_lch_regs) |
696 | p->clear_lch_regs(free_ch); | |
5e1c5ff4 | 697 | |
f8151e5c | 698 | if (cpu_class_is_omap2()) |
1a8bfa1e TL |
699 | omap_clear_dma(free_ch); |
700 | ||
701 | spin_unlock_irqrestore(&dma_chan_lock, flags); | |
702 | ||
703 | chan->dev_name = dev_name; | |
704 | chan->callback = callback; | |
705 | chan->data = data; | |
a92fda19 | 706 | chan->flags = 0; |
97b7f715 | 707 | |
f8151e5c | 708 | #ifndef CONFIG_ARCH_OMAP1 |
97b7f715 TL |
709 | if (cpu_class_is_omap2()) { |
710 | chan->chain_id = -1; | |
711 | chan->next_linked_ch = -1; | |
712 | } | |
f8151e5c | 713 | #endif |
97b7f715 | 714 | |
7ff879db | 715 | chan->enabled_irqs = OMAP_DMA_DROP_IRQ | OMAP_DMA_BLOCK_IRQ; |
1a8bfa1e | 716 | |
7ff879db TL |
717 | if (cpu_class_is_omap1()) |
718 | chan->enabled_irqs |= OMAP1_DMA_TOUT_IRQ; | |
f8151e5c | 719 | else if (cpu_class_is_omap2()) |
7ff879db TL |
720 | chan->enabled_irqs |= OMAP2_DMA_MISALIGNED_ERR_IRQ | |
721 | OMAP2_DMA_TRANS_ERR_IRQ; | |
1a8bfa1e TL |
722 | |
723 | if (cpu_is_omap16xx()) { | |
724 | /* If the sync device is set, configure it dynamically. */ | |
725 | if (dev_id != 0) { | |
726 | set_gdma_dev(free_ch + 1, dev_id); | |
727 | dev_id = free_ch + 1; | |
728 | } | |
97b7f715 TL |
729 | /* |
730 | * Disable the 1510 compatibility mode and set the sync device | |
731 | * id. | |
732 | */ | |
f31cc962 | 733 | p->dma_write(dev_id | (1 << 10), CCR, free_ch); |
557096fe | 734 | } else if (cpu_is_omap7xx() || cpu_is_omap15xx()) { |
f31cc962 | 735 | p->dma_write(dev_id, CCR, free_ch); |
1a8bfa1e TL |
736 | } |
737 | ||
f8151e5c | 738 | if (cpu_class_is_omap2()) { |
1a8bfa1e | 739 | omap2_enable_irq_lch(free_ch); |
1a8bfa1e TL |
740 | omap_enable_channel_irq(free_ch); |
741 | /* Clear the CSR register and IRQ status register */ | |
f31cc962 MK |
742 | p->dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR, free_ch); |
743 | p->dma_write(1 << free_ch, IRQSTATUS_L0, 0); | |
1a8bfa1e TL |
744 | } |
745 | ||
746 | *dma_ch_out = free_ch; | |
747 | ||
748 | return 0; | |
749 | } | |
97b7f715 | 750 | EXPORT_SYMBOL(omap_request_dma); |
1a8bfa1e TL |
751 | |
752 | void omap_free_dma(int lch) | |
753 | { | |
754 | unsigned long flags; | |
755 | ||
1a8bfa1e | 756 | if (dma_chan[lch].dev_id == -1) { |
97b7f715 | 757 | pr_err("omap_dma: trying to free unallocated DMA channel %d\n", |
1a8bfa1e | 758 | lch); |
1a8bfa1e TL |
759 | return; |
760 | } | |
97b7f715 | 761 | |
1a8bfa1e TL |
762 | if (cpu_class_is_omap1()) { |
763 | /* Disable all DMA interrupts for the channel. */ | |
f31cc962 | 764 | p->dma_write(0, CICR, lch); |
1a8bfa1e | 765 | /* Make sure the DMA transfer is stopped. */ |
f31cc962 | 766 | p->dma_write(0, CCR, lch); |
1a8bfa1e TL |
767 | } |
768 | ||
f8151e5c | 769 | if (cpu_class_is_omap2()) { |
ada8d4a5 | 770 | omap2_disable_irq_lch(lch); |
1a8bfa1e TL |
771 | |
772 | /* Clear the CSR register and IRQ status register */ | |
f31cc962 MK |
773 | p->dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR, lch); |
774 | p->dma_write(1 << lch, IRQSTATUS_L0, lch); | |
1a8bfa1e TL |
775 | |
776 | /* Disable all DMA interrupts for the channel. */ | |
f31cc962 | 777 | p->dma_write(0, CICR, lch); |
1a8bfa1e TL |
778 | |
779 | /* Make sure the DMA transfer is stopped. */ | |
f31cc962 | 780 | p->dma_write(0, CCR, lch); |
1a8bfa1e TL |
781 | omap_clear_dma(lch); |
782 | } | |
da1b94e6 SS |
783 | |
784 | spin_lock_irqsave(&dma_chan_lock, flags); | |
785 | dma_chan[lch].dev_id = -1; | |
786 | dma_chan[lch].next_lch = -1; | |
787 | dma_chan[lch].callback = NULL; | |
788 | spin_unlock_irqrestore(&dma_chan_lock, flags); | |
1a8bfa1e | 789 | } |
97b7f715 | 790 | EXPORT_SYMBOL(omap_free_dma); |
1a8bfa1e | 791 | |
f8151e5c AG |
792 | /** |
793 | * @brief omap_dma_set_global_params : Set global priority settings for dma | |
794 | * | |
795 | * @param arb_rate | |
796 | * @param max_fifo_depth | |
70cf644c AA |
797 | * @param tparams - Number of threads to reserve : DMA_THREAD_RESERVE_NORM |
798 | * DMA_THREAD_RESERVE_ONET | |
799 | * DMA_THREAD_RESERVE_TWOT | |
800 | * DMA_THREAD_RESERVE_THREET | |
f8151e5c AG |
801 | */ |
802 | void | |
803 | omap_dma_set_global_params(int arb_rate, int max_fifo_depth, int tparams) | |
804 | { | |
805 | u32 reg; | |
806 | ||
807 | if (!cpu_class_is_omap2()) { | |
8e86f427 | 808 | printk(KERN_ERR "FIXME: no %s on 15xx/16xx\n", __func__); |
f8151e5c AG |
809 | return; |
810 | } | |
811 | ||
70cf644c AA |
812 | if (max_fifo_depth == 0) |
813 | max_fifo_depth = 1; | |
f8151e5c AG |
814 | if (arb_rate == 0) |
815 | arb_rate = 1; | |
816 | ||
70cf644c AA |
817 | reg = 0xff & max_fifo_depth; |
818 | reg |= (0x3 & tparams) << 12; | |
819 | reg |= (arb_rate & 0xff) << 16; | |
f8151e5c | 820 | |
f31cc962 | 821 | p->dma_write(reg, GCR, 0); |
f8151e5c AG |
822 | } |
823 | EXPORT_SYMBOL(omap_dma_set_global_params); | |
824 | ||
825 | /** | |
826 | * @brief omap_dma_set_prio_lch : Set channel wise priority settings | |
827 | * | |
828 | * @param lch | |
829 | * @param read_prio - Read priority | |
830 | * @param write_prio - Write priority | |
831 | * Both of the above can be set with one of the following values : | |
832 | * DMA_CH_PRIO_HIGH/DMA_CH_PRIO_LOW | |
833 | */ | |
834 | int | |
835 | omap_dma_set_prio_lch(int lch, unsigned char read_prio, | |
836 | unsigned char write_prio) | |
837 | { | |
0499bdeb | 838 | u32 l; |
f8151e5c | 839 | |
4d96372e | 840 | if (unlikely((lch < 0 || lch >= dma_lch_count))) { |
f8151e5c AG |
841 | printk(KERN_ERR "Invalid channel id\n"); |
842 | return -EINVAL; | |
843 | } | |
f31cc962 | 844 | l = p->dma_read(CCR, lch); |
0499bdeb | 845 | l &= ~((1 << 6) | (1 << 26)); |
44169075 | 846 | if (cpu_is_omap2430() || cpu_is_omap34xx() || cpu_is_omap44xx()) |
0499bdeb | 847 | l |= ((read_prio & 0x1) << 6) | ((write_prio & 0x1) << 26); |
f8151e5c | 848 | else |
0499bdeb TL |
849 | l |= ((read_prio & 0x1) << 6); |
850 | ||
f31cc962 | 851 | p->dma_write(l, CCR, lch); |
f8151e5c | 852 | |
f8151e5c AG |
853 | return 0; |
854 | } | |
855 | EXPORT_SYMBOL(omap_dma_set_prio_lch); | |
856 | ||
1a8bfa1e TL |
857 | /* |
858 | * Clears any DMA state so the DMA engine is ready to restart with new buffers | |
859 | * through omap_start_dma(). Any buffers in flight are discarded. | |
860 | */ | |
861 | void omap_clear_dma(int lch) | |
862 | { | |
863 | unsigned long flags; | |
864 | ||
865 | local_irq_save(flags); | |
f31cc962 | 866 | p->clear_dma(lch); |
1a8bfa1e TL |
867 | local_irq_restore(flags); |
868 | } | |
97b7f715 | 869 | EXPORT_SYMBOL(omap_clear_dma); |
1a8bfa1e TL |
870 | |
871 | void omap_start_dma(int lch) | |
872 | { | |
0499bdeb TL |
873 | u32 l; |
874 | ||
519e6166 | 875 | /* |
876 | * The CPC/CDAC register needs to be initialized to zero | |
877 | * before starting dma transfer. | |
878 | */ | |
879 | if (cpu_is_omap15xx()) | |
f31cc962 | 880 | p->dma_write(0, CPC, lch); |
519e6166 | 881 | else |
f31cc962 | 882 | p->dma_write(0, CDAC, lch); |
519e6166 | 883 | |
5e1c5ff4 TL |
884 | if (!omap_dma_in_1510_mode() && dma_chan[lch].next_lch != -1) { |
885 | int next_lch, cur_lch; | |
f31cc962 | 886 | char dma_chan_link_map[dma_lch_count]; |
5e1c5ff4 TL |
887 | |
888 | dma_chan_link_map[lch] = 1; | |
889 | /* Set the link register of the first channel */ | |
890 | enable_lnk(lch); | |
891 | ||
892 | memset(dma_chan_link_map, 0, sizeof(dma_chan_link_map)); | |
893 | cur_lch = dma_chan[lch].next_lch; | |
894 | do { | |
895 | next_lch = dma_chan[cur_lch].next_lch; | |
896 | ||
1a8bfa1e | 897 | /* The loop case: we've been here already */ |
5e1c5ff4 TL |
898 | if (dma_chan_link_map[cur_lch]) |
899 | break; | |
900 | /* Mark the current channel */ | |
901 | dma_chan_link_map[cur_lch] = 1; | |
902 | ||
903 | enable_lnk(cur_lch); | |
1a8bfa1e | 904 | omap_enable_channel_irq(cur_lch); |
5e1c5ff4 TL |
905 | |
906 | cur_lch = next_lch; | |
907 | } while (next_lch != -1); | |
d3c9be2f | 908 | } else if (IS_DMA_ERRATA(DMA_ERRATA_PARALLEL_CHANNELS)) |
f31cc962 | 909 | p->dma_write(lch, CLNK_CTRL, lch); |
5e1c5ff4 | 910 | |
1a8bfa1e TL |
911 | omap_enable_channel_irq(lch); |
912 | ||
f31cc962 | 913 | l = p->dma_read(CCR, lch); |
0499bdeb | 914 | |
d3c9be2f MK |
915 | if (IS_DMA_ERRATA(DMA_ERRATA_IFRAME_BUFFERING)) |
916 | l |= OMAP_DMA_CCR_BUFFERING_DISABLE; | |
0499bdeb | 917 | l |= OMAP_DMA_CCR_EN; |
d3c9be2f | 918 | |
f31cc962 | 919 | p->dma_write(l, CCR, lch); |
5e1c5ff4 | 920 | |
5e1c5ff4 TL |
921 | dma_chan[lch].flags |= OMAP_DMA_ACTIVE; |
922 | } | |
97b7f715 | 923 | EXPORT_SYMBOL(omap_start_dma); |
5e1c5ff4 TL |
924 | |
925 | void omap_stop_dma(int lch) | |
926 | { | |
0499bdeb TL |
927 | u32 l; |
928 | ||
9da65a99 SS |
929 | /* Disable all interrupts on the channel */ |
930 | if (cpu_class_is_omap1()) | |
f31cc962 | 931 | p->dma_write(0, CICR, lch); |
9da65a99 | 932 | |
f31cc962 | 933 | l = p->dma_read(CCR, lch); |
d3c9be2f MK |
934 | if (IS_DMA_ERRATA(DMA_ERRATA_i541) && |
935 | (l & OMAP_DMA_CCR_SEL_SRC_DST_SYNC)) { | |
0e4905c0 PU |
936 | int i = 0; |
937 | u32 sys_cf; | |
938 | ||
939 | /* Configure No-Standby */ | |
f31cc962 | 940 | l = p->dma_read(OCP_SYSCONFIG, lch); |
0e4905c0 PU |
941 | sys_cf = l; |
942 | l &= ~DMA_SYSCONFIG_MIDLEMODE_MASK; | |
943 | l |= DMA_SYSCONFIG_MIDLEMODE(DMA_IDLEMODE_NO_IDLE); | |
f31cc962 | 944 | p->dma_write(l , OCP_SYSCONFIG, 0); |
0e4905c0 | 945 | |
f31cc962 | 946 | l = p->dma_read(CCR, lch); |
0e4905c0 | 947 | l &= ~OMAP_DMA_CCR_EN; |
f31cc962 | 948 | p->dma_write(l, CCR, lch); |
0e4905c0 PU |
949 | |
950 | /* Wait for sDMA FIFO drain */ | |
f31cc962 | 951 | l = p->dma_read(CCR, lch); |
0e4905c0 PU |
952 | while (i < 100 && (l & (OMAP_DMA_CCR_RD_ACTIVE | |
953 | OMAP_DMA_CCR_WR_ACTIVE))) { | |
954 | udelay(5); | |
955 | i++; | |
f31cc962 | 956 | l = p->dma_read(CCR, lch); |
0e4905c0 PU |
957 | } |
958 | if (i >= 100) | |
959 | printk(KERN_ERR "DMA drain did not complete on " | |
960 | "lch %d\n", lch); | |
961 | /* Restore OCP_SYSCONFIG */ | |
f31cc962 | 962 | p->dma_write(sys_cf, OCP_SYSCONFIG, lch); |
0e4905c0 PU |
963 | } else { |
964 | l &= ~OMAP_DMA_CCR_EN; | |
f31cc962 | 965 | p->dma_write(l, CCR, lch); |
0e4905c0 | 966 | } |
9da65a99 | 967 | |
5e1c5ff4 TL |
968 | if (!omap_dma_in_1510_mode() && dma_chan[lch].next_lch != -1) { |
969 | int next_lch, cur_lch = lch; | |
f31cc962 | 970 | char dma_chan_link_map[dma_lch_count]; |
5e1c5ff4 TL |
971 | |
972 | memset(dma_chan_link_map, 0, sizeof(dma_chan_link_map)); | |
973 | do { | |
974 | /* The loop case: we've been here already */ | |
975 | if (dma_chan_link_map[cur_lch]) | |
976 | break; | |
977 | /* Mark the current channel */ | |
978 | dma_chan_link_map[cur_lch] = 1; | |
979 | ||
980 | disable_lnk(cur_lch); | |
981 | ||
982 | next_lch = dma_chan[cur_lch].next_lch; | |
983 | cur_lch = next_lch; | |
984 | } while (next_lch != -1); | |
5e1c5ff4 | 985 | } |
1a8bfa1e | 986 | |
5e1c5ff4 TL |
987 | dma_chan[lch].flags &= ~OMAP_DMA_ACTIVE; |
988 | } | |
97b7f715 | 989 | EXPORT_SYMBOL(omap_stop_dma); |
5e1c5ff4 | 990 | |
709eb3e5 TL |
991 | /* |
992 | * Allows changing the DMA callback function or data. This may be needed if | |
993 | * the driver shares a single DMA channel for multiple dma triggers. | |
994 | */ | |
995 | int omap_set_dma_callback(int lch, | |
97b7f715 | 996 | void (*callback)(int lch, u16 ch_status, void *data), |
709eb3e5 TL |
997 | void *data) |
998 | { | |
999 | unsigned long flags; | |
1000 | ||
1001 | if (lch < 0) | |
1002 | return -ENODEV; | |
1003 | ||
1004 | spin_lock_irqsave(&dma_chan_lock, flags); | |
1005 | if (dma_chan[lch].dev_id == -1) { | |
1006 | printk(KERN_ERR "DMA callback for not set for free channel\n"); | |
1007 | spin_unlock_irqrestore(&dma_chan_lock, flags); | |
1008 | return -EINVAL; | |
1009 | } | |
1010 | dma_chan[lch].callback = callback; | |
1011 | dma_chan[lch].data = data; | |
1012 | spin_unlock_irqrestore(&dma_chan_lock, flags); | |
1013 | ||
1014 | return 0; | |
1015 | } | |
97b7f715 | 1016 | EXPORT_SYMBOL(omap_set_dma_callback); |
709eb3e5 | 1017 | |
1a8bfa1e TL |
1018 | /* |
1019 | * Returns current physical source address for the given DMA channel. | |
1020 | * If the channel is running the caller must disable interrupts prior calling | |
1021 | * this function and process the returned value before re-enabling interrupt to | |
1022 | * prevent races with the interrupt handler. Note that in continuous mode there | |
25985edc | 1023 | * is a chance for CSSA_L register overflow between the two reads resulting |
1a8bfa1e TL |
1024 | * in incorrect return value. |
1025 | */ | |
1026 | dma_addr_t omap_get_dma_src_pos(int lch) | |
5e1c5ff4 | 1027 | { |
0695de32 | 1028 | dma_addr_t offset = 0; |
5e1c5ff4 | 1029 | |
0499bdeb | 1030 | if (cpu_is_omap15xx()) |
f31cc962 | 1031 | offset = p->dma_read(CPC, lch); |
0499bdeb | 1032 | else |
f31cc962 | 1033 | offset = p->dma_read(CSAC, lch); |
5e1c5ff4 | 1034 | |
d3c9be2f | 1035 | if (IS_DMA_ERRATA(DMA_ERRATA_3_3) && offset == 0) |
f31cc962 | 1036 | offset = p->dma_read(CSAC, lch); |
0499bdeb | 1037 | |
7ba96680 PU |
1038 | if (!cpu_is_omap15xx()) { |
1039 | /* | |
1040 | * CDAC == 0 indicates that the DMA transfer on the channel has | |
1041 | * not been started (no data has been transferred so far). | |
1042 | * Return the programmed source start address in this case. | |
1043 | */ | |
1044 | if (likely(p->dma_read(CDAC, lch))) | |
1045 | offset = p->dma_read(CSAC, lch); | |
1046 | else | |
1047 | offset = p->dma_read(CSSA, lch); | |
1048 | } | |
1049 | ||
0499bdeb | 1050 | if (cpu_class_is_omap1()) |
f31cc962 | 1051 | offset |= (p->dma_read(CSSA, lch) & 0xFFFF0000); |
5e1c5ff4 | 1052 | |
1a8bfa1e | 1053 | return offset; |
5e1c5ff4 | 1054 | } |
97b7f715 | 1055 | EXPORT_SYMBOL(omap_get_dma_src_pos); |
5e1c5ff4 | 1056 | |
1a8bfa1e TL |
1057 | /* |
1058 | * Returns current physical destination address for the given DMA channel. | |
1059 | * If the channel is running the caller must disable interrupts prior calling | |
1060 | * this function and process the returned value before re-enabling interrupt to | |
1061 | * prevent races with the interrupt handler. Note that in continuous mode there | |
25985edc | 1062 | * is a chance for CDSA_L register overflow between the two reads resulting |
1a8bfa1e TL |
1063 | * in incorrect return value. |
1064 | */ | |
1065 | dma_addr_t omap_get_dma_dst_pos(int lch) | |
5e1c5ff4 | 1066 | { |
0695de32 | 1067 | dma_addr_t offset = 0; |
5e1c5ff4 | 1068 | |
0499bdeb | 1069 | if (cpu_is_omap15xx()) |
f31cc962 | 1070 | offset = p->dma_read(CPC, lch); |
0499bdeb | 1071 | else |
f31cc962 | 1072 | offset = p->dma_read(CDAC, lch); |
5e1c5ff4 | 1073 | |
0499bdeb TL |
1074 | /* |
1075 | * omap 3.2/3.3 erratum: sometimes 0 is returned if CSAC/CDAC is | |
1076 | * read before the DMA controller finished disabling the channel. | |
1077 | */ | |
06e8077b | 1078 | if (!cpu_is_omap15xx() && offset == 0) { |
f31cc962 | 1079 | offset = p->dma_read(CDAC, lch); |
06e8077b PU |
1080 | /* |
1081 | * CDAC == 0 indicates that the DMA transfer on the channel has | |
1082 | * not been started (no data has been transferred so far). | |
1083 | * Return the programmed destination start address in this case. | |
1084 | */ | |
1085 | if (unlikely(!offset)) | |
1086 | offset = p->dma_read(CDSA, lch); | |
1087 | } | |
0499bdeb TL |
1088 | |
1089 | if (cpu_class_is_omap1()) | |
f31cc962 | 1090 | offset |= (p->dma_read(CDSA, lch) & 0xFFFF0000); |
5e1c5ff4 | 1091 | |
1a8bfa1e | 1092 | return offset; |
5e1c5ff4 | 1093 | } |
97b7f715 | 1094 | EXPORT_SYMBOL(omap_get_dma_dst_pos); |
0499bdeb TL |
1095 | |
1096 | int omap_get_dma_active_status(int lch) | |
1097 | { | |
f31cc962 | 1098 | return (p->dma_read(CCR, lch) & OMAP_DMA_CCR_EN) != 0; |
5e1c5ff4 | 1099 | } |
0499bdeb | 1100 | EXPORT_SYMBOL(omap_get_dma_active_status); |
5e1c5ff4 | 1101 | |
1a8bfa1e | 1102 | int omap_dma_running(void) |
5e1c5ff4 | 1103 | { |
1a8bfa1e | 1104 | int lch; |
5e1c5ff4 | 1105 | |
f8e9e984 JK |
1106 | if (cpu_class_is_omap1()) |
1107 | if (omap_lcd_dma_running()) | |
1a8bfa1e | 1108 | return 1; |
5e1c5ff4 | 1109 | |
1a8bfa1e | 1110 | for (lch = 0; lch < dma_chan_count; lch++) |
f31cc962 | 1111 | if (p->dma_read(CCR, lch) & OMAP_DMA_CCR_EN) |
1a8bfa1e | 1112 | return 1; |
5e1c5ff4 | 1113 | |
1a8bfa1e | 1114 | return 0; |
5e1c5ff4 TL |
1115 | } |
1116 | ||
1117 | /* | |
1118 | * lch_queue DMA will start right after lch_head one is finished. | |
1119 | * For this DMA link to start, you still need to start (see omap_start_dma) | |
1120 | * the first one. That will fire up the entire queue. | |
1121 | */ | |
97b7f715 | 1122 | void omap_dma_link_lch(int lch_head, int lch_queue) |
5e1c5ff4 TL |
1123 | { |
1124 | if (omap_dma_in_1510_mode()) { | |
9f0f4ae5 | 1125 | if (lch_head == lch_queue) { |
f31cc962 | 1126 | p->dma_write(p->dma_read(CCR, lch_head) | (3 << 8), |
a4c537c7 | 1127 | CCR, lch_head); |
9f0f4ae5 JK |
1128 | return; |
1129 | } | |
5e1c5ff4 TL |
1130 | printk(KERN_ERR "DMA linking is not supported in 1510 mode\n"); |
1131 | BUG(); | |
1132 | return; | |
1133 | } | |
1134 | ||
1135 | if ((dma_chan[lch_head].dev_id == -1) || | |
1136 | (dma_chan[lch_queue].dev_id == -1)) { | |
1a8bfa1e TL |
1137 | printk(KERN_ERR "omap_dma: trying to link " |
1138 | "non requested channels\n"); | |
5e1c5ff4 TL |
1139 | dump_stack(); |
1140 | } | |
1141 | ||
1142 | dma_chan[lch_head].next_lch = lch_queue; | |
1143 | } | |
97b7f715 | 1144 | EXPORT_SYMBOL(omap_dma_link_lch); |
5e1c5ff4 TL |
1145 | |
1146 | /* | |
1147 | * Once the DMA queue is stopped, we can destroy it. | |
1148 | */ | |
97b7f715 | 1149 | void omap_dma_unlink_lch(int lch_head, int lch_queue) |
5e1c5ff4 TL |
1150 | { |
1151 | if (omap_dma_in_1510_mode()) { | |
9f0f4ae5 | 1152 | if (lch_head == lch_queue) { |
f31cc962 | 1153 | p->dma_write(p->dma_read(CCR, lch_head) & ~(3 << 8), |
a4c537c7 | 1154 | CCR, lch_head); |
9f0f4ae5 JK |
1155 | return; |
1156 | } | |
5e1c5ff4 TL |
1157 | printk(KERN_ERR "DMA linking is not supported in 1510 mode\n"); |
1158 | BUG(); | |
1159 | return; | |
1160 | } | |
1161 | ||
1162 | if (dma_chan[lch_head].next_lch != lch_queue || | |
1163 | dma_chan[lch_head].next_lch == -1) { | |
1a8bfa1e TL |
1164 | printk(KERN_ERR "omap_dma: trying to unlink " |
1165 | "non linked channels\n"); | |
5e1c5ff4 TL |
1166 | dump_stack(); |
1167 | } | |
1168 | ||
5e1c5ff4 | 1169 | if ((dma_chan[lch_head].flags & OMAP_DMA_ACTIVE) || |
247421fd | 1170 | (dma_chan[lch_queue].flags & OMAP_DMA_ACTIVE)) { |
1a8bfa1e TL |
1171 | printk(KERN_ERR "omap_dma: You need to stop the DMA channels " |
1172 | "before unlinking\n"); | |
5e1c5ff4 TL |
1173 | dump_stack(); |
1174 | } | |
1175 | ||
1176 | dma_chan[lch_head].next_lch = -1; | |
1177 | } | |
97b7f715 TL |
1178 | EXPORT_SYMBOL(omap_dma_unlink_lch); |
1179 | ||
f8151e5c AG |
1180 | #ifndef CONFIG_ARCH_OMAP1 |
1181 | /* Create chain of DMA channesls */ | |
1182 | static void create_dma_lch_chain(int lch_head, int lch_queue) | |
1183 | { | |
0499bdeb | 1184 | u32 l; |
f8151e5c AG |
1185 | |
1186 | /* Check if this is the first link in chain */ | |
1187 | if (dma_chan[lch_head].next_linked_ch == -1) { | |
1188 | dma_chan[lch_head].next_linked_ch = lch_queue; | |
1189 | dma_chan[lch_head].prev_linked_ch = lch_queue; | |
1190 | dma_chan[lch_queue].next_linked_ch = lch_head; | |
1191 | dma_chan[lch_queue].prev_linked_ch = lch_head; | |
1192 | } | |
1193 | ||
1194 | /* a link exists, link the new channel in circular chain */ | |
1195 | else { | |
1196 | dma_chan[lch_queue].next_linked_ch = | |
1197 | dma_chan[lch_head].next_linked_ch; | |
1198 | dma_chan[lch_queue].prev_linked_ch = lch_head; | |
1199 | dma_chan[lch_head].next_linked_ch = lch_queue; | |
1200 | dma_chan[dma_chan[lch_queue].next_linked_ch].prev_linked_ch = | |
1201 | lch_queue; | |
1202 | } | |
1203 | ||
f31cc962 | 1204 | l = p->dma_read(CLNK_CTRL, lch_head); |
0499bdeb TL |
1205 | l &= ~(0x1f); |
1206 | l |= lch_queue; | |
f31cc962 | 1207 | p->dma_write(l, CLNK_CTRL, lch_head); |
f8151e5c | 1208 | |
f31cc962 | 1209 | l = p->dma_read(CLNK_CTRL, lch_queue); |
0499bdeb TL |
1210 | l &= ~(0x1f); |
1211 | l |= (dma_chan[lch_queue].next_linked_ch); | |
f31cc962 | 1212 | p->dma_write(l, CLNK_CTRL, lch_queue); |
f8151e5c AG |
1213 | } |
1214 | ||
1215 | /** | |
1216 | * @brief omap_request_dma_chain : Request a chain of DMA channels | |
1217 | * | |
1218 | * @param dev_id - Device id using the dma channel | |
1219 | * @param dev_name - Device name | |
1220 | * @param callback - Call back function | |
1221 | * @chain_id - | |
1222 | * @no_of_chans - Number of channels requested | |
1223 | * @chain_mode - Dynamic or static chaining : OMAP_DMA_STATIC_CHAIN | |
1224 | * OMAP_DMA_DYNAMIC_CHAIN | |
1225 | * @params - Channel parameters | |
1226 | * | |
af901ca1 | 1227 | * @return - Success : 0 |
f8151e5c AG |
1228 | * Failure: -EINVAL/-ENOMEM |
1229 | */ | |
1230 | int omap_request_dma_chain(int dev_id, const char *dev_name, | |
279b918d | 1231 | void (*callback) (int lch, u16 ch_status, |
f8151e5c AG |
1232 | void *data), |
1233 | int *chain_id, int no_of_chans, int chain_mode, | |
1234 | struct omap_dma_channel_params params) | |
1235 | { | |
1236 | int *channels; | |
1237 | int i, err; | |
1238 | ||
1239 | /* Is the chain mode valid ? */ | |
1240 | if (chain_mode != OMAP_DMA_STATIC_CHAIN | |
1241 | && chain_mode != OMAP_DMA_DYNAMIC_CHAIN) { | |
1242 | printk(KERN_ERR "Invalid chain mode requested\n"); | |
1243 | return -EINVAL; | |
1244 | } | |
1245 | ||
1246 | if (unlikely((no_of_chans < 1 | |
4d96372e | 1247 | || no_of_chans > dma_lch_count))) { |
f8151e5c AG |
1248 | printk(KERN_ERR "Invalid Number of channels requested\n"); |
1249 | return -EINVAL; | |
1250 | } | |
1251 | ||
ea221a6a | 1252 | /* |
1253 | * Allocate a queue to maintain the status of the channels | |
1254 | * in the chain | |
1255 | */ | |
f8151e5c AG |
1256 | channels = kmalloc(sizeof(*channels) * no_of_chans, GFP_KERNEL); |
1257 | if (channels == NULL) { | |
1258 | printk(KERN_ERR "omap_dma: No memory for channel queue\n"); | |
1259 | return -ENOMEM; | |
1260 | } | |
1261 | ||
1262 | /* request and reserve DMA channels for the chain */ | |
1263 | for (i = 0; i < no_of_chans; i++) { | |
1264 | err = omap_request_dma(dev_id, dev_name, | |
c0fc18c5 | 1265 | callback, NULL, &channels[i]); |
f8151e5c AG |
1266 | if (err < 0) { |
1267 | int j; | |
1268 | for (j = 0; j < i; j++) | |
1269 | omap_free_dma(channels[j]); | |
1270 | kfree(channels); | |
1271 | printk(KERN_ERR "omap_dma: Request failed %d\n", err); | |
1272 | return err; | |
1273 | } | |
f8151e5c AG |
1274 | dma_chan[channels[i]].prev_linked_ch = -1; |
1275 | dma_chan[channels[i]].state = DMA_CH_NOTSTARTED; | |
1276 | ||
1277 | /* | |
1278 | * Allowing client drivers to set common parameters now, | |
1279 | * so that later only relevant (src_start, dest_start | |
1280 | * and element count) can be set | |
1281 | */ | |
1282 | omap_set_dma_params(channels[i], ¶ms); | |
1283 | } | |
1284 | ||
1285 | *chain_id = channels[0]; | |
1286 | dma_linked_lch[*chain_id].linked_dmach_q = channels; | |
1287 | dma_linked_lch[*chain_id].chain_mode = chain_mode; | |
1288 | dma_linked_lch[*chain_id].chain_state = DMA_CHAIN_NOTSTARTED; | |
1289 | dma_linked_lch[*chain_id].no_of_lchs_linked = no_of_chans; | |
1290 | ||
1291 | for (i = 0; i < no_of_chans; i++) | |
1292 | dma_chan[channels[i]].chain_id = *chain_id; | |
1293 | ||
1294 | /* Reset the Queue pointers */ | |
1295 | OMAP_DMA_CHAIN_QINIT(*chain_id); | |
1296 | ||
1297 | /* Set up the chain */ | |
1298 | if (no_of_chans == 1) | |
1299 | create_dma_lch_chain(channels[0], channels[0]); | |
1300 | else { | |
1301 | for (i = 0; i < (no_of_chans - 1); i++) | |
1302 | create_dma_lch_chain(channels[i], channels[i + 1]); | |
1303 | } | |
97b7f715 | 1304 | |
f8151e5c AG |
1305 | return 0; |
1306 | } | |
1307 | EXPORT_SYMBOL(omap_request_dma_chain); | |
1308 | ||
1309 | /** | |
1310 | * @brief omap_modify_dma_chain_param : Modify the chain's params - Modify the | |
1311 | * params after setting it. Dont do this while dma is running!! | |
1312 | * | |
1313 | * @param chain_id - Chained logical channel id. | |
1314 | * @param params | |
1315 | * | |
1316 | * @return - Success : 0 | |
1317 | * Failure : -EINVAL | |
1318 | */ | |
1319 | int omap_modify_dma_chain_params(int chain_id, | |
1320 | struct omap_dma_channel_params params) | |
1321 | { | |
1322 | int *channels; | |
1323 | u32 i; | |
1324 | ||
1325 | /* Check for input params */ | |
1326 | if (unlikely((chain_id < 0 | |
4d96372e | 1327 | || chain_id >= dma_lch_count))) { |
f8151e5c AG |
1328 | printk(KERN_ERR "Invalid chain id\n"); |
1329 | return -EINVAL; | |
1330 | } | |
1331 | ||
1332 | /* Check if the chain exists */ | |
1333 | if (dma_linked_lch[chain_id].linked_dmach_q == NULL) { | |
1334 | printk(KERN_ERR "Chain doesn't exists\n"); | |
1335 | return -EINVAL; | |
1336 | } | |
1337 | channels = dma_linked_lch[chain_id].linked_dmach_q; | |
1338 | ||
1339 | for (i = 0; i < dma_linked_lch[chain_id].no_of_lchs_linked; i++) { | |
1340 | /* | |
1341 | * Allowing client drivers to set common parameters now, | |
1342 | * so that later only relevant (src_start, dest_start | |
1343 | * and element count) can be set | |
1344 | */ | |
1345 | omap_set_dma_params(channels[i], ¶ms); | |
1346 | } | |
97b7f715 | 1347 | |
f8151e5c AG |
1348 | return 0; |
1349 | } | |
1350 | EXPORT_SYMBOL(omap_modify_dma_chain_params); | |
1351 | ||
1352 | /** | |
1353 | * @brief omap_free_dma_chain - Free all the logical channels in a chain. | |
1354 | * | |
1355 | * @param chain_id | |
1356 | * | |
1357 | * @return - Success : 0 | |
1358 | * Failure : -EINVAL | |
1359 | */ | |
1360 | int omap_free_dma_chain(int chain_id) | |
1361 | { | |
1362 | int *channels; | |
1363 | u32 i; | |
1364 | ||
1365 | /* Check for input params */ | |
4d96372e | 1366 | if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) { |
f8151e5c AG |
1367 | printk(KERN_ERR "Invalid chain id\n"); |
1368 | return -EINVAL; | |
1369 | } | |
1370 | ||
1371 | /* Check if the chain exists */ | |
1372 | if (dma_linked_lch[chain_id].linked_dmach_q == NULL) { | |
1373 | printk(KERN_ERR "Chain doesn't exists\n"); | |
1374 | return -EINVAL; | |
1375 | } | |
1376 | ||
1377 | channels = dma_linked_lch[chain_id].linked_dmach_q; | |
1378 | for (i = 0; i < dma_linked_lch[chain_id].no_of_lchs_linked; i++) { | |
1379 | dma_chan[channels[i]].next_linked_ch = -1; | |
1380 | dma_chan[channels[i]].prev_linked_ch = -1; | |
1381 | dma_chan[channels[i]].chain_id = -1; | |
1382 | dma_chan[channels[i]].state = DMA_CH_NOTSTARTED; | |
1383 | omap_free_dma(channels[i]); | |
1384 | } | |
1385 | ||
1386 | kfree(channels); | |
1387 | ||
1388 | dma_linked_lch[chain_id].linked_dmach_q = NULL; | |
1389 | dma_linked_lch[chain_id].chain_mode = -1; | |
1390 | dma_linked_lch[chain_id].chain_state = -1; | |
97b7f715 | 1391 | |
f8151e5c AG |
1392 | return (0); |
1393 | } | |
1394 | EXPORT_SYMBOL(omap_free_dma_chain); | |
1395 | ||
1396 | /** | |
1397 | * @brief omap_dma_chain_status - Check if the chain is in | |
1398 | * active / inactive state. | |
1399 | * @param chain_id | |
1400 | * | |
1401 | * @return - Success : OMAP_DMA_CHAIN_ACTIVE/OMAP_DMA_CHAIN_INACTIVE | |
1402 | * Failure : -EINVAL | |
1403 | */ | |
1404 | int omap_dma_chain_status(int chain_id) | |
1405 | { | |
1406 | /* Check for input params */ | |
4d96372e | 1407 | if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) { |
f8151e5c AG |
1408 | printk(KERN_ERR "Invalid chain id\n"); |
1409 | return -EINVAL; | |
1410 | } | |
1411 | ||
1412 | /* Check if the chain exists */ | |
1413 | if (dma_linked_lch[chain_id].linked_dmach_q == NULL) { | |
1414 | printk(KERN_ERR "Chain doesn't exists\n"); | |
1415 | return -EINVAL; | |
1416 | } | |
1417 | pr_debug("CHAINID=%d, qcnt=%d\n", chain_id, | |
1418 | dma_linked_lch[chain_id].q_count); | |
1419 | ||
1420 | if (OMAP_DMA_CHAIN_QEMPTY(chain_id)) | |
1421 | return OMAP_DMA_CHAIN_INACTIVE; | |
97b7f715 | 1422 | |
f8151e5c AG |
1423 | return OMAP_DMA_CHAIN_ACTIVE; |
1424 | } | |
1425 | EXPORT_SYMBOL(omap_dma_chain_status); | |
1426 | ||
1427 | /** | |
1428 | * @brief omap_dma_chain_a_transfer - Get a free channel from a chain, | |
1429 | * set the params and start the transfer. | |
1430 | * | |
1431 | * @param chain_id | |
1432 | * @param src_start - buffer start address | |
1433 | * @param dest_start - Dest address | |
1434 | * @param elem_count | |
1435 | * @param frame_count | |
1436 | * @param callbk_data - channel callback parameter data. | |
1437 | * | |
f4b6a7ef | 1438 | * @return - Success : 0 |
f8151e5c AG |
1439 | * Failure: -EINVAL/-EBUSY |
1440 | */ | |
1441 | int omap_dma_chain_a_transfer(int chain_id, int src_start, int dest_start, | |
1442 | int elem_count, int frame_count, void *callbk_data) | |
1443 | { | |
1444 | int *channels; | |
0499bdeb | 1445 | u32 l, lch; |
f8151e5c AG |
1446 | int start_dma = 0; |
1447 | ||
97b7f715 TL |
1448 | /* |
1449 | * if buffer size is less than 1 then there is | |
1450 | * no use of starting the chain | |
1451 | */ | |
f8151e5c AG |
1452 | if (elem_count < 1) { |
1453 | printk(KERN_ERR "Invalid buffer size\n"); | |
1454 | return -EINVAL; | |
1455 | } | |
1456 | ||
1457 | /* Check for input params */ | |
1458 | if (unlikely((chain_id < 0 | |
4d96372e | 1459 | || chain_id >= dma_lch_count))) { |
f8151e5c AG |
1460 | printk(KERN_ERR "Invalid chain id\n"); |
1461 | return -EINVAL; | |
1462 | } | |
1463 | ||
1464 | /* Check if the chain exists */ | |
1465 | if (dma_linked_lch[chain_id].linked_dmach_q == NULL) { | |
1466 | printk(KERN_ERR "Chain doesn't exist\n"); | |
1467 | return -EINVAL; | |
1468 | } | |
1469 | ||
1470 | /* Check if all the channels in chain are in use */ | |
1471 | if (OMAP_DMA_CHAIN_QFULL(chain_id)) | |
1472 | return -EBUSY; | |
1473 | ||
1474 | /* Frame count may be negative in case of indexed transfers */ | |
1475 | channels = dma_linked_lch[chain_id].linked_dmach_q; | |
1476 | ||
1477 | /* Get a free channel */ | |
1478 | lch = channels[dma_linked_lch[chain_id].q_tail]; | |
1479 | ||
1480 | /* Store the callback data */ | |
1481 | dma_chan[lch].data = callbk_data; | |
1482 | ||
1483 | /* Increment the q_tail */ | |
1484 | OMAP_DMA_CHAIN_INCQTAIL(chain_id); | |
1485 | ||
1486 | /* Set the params to the free channel */ | |
1487 | if (src_start != 0) | |
f31cc962 | 1488 | p->dma_write(src_start, CSSA, lch); |
f8151e5c | 1489 | if (dest_start != 0) |
f31cc962 | 1490 | p->dma_write(dest_start, CDSA, lch); |
f8151e5c AG |
1491 | |
1492 | /* Write the buffer size */ | |
f31cc962 MK |
1493 | p->dma_write(elem_count, CEN, lch); |
1494 | p->dma_write(frame_count, CFN, lch); | |
f8151e5c | 1495 | |
97b7f715 TL |
1496 | /* |
1497 | * If the chain is dynamically linked, | |
1498 | * then we may have to start the chain if its not active | |
1499 | */ | |
f8151e5c AG |
1500 | if (dma_linked_lch[chain_id].chain_mode == OMAP_DMA_DYNAMIC_CHAIN) { |
1501 | ||
97b7f715 TL |
1502 | /* |
1503 | * In Dynamic chain, if the chain is not started, | |
1504 | * queue the channel | |
1505 | */ | |
f8151e5c AG |
1506 | if (dma_linked_lch[chain_id].chain_state == |
1507 | DMA_CHAIN_NOTSTARTED) { | |
1508 | /* Enable the link in previous channel */ | |
1509 | if (dma_chan[dma_chan[lch].prev_linked_ch].state == | |
1510 | DMA_CH_QUEUED) | |
1511 | enable_lnk(dma_chan[lch].prev_linked_ch); | |
1512 | dma_chan[lch].state = DMA_CH_QUEUED; | |
1513 | } | |
1514 | ||
97b7f715 TL |
1515 | /* |
1516 | * Chain is already started, make sure its active, | |
1517 | * if not then start the chain | |
1518 | */ | |
f8151e5c AG |
1519 | else { |
1520 | start_dma = 1; | |
1521 | ||
1522 | if (dma_chan[dma_chan[lch].prev_linked_ch].state == | |
1523 | DMA_CH_STARTED) { | |
1524 | enable_lnk(dma_chan[lch].prev_linked_ch); | |
1525 | dma_chan[lch].state = DMA_CH_QUEUED; | |
1526 | start_dma = 0; | |
f31cc962 | 1527 | if (0 == ((1 << 7) & p->dma_read( |
a4c537c7 | 1528 | CCR, dma_chan[lch].prev_linked_ch))) { |
f8151e5c AG |
1529 | disable_lnk(dma_chan[lch]. |
1530 | prev_linked_ch); | |
1531 | pr_debug("\n prev ch is stopped\n"); | |
1532 | start_dma = 1; | |
1533 | } | |
1534 | } | |
1535 | ||
1536 | else if (dma_chan[dma_chan[lch].prev_linked_ch].state | |
1537 | == DMA_CH_QUEUED) { | |
1538 | enable_lnk(dma_chan[lch].prev_linked_ch); | |
1539 | dma_chan[lch].state = DMA_CH_QUEUED; | |
1540 | start_dma = 0; | |
1541 | } | |
1542 | omap_enable_channel_irq(lch); | |
1543 | ||
f31cc962 | 1544 | l = p->dma_read(CCR, lch); |
f8151e5c | 1545 | |
0499bdeb TL |
1546 | if ((0 == (l & (1 << 24)))) |
1547 | l &= ~(1 << 25); | |
f8151e5c | 1548 | else |
0499bdeb | 1549 | l |= (1 << 25); |
f8151e5c | 1550 | if (start_dma == 1) { |
0499bdeb TL |
1551 | if (0 == (l & (1 << 7))) { |
1552 | l |= (1 << 7); | |
f8151e5c AG |
1553 | dma_chan[lch].state = DMA_CH_STARTED; |
1554 | pr_debug("starting %d\n", lch); | |
f31cc962 | 1555 | p->dma_write(l, CCR, lch); |
f8151e5c AG |
1556 | } else |
1557 | start_dma = 0; | |
1558 | } else { | |
0499bdeb | 1559 | if (0 == (l & (1 << 7))) |
f31cc962 | 1560 | p->dma_write(l, CCR, lch); |
f8151e5c AG |
1561 | } |
1562 | dma_chan[lch].flags |= OMAP_DMA_ACTIVE; | |
1563 | } | |
1564 | } | |
97b7f715 | 1565 | |
f4b6a7ef | 1566 | return 0; |
f8151e5c AG |
1567 | } |
1568 | EXPORT_SYMBOL(omap_dma_chain_a_transfer); | |
1569 | ||
1570 | /** | |
1571 | * @brief omap_start_dma_chain_transfers - Start the chain | |
1572 | * | |
1573 | * @param chain_id | |
1574 | * | |
1575 | * @return - Success : 0 | |
1576 | * Failure : -EINVAL/-EBUSY | |
1577 | */ | |
1578 | int omap_start_dma_chain_transfers(int chain_id) | |
1579 | { | |
1580 | int *channels; | |
0499bdeb | 1581 | u32 l, i; |
f8151e5c | 1582 | |
4d96372e | 1583 | if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) { |
f8151e5c AG |
1584 | printk(KERN_ERR "Invalid chain id\n"); |
1585 | return -EINVAL; | |
1586 | } | |
1587 | ||
1588 | channels = dma_linked_lch[chain_id].linked_dmach_q; | |
1589 | ||
1590 | if (dma_linked_lch[channels[0]].chain_state == DMA_CHAIN_STARTED) { | |
1591 | printk(KERN_ERR "Chain is already started\n"); | |
1592 | return -EBUSY; | |
1593 | } | |
1594 | ||
1595 | if (dma_linked_lch[chain_id].chain_mode == OMAP_DMA_STATIC_CHAIN) { | |
1596 | for (i = 0; i < dma_linked_lch[chain_id].no_of_lchs_linked; | |
1597 | i++) { | |
1598 | enable_lnk(channels[i]); | |
1599 | omap_enable_channel_irq(channels[i]); | |
1600 | } | |
1601 | } else { | |
1602 | omap_enable_channel_irq(channels[0]); | |
1603 | } | |
1604 | ||
f31cc962 | 1605 | l = p->dma_read(CCR, channels[0]); |
0499bdeb | 1606 | l |= (1 << 7); |
f8151e5c AG |
1607 | dma_linked_lch[chain_id].chain_state = DMA_CHAIN_STARTED; |
1608 | dma_chan[channels[0]].state = DMA_CH_STARTED; | |
1609 | ||
0499bdeb TL |
1610 | if ((0 == (l & (1 << 24)))) |
1611 | l &= ~(1 << 25); | |
f8151e5c | 1612 | else |
0499bdeb | 1613 | l |= (1 << 25); |
f31cc962 | 1614 | p->dma_write(l, CCR, channels[0]); |
f8151e5c AG |
1615 | |
1616 | dma_chan[channels[0]].flags |= OMAP_DMA_ACTIVE; | |
97b7f715 | 1617 | |
f8151e5c AG |
1618 | return 0; |
1619 | } | |
1620 | EXPORT_SYMBOL(omap_start_dma_chain_transfers); | |
1621 | ||
1622 | /** | |
1623 | * @brief omap_stop_dma_chain_transfers - Stop the dma transfer of a chain. | |
1624 | * | |
1625 | * @param chain_id | |
1626 | * | |
1627 | * @return - Success : 0 | |
1628 | * Failure : EINVAL | |
1629 | */ | |
1630 | int omap_stop_dma_chain_transfers(int chain_id) | |
1631 | { | |
1632 | int *channels; | |
0499bdeb | 1633 | u32 l, i; |
d3c9be2f | 1634 | u32 sys_cf = 0; |
f8151e5c AG |
1635 | |
1636 | /* Check for input params */ | |
4d96372e | 1637 | if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) { |
f8151e5c AG |
1638 | printk(KERN_ERR "Invalid chain id\n"); |
1639 | return -EINVAL; | |
1640 | } | |
1641 | ||
1642 | /* Check if the chain exists */ | |
1643 | if (dma_linked_lch[chain_id].linked_dmach_q == NULL) { | |
1644 | printk(KERN_ERR "Chain doesn't exists\n"); | |
1645 | return -EINVAL; | |
1646 | } | |
1647 | channels = dma_linked_lch[chain_id].linked_dmach_q; | |
1648 | ||
d3c9be2f | 1649 | if (IS_DMA_ERRATA(DMA_ERRATA_i88)) { |
f31cc962 | 1650 | sys_cf = p->dma_read(OCP_SYSCONFIG, 0); |
d3c9be2f MK |
1651 | l = sys_cf; |
1652 | /* Middle mode reg set no Standby */ | |
1653 | l &= ~((1 << 12)|(1 << 13)); | |
f31cc962 | 1654 | p->dma_write(l, OCP_SYSCONFIG, 0); |
d3c9be2f | 1655 | } |
f8151e5c AG |
1656 | |
1657 | for (i = 0; i < dma_linked_lch[chain_id].no_of_lchs_linked; i++) { | |
1658 | ||
1659 | /* Stop the Channel transmission */ | |
f31cc962 | 1660 | l = p->dma_read(CCR, channels[i]); |
0499bdeb | 1661 | l &= ~(1 << 7); |
f31cc962 | 1662 | p->dma_write(l, CCR, channels[i]); |
f8151e5c AG |
1663 | |
1664 | /* Disable the link in all the channels */ | |
1665 | disable_lnk(channels[i]); | |
1666 | dma_chan[channels[i]].state = DMA_CH_NOTSTARTED; | |
1667 | ||
1668 | } | |
1669 | dma_linked_lch[chain_id].chain_state = DMA_CHAIN_NOTSTARTED; | |
1670 | ||
1671 | /* Reset the Queue pointers */ | |
1672 | OMAP_DMA_CHAIN_QINIT(chain_id); | |
1673 | ||
d3c9be2f | 1674 | if (IS_DMA_ERRATA(DMA_ERRATA_i88)) |
f31cc962 | 1675 | p->dma_write(sys_cf, OCP_SYSCONFIG, 0); |
97b7f715 | 1676 | |
f8151e5c AG |
1677 | return 0; |
1678 | } | |
1679 | EXPORT_SYMBOL(omap_stop_dma_chain_transfers); | |
1680 | ||
1681 | /* Get the index of the ongoing DMA in chain */ | |
1682 | /** | |
1683 | * @brief omap_get_dma_chain_index - Get the element and frame index | |
1684 | * of the ongoing DMA in chain | |
1685 | * | |
1686 | * @param chain_id | |
1687 | * @param ei - Element index | |
1688 | * @param fi - Frame index | |
1689 | * | |
1690 | * @return - Success : 0 | |
1691 | * Failure : -EINVAL | |
1692 | */ | |
1693 | int omap_get_dma_chain_index(int chain_id, int *ei, int *fi) | |
1694 | { | |
1695 | int lch; | |
1696 | int *channels; | |
1697 | ||
1698 | /* Check for input params */ | |
4d96372e | 1699 | if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) { |
f8151e5c AG |
1700 | printk(KERN_ERR "Invalid chain id\n"); |
1701 | return -EINVAL; | |
1702 | } | |
1703 | ||
1704 | /* Check if the chain exists */ | |
1705 | if (dma_linked_lch[chain_id].linked_dmach_q == NULL) { | |
1706 | printk(KERN_ERR "Chain doesn't exists\n"); | |
1707 | return -EINVAL; | |
1708 | } | |
1709 | if ((!ei) || (!fi)) | |
1710 | return -EINVAL; | |
1711 | ||
1712 | channels = dma_linked_lch[chain_id].linked_dmach_q; | |
1713 | ||
1714 | /* Get the current channel */ | |
1715 | lch = channels[dma_linked_lch[chain_id].q_head]; | |
1716 | ||
f31cc962 MK |
1717 | *ei = p->dma_read(CCEN, lch); |
1718 | *fi = p->dma_read(CCFN, lch); | |
f8151e5c AG |
1719 | |
1720 | return 0; | |
1721 | } | |
1722 | EXPORT_SYMBOL(omap_get_dma_chain_index); | |
1723 | ||
1724 | /** | |
1725 | * @brief omap_get_dma_chain_dst_pos - Get the destination position of the | |
1726 | * ongoing DMA in chain | |
1727 | * | |
1728 | * @param chain_id | |
1729 | * | |
1730 | * @return - Success : Destination position | |
1731 | * Failure : -EINVAL | |
1732 | */ | |
1733 | int omap_get_dma_chain_dst_pos(int chain_id) | |
1734 | { | |
1735 | int lch; | |
1736 | int *channels; | |
1737 | ||
1738 | /* Check for input params */ | |
4d96372e | 1739 | if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) { |
f8151e5c AG |
1740 | printk(KERN_ERR "Invalid chain id\n"); |
1741 | return -EINVAL; | |
1742 | } | |
1743 | ||
1744 | /* Check if the chain exists */ | |
1745 | if (dma_linked_lch[chain_id].linked_dmach_q == NULL) { | |
1746 | printk(KERN_ERR "Chain doesn't exists\n"); | |
1747 | return -EINVAL; | |
1748 | } | |
1749 | ||
1750 | channels = dma_linked_lch[chain_id].linked_dmach_q; | |
1751 | ||
1752 | /* Get the current channel */ | |
1753 | lch = channels[dma_linked_lch[chain_id].q_head]; | |
1754 | ||
f31cc962 | 1755 | return p->dma_read(CDAC, lch); |
f8151e5c AG |
1756 | } |
1757 | EXPORT_SYMBOL(omap_get_dma_chain_dst_pos); | |
1758 | ||
1759 | /** | |
1760 | * @brief omap_get_dma_chain_src_pos - Get the source position | |
1761 | * of the ongoing DMA in chain | |
1762 | * @param chain_id | |
1763 | * | |
1764 | * @return - Success : Destination position | |
1765 | * Failure : -EINVAL | |
1766 | */ | |
1767 | int omap_get_dma_chain_src_pos(int chain_id) | |
1768 | { | |
1769 | int lch; | |
1770 | int *channels; | |
1771 | ||
1772 | /* Check for input params */ | |
4d96372e | 1773 | if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) { |
f8151e5c AG |
1774 | printk(KERN_ERR "Invalid chain id\n"); |
1775 | return -EINVAL; | |
1776 | } | |
1777 | ||
1778 | /* Check if the chain exists */ | |
1779 | if (dma_linked_lch[chain_id].linked_dmach_q == NULL) { | |
1780 | printk(KERN_ERR "Chain doesn't exists\n"); | |
1781 | return -EINVAL; | |
1782 | } | |
1783 | ||
1784 | channels = dma_linked_lch[chain_id].linked_dmach_q; | |
1785 | ||
1786 | /* Get the current channel */ | |
1787 | lch = channels[dma_linked_lch[chain_id].q_head]; | |
1788 | ||
f31cc962 | 1789 | return p->dma_read(CSAC, lch); |
f8151e5c AG |
1790 | } |
1791 | EXPORT_SYMBOL(omap_get_dma_chain_src_pos); | |
97b7f715 | 1792 | #endif /* ifndef CONFIG_ARCH_OMAP1 */ |
f8151e5c | 1793 | |
1a8bfa1e TL |
1794 | /*----------------------------------------------------------------------------*/ |
1795 | ||
1796 | #ifdef CONFIG_ARCH_OMAP1 | |
1797 | ||
1798 | static int omap1_dma_handle_ch(int ch) | |
1799 | { | |
0499bdeb | 1800 | u32 csr; |
1a8bfa1e TL |
1801 | |
1802 | if (enable_1510_mode && ch >= 6) { | |
1803 | csr = dma_chan[ch].saved_csr; | |
1804 | dma_chan[ch].saved_csr = 0; | |
1805 | } else | |
f31cc962 | 1806 | csr = p->dma_read(CSR, ch); |
1a8bfa1e TL |
1807 | if (enable_1510_mode && ch <= 2 && (csr >> 7) != 0) { |
1808 | dma_chan[ch + 6].saved_csr = csr >> 7; | |
1809 | csr &= 0x7f; | |
1810 | } | |
1811 | if ((csr & 0x3f) == 0) | |
1812 | return 0; | |
1813 | if (unlikely(dma_chan[ch].dev_id == -1)) { | |
1814 | printk(KERN_WARNING "Spurious interrupt from DMA channel " | |
1815 | "%d (CSR %04x)\n", ch, csr); | |
1816 | return 0; | |
1817 | } | |
7ff879db | 1818 | if (unlikely(csr & OMAP1_DMA_TOUT_IRQ)) |
1a8bfa1e TL |
1819 | printk(KERN_WARNING "DMA timeout with device %d\n", |
1820 | dma_chan[ch].dev_id); | |
1821 | if (unlikely(csr & OMAP_DMA_DROP_IRQ)) | |
1822 | printk(KERN_WARNING "DMA synchronization event drop occurred " | |
1823 | "with device %d\n", dma_chan[ch].dev_id); | |
1824 | if (likely(csr & OMAP_DMA_BLOCK_IRQ)) | |
1825 | dma_chan[ch].flags &= ~OMAP_DMA_ACTIVE; | |
1826 | if (likely(dma_chan[ch].callback != NULL)) | |
1827 | dma_chan[ch].callback(ch, csr, dma_chan[ch].data); | |
97b7f715 | 1828 | |
1a8bfa1e TL |
1829 | return 1; |
1830 | } | |
1831 | ||
0cd61b68 | 1832 | static irqreturn_t omap1_dma_irq_handler(int irq, void *dev_id) |
1a8bfa1e TL |
1833 | { |
1834 | int ch = ((int) dev_id) - 1; | |
1835 | int handled = 0; | |
1836 | ||
1837 | for (;;) { | |
1838 | int handled_now = 0; | |
1839 | ||
1840 | handled_now += omap1_dma_handle_ch(ch); | |
1841 | if (enable_1510_mode && dma_chan[ch + 6].saved_csr) | |
1842 | handled_now += omap1_dma_handle_ch(ch + 6); | |
1843 | if (!handled_now) | |
1844 | break; | |
1845 | handled += handled_now; | |
1846 | } | |
1847 | ||
1848 | return handled ? IRQ_HANDLED : IRQ_NONE; | |
1849 | } | |
1850 | ||
1851 | #else | |
1852 | #define omap1_dma_irq_handler NULL | |
1853 | #endif | |
1854 | ||
140455fa | 1855 | #ifdef CONFIG_ARCH_OMAP2PLUS |
1a8bfa1e TL |
1856 | |
1857 | static int omap2_dma_handle_ch(int ch) | |
1858 | { | |
f31cc962 | 1859 | u32 status = p->dma_read(CSR, ch); |
1a8bfa1e | 1860 | |
3151369d JY |
1861 | if (!status) { |
1862 | if (printk_ratelimit()) | |
97b7f715 TL |
1863 | printk(KERN_WARNING "Spurious DMA IRQ for lch %d\n", |
1864 | ch); | |
f31cc962 | 1865 | p->dma_write(1 << ch, IRQSTATUS_L0, ch); |
1a8bfa1e | 1866 | return 0; |
3151369d JY |
1867 | } |
1868 | if (unlikely(dma_chan[ch].dev_id == -1)) { | |
1869 | if (printk_ratelimit()) | |
1870 | printk(KERN_WARNING "IRQ %04x for non-allocated DMA" | |
1871 | "channel %d\n", status, ch); | |
1a8bfa1e | 1872 | return 0; |
3151369d | 1873 | } |
1a8bfa1e TL |
1874 | if (unlikely(status & OMAP_DMA_DROP_IRQ)) |
1875 | printk(KERN_INFO | |
1876 | "DMA synchronization event drop occurred with device " | |
1877 | "%d\n", dma_chan[ch].dev_id); | |
a50f18c7 | 1878 | if (unlikely(status & OMAP2_DMA_TRANS_ERR_IRQ)) { |
1a8bfa1e TL |
1879 | printk(KERN_INFO "DMA transaction error with device %d\n", |
1880 | dma_chan[ch].dev_id); | |
d3c9be2f | 1881 | if (IS_DMA_ERRATA(DMA_ERRATA_i378)) { |
a50f18c7 SS |
1882 | u32 ccr; |
1883 | ||
f31cc962 | 1884 | ccr = p->dma_read(CCR, ch); |
a50f18c7 | 1885 | ccr &= ~OMAP_DMA_CCR_EN; |
f31cc962 | 1886 | p->dma_write(ccr, CCR, ch); |
a50f18c7 SS |
1887 | dma_chan[ch].flags &= ~OMAP_DMA_ACTIVE; |
1888 | } | |
1889 | } | |
7ff879db TL |
1890 | if (unlikely(status & OMAP2_DMA_SECURE_ERR_IRQ)) |
1891 | printk(KERN_INFO "DMA secure error with device %d\n", | |
1892 | dma_chan[ch].dev_id); | |
1893 | if (unlikely(status & OMAP2_DMA_MISALIGNED_ERR_IRQ)) | |
1894 | printk(KERN_INFO "DMA misaligned error with device %d\n", | |
1895 | dma_chan[ch].dev_id); | |
1a8bfa1e | 1896 | |
4fb699b4 | 1897 | p->dma_write(status, CSR, ch); |
f31cc962 | 1898 | p->dma_write(1 << ch, IRQSTATUS_L0, ch); |
e860e6da | 1899 | /* read back the register to flush the write */ |
f31cc962 | 1900 | p->dma_read(IRQSTATUS_L0, ch); |
1a8bfa1e | 1901 | |
f8151e5c AG |
1902 | /* If the ch is not chained then chain_id will be -1 */ |
1903 | if (dma_chan[ch].chain_id != -1) { | |
1904 | int chain_id = dma_chan[ch].chain_id; | |
1905 | dma_chan[ch].state = DMA_CH_NOTSTARTED; | |
f31cc962 | 1906 | if (p->dma_read(CLNK_CTRL, ch) & (1 << 15)) |
f8151e5c AG |
1907 | dma_chan[dma_chan[ch].next_linked_ch].state = |
1908 | DMA_CH_STARTED; | |
1909 | if (dma_linked_lch[chain_id].chain_mode == | |
1910 | OMAP_DMA_DYNAMIC_CHAIN) | |
1911 | disable_lnk(ch); | |
1912 | ||
1913 | if (!OMAP_DMA_CHAIN_QEMPTY(chain_id)) | |
1914 | OMAP_DMA_CHAIN_INCQHEAD(chain_id); | |
1915 | ||
f31cc962 | 1916 | status = p->dma_read(CSR, ch); |
4fb699b4 | 1917 | p->dma_write(status, CSR, ch); |
f8151e5c AG |
1918 | } |
1919 | ||
538528de JN |
1920 | if (likely(dma_chan[ch].callback != NULL)) |
1921 | dma_chan[ch].callback(ch, status, dma_chan[ch].data); | |
f8151e5c | 1922 | |
1a8bfa1e TL |
1923 | return 0; |
1924 | } | |
1925 | ||
1926 | /* STATUS register count is from 1-32 while our is 0-31 */ | |
0cd61b68 | 1927 | static irqreturn_t omap2_dma_irq_handler(int irq, void *dev_id) |
1a8bfa1e | 1928 | { |
52176e70 | 1929 | u32 val, enable_reg; |
1a8bfa1e TL |
1930 | int i; |
1931 | ||
f31cc962 | 1932 | val = p->dma_read(IRQSTATUS_L0, 0); |
3151369d JY |
1933 | if (val == 0) { |
1934 | if (printk_ratelimit()) | |
1935 | printk(KERN_WARNING "Spurious DMA IRQ\n"); | |
1936 | return IRQ_HANDLED; | |
1937 | } | |
f31cc962 | 1938 | enable_reg = p->dma_read(IRQENABLE_L0, 0); |
52176e70 | 1939 | val &= enable_reg; /* Dispatch only relevant interrupts */ |
4d96372e | 1940 | for (i = 0; i < dma_lch_count && val != 0; i++) { |
3151369d JY |
1941 | if (val & 1) |
1942 | omap2_dma_handle_ch(i); | |
1943 | val >>= 1; | |
1a8bfa1e TL |
1944 | } |
1945 | ||
1946 | return IRQ_HANDLED; | |
1947 | } | |
1948 | ||
1949 | static struct irqaction omap24xx_dma_irq = { | |
1950 | .name = "DMA", | |
1951 | .handler = omap2_dma_irq_handler, | |
52e405ea | 1952 | .flags = IRQF_DISABLED |
1a8bfa1e TL |
1953 | }; |
1954 | ||
1955 | #else | |
1956 | static struct irqaction omap24xx_dma_irq; | |
1957 | #endif | |
1958 | ||
1959 | /*----------------------------------------------------------------------------*/ | |
5e1c5ff4 | 1960 | |
f2d11858 TK |
1961 | void omap_dma_global_context_save(void) |
1962 | { | |
1963 | omap_dma_global_context.dma_irqenable_l0 = | |
f31cc962 | 1964 | p->dma_read(IRQENABLE_L0, 0); |
f2d11858 | 1965 | omap_dma_global_context.dma_ocp_sysconfig = |
f31cc962 MK |
1966 | p->dma_read(OCP_SYSCONFIG, 0); |
1967 | omap_dma_global_context.dma_gcr = p->dma_read(GCR, 0); | |
f2d11858 TK |
1968 | } |
1969 | ||
1970 | void omap_dma_global_context_restore(void) | |
1971 | { | |
bf07c9f2 AK |
1972 | int ch; |
1973 | ||
f31cc962 MK |
1974 | p->dma_write(omap_dma_global_context.dma_gcr, GCR, 0); |
1975 | p->dma_write(omap_dma_global_context.dma_ocp_sysconfig, | |
a4c537c7 | 1976 | OCP_SYSCONFIG, 0); |
f31cc962 | 1977 | p->dma_write(omap_dma_global_context.dma_irqenable_l0, |
a4c537c7 | 1978 | IRQENABLE_L0, 0); |
f2d11858 | 1979 | |
d3c9be2f | 1980 | if (IS_DMA_ERRATA(DMA_ROMCODE_BUG)) |
f31cc962 | 1981 | p->dma_write(0x3 , IRQSTATUS_L0, 0); |
bf07c9f2 AK |
1982 | |
1983 | for (ch = 0; ch < dma_chan_count; ch++) | |
1984 | if (dma_chan[ch].dev_id != -1) | |
1985 | omap_clear_dma(ch); | |
f2d11858 TK |
1986 | } |
1987 | ||
f31cc962 | 1988 | static int __devinit omap_system_dma_probe(struct platform_device *pdev) |
d3c9be2f | 1989 | { |
f31cc962 MK |
1990 | int ch, ret = 0; |
1991 | int dma_irq; | |
1992 | char irq_name[4]; | |
1993 | int irq_rel; | |
1994 | ||
1995 | p = pdev->dev.platform_data; | |
1996 | if (!p) { | |
1997 | dev_err(&pdev->dev, "%s: System DMA initialized without" | |
1998 | "platform data\n", __func__); | |
1999 | return -EINVAL; | |
0499bdeb | 2000 | } |
4d96372e | 2001 | |
f31cc962 MK |
2002 | d = p->dma_attr; |
2003 | errata = p->errata; | |
a4c537c7 | 2004 | |
f31cc962 | 2005 | if ((d->dev_caps & RESERVE_CHANNEL) && omap_dma_reserve_channels |
2263f022 | 2006 | && (omap_dma_reserve_channels <= dma_lch_count)) |
f31cc962 | 2007 | d->lch_count = omap_dma_reserve_channels; |
2263f022 | 2008 | |
f31cc962 MK |
2009 | dma_lch_count = d->lch_count; |
2010 | dma_chan_count = dma_lch_count; | |
2011 | dma_chan = d->chan; | |
2012 | enable_1510_mode = d->dev_caps & ENABLE_1510_MODE; | |
4d96372e TL |
2013 | |
2014 | if (cpu_class_is_omap2()) { | |
2015 | dma_linked_lch = kzalloc(sizeof(struct dma_link_info) * | |
2016 | dma_lch_count, GFP_KERNEL); | |
2017 | if (!dma_linked_lch) { | |
f31cc962 MK |
2018 | ret = -ENOMEM; |
2019 | goto exit_dma_lch_fail; | |
4d96372e TL |
2020 | } |
2021 | } | |
2022 | ||
5e1c5ff4 | 2023 | spin_lock_init(&dma_chan_lock); |
5e1c5ff4 | 2024 | for (ch = 0; ch < dma_chan_count; ch++) { |
1a8bfa1e | 2025 | omap_clear_dma(ch); |
ada8d4a5 MW |
2026 | if (cpu_class_is_omap2()) |
2027 | omap2_disable_irq_lch(ch); | |
2028 | ||
5e1c5ff4 TL |
2029 | dma_chan[ch].dev_id = -1; |
2030 | dma_chan[ch].next_lch = -1; | |
2031 | ||
2032 | if (ch >= 6 && enable_1510_mode) | |
2033 | continue; | |
2034 | ||
1a8bfa1e | 2035 | if (cpu_class_is_omap1()) { |
97b7f715 TL |
2036 | /* |
2037 | * request_irq() doesn't like dev_id (ie. ch) being | |
2038 | * zero, so we have to kludge around this. | |
2039 | */ | |
f31cc962 MK |
2040 | sprintf(&irq_name[0], "%d", ch); |
2041 | dma_irq = platform_get_irq_byname(pdev, irq_name); | |
2042 | ||
2043 | if (dma_irq < 0) { | |
2044 | ret = dma_irq; | |
2045 | goto exit_dma_irq_fail; | |
2046 | } | |
2047 | ||
2048 | /* INT_DMA_LCD is handled in lcd_dma.c */ | |
2049 | if (dma_irq == INT_DMA_LCD) | |
2050 | continue; | |
2051 | ||
2052 | ret = request_irq(dma_irq, | |
1a8bfa1e TL |
2053 | omap1_dma_irq_handler, 0, "DMA", |
2054 | (void *) (ch + 1)); | |
f31cc962 MK |
2055 | if (ret != 0) |
2056 | goto exit_dma_irq_fail; | |
1a8bfa1e TL |
2057 | } |
2058 | } | |
2059 | ||
44169075 | 2060 | if (cpu_is_omap2430() || cpu_is_omap34xx() || cpu_is_omap44xx()) |
f8151e5c AG |
2061 | omap_dma_set_global_params(DMA_DEFAULT_ARB_RATE, |
2062 | DMA_DEFAULT_FIFO_DEPTH, 0); | |
2063 | ||
44169075 | 2064 | if (cpu_class_is_omap2()) { |
f31cc962 MK |
2065 | strcpy(irq_name, "0"); |
2066 | dma_irq = platform_get_irq_byname(pdev, irq_name); | |
2067 | if (dma_irq < 0) { | |
2068 | dev_err(&pdev->dev, "failed: request IRQ %d", dma_irq); | |
2069 | goto exit_dma_lch_fail; | |
2070 | } | |
2071 | ret = setup_irq(dma_irq, &omap24xx_dma_irq); | |
2072 | if (ret) { | |
2073 | dev_err(&pdev->dev, "set_up failed for IRQ %d" | |
2074 | "for DMA (error %d)\n", dma_irq, ret); | |
2075 | goto exit_dma_lch_fail; | |
ba50ea7e | 2076 | } |
aecedb94 KJ |
2077 | } |
2078 | ||
f31cc962 MK |
2079 | /* reserve dma channels 0 and 1 in high security devices */ |
2080 | if (cpu_is_omap34xx() && | |
2081 | (omap_type() != OMAP2_DEVICE_TYPE_GP)) { | |
2082 | printk(KERN_INFO "Reserving DMA channels 0 and 1 for " | |
2083 | "HS ROM code\n"); | |
2084 | dma_chan[0].dev_id = 0; | |
2085 | dma_chan[1].dev_id = 1; | |
2086 | } | |
2087 | p->show_dma_caps(); | |
5e1c5ff4 | 2088 | return 0; |
7e9bf847 | 2089 | |
f31cc962 MK |
2090 | exit_dma_irq_fail: |
2091 | dev_err(&pdev->dev, "unable to request IRQ %d" | |
2092 | "for DMA (error %d)\n", dma_irq, ret); | |
2093 | for (irq_rel = 0; irq_rel < ch; irq_rel++) { | |
2094 | dma_irq = platform_get_irq(pdev, irq_rel); | |
2095 | free_irq(dma_irq, (void *)(irq_rel + 1)); | |
2096 | } | |
2097 | ||
2098 | exit_dma_lch_fail: | |
2099 | kfree(p); | |
2100 | kfree(d); | |
7e9bf847 | 2101 | kfree(dma_chan); |
f31cc962 MK |
2102 | return ret; |
2103 | } | |
7e9bf847 | 2104 | |
f31cc962 MK |
2105 | static int __devexit omap_system_dma_remove(struct platform_device *pdev) |
2106 | { | |
2107 | int dma_irq; | |
7e9bf847 | 2108 | |
f31cc962 MK |
2109 | if (cpu_class_is_omap2()) { |
2110 | char irq_name[4]; | |
2111 | strcpy(irq_name, "0"); | |
2112 | dma_irq = platform_get_irq_byname(pdev, irq_name); | |
2113 | remove_irq(dma_irq, &omap24xx_dma_irq); | |
2114 | } else { | |
2115 | int irq_rel = 0; | |
2116 | for ( ; irq_rel < dma_chan_count; irq_rel++) { | |
2117 | dma_irq = platform_get_irq(pdev, irq_rel); | |
2118 | free_irq(dma_irq, (void *)(irq_rel + 1)); | |
2119 | } | |
2120 | } | |
2121 | kfree(p); | |
2122 | kfree(d); | |
2123 | kfree(dma_chan); | |
2124 | return 0; | |
2125 | } | |
2126 | ||
2127 | static struct platform_driver omap_system_dma_driver = { | |
2128 | .probe = omap_system_dma_probe, | |
3e2e613f | 2129 | .remove = __devexit_p(omap_system_dma_remove), |
f31cc962 MK |
2130 | .driver = { |
2131 | .name = "omap_dma_system" | |
2132 | }, | |
2133 | }; | |
2134 | ||
2135 | static int __init omap_system_dma_init(void) | |
2136 | { | |
2137 | return platform_driver_register(&omap_system_dma_driver); | |
2138 | } | |
2139 | arch_initcall(omap_system_dma_init); | |
2140 | ||
2141 | static void __exit omap_system_dma_exit(void) | |
2142 | { | |
2143 | platform_driver_unregister(&omap_system_dma_driver); | |
5e1c5ff4 TL |
2144 | } |
2145 | ||
f31cc962 MK |
2146 | MODULE_DESCRIPTION("OMAP SYSTEM DMA DRIVER"); |
2147 | MODULE_LICENSE("GPL"); | |
2148 | MODULE_ALIAS("platform:" DRIVER_NAME); | |
2149 | MODULE_AUTHOR("Texas Instruments Inc"); | |
5e1c5ff4 | 2150 | |
2263f022 SS |
2151 | /* |
2152 | * Reserve the omap SDMA channels using cmdline bootarg | |
2153 | * "omap_dma_reserve_ch=". The valid range is 1 to 32 | |
2154 | */ | |
2155 | static int __init omap_dma_cmdline_reserve_ch(char *str) | |
2156 | { | |
2157 | if (get_option(&str, &omap_dma_reserve_channels) != 1) | |
2158 | omap_dma_reserve_channels = 0; | |
2159 | return 1; | |
2160 | } | |
2161 | ||
2162 | __setup("omap_dma_reserve_ch=", omap_dma_cmdline_reserve_ch); | |
2163 | ||
5e1c5ff4 | 2164 |