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[OMAP850] Changes to base IO subsystem, v2
[linux-2.6-block.git] / arch / arm / plat-omap / dma.c
CommitLineData
5e1c5ff4
TL		 1/*
2 * linux/arch/arm/plat-omap/dma.c
3 *
97b7f715 4 * Copyright (C) 2003 - 2008 Nokia Corporation
96de0e25 5 * Author: Juha Yrjölä <juha.yrjola@nokia.com>
5e1c5ff4
TL		 6 * DMA channel linking for 1610 by Samuel Ortiz <samuel.ortiz@nokia.com>
7 * Graphics DMA and LCD DMA graphics tranformations
8 * by Imre Deak <imre.deak@nokia.com>
f8151e5c 9 * OMAP2/3 support Copyright (C) 2004-2007 Texas Instruments, Inc.
1a8bfa1e 10 * Merged to support both OMAP1 and OMAP2 by Tony Lindgren <tony@atomide.com>
5e1c5ff4
TL		 11 * Some functions based on earlier dma-omap.c Copyright (C) 2001 RidgeRun, Inc.
12 *
13 * Support functions for the OMAP internal DMA channels.
14 *
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License version 2 as
17 * published by the Free Software Foundation.
18 *
19 */
20
21#include <linux/module.h>
22#include <linux/init.h>
23#include <linux/sched.h>
24#include <linux/spinlock.h>
25#include <linux/errno.h>
26#include <linux/interrupt.h>
418ca1f0 27#include <linux/irq.h>
97b7f715 28#include <linux/io.h>
5e1c5ff4
TL		 29
30#include <asm/system.h>
a09e64fb 31#include <mach/hardware.h>
dcea83ad 32#include <mach/dma.h>
5e1c5ff4 33
a09e64fb 34#include <mach/tc.h>
5e1c5ff4 35
f8151e5c
AG		 36#undef DEBUG
37
38#ifndef CONFIG_ARCH_OMAP1
39enum { DMA_CH_ALLOC_DONE, DMA_CH_PARAMS_SET_DONE, DMA_CH_STARTED,
40 DMA_CH_QUEUED, DMA_CH_NOTSTARTED, DMA_CH_PAUSED, DMA_CH_LINK_ENABLED
41};
42
43enum { DMA_CHAIN_STARTED, DMA_CHAIN_NOTSTARTED };
1a8bfa1e 44#endif
5e1c5ff4 45
97b7f715
TL		 46#define OMAP_DMA_ACTIVE 0x01
47#define OMAP_DMA_CCR_EN (1 << 7)
7ff879db 48#define OMAP2_DMA_CSR_CLEAR_MASK 0xffe
5e1c5ff4 49
97b7f715 50#define OMAP_FUNC_MUX_ARM_BASE (0xfffe1000 + 0xec)
5e1c5ff4 51
97b7f715 52static int enable_1510_mode;
5e1c5ff4
TL		 53
54struct omap_dma_lch {
55 int next_lch;
56 int dev_id;
57 u16 saved_csr;
58 u16 enabled_irqs;
59 const char *dev_name;
97b7f715 60 void (*callback)(int lch, u16 ch_status, void *data);
5e1c5ff4 61 void *data;
f8151e5c
AG		 62
63#ifndef CONFIG_ARCH_OMAP1
64 /* required for Dynamic chaining */
65 int prev_linked_ch;
66 int next_linked_ch;
67 int state;
68 int chain_id;
69
70 int status;
71#endif
5e1c5ff4
TL		 72 long flags;
73};
74
f8151e5c
AG		 75struct dma_link_info {
76 int *linked_dmach_q;
77 int no_of_lchs_linked;
78
79 int q_count;
80 int q_tail;
81 int q_head;
82
83 int chain_state;
84 int chain_mode;
85
86};
87
4d96372e
TL		 88static struct dma_link_info *dma_linked_lch;
89
90#ifndef CONFIG_ARCH_OMAP1
f8151e5c
AG		 91
92/* Chain handling macros */
93#define OMAP_DMA_CHAIN_QINIT(chain_id) \
94 do { \
95 dma_linked_lch[chain_id].q_head = \
96 dma_linked_lch[chain_id].q_tail = \
97 dma_linked_lch[chain_id].q_count = 0; \
98 } while (0)
99#define OMAP_DMA_CHAIN_QFULL(chain_id) \
100 (dma_linked_lch[chain_id].no_of_lchs_linked == \
101 dma_linked_lch[chain_id].q_count)
102#define OMAP_DMA_CHAIN_QLAST(chain_id) \
103 do { \
104 ((dma_linked_lch[chain_id].no_of_lchs_linked-1) == \
105 dma_linked_lch[chain_id].q_count) \
106 } while (0)
107#define OMAP_DMA_CHAIN_QEMPTY(chain_id) \
108 (0 == dma_linked_lch[chain_id].q_count)
109#define __OMAP_DMA_CHAIN_INCQ(end) \
110 ((end) = ((end)+1) % dma_linked_lch[chain_id].no_of_lchs_linked)
111#define OMAP_DMA_CHAIN_INCQHEAD(chain_id) \
112 do { \
113 __OMAP_DMA_CHAIN_INCQ(dma_linked_lch[chain_id].q_head); \
114 dma_linked_lch[chain_id].q_count--; \
115 } while (0)
116
117#define OMAP_DMA_CHAIN_INCQTAIL(chain_id) \
118 do { \
119 __OMAP_DMA_CHAIN_INCQ(dma_linked_lch[chain_id].q_tail); \
120 dma_linked_lch[chain_id].q_count++; \
121 } while (0)
122#endif
4d96372e
TL		 123
124static int dma_lch_count;
5e1c5ff4
TL		 125static int dma_chan_count;
126
127static spinlock_t dma_chan_lock;
4d96372e 128static struct omap_dma_lch *dma_chan;
0499bdeb 129static void __iomem *omap_dma_base;
5e1c5ff4 130
4d96372e 131static const u8 omap1_dma_irq[OMAP1_LOGICAL_DMA_CH_COUNT] = {
5e1c5ff4
TL		 132 INT_DMA_CH0_6, INT_DMA_CH1_7, INT_DMA_CH2_8, INT_DMA_CH3,
133 INT_DMA_CH4, INT_DMA_CH5, INT_1610_DMA_CH6, INT_1610_DMA_CH7,
134 INT_1610_DMA_CH8, INT_1610_DMA_CH9, INT_1610_DMA_CH10,
135 INT_1610_DMA_CH11, INT_1610_DMA_CH12, INT_1610_DMA_CH13,
136 INT_1610_DMA_CH14, INT_1610_DMA_CH15, INT_DMA_LCD
137};
138
f8151e5c
AG		 139static inline void disable_lnk(int lch);
140static void omap_disable_channel_irq(int lch);
141static inline void omap_enable_channel_irq(int lch);
142
1a8bfa1e 143#define REVISIT_24XX() printk(KERN_ERR "FIXME: no %s on 24xx\n", \
8e86f427 144 __func__);
1a8bfa1e 145
0499bdeb
TL		 146#define dma_read(reg) \
147({ \
148 u32 __val; \
149 if (cpu_class_is_omap1()) \
150 __val = __raw_readw(omap_dma_base + OMAP1_DMA_##reg); \
151 else \
152 __val = __raw_readl(omap_dma_base + OMAP_DMA4_##reg); \
153 __val; \
154})
155
156#define dma_write(val, reg) \
157({ \
158 if (cpu_class_is_omap1()) \
159 __raw_writew((u16)(val), omap_dma_base + OMAP1_DMA_##reg); \
160 else \
161 __raw_writel((val), omap_dma_base + OMAP_DMA4_##reg); \
162})
163
1a8bfa1e
TL		 164#ifdef CONFIG_ARCH_OMAP15XX
165/* Returns 1 if the DMA module is in OMAP1510-compatible mode, 0 otherwise */
166int omap_dma_in_1510_mode(void)
167{
168 return enable_1510_mode;
169}
170#else
171#define omap_dma_in_1510_mode() 0
172#endif
173
174#ifdef CONFIG_ARCH_OMAP1
5e1c5ff4
TL		 175static inline int get_gdma_dev(int req)
176{
177 u32 reg = OMAP_FUNC_MUX_ARM_BASE + ((req - 1) / 5) * 4;
178 int shift = ((req - 1) % 5) * 6;
179
180 return ((omap_readl(reg) >> shift) & 0x3f) + 1;
181}
182
183static inline void set_gdma_dev(int req, int dev)
184{
185 u32 reg = OMAP_FUNC_MUX_ARM_BASE + ((req - 1) / 5) * 4;
186 int shift = ((req - 1) % 5) * 6;
187 u32 l;
188
189 l = omap_readl(reg);
190 l &= ~(0x3f << shift);
191 l |= (dev - 1) << shift;
192 omap_writel(l, reg);
193}
1a8bfa1e
TL		 194#else
195#define set_gdma_dev(req, dev) do {} while (0)
196#endif
5e1c5ff4 197
0499bdeb 198/* Omap1 only */
5e1c5ff4
TL		 199static void clear_lch_regs(int lch)
200{
201 int i;
0499bdeb 202 void __iomem *lch_base = omap_dma_base + OMAP1_DMA_CH_BASE(lch);
5e1c5ff4
TL		 203
204 for (i = 0; i < 0x2c; i += 2)
0499bdeb 205 __raw_writew(0, lch_base + i);
5e1c5ff4
TL		 206}
207
709eb3e5 208void omap_set_dma_priority(int lch, int dst_port, int priority)
5e1c5ff4
TL		 209{
210 unsigned long reg;
211 u32 l;
212
709eb3e5
TL		 213 if (cpu_class_is_omap1()) {
214 switch (dst_port) {
215 case OMAP_DMA_PORT_OCP_T1: /* FFFECC00 */
216 reg = OMAP_TC_OCPT1_PRIOR;
217 break;
218 case OMAP_DMA_PORT_OCP_T2: /* FFFECCD0 */
219 reg = OMAP_TC_OCPT2_PRIOR;
220 break;
221 case OMAP_DMA_PORT_EMIFF: /* FFFECC08 */
222 reg = OMAP_TC_EMIFF_PRIOR;
223 break;
224 case OMAP_DMA_PORT_EMIFS: /* FFFECC04 */
225 reg = OMAP_TC_EMIFS_PRIOR;
226 break;
227 default:
228 BUG();
229 return;
230 }
231 l = omap_readl(reg);
232 l &= ~(0xf << 8);
233 l |= (priority & 0xf) << 8;
234 omap_writel(l, reg);
235 }
236
f8151e5c 237 if (cpu_class_is_omap2()) {
0499bdeb
TL		 238 u32 ccr;
239
240 ccr = dma_read(CCR(lch));
709eb3e5 241 if (priority)
0499bdeb 242 ccr |= (1 << 6);
709eb3e5 243 else
0499bdeb
TL		 244 ccr &= ~(1 << 6);
245 dma_write(ccr, CCR(lch));
5e1c5ff4 246 }
5e1c5ff4 247}
97b7f715 248EXPORT_SYMBOL(omap_set_dma_priority);
5e1c5ff4
TL		 249
250void omap_set_dma_transfer_params(int lch, int data_type, int elem_count,
1a8bfa1e
TL		 251 int frame_count, int sync_mode,
252 int dma_trigger, int src_or_dst_synch)
5e1c5ff4 253{
0499bdeb
TL		 254 u32 l;
255
256 l = dma_read(CSDP(lch));
257 l &= ~0x03;
258 l |= data_type;
259 dma_write(l, CSDP(lch));
5e1c5ff4 260
1a8bfa1e 261 if (cpu_class_is_omap1()) {
0499bdeb
TL		 262 u16 ccr;
263
264 ccr = dma_read(CCR(lch));
265 ccr &= ~(1 << 5);
1a8bfa1e 266 if (sync_mode == OMAP_DMA_SYNC_FRAME)
0499bdeb
TL		 267 ccr |= 1 << 5;
268 dma_write(ccr, CCR(lch));
1a8bfa1e 269
0499bdeb
TL		 270 ccr = dma_read(CCR2(lch));
271 ccr &= ~(1 << 2);
1a8bfa1e 272 if (sync_mode == OMAP_DMA_SYNC_BLOCK)
0499bdeb
TL		 273 ccr |= 1 << 2;
274 dma_write(ccr, CCR2(lch));
1a8bfa1e
TL		 275 }
276
f8151e5c 277 if (cpu_class_is_omap2() && dma_trigger) {
0499bdeb 278 u32 val;
1a8bfa1e 279
0499bdeb 280 val = dma_read(CCR(lch));
4b3cf448
AG		 281
282 /* DMA_SYNCHRO_CONTROL_UPPER depends on the channel number */
283 val &= ~((3 << 19) | 0x1f);
284 val |= (dma_trigger & ~0x1f) << 14;
285 val |= dma_trigger & 0x1f;
5e1c5ff4 286
1a8bfa1e
TL		 287 if (sync_mode & OMAP_DMA_SYNC_FRAME)
288 val |= 1 << 5;
eca9e56e
PU		 289 else
290 val &= ~(1 << 5);
5e1c5ff4 291
1a8bfa1e
TL		 292 if (sync_mode & OMAP_DMA_SYNC_BLOCK)
293 val |= 1 << 18;
eca9e56e
PU		 294 else
295 val &= ~(1 << 18);
5e1c5ff4 296
1a8bfa1e
TL		 297 if (src_or_dst_synch)
298 val |= 1 << 24; /* source synch */
299 else
300 val &= ~(1 << 24); /* dest synch */
301
0499bdeb 302 dma_write(val, CCR(lch));
1a8bfa1e
TL		 303 }
304
0499bdeb
TL		 305 dma_write(elem_count, CEN(lch));
306 dma_write(frame_count, CFN(lch));
5e1c5ff4 307}
97b7f715 308EXPORT_SYMBOL(omap_set_dma_transfer_params);
1a8bfa1e 309
5e1c5ff4
TL		 310void omap_set_dma_color_mode(int lch, enum omap_dma_color_mode mode, u32 color)
311{
312 u16 w;
313
314 BUG_ON(omap_dma_in_1510_mode());
315
f8151e5c 316 if (cpu_class_is_omap2()) {
1a8bfa1e
TL		 317 REVISIT_24XX();
318 return;
319 }
320
0499bdeb
TL		 321 w = dma_read(CCR2(lch));
322 w &= ~0x03;
323
5e1c5ff4
TL		 324 switch (mode) {
325 case OMAP_DMA_CONSTANT_FILL:
326 w |= 0x01;
327 break;
328 case OMAP_DMA_TRANSPARENT_COPY:
329 w |= 0x02;
330 break;
331 case OMAP_DMA_COLOR_DIS:
332 break;
333 default:
334 BUG();
335 }
0499bdeb 336 dma_write(w, CCR2(lch));
5e1c5ff4 337
0499bdeb
TL		 338 w = dma_read(LCH_CTRL(lch));
339 w &= ~0x0f;
5e1c5ff4
TL		 340 /* Default is channel type 2D */
341 if (mode) {
0499bdeb
TL		 342 dma_write((u16)color, COLOR_L(lch));
343 dma_write((u16)(color >> 16), COLOR_U(lch));
5e1c5ff4
TL		 344 w |= 1; /* Channel type G */
345 }
0499bdeb 346 dma_write(w, LCH_CTRL(lch));
5e1c5ff4 347}
97b7f715 348EXPORT_SYMBOL(omap_set_dma_color_mode);
5e1c5ff4 349
709eb3e5
TL		 350void omap_set_dma_write_mode(int lch, enum omap_dma_write_mode mode)
351{
f8151e5c 352 if (cpu_class_is_omap2()) {
0499bdeb
TL		 353 u32 csdp;
354
355 csdp = dma_read(CSDP(lch));
356 csdp &= ~(0x3 << 16);
357 csdp |= (mode << 16);
358 dma_write(csdp, CSDP(lch));
709eb3e5
TL		 359 }
360}
97b7f715 361EXPORT_SYMBOL(omap_set_dma_write_mode);
709eb3e5 362
0499bdeb
TL		 363void omap_set_dma_channel_mode(int lch, enum omap_dma_channel_mode mode)
364{
365 if (cpu_class_is_omap1() && !cpu_is_omap15xx()) {
366 u32 l;
367
368 l = dma_read(LCH_CTRL(lch));
369 l &= ~0x7;
370 l |= mode;
371 dma_write(l, LCH_CTRL(lch));
372 }
373}
374EXPORT_SYMBOL(omap_set_dma_channel_mode);
375
1a8bfa1e 376/* Note that src_port is only for omap1 */
5e1c5ff4 377void omap_set_dma_src_params(int lch, int src_port, int src_amode,
1a8bfa1e
TL		 378 unsigned long src_start,
379 int src_ei, int src_fi)
5e1c5ff4 380{
97b7f715
TL		 381 u32 l;
382
1a8bfa1e 383 if (cpu_class_is_omap1()) {
0499bdeb 384 u16 w;
1a8bfa1e 385
0499bdeb
TL		 386 w = dma_read(CSDP(lch));
387 w &= ~(0x1f << 2);
388 w |= src_port << 2;
389 dma_write(w, CSDP(lch));
97b7f715 390 }
1a8bfa1e 391
97b7f715
TL		 392 l = dma_read(CCR(lch));
393 l &= ~(0x03 << 12);
394 l |= src_amode << 12;
395 dma_write(l, CCR(lch));
0499bdeb 396
97b7f715 397 if (cpu_class_is_omap1()) {
0499bdeb
TL		 398 dma_write(src_start >> 16, CSSA_U(lch));
399 dma_write((u16)src_start, CSSA_L(lch));
1a8bfa1e 400 }
5e1c5ff4 401
97b7f715 402 if (cpu_class_is_omap2())
0499bdeb 403 dma_write(src_start, CSSA(lch));
97b7f715
TL		 404
405 dma_write(src_ei, CSEI(lch));
406 dma_write(src_fi, CSFI(lch));
1a8bfa1e 407}
97b7f715 408EXPORT_SYMBOL(omap_set_dma_src_params);
5e1c5ff4 409
97b7f715 410void omap_set_dma_params(int lch, struct omap_dma_channel_params *params)
1a8bfa1e
TL		 411{
412 omap_set_dma_transfer_params(lch, params->data_type,
413 params->elem_count, params->frame_count,
414 params->sync_mode, params->trigger,
415 params->src_or_dst_synch);
416 omap_set_dma_src_params(lch, params->src_port,
417 params->src_amode, params->src_start,
418 params->src_ei, params->src_fi);
419
420 omap_set_dma_dest_params(lch, params->dst_port,
421 params->dst_amode, params->dst_start,
422 params->dst_ei, params->dst_fi);
f8151e5c
AG		 423 if (params->read_prio || params->write_prio)
424 omap_dma_set_prio_lch(lch, params->read_prio,
425 params->write_prio);
5e1c5ff4 426}
97b7f715 427EXPORT_SYMBOL(omap_set_dma_params);
5e1c5ff4
TL		 428
429void omap_set_dma_src_index(int lch, int eidx, int fidx)
430{
97b7f715 431 if (cpu_class_is_omap2())
1a8bfa1e 432 return;
97b7f715 433
0499bdeb
TL		 434 dma_write(eidx, CSEI(lch));
435 dma_write(fidx, CSFI(lch));
5e1c5ff4 436}
97b7f715 437EXPORT_SYMBOL(omap_set_dma_src_index);
5e1c5ff4
TL		 438
439void omap_set_dma_src_data_pack(int lch, int enable)
440{
0499bdeb
TL		 441 u32 l;
442
443 l = dma_read(CSDP(lch));
444 l &= ~(1 << 6);
1a8bfa1e 445 if (enable)
0499bdeb
TL		 446 l |= (1 << 6);
447 dma_write(l, CSDP(lch));
5e1c5ff4 448}
97b7f715 449EXPORT_SYMBOL(omap_set_dma_src_data_pack);
5e1c5ff4
TL		 450
451void omap_set_dma_src_burst_mode(int lch, enum omap_dma_burst_mode burst_mode)
452{
6dc3c8f2 453 unsigned int burst = 0;
0499bdeb
TL		 454 u32 l;
455
456 l = dma_read(CSDP(lch));
457 l &= ~(0x03 << 7);
5e1c5ff4 458
5e1c5ff4
TL		 459 switch (burst_mode) {
460 case OMAP_DMA_DATA_BURST_DIS:
461 break;
462 case OMAP_DMA_DATA_BURST_4:
f8151e5c 463 if (cpu_class_is_omap2())
6dc3c8f2
KP		 464 burst = 0x1;
465 else
466 burst = 0x2;
5e1c5ff4
TL		 467 break;
468 case OMAP_DMA_DATA_BURST_8:
f8151e5c 469 if (cpu_class_is_omap2()) {
6dc3c8f2
KP		 470 burst = 0x2;
471 break;
472 }
473 /* not supported by current hardware on OMAP1
5e1c5ff4
TL		 474 * w |= (0x03 << 7);
475 * fall through
476 */
6dc3c8f2 477 case OMAP_DMA_DATA_BURST_16:
f8151e5c 478 if (cpu_class_is_omap2()) {
6dc3c8f2
KP		 479 burst = 0x3;
480 break;
481 }
482 /* OMAP1 don't support burst 16
483 * fall through
484 */
5e1c5ff4
TL		 485 default:
486 BUG();
487 }
0499bdeb
TL		 488
489 l |= (burst << 7);
490 dma_write(l, CSDP(lch));
5e1c5ff4 491}
97b7f715 492EXPORT_SYMBOL(omap_set_dma_src_burst_mode);
5e1c5ff4 493
1a8bfa1e 494/* Note that dest_port is only for OMAP1 */
5e1c5ff4 495void omap_set_dma_dest_params(int lch, int dest_port, int dest_amode,
1a8bfa1e
TL		 496 unsigned long dest_start,
497 int dst_ei, int dst_fi)
5e1c5ff4 498{
0499bdeb
TL		 499 u32 l;
500
1a8bfa1e 501 if (cpu_class_is_omap1()) {
0499bdeb
TL		 502 l = dma_read(CSDP(lch));
503 l &= ~(0x1f << 9);
504 l |= dest_port << 9;
505 dma_write(l, CSDP(lch));
1a8bfa1e 506 }
5e1c5ff4 507
0499bdeb
TL		 508 l = dma_read(CCR(lch));
509 l &= ~(0x03 << 14);
510 l |= dest_amode << 14;
511 dma_write(l, CCR(lch));
1a8bfa1e
TL		 512
513 if (cpu_class_is_omap1()) {
0499bdeb
TL		 514 dma_write(dest_start >> 16, CDSA_U(lch));
515 dma_write(dest_start, CDSA_L(lch));
1a8bfa1e 516 }
5e1c5ff4 517
f8151e5c 518 if (cpu_class_is_omap2())
0499bdeb 519 dma_write(dest_start, CDSA(lch));
5e1c5ff4 520
0499bdeb
TL		 521 dma_write(dst_ei, CDEI(lch));
522 dma_write(dst_fi, CDFI(lch));
5e1c5ff4 523}
97b7f715 524EXPORT_SYMBOL(omap_set_dma_dest_params);
5e1c5ff4
TL		 525
526void omap_set_dma_dest_index(int lch, int eidx, int fidx)
527{
97b7f715 528 if (cpu_class_is_omap2())
1a8bfa1e 529 return;
97b7f715 530
0499bdeb
TL		 531 dma_write(eidx, CDEI(lch));
532 dma_write(fidx, CDFI(lch));
5e1c5ff4 533}
97b7f715 534EXPORT_SYMBOL(omap_set_dma_dest_index);
5e1c5ff4
TL		 535
536void omap_set_dma_dest_data_pack(int lch, int enable)
537{
0499bdeb
TL		 538 u32 l;
539
540 l = dma_read(CSDP(lch));
541 l &= ~(1 << 13);
1a8bfa1e 542 if (enable)
0499bdeb
TL		 543 l |= 1 << 13;
544 dma_write(l, CSDP(lch));
5e1c5ff4 545}
97b7f715 546EXPORT_SYMBOL(omap_set_dma_dest_data_pack);
5e1c5ff4
TL		 547
548void omap_set_dma_dest_burst_mode(int lch, enum omap_dma_burst_mode burst_mode)
549{
6dc3c8f2 550 unsigned int burst = 0;
0499bdeb
TL		 551 u32 l;
552
553 l = dma_read(CSDP(lch));
554 l &= ~(0x03 << 14);
5e1c5ff4 555
5e1c5ff4
TL		 556 switch (burst_mode) {
557 case OMAP_DMA_DATA_BURST_DIS:
558 break;
559 case OMAP_DMA_DATA_BURST_4:
f8151e5c 560 if (cpu_class_is_omap2())
6dc3c8f2
KP		 561 burst = 0x1;
562 else
563 burst = 0x2;
5e1c5ff4
TL		 564 break;
565 case OMAP_DMA_DATA_BURST_8:
f8151e5c 566 if (cpu_class_is_omap2())
6dc3c8f2
KP		 567 burst = 0x2;
568 else
569 burst = 0x3;
5e1c5ff4 570 break;
6dc3c8f2 571 case OMAP_DMA_DATA_BURST_16:
f8151e5c 572 if (cpu_class_is_omap2()) {
6dc3c8f2
KP		 573 burst = 0x3;
574 break;
575 }
576 /* OMAP1 don't support burst 16
577 * fall through
578 */
5e1c5ff4
TL		 579 default:
580 printk(KERN_ERR "Invalid DMA burst mode\n");
581 BUG();
582 return;
583 }
0499bdeb
TL		 584 l |= (burst << 14);
585 dma_write(l, CSDP(lch));
5e1c5ff4 586}
97b7f715 587EXPORT_SYMBOL(omap_set_dma_dest_burst_mode);
5e1c5ff4 588
1a8bfa1e 589static inline void omap_enable_channel_irq(int lch)
5e1c5ff4 590{
1a8bfa1e 591 u32 status;
5e1c5ff4 592
7ff879db
TL		 593 /* Clear CSR */
594 if (cpu_class_is_omap1())
0499bdeb 595 status = dma_read(CSR(lch));
f8151e5c 596 else if (cpu_class_is_omap2())
0499bdeb 597 dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR(lch));
1a8bfa1e 598
5e1c5ff4 599 /* Enable some nice interrupts. */
0499bdeb 600 dma_write(dma_chan[lch].enabled_irqs, CICR(lch));
5e1c5ff4
TL		 601}
602
1a8bfa1e 603static void omap_disable_channel_irq(int lch)
5e1c5ff4 604{
f8151e5c 605 if (cpu_class_is_omap2())
0499bdeb 606 dma_write(0, CICR(lch));
1a8bfa1e
TL		 607}
608
609void omap_enable_dma_irq(int lch, u16 bits)
610{
611 dma_chan[lch].enabled_irqs |= bits;
612}
97b7f715 613EXPORT_SYMBOL(omap_enable_dma_irq);
5e1c5ff4 614
1a8bfa1e
TL		 615void omap_disable_dma_irq(int lch, u16 bits)
616{
617 dma_chan[lch].enabled_irqs &= ~bits;
618}
97b7f715 619EXPORT_SYMBOL(omap_disable_dma_irq);
1a8bfa1e
TL		 620
621static inline void enable_lnk(int lch)
622{
0499bdeb
TL		 623 u32 l;
624
625 l = dma_read(CLNK_CTRL(lch));
626
1a8bfa1e 627 if (cpu_class_is_omap1())
0499bdeb 628 l &= ~(1 << 14);
5e1c5ff4 629
1a8bfa1e 630 /* Set the ENABLE_LNK bits */
5e1c5ff4 631 if (dma_chan[lch].next_lch != -1)
0499bdeb 632 l = dma_chan[lch].next_lch | (1 << 15);
f8151e5c
AG		 633
634#ifndef CONFIG_ARCH_OMAP1
97b7f715
TL		 635 if (cpu_class_is_omap2())
636 if (dma_chan[lch].next_linked_ch != -1)
637 l = dma_chan[lch].next_linked_ch | (1 << 15);
f8151e5c 638#endif
0499bdeb
TL		 639
640 dma_write(l, CLNK_CTRL(lch));
5e1c5ff4
TL		 641}
642
643static inline void disable_lnk(int lch)
644{
0499bdeb
TL		 645 u32 l;
646
647 l = dma_read(CLNK_CTRL(lch));
648
5e1c5ff4 649 /* Disable interrupts */
1a8bfa1e 650 if (cpu_class_is_omap1()) {
0499bdeb 651 dma_write(0, CICR(lch));
1a8bfa1e 652 /* Set the STOP_LNK bit */
0499bdeb 653 l |= 1 << 14;
1a8bfa1e 654 }
5e1c5ff4 655
f8151e5c 656 if (cpu_class_is_omap2()) {
1a8bfa1e
TL		 657 omap_disable_channel_irq(lch);
658 /* Clear the ENABLE_LNK bit */
0499bdeb 659 l &= ~(1 << 15);
1a8bfa1e 660 }
5e1c5ff4 661
0499bdeb 662 dma_write(l, CLNK_CTRL(lch));
5e1c5ff4
TL		 663 dma_chan[lch].flags &= ~OMAP_DMA_ACTIVE;
664}
665
1a8bfa1e 666static inline void omap2_enable_irq_lch(int lch)
5e1c5ff4 667{
1a8bfa1e
TL		 668 u32 val;
669
f8151e5c 670 if (!cpu_class_is_omap2())
1a8bfa1e
TL		 671 return;
672
0499bdeb 673 val = dma_read(IRQENABLE_L0);
1a8bfa1e 674 val |= 1 << lch;
0499bdeb 675 dma_write(val, IRQENABLE_L0);
1a8bfa1e
TL		 676}
677
678int omap_request_dma(int dev_id, const char *dev_name,
97b7f715 679 void (*callback)(int lch, u16 ch_status, void *data),
1a8bfa1e
TL		 680 void *data, int *dma_ch_out)
681{
682 int ch, free_ch = -1;
683 unsigned long flags;
684 struct omap_dma_lch *chan;
685
686 spin_lock_irqsave(&dma_chan_lock, flags);
687 for (ch = 0; ch < dma_chan_count; ch++) {
688 if (free_ch == -1 && dma_chan[ch].dev_id == -1) {
689 free_ch = ch;
690 if (dev_id == 0)
691 break;
692 }
693 }
694 if (free_ch == -1) {
695 spin_unlock_irqrestore(&dma_chan_lock, flags);
696 return -EBUSY;
697 }
698 chan = dma_chan + free_ch;
699 chan->dev_id = dev_id;
700
701 if (cpu_class_is_omap1())
702 clear_lch_regs(free_ch);
5e1c5ff4 703
f8151e5c 704 if (cpu_class_is_omap2())
1a8bfa1e
TL		 705 omap_clear_dma(free_ch);
706
707 spin_unlock_irqrestore(&dma_chan_lock, flags);
708
709 chan->dev_name = dev_name;
710 chan->callback = callback;
711 chan->data = data;
a92fda19 712 chan->flags = 0;
97b7f715 713
f8151e5c 714#ifndef CONFIG_ARCH_OMAP1
97b7f715
TL		 715 if (cpu_class_is_omap2()) {
716 chan->chain_id = -1;
717 chan->next_linked_ch = -1;
718 }
f8151e5c 719#endif
97b7f715 720
7ff879db 721 chan->enabled_irqs = OMAP_DMA_DROP_IRQ | OMAP_DMA_BLOCK_IRQ;
1a8bfa1e 722
7ff879db
TL		 723 if (cpu_class_is_omap1())
724 chan->enabled_irqs |= OMAP1_DMA_TOUT_IRQ;
f8151e5c 725 else if (cpu_class_is_omap2())
7ff879db
TL		 726 chan->enabled_irqs |= OMAP2_DMA_MISALIGNED_ERR_IRQ |
727 OMAP2_DMA_TRANS_ERR_IRQ;
1a8bfa1e
TL		 728
729 if (cpu_is_omap16xx()) {
730 /* If the sync device is set, configure it dynamically. */
731 if (dev_id != 0) {
732 set_gdma_dev(free_ch + 1, dev_id);
733 dev_id = free_ch + 1;
734 }
97b7f715
TL		 735 /*
736 * Disable the 1510 compatibility mode and set the sync device
737 * id.
738 */
0499bdeb 739 dma_write(dev_id | (1 << 10), CCR(free_ch));
1a8bfa1e 740 } else if (cpu_is_omap730() || cpu_is_omap15xx()) {
0499bdeb 741 dma_write(dev_id, CCR(free_ch));
1a8bfa1e
TL		 742 }
743
f8151e5c 744 if (cpu_class_is_omap2()) {
1a8bfa1e 745 omap2_enable_irq_lch(free_ch);
1a8bfa1e
TL		 746 omap_enable_channel_irq(free_ch);
747 /* Clear the CSR register and IRQ status register */
0499bdeb
TL		 748 dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR(free_ch));
749 dma_write(1 << free_ch, IRQSTATUS_L0);
1a8bfa1e
TL		 750 }
751
752 *dma_ch_out = free_ch;
753
754 return 0;
755}
97b7f715 756EXPORT_SYMBOL(omap_request_dma);
1a8bfa1e
TL		 757
758void omap_free_dma(int lch)
759{
760 unsigned long flags;
761
762 spin_lock_irqsave(&dma_chan_lock, flags);
763 if (dma_chan[lch].dev_id == -1) {
97b7f715 764 pr_err("omap_dma: trying to free unallocated DMA channel %d\n",
1a8bfa1e
TL		 765 lch);
766 spin_unlock_irqrestore(&dma_chan_lock, flags);
767 return;
768 }
97b7f715 769
1a8bfa1e
TL		 770 dma_chan[lch].dev_id = -1;
771 dma_chan[lch].next_lch = -1;
772 dma_chan[lch].callback = NULL;
773 spin_unlock_irqrestore(&dma_chan_lock, flags);
774
775 if (cpu_class_is_omap1()) {
776 /* Disable all DMA interrupts for the channel. */
0499bdeb 777 dma_write(0, CICR(lch));
1a8bfa1e 778 /* Make sure the DMA transfer is stopped. */
0499bdeb 779 dma_write(0, CCR(lch));
1a8bfa1e
TL		 780 }
781
f8151e5c 782 if (cpu_class_is_omap2()) {
1a8bfa1e
TL		 783 u32 val;
784 /* Disable interrupts */
0499bdeb 785 val = dma_read(IRQENABLE_L0);
1a8bfa1e 786 val &= ~(1 << lch);
0499bdeb 787 dma_write(val, IRQENABLE_L0);
1a8bfa1e
TL		 788
789 /* Clear the CSR register and IRQ status register */
0499bdeb
TL		 790 dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR(lch));
791 dma_write(1 << lch, IRQSTATUS_L0);
1a8bfa1e
TL		 792
793 /* Disable all DMA interrupts for the channel. */
0499bdeb 794 dma_write(0, CICR(lch));
1a8bfa1e
TL		 795
796 /* Make sure the DMA transfer is stopped. */
0499bdeb 797 dma_write(0, CCR(lch));
1a8bfa1e
TL		 798 omap_clear_dma(lch);
799 }
800}
97b7f715 801EXPORT_SYMBOL(omap_free_dma);
1a8bfa1e 802
f8151e5c
AG		 803/**
804 * @brief omap_dma_set_global_params : Set global priority settings for dma
805 *
806 * @param arb_rate
807 * @param max_fifo_depth
808 * @param tparams - Number of thereads to reserve : DMA_THREAD_RESERVE_NORM
809 * DMA_THREAD_RESERVE_ONET
810 * DMA_THREAD_RESERVE_TWOT
811 * DMA_THREAD_RESERVE_THREET
812 */
813void
814omap_dma_set_global_params(int arb_rate, int max_fifo_depth, int tparams)
815{
816 u32 reg;
817
818 if (!cpu_class_is_omap2()) {
8e86f427 819 printk(KERN_ERR "FIXME: no %s on 15xx/16xx\n", __func__);
f8151e5c
AG		 820 return;
821 }
822
823 if (arb_rate == 0)
824 arb_rate = 1;
825
826 reg = (arb_rate & 0xff) << 16;
827 reg |= (0xff & max_fifo_depth);
828
0499bdeb 829 dma_write(reg, GCR);
f8151e5c
AG		 830}
831EXPORT_SYMBOL(omap_dma_set_global_params);
832
833/**
834 * @brief omap_dma_set_prio_lch : Set channel wise priority settings
835 *
836 * @param lch
837 * @param read_prio - Read priority
838 * @param write_prio - Write priority
839 * Both of the above can be set with one of the following values :
840 * DMA_CH_PRIO_HIGH/DMA_CH_PRIO_LOW
841 */
842int
843omap_dma_set_prio_lch(int lch, unsigned char read_prio,
844 unsigned char write_prio)
845{
0499bdeb 846 u32 l;
f8151e5c 847
4d96372e 848 if (unlikely((lch < 0 || lch >= dma_lch_count))) {
f8151e5c
AG		 849 printk(KERN_ERR "Invalid channel id\n");
850 return -EINVAL;
851 }
0499bdeb
TL		 852 l = dma_read(CCR(lch));
853 l &= ~((1 << 6) | (1 << 26));
f8151e5c 854 if (cpu_is_omap2430() || cpu_is_omap34xx())
0499bdeb 855 l |= ((read_prio & 0x1) << 6) | ((write_prio & 0x1) << 26);
f8151e5c 856 else
0499bdeb
TL		 857 l |= ((read_prio & 0x1) << 6);
858
859 dma_write(l, CCR(lch));
f8151e5c 860
f8151e5c
AG		 861 return 0;
862}
863EXPORT_SYMBOL(omap_dma_set_prio_lch);
864
1a8bfa1e
TL		 865/*
866 * Clears any DMA state so the DMA engine is ready to restart with new buffers
867 * through omap_start_dma(). Any buffers in flight are discarded.
868 */
869void omap_clear_dma(int lch)
870{
871 unsigned long flags;
872
873 local_irq_save(flags);
874
875 if (cpu_class_is_omap1()) {
0499bdeb
TL		 876 u32 l;
877
878 l = dma_read(CCR(lch));
879 l &= ~OMAP_DMA_CCR_EN;
880 dma_write(l, CCR(lch));
1a8bfa1e
TL		 881
882 /* Clear pending interrupts */
0499bdeb 883 l = dma_read(CSR(lch));
1a8bfa1e
TL		 884 }
885
f8151e5c 886 if (cpu_class_is_omap2()) {
1a8bfa1e 887 int i;
0499bdeb 888 void __iomem *lch_base = omap_dma_base + OMAP_DMA4_CH_BASE(lch);
1a8bfa1e 889 for (i = 0; i < 0x44; i += 4)
0499bdeb 890 __raw_writel(0, lch_base + i);
1a8bfa1e
TL		 891 }
892
893 local_irq_restore(flags);
894}
97b7f715 895EXPORT_SYMBOL(omap_clear_dma);
1a8bfa1e
TL		 896
897void omap_start_dma(int lch)
898{
0499bdeb
TL		 899 u32 l;
900
5e1c5ff4
TL		 901 if (!omap_dma_in_1510_mode() && dma_chan[lch].next_lch != -1) {
902 int next_lch, cur_lch;
4d96372e 903 char dma_chan_link_map[OMAP_DMA4_LOGICAL_DMA_CH_COUNT];
5e1c5ff4
TL		 904
905 dma_chan_link_map[lch] = 1;
906 /* Set the link register of the first channel */
907 enable_lnk(lch);
908
909 memset(dma_chan_link_map, 0, sizeof(dma_chan_link_map));
910 cur_lch = dma_chan[lch].next_lch;
911 do {
912 next_lch = dma_chan[cur_lch].next_lch;
913
1a8bfa1e 914 /* The loop case: we've been here already */
5e1c5ff4
TL		 915 if (dma_chan_link_map[cur_lch])
916 break;
917 /* Mark the current channel */
918 dma_chan_link_map[cur_lch] = 1;
919
920 enable_lnk(cur_lch);
1a8bfa1e 921 omap_enable_channel_irq(cur_lch);
5e1c5ff4
TL		 922
923 cur_lch = next_lch;
924 } while (next_lch != -1);
f8151e5c 925 } else if (cpu_class_is_omap2()) {
1a8bfa1e 926 /* Errata: Need to write lch even if not using chaining */
0499bdeb 927 dma_write(lch, CLNK_CTRL(lch));
5e1c5ff4
TL		 928 }
929
1a8bfa1e
TL		 930 omap_enable_channel_irq(lch);
931
0499bdeb
TL		 932 l = dma_read(CCR(lch));
933
97b7f715
TL		 934 /*
935 * Errata: On ES2.0 BUFFERING disable must be set.
936 * This will always fail on ES1.0
937 */
0499bdeb
TL		 938 if (cpu_is_omap24xx())
939 l |= OMAP_DMA_CCR_EN;
1a8bfa1e 940
0499bdeb
TL		 941 l |= OMAP_DMA_CCR_EN;
942 dma_write(l, CCR(lch));
5e1c5ff4 943
5e1c5ff4
TL		 944 dma_chan[lch].flags |= OMAP_DMA_ACTIVE;
945}
97b7f715 946EXPORT_SYMBOL(omap_start_dma);
5e1c5ff4
TL		 947
948void omap_stop_dma(int lch)
949{
0499bdeb
TL		 950 u32 l;
951
5e1c5ff4
TL		 952 if (!omap_dma_in_1510_mode() && dma_chan[lch].next_lch != -1) {
953 int next_lch, cur_lch = lch;
4d96372e 954 char dma_chan_link_map[OMAP_DMA4_LOGICAL_DMA_CH_COUNT];
5e1c5ff4
TL		 955
956 memset(dma_chan_link_map, 0, sizeof(dma_chan_link_map));
957 do {
958 /* The loop case: we've been here already */
959 if (dma_chan_link_map[cur_lch])
960 break;
961 /* Mark the current channel */
962 dma_chan_link_map[cur_lch] = 1;
963
964 disable_lnk(cur_lch);
965
966 next_lch = dma_chan[cur_lch].next_lch;
967 cur_lch = next_lch;
968 } while (next_lch != -1);
969
970 return;
971 }
1a8bfa1e 972
5e1c5ff4 973 /* Disable all interrupts on the channel */
1a8bfa1e 974 if (cpu_class_is_omap1())
0499bdeb
TL		 975 dma_write(0, CICR(lch));
976
977 l = dma_read(CCR(lch));
978 l &= ~OMAP_DMA_CCR_EN;
979 dma_write(l, CCR(lch));
5e1c5ff4 980
5e1c5ff4
TL		 981 dma_chan[lch].flags &= ~OMAP_DMA_ACTIVE;
982}
97b7f715 983EXPORT_SYMBOL(omap_stop_dma);
5e1c5ff4 984
709eb3e5
TL		 985/*
986 * Allows changing the DMA callback function or data. This may be needed if
987 * the driver shares a single DMA channel for multiple dma triggers.
988 */
989int omap_set_dma_callback(int lch,
97b7f715 990 void (*callback)(int lch, u16 ch_status, void *data),
709eb3e5
TL		 991 void *data)
992{
993 unsigned long flags;
994
995 if (lch < 0)
996 return -ENODEV;
997
998 spin_lock_irqsave(&dma_chan_lock, flags);
999 if (dma_chan[lch].dev_id == -1) {
1000 printk(KERN_ERR "DMA callback for not set for free channel\n");
1001 spin_unlock_irqrestore(&dma_chan_lock, flags);
1002 return -EINVAL;
1003 }
1004 dma_chan[lch].callback = callback;
1005 dma_chan[lch].data = data;
1006 spin_unlock_irqrestore(&dma_chan_lock, flags);
1007
1008 return 0;
1009}
97b7f715 1010EXPORT_SYMBOL(omap_set_dma_callback);
709eb3e5 1011
1a8bfa1e
TL		 1012/*
1013 * Returns current physical source address for the given DMA channel.
1014 * If the channel is running the caller must disable interrupts prior calling
1015 * this function and process the returned value before re-enabling interrupt to
1016 * prevent races with the interrupt handler. Note that in continuous mode there
1017 * is a chance for CSSA_L register overflow inbetween the two reads resulting
1018 * in incorrect return value.
1019 */
1020dma_addr_t omap_get_dma_src_pos(int lch)
5e1c5ff4 1021{
0695de32 1022 dma_addr_t offset = 0;
5e1c5ff4 1023
0499bdeb
TL		 1024 if (cpu_is_omap15xx())
1025 offset = dma_read(CPC(lch));
1026 else
1027 offset = dma_read(CSAC(lch));
5e1c5ff4 1028
0499bdeb
TL		 1029 /*
1030 * omap 3.2/3.3 erratum: sometimes 0 is returned if CSAC/CDAC is
1031 * read before the DMA controller finished disabling the channel.
1032 */
1033 if (!cpu_is_omap15xx() && offset == 0)
1034 offset = dma_read(CSAC(lch));
1035
1036 if (cpu_class_is_omap1())
1037 offset |= (dma_read(CSSA_U(lch)) << 16);
5e1c5ff4 1038
1a8bfa1e 1039 return offset;
5e1c5ff4 1040}
97b7f715 1041EXPORT_SYMBOL(omap_get_dma_src_pos);
5e1c5ff4 1042
1a8bfa1e
TL		 1043/*
1044 * Returns current physical destination address for the given DMA channel.
1045 * If the channel is running the caller must disable interrupts prior calling
1046 * this function and process the returned value before re-enabling interrupt to
1047 * prevent races with the interrupt handler. Note that in continuous mode there
1048 * is a chance for CDSA_L register overflow inbetween the two reads resulting
1049 * in incorrect return value.
1050 */
1051dma_addr_t omap_get_dma_dst_pos(int lch)
5e1c5ff4 1052{
0695de32 1053 dma_addr_t offset = 0;
5e1c5ff4 1054
0499bdeb
TL		 1055 if (cpu_is_omap15xx())
1056 offset = dma_read(CPC(lch));
1057 else
1058 offset = dma_read(CDAC(lch));
5e1c5ff4 1059
0499bdeb
TL		 1060 /*
1061 * omap 3.2/3.3 erratum: sometimes 0 is returned if CSAC/CDAC is
1062 * read before the DMA controller finished disabling the channel.
1063 */
1064 if (!cpu_is_omap15xx() && offset == 0)
1065 offset = dma_read(CDAC(lch));
1066
1067 if (cpu_class_is_omap1())
1068 offset |= (dma_read(CDSA_U(lch)) << 16);
5e1c5ff4 1069
1a8bfa1e 1070 return offset;
5e1c5ff4 1071}
97b7f715 1072EXPORT_SYMBOL(omap_get_dma_dst_pos);
0499bdeb
TL		 1073
1074int omap_get_dma_active_status(int lch)
1075{
1076 return (dma_read(CCR(lch)) & OMAP_DMA_CCR_EN) != 0;
5e1c5ff4 1077}
0499bdeb 1078EXPORT_SYMBOL(omap_get_dma_active_status);
5e1c5ff4 1079
1a8bfa1e 1080int omap_dma_running(void)
5e1c5ff4 1081{
1a8bfa1e 1082 int lch;
5e1c5ff4 1083
1a8bfa1e
TL		 1084 /* Check if LCD DMA is running */
1085 if (cpu_is_omap16xx())
1086 if (omap_readw(OMAP1610_DMA_LCD_CCR) & OMAP_DMA_CCR_EN)
1087 return 1;
5e1c5ff4 1088
1a8bfa1e 1089 for (lch = 0; lch < dma_chan_count; lch++)
0499bdeb 1090 if (dma_read(CCR(lch)) & OMAP_DMA_CCR_EN)
1a8bfa1e 1091 return 1;
5e1c5ff4 1092
1a8bfa1e 1093 return 0;
5e1c5ff4
TL		 1094}
1095
1096/*
1097 * lch_queue DMA will start right after lch_head one is finished.
1098 * For this DMA link to start, you still need to start (see omap_start_dma)
1099 * the first one. That will fire up the entire queue.
1100 */
97b7f715 1101void omap_dma_link_lch(int lch_head, int lch_queue)
5e1c5ff4
TL		 1102{
1103 if (omap_dma_in_1510_mode()) {
1104 printk(KERN_ERR "DMA linking is not supported in 1510 mode\n");
1105 BUG();
1106 return;
1107 }
1108
1109 if ((dma_chan[lch_head].dev_id == -1) ||
1110 (dma_chan[lch_queue].dev_id == -1)) {
1a8bfa1e
TL		 1111 printk(KERN_ERR "omap_dma: trying to link "
1112 "non requested channels\n");
5e1c5ff4
TL		 1113 dump_stack();
1114 }
1115
1116 dma_chan[lch_head].next_lch = lch_queue;
1117}
97b7f715 1118EXPORT_SYMBOL(omap_dma_link_lch);
5e1c5ff4
TL		 1119
1120/*
1121 * Once the DMA queue is stopped, we can destroy it.
1122 */
97b7f715 1123void omap_dma_unlink_lch(int lch_head, int lch_queue)
5e1c5ff4
TL		 1124{
1125 if (omap_dma_in_1510_mode()) {
1126 printk(KERN_ERR "DMA linking is not supported in 1510 mode\n");
1127 BUG();
1128 return;
1129 }
1130
1131 if (dma_chan[lch_head].next_lch != lch_queue ||
1132 dma_chan[lch_head].next_lch == -1) {
1a8bfa1e
TL		 1133 printk(KERN_ERR "omap_dma: trying to unlink "
1134 "non linked channels\n");
5e1c5ff4
TL		 1135 dump_stack();
1136 }
1137
5e1c5ff4
TL		 1138 if ((dma_chan[lch_head].flags & OMAP_DMA_ACTIVE) ||
1139 (dma_chan[lch_head].flags & OMAP_DMA_ACTIVE)) {
1a8bfa1e
TL		 1140 printk(KERN_ERR "omap_dma: You need to stop the DMA channels "
1141 "before unlinking\n");
5e1c5ff4
TL		 1142 dump_stack();
1143 }
1144
1145 dma_chan[lch_head].next_lch = -1;
1146}
97b7f715
TL		 1147EXPORT_SYMBOL(omap_dma_unlink_lch);
1148
1149/*----------------------------------------------------------------------------*/
5e1c5ff4 1150
f8151e5c
AG		 1151#ifndef CONFIG_ARCH_OMAP1
1152/* Create chain of DMA channesls */
1153static void create_dma_lch_chain(int lch_head, int lch_queue)
1154{
0499bdeb 1155 u32 l;
f8151e5c
AG		 1156
1157 /* Check if this is the first link in chain */
1158 if (dma_chan[lch_head].next_linked_ch == -1) {
1159 dma_chan[lch_head].next_linked_ch = lch_queue;
1160 dma_chan[lch_head].prev_linked_ch = lch_queue;
1161 dma_chan[lch_queue].next_linked_ch = lch_head;
1162 dma_chan[lch_queue].prev_linked_ch = lch_head;
1163 }
1164
1165 /* a link exists, link the new channel in circular chain */
1166 else {
1167 dma_chan[lch_queue].next_linked_ch =
1168 dma_chan[lch_head].next_linked_ch;
1169 dma_chan[lch_queue].prev_linked_ch = lch_head;
1170 dma_chan[lch_head].next_linked_ch = lch_queue;
1171 dma_chan[dma_chan[lch_queue].next_linked_ch].prev_linked_ch =
1172 lch_queue;
1173 }
1174
0499bdeb
TL		 1175 l = dma_read(CLNK_CTRL(lch_head));
1176 l &= ~(0x1f);
1177 l |= lch_queue;
1178 dma_write(l, CLNK_CTRL(lch_head));
f8151e5c 1179
0499bdeb
TL		 1180 l = dma_read(CLNK_CTRL(lch_queue));
1181 l &= ~(0x1f);
1182 l |= (dma_chan[lch_queue].next_linked_ch);
1183 dma_write(l, CLNK_CTRL(lch_queue));
f8151e5c
AG		 1184}
1185
1186/**
1187 * @brief omap_request_dma_chain : Request a chain of DMA channels
1188 *
1189 * @param dev_id - Device id using the dma channel
1190 * @param dev_name - Device name
1191 * @param callback - Call back function
1192 * @chain_id -
1193 * @no_of_chans - Number of channels requested
1194 * @chain_mode - Dynamic or static chaining : OMAP_DMA_STATIC_CHAIN
1195 * OMAP_DMA_DYNAMIC_CHAIN
1196 * @params - Channel parameters
1197 *
1198 * @return - Succes : 0
1199 * Failure: -EINVAL/-ENOMEM
1200 */
1201int omap_request_dma_chain(int dev_id, const char *dev_name,
1202 void (*callback) (int chain_id, u16 ch_status,
1203 void *data),
1204 int *chain_id, int no_of_chans, int chain_mode,
1205 struct omap_dma_channel_params params)
1206{
1207 int *channels;
1208 int i, err;
1209
1210 /* Is the chain mode valid ? */
1211 if (chain_mode != OMAP_DMA_STATIC_CHAIN
1212 && chain_mode != OMAP_DMA_DYNAMIC_CHAIN) {
1213 printk(KERN_ERR "Invalid chain mode requested\n");
1214 return -EINVAL;
1215 }
1216
1217 if (unlikely((no_of_chans < 1
4d96372e 1218 || no_of_chans > dma_lch_count))) {
f8151e5c
AG		 1219 printk(KERN_ERR "Invalid Number of channels requested\n");
1220 return -EINVAL;
1221 }
1222
1223 /* Allocate a queue to maintain the status of the channels
1224 * in the chain */
1225 channels = kmalloc(sizeof(*channels) * no_of_chans, GFP_KERNEL);
1226 if (channels == NULL) {
1227 printk(KERN_ERR "omap_dma: No memory for channel queue\n");
1228 return -ENOMEM;
1229 }
1230
1231 /* request and reserve DMA channels for the chain */
1232 for (i = 0; i < no_of_chans; i++) {
1233 err = omap_request_dma(dev_id, dev_name,
c0fc18c5 1234 callback, NULL, &channels[i]);
f8151e5c
AG		 1235 if (err < 0) {
1236 int j;
1237 for (j = 0; j < i; j++)
1238 omap_free_dma(channels[j]);
1239 kfree(channels);
1240 printk(KERN_ERR "omap_dma: Request failed %d\n", err);
1241 return err;
1242 }
f8151e5c
AG		 1243 dma_chan[channels[i]].prev_linked_ch = -1;
1244 dma_chan[channels[i]].state = DMA_CH_NOTSTARTED;
1245
1246 /*
1247 * Allowing client drivers to set common parameters now,
1248 * so that later only relevant (src_start, dest_start
1249 * and element count) can be set
1250 */
1251 omap_set_dma_params(channels[i], &params);
1252 }
1253
1254 *chain_id = channels[0];
1255 dma_linked_lch[*chain_id].linked_dmach_q = channels;
1256 dma_linked_lch[*chain_id].chain_mode = chain_mode;
1257 dma_linked_lch[*chain_id].chain_state = DMA_CHAIN_NOTSTARTED;
1258 dma_linked_lch[*chain_id].no_of_lchs_linked = no_of_chans;
1259
1260 for (i = 0; i < no_of_chans; i++)
1261 dma_chan[channels[i]].chain_id = *chain_id;
1262
1263 /* Reset the Queue pointers */
1264 OMAP_DMA_CHAIN_QINIT(*chain_id);
1265
1266 /* Set up the chain */
1267 if (no_of_chans == 1)
1268 create_dma_lch_chain(channels[0], channels[0]);
1269 else {
1270 for (i = 0; i < (no_of_chans - 1); i++)
1271 create_dma_lch_chain(channels[i], channels[i + 1]);
1272 }
97b7f715 1273
f8151e5c
AG		 1274 return 0;
1275}
1276EXPORT_SYMBOL(omap_request_dma_chain);
1277
1278/**
1279 * @brief omap_modify_dma_chain_param : Modify the chain's params - Modify the
1280 * params after setting it. Dont do this while dma is running!!
1281 *
1282 * @param chain_id - Chained logical channel id.
1283 * @param params
1284 *
1285 * @return - Success : 0
1286 * Failure : -EINVAL
1287 */
1288int omap_modify_dma_chain_params(int chain_id,
1289 struct omap_dma_channel_params params)
1290{
1291 int *channels;
1292 u32 i;
1293
1294 /* Check for input params */
1295 if (unlikely((chain_id < 0
4d96372e 1296 || chain_id >= dma_lch_count))) {
f8151e5c
AG		 1297 printk(KERN_ERR "Invalid chain id\n");
1298 return -EINVAL;
1299 }
1300
1301 /* Check if the chain exists */
1302 if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1303 printk(KERN_ERR "Chain doesn't exists\n");
1304 return -EINVAL;
1305 }
1306 channels = dma_linked_lch[chain_id].linked_dmach_q;
1307
1308 for (i = 0; i < dma_linked_lch[chain_id].no_of_lchs_linked; i++) {
1309 /*
1310 * Allowing client drivers to set common parameters now,
1311 * so that later only relevant (src_start, dest_start
1312 * and element count) can be set
1313 */
1314 omap_set_dma_params(channels[i], &params);
1315 }
97b7f715 1316
f8151e5c
AG		 1317 return 0;
1318}
1319EXPORT_SYMBOL(omap_modify_dma_chain_params);
1320
1321/**
1322 * @brief omap_free_dma_chain - Free all the logical channels in a chain.
1323 *
1324 * @param chain_id
1325 *
1326 * @return - Success : 0
1327 * Failure : -EINVAL
1328 */
1329int omap_free_dma_chain(int chain_id)
1330{
1331 int *channels;
1332 u32 i;
1333
1334 /* Check for input params */
4d96372e 1335 if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
f8151e5c
AG		 1336 printk(KERN_ERR "Invalid chain id\n");
1337 return -EINVAL;
1338 }
1339
1340 /* Check if the chain exists */
1341 if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1342 printk(KERN_ERR "Chain doesn't exists\n");
1343 return -EINVAL;
1344 }
1345
1346 channels = dma_linked_lch[chain_id].linked_dmach_q;
1347 for (i = 0; i < dma_linked_lch[chain_id].no_of_lchs_linked; i++) {
1348 dma_chan[channels[i]].next_linked_ch = -1;
1349 dma_chan[channels[i]].prev_linked_ch = -1;
1350 dma_chan[channels[i]].chain_id = -1;
1351 dma_chan[channels[i]].state = DMA_CH_NOTSTARTED;
1352 omap_free_dma(channels[i]);
1353 }
1354
1355 kfree(channels);
1356
1357 dma_linked_lch[chain_id].linked_dmach_q = NULL;
1358 dma_linked_lch[chain_id].chain_mode = -1;
1359 dma_linked_lch[chain_id].chain_state = -1;
97b7f715 1360
f8151e5c
AG		 1361 return (0);
1362}
1363EXPORT_SYMBOL(omap_free_dma_chain);
1364
1365/**
1366 * @brief omap_dma_chain_status - Check if the chain is in
1367 * active / inactive state.
1368 * @param chain_id
1369 *
1370 * @return - Success : OMAP_DMA_CHAIN_ACTIVE/OMAP_DMA_CHAIN_INACTIVE
1371 * Failure : -EINVAL
1372 */
1373int omap_dma_chain_status(int chain_id)
1374{
1375 /* Check for input params */
4d96372e 1376 if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
f8151e5c
AG		 1377 printk(KERN_ERR "Invalid chain id\n");
1378 return -EINVAL;
1379 }
1380
1381 /* Check if the chain exists */
1382 if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1383 printk(KERN_ERR "Chain doesn't exists\n");
1384 return -EINVAL;
1385 }
1386 pr_debug("CHAINID=%d, qcnt=%d\n", chain_id,
1387 dma_linked_lch[chain_id].q_count);
1388
1389 if (OMAP_DMA_CHAIN_QEMPTY(chain_id))
1390 return OMAP_DMA_CHAIN_INACTIVE;
97b7f715 1391
f8151e5c
AG		 1392 return OMAP_DMA_CHAIN_ACTIVE;
1393}
1394EXPORT_SYMBOL(omap_dma_chain_status);
1395
1396/**
1397 * @brief omap_dma_chain_a_transfer - Get a free channel from a chain,
1398 * set the params and start the transfer.
1399 *
1400 * @param chain_id
1401 * @param src_start - buffer start address
1402 * @param dest_start - Dest address
1403 * @param elem_count
1404 * @param frame_count
1405 * @param callbk_data - channel callback parameter data.
1406 *
f4b6a7ef 1407 * @return - Success : 0
f8151e5c
AG		 1408 * Failure: -EINVAL/-EBUSY
1409 */
1410int omap_dma_chain_a_transfer(int chain_id, int src_start, int dest_start,
1411 int elem_count, int frame_count, void *callbk_data)
1412{
1413 int *channels;
0499bdeb 1414 u32 l, lch;
f8151e5c
AG		 1415 int start_dma = 0;
1416
97b7f715
TL		 1417 /*
1418 * if buffer size is less than 1 then there is
1419 * no use of starting the chain
1420 */
f8151e5c
AG		 1421 if (elem_count < 1) {
1422 printk(KERN_ERR "Invalid buffer size\n");
1423 return -EINVAL;
1424 }
1425
1426 /* Check for input params */
1427 if (unlikely((chain_id < 0
4d96372e 1428 || chain_id >= dma_lch_count))) {
f8151e5c
AG		 1429 printk(KERN_ERR "Invalid chain id\n");
1430 return -EINVAL;
1431 }
1432
1433 /* Check if the chain exists */
1434 if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1435 printk(KERN_ERR "Chain doesn't exist\n");
1436 return -EINVAL;
1437 }
1438
1439 /* Check if all the channels in chain are in use */
1440 if (OMAP_DMA_CHAIN_QFULL(chain_id))
1441 return -EBUSY;
1442
1443 /* Frame count may be negative in case of indexed transfers */
1444 channels = dma_linked_lch[chain_id].linked_dmach_q;
1445
1446 /* Get a free channel */
1447 lch = channels[dma_linked_lch[chain_id].q_tail];
1448
1449 /* Store the callback data */
1450 dma_chan[lch].data = callbk_data;
1451
1452 /* Increment the q_tail */
1453 OMAP_DMA_CHAIN_INCQTAIL(chain_id);
1454
1455 /* Set the params to the free channel */
1456 if (src_start != 0)
0499bdeb 1457 dma_write(src_start, CSSA(lch));
f8151e5c 1458 if (dest_start != 0)
0499bdeb 1459 dma_write(dest_start, CDSA(lch));
f8151e5c
AG		 1460
1461 /* Write the buffer size */
0499bdeb
TL		 1462 dma_write(elem_count, CEN(lch));
1463 dma_write(frame_count, CFN(lch));
f8151e5c 1464
97b7f715
TL		 1465 /*
1466 * If the chain is dynamically linked,
1467 * then we may have to start the chain if its not active
1468 */
f8151e5c
AG		 1469 if (dma_linked_lch[chain_id].chain_mode == OMAP_DMA_DYNAMIC_CHAIN) {
1470
97b7f715
TL		 1471 /*
1472 * In Dynamic chain, if the chain is not started,
1473 * queue the channel
1474 */
f8151e5c
AG		 1475 if (dma_linked_lch[chain_id].chain_state ==
1476 DMA_CHAIN_NOTSTARTED) {
1477 /* Enable the link in previous channel */
1478 if (dma_chan[dma_chan[lch].prev_linked_ch].state ==
1479 DMA_CH_QUEUED)
1480 enable_lnk(dma_chan[lch].prev_linked_ch);
1481 dma_chan[lch].state = DMA_CH_QUEUED;
1482 }
1483
97b7f715
TL		 1484 /*
1485 * Chain is already started, make sure its active,
1486 * if not then start the chain
1487 */
f8151e5c
AG		 1488 else {
1489 start_dma = 1;
1490
1491 if (dma_chan[dma_chan[lch].prev_linked_ch].state ==
1492 DMA_CH_STARTED) {
1493 enable_lnk(dma_chan[lch].prev_linked_ch);
1494 dma_chan[lch].state = DMA_CH_QUEUED;
1495 start_dma = 0;
0499bdeb
TL		 1496 if (0 == ((1 << 7) & dma_read(
1497 CCR(dma_chan[lch].prev_linked_ch)))) {
f8151e5c
AG		 1498 disable_lnk(dma_chan[lch].
1499 prev_linked_ch);
1500 pr_debug("\n prev ch is stopped\n");
1501 start_dma = 1;
1502 }
1503 }
1504
1505 else if (dma_chan[dma_chan[lch].prev_linked_ch].state
1506 == DMA_CH_QUEUED) {
1507 enable_lnk(dma_chan[lch].prev_linked_ch);
1508 dma_chan[lch].state = DMA_CH_QUEUED;
1509 start_dma = 0;
1510 }
1511 omap_enable_channel_irq(lch);
1512
0499bdeb 1513 l = dma_read(CCR(lch));
f8151e5c 1514
0499bdeb
TL		 1515 if ((0 == (l & (1 << 24))))
1516 l &= ~(1 << 25);
f8151e5c 1517 else
0499bdeb 1518 l |= (1 << 25);
f8151e5c 1519 if (start_dma == 1) {
0499bdeb
TL		 1520 if (0 == (l & (1 << 7))) {
1521 l |= (1 << 7);
f8151e5c
AG		 1522 dma_chan[lch].state = DMA_CH_STARTED;
1523 pr_debug("starting %d\n", lch);
0499bdeb 1524 dma_write(l, CCR(lch));
f8151e5c
AG		 1525 } else
1526 start_dma = 0;
1527 } else {
0499bdeb
TL		 1528 if (0 == (l & (1 << 7)))
1529 dma_write(l, CCR(lch));
f8151e5c
AG		 1530 }
1531 dma_chan[lch].flags |= OMAP_DMA_ACTIVE;
1532 }
1533 }
97b7f715 1534
f4b6a7ef 1535 return 0;
f8151e5c
AG		 1536}
1537EXPORT_SYMBOL(omap_dma_chain_a_transfer);
1538
1539/**
1540 * @brief omap_start_dma_chain_transfers - Start the chain
1541 *
1542 * @param chain_id
1543 *
1544 * @return - Success : 0
1545 * Failure : -EINVAL/-EBUSY
1546 */
1547int omap_start_dma_chain_transfers(int chain_id)
1548{
1549 int *channels;
0499bdeb 1550 u32 l, i;
f8151e5c 1551
4d96372e 1552 if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
f8151e5c
AG		 1553 printk(KERN_ERR "Invalid chain id\n");
1554 return -EINVAL;
1555 }
1556
1557 channels = dma_linked_lch[chain_id].linked_dmach_q;
1558
1559 if (dma_linked_lch[channels[0]].chain_state == DMA_CHAIN_STARTED) {
1560 printk(KERN_ERR "Chain is already started\n");
1561 return -EBUSY;
1562 }
1563
1564 if (dma_linked_lch[chain_id].chain_mode == OMAP_DMA_STATIC_CHAIN) {
1565 for (i = 0; i < dma_linked_lch[chain_id].no_of_lchs_linked;
1566 i++) {
1567 enable_lnk(channels[i]);
1568 omap_enable_channel_irq(channels[i]);
1569 }
1570 } else {
1571 omap_enable_channel_irq(channels[0]);
1572 }
1573
0499bdeb
TL		 1574 l = dma_read(CCR(channels[0]));
1575 l |= (1 << 7);
f8151e5c
AG		 1576 dma_linked_lch[chain_id].chain_state = DMA_CHAIN_STARTED;
1577 dma_chan[channels[0]].state = DMA_CH_STARTED;
1578
0499bdeb
TL		 1579 if ((0 == (l & (1 << 24))))
1580 l &= ~(1 << 25);
f8151e5c 1581 else
0499bdeb
TL		 1582 l |= (1 << 25);
1583 dma_write(l, CCR(channels[0]));
f8151e5c
AG		 1584
1585 dma_chan[channels[0]].flags |= OMAP_DMA_ACTIVE;
97b7f715 1586
f8151e5c
AG		 1587 return 0;
1588}
1589EXPORT_SYMBOL(omap_start_dma_chain_transfers);
1590
1591/**
1592 * @brief omap_stop_dma_chain_transfers - Stop the dma transfer of a chain.
1593 *
1594 * @param chain_id
1595 *
1596 * @return - Success : 0
1597 * Failure : EINVAL
1598 */
1599int omap_stop_dma_chain_transfers(int chain_id)
1600{
1601 int *channels;
0499bdeb 1602 u32 l, i;
f8151e5c
AG		 1603 u32 sys_cf;
1604
1605 /* Check for input params */
4d96372e 1606 if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
f8151e5c
AG		 1607 printk(KERN_ERR "Invalid chain id\n");
1608 return -EINVAL;
1609 }
1610
1611 /* Check if the chain exists */
1612 if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1613 printk(KERN_ERR "Chain doesn't exists\n");
1614 return -EINVAL;
1615 }
1616 channels = dma_linked_lch[chain_id].linked_dmach_q;
1617
97b7f715
TL		 1618 /*
1619 * DMA Errata:
f8151e5c
AG		 1620 * Special programming model needed to disable DMA before end of block
1621 */
0499bdeb
TL		 1622 sys_cf = dma_read(OCP_SYSCONFIG);
1623 l = sys_cf;
f8151e5c 1624 /* Middle mode reg set no Standby */
0499bdeb
TL		 1625 l &= ~((1 << 12)|(1 << 13));
1626 dma_write(l, OCP_SYSCONFIG);
f8151e5c
AG		 1627
1628 for (i = 0; i < dma_linked_lch[chain_id].no_of_lchs_linked; i++) {
1629
1630 /* Stop the Channel transmission */
0499bdeb
TL		 1631 l = dma_read(CCR(channels[i]));
1632 l &= ~(1 << 7);
1633 dma_write(l, CCR(channels[i]));
f8151e5c
AG		 1634
1635 /* Disable the link in all the channels */
1636 disable_lnk(channels[i]);
1637 dma_chan[channels[i]].state = DMA_CH_NOTSTARTED;
1638
1639 }
1640 dma_linked_lch[chain_id].chain_state = DMA_CHAIN_NOTSTARTED;
1641
1642 /* Reset the Queue pointers */
1643 OMAP_DMA_CHAIN_QINIT(chain_id);
1644
1645 /* Errata - put in the old value */
0499bdeb 1646 dma_write(sys_cf, OCP_SYSCONFIG);
97b7f715 1647
f8151e5c
AG		 1648 return 0;
1649}
1650EXPORT_SYMBOL(omap_stop_dma_chain_transfers);
1651
1652/* Get the index of the ongoing DMA in chain */
1653/**
1654 * @brief omap_get_dma_chain_index - Get the element and frame index
1655 * of the ongoing DMA in chain
1656 *
1657 * @param chain_id
1658 * @param ei - Element index
1659 * @param fi - Frame index
1660 *
1661 * @return - Success : 0
1662 * Failure : -EINVAL
1663 */
1664int omap_get_dma_chain_index(int chain_id, int *ei, int *fi)
1665{
1666 int lch;
1667 int *channels;
1668
1669 /* Check for input params */
4d96372e 1670 if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
f8151e5c
AG		 1671 printk(KERN_ERR "Invalid chain id\n");
1672 return -EINVAL;
1673 }
1674
1675 /* Check if the chain exists */
1676 if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1677 printk(KERN_ERR "Chain doesn't exists\n");
1678 return -EINVAL;
1679 }
1680 if ((!ei) || (!fi))
1681 return -EINVAL;
1682
1683 channels = dma_linked_lch[chain_id].linked_dmach_q;
1684
1685 /* Get the current channel */
1686 lch = channels[dma_linked_lch[chain_id].q_head];
1687
0499bdeb
TL		 1688 *ei = dma_read(CCEN(lch));
1689 *fi = dma_read(CCFN(lch));
f8151e5c
AG		 1690
1691 return 0;
1692}
1693EXPORT_SYMBOL(omap_get_dma_chain_index);
1694
1695/**
1696 * @brief omap_get_dma_chain_dst_pos - Get the destination position of the
1697 * ongoing DMA in chain
1698 *
1699 * @param chain_id
1700 *
1701 * @return - Success : Destination position
1702 * Failure : -EINVAL
1703 */
1704int omap_get_dma_chain_dst_pos(int chain_id)
1705{
1706 int lch;
1707 int *channels;
1708
1709 /* Check for input params */
4d96372e 1710 if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
f8151e5c
AG		 1711 printk(KERN_ERR "Invalid chain id\n");
1712 return -EINVAL;
1713 }
1714
1715 /* Check if the chain exists */
1716 if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1717 printk(KERN_ERR "Chain doesn't exists\n");
1718 return -EINVAL;
1719 }
1720
1721 channels = dma_linked_lch[chain_id].linked_dmach_q;
1722
1723 /* Get the current channel */
1724 lch = channels[dma_linked_lch[chain_id].q_head];
1725
0499bdeb 1726 return dma_read(CDAC(lch));
f8151e5c
AG		 1727}
1728EXPORT_SYMBOL(omap_get_dma_chain_dst_pos);
1729
1730/**
1731 * @brief omap_get_dma_chain_src_pos - Get the source position
1732 * of the ongoing DMA in chain
1733 * @param chain_id
1734 *
1735 * @return - Success : Destination position
1736 * Failure : -EINVAL
1737 */
1738int omap_get_dma_chain_src_pos(int chain_id)
1739{
1740 int lch;
1741 int *channels;
1742
1743 /* Check for input params */
4d96372e 1744 if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
f8151e5c
AG		 1745 printk(KERN_ERR "Invalid chain id\n");
1746 return -EINVAL;
1747 }
1748
1749 /* Check if the chain exists */
1750 if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1751 printk(KERN_ERR "Chain doesn't exists\n");
1752 return -EINVAL;
1753 }
1754
1755 channels = dma_linked_lch[chain_id].linked_dmach_q;
1756
1757 /* Get the current channel */
1758 lch = channels[dma_linked_lch[chain_id].q_head];
1759
0499bdeb 1760 return dma_read(CSAC(lch));
f8151e5c
AG		 1761}
1762EXPORT_SYMBOL(omap_get_dma_chain_src_pos);
97b7f715 1763#endif /* ifndef CONFIG_ARCH_OMAP1 */
f8151e5c 1764
1a8bfa1e
TL		 1765/*----------------------------------------------------------------------------*/
1766
1767#ifdef CONFIG_ARCH_OMAP1
1768
1769static int omap1_dma_handle_ch(int ch)
1770{
0499bdeb 1771 u32 csr;
1a8bfa1e
TL		 1772
1773 if (enable_1510_mode && ch >= 6) {
1774 csr = dma_chan[ch].saved_csr;
1775 dma_chan[ch].saved_csr = 0;
1776 } else
0499bdeb 1777 csr = dma_read(CSR(ch));
1a8bfa1e
TL		 1778 if (enable_1510_mode && ch <= 2 && (csr >> 7) != 0) {
1779 dma_chan[ch + 6].saved_csr = csr >> 7;
1780 csr &= 0x7f;
1781 }
1782 if ((csr & 0x3f) == 0)
1783 return 0;
1784 if (unlikely(dma_chan[ch].dev_id == -1)) {
1785 printk(KERN_WARNING "Spurious interrupt from DMA channel "
1786 "%d (CSR %04x)\n", ch, csr);
1787 return 0;
1788 }
7ff879db 1789 if (unlikely(csr & OMAP1_DMA_TOUT_IRQ))
1a8bfa1e
TL		 1790 printk(KERN_WARNING "DMA timeout with device %d\n",
1791 dma_chan[ch].dev_id);
1792 if (unlikely(csr & OMAP_DMA_DROP_IRQ))
1793 printk(KERN_WARNING "DMA synchronization event drop occurred "
1794 "with device %d\n", dma_chan[ch].dev_id);
1795 if (likely(csr & OMAP_DMA_BLOCK_IRQ))
1796 dma_chan[ch].flags &= ~OMAP_DMA_ACTIVE;
1797 if (likely(dma_chan[ch].callback != NULL))
1798 dma_chan[ch].callback(ch, csr, dma_chan[ch].data);
97b7f715 1799
1a8bfa1e
TL		 1800 return 1;
1801}
1802
0cd61b68 1803static irqreturn_t omap1_dma_irq_handler(int irq, void *dev_id)
1a8bfa1e
TL		 1804{
1805 int ch = ((int) dev_id) - 1;
1806 int handled = 0;
1807
1808 for (;;) {
1809 int handled_now = 0;
1810
1811 handled_now += omap1_dma_handle_ch(ch);
1812 if (enable_1510_mode && dma_chan[ch + 6].saved_csr)
1813 handled_now += omap1_dma_handle_ch(ch + 6);
1814 if (!handled_now)
1815 break;
1816 handled += handled_now;
1817 }
1818
1819 return handled ? IRQ_HANDLED : IRQ_NONE;
1820}
1821
1822#else
1823#define omap1_dma_irq_handler NULL
1824#endif
1825
f8151e5c 1826#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
1a8bfa1e
TL		 1827
1828static int omap2_dma_handle_ch(int ch)
1829{
0499bdeb 1830 u32 status = dma_read(CSR(ch));
1a8bfa1e 1831
3151369d
JY		 1832 if (!status) {
1833 if (printk_ratelimit())
97b7f715
TL		 1834 printk(KERN_WARNING "Spurious DMA IRQ for lch %d\n",
1835 ch);
0499bdeb 1836 dma_write(1 << ch, IRQSTATUS_L0);
1a8bfa1e 1837 return 0;
3151369d
JY		 1838 }
1839 if (unlikely(dma_chan[ch].dev_id == -1)) {
1840 if (printk_ratelimit())
1841 printk(KERN_WARNING "IRQ %04x for non-allocated DMA"
1842 "channel %d\n", status, ch);
1a8bfa1e 1843 return 0;
3151369d 1844 }
1a8bfa1e
TL		 1845 if (unlikely(status & OMAP_DMA_DROP_IRQ))
1846 printk(KERN_INFO
1847 "DMA synchronization event drop occurred with device "
1848 "%d\n", dma_chan[ch].dev_id);
a50f18c7 1849 if (unlikely(status & OMAP2_DMA_TRANS_ERR_IRQ)) {
1a8bfa1e
TL		 1850 printk(KERN_INFO "DMA transaction error with device %d\n",
1851 dma_chan[ch].dev_id);
a50f18c7
SS		 1852 if (cpu_class_is_omap2()) {
1853 /* Errata: sDMA Channel is not disabled
1854 * after a transaction error. So we explicitely
1855 * disable the channel
1856 */
1857 u32 ccr;
1858
1859 ccr = dma_read(CCR(ch));
1860 ccr &= ~OMAP_DMA_CCR_EN;
1861 dma_write(ccr, CCR(ch));
1862 dma_chan[ch].flags &= ~OMAP_DMA_ACTIVE;
1863 }
1864 }
7ff879db
TL		 1865 if (unlikely(status & OMAP2_DMA_SECURE_ERR_IRQ))
1866 printk(KERN_INFO "DMA secure error with device %d\n",
1867 dma_chan[ch].dev_id);
1868 if (unlikely(status & OMAP2_DMA_MISALIGNED_ERR_IRQ))
1869 printk(KERN_INFO "DMA misaligned error with device %d\n",
1870 dma_chan[ch].dev_id);
1a8bfa1e 1871
0499bdeb
TL		 1872 dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR(ch));
1873 dma_write(1 << ch, IRQSTATUS_L0);
1a8bfa1e 1874
f8151e5c
AG		 1875 /* If the ch is not chained then chain_id will be -1 */
1876 if (dma_chan[ch].chain_id != -1) {
1877 int chain_id = dma_chan[ch].chain_id;
1878 dma_chan[ch].state = DMA_CH_NOTSTARTED;
0499bdeb 1879 if (dma_read(CLNK_CTRL(ch)) & (1 << 15))
f8151e5c
AG		 1880 dma_chan[dma_chan[ch].next_linked_ch].state =
1881 DMA_CH_STARTED;
1882 if (dma_linked_lch[chain_id].chain_mode ==
1883 OMAP_DMA_DYNAMIC_CHAIN)
1884 disable_lnk(ch);
1885
1886 if (!OMAP_DMA_CHAIN_QEMPTY(chain_id))
1887 OMAP_DMA_CHAIN_INCQHEAD(chain_id);
1888
0499bdeb 1889 status = dma_read(CSR(ch));
f8151e5c
AG		 1890 }
1891
320ce6f6
JY		 1892 dma_write(status, CSR(ch));
1893
538528de
JN		 1894 if (likely(dma_chan[ch].callback != NULL))
1895 dma_chan[ch].callback(ch, status, dma_chan[ch].data);
f8151e5c 1896
1a8bfa1e
TL		 1897 return 0;
1898}
1899
1900/* STATUS register count is from 1-32 while our is 0-31 */
0cd61b68 1901static irqreturn_t omap2_dma_irq_handler(int irq, void *dev_id)
1a8bfa1e
TL		 1902{
1903 u32 val;
1904 int i;
1905
0499bdeb 1906 val = dma_read(IRQSTATUS_L0);
3151369d
JY		 1907 if (val == 0) {
1908 if (printk_ratelimit())
1909 printk(KERN_WARNING "Spurious DMA IRQ\n");
1910 return IRQ_HANDLED;
1911 }
4d96372e 1912 for (i = 0; i < dma_lch_count && val != 0; i++) {
3151369d
JY		 1913 if (val & 1)
1914 omap2_dma_handle_ch(i);
1915 val >>= 1;
1a8bfa1e
TL		 1916 }
1917
1918 return IRQ_HANDLED;
1919}
1920
1921static struct irqaction omap24xx_dma_irq = {
1922 .name = "DMA",
1923 .handler = omap2_dma_irq_handler,
52e405ea 1924 .flags = IRQF_DISABLED
1a8bfa1e
TL		 1925};
1926
1927#else
1928static struct irqaction omap24xx_dma_irq;
1929#endif
1930
1931/*----------------------------------------------------------------------------*/
5e1c5ff4
TL		 1932
1933static struct lcd_dma_info {
1934 spinlock_t lock;
1935 int reserved;
97b7f715 1936 void (*callback)(u16 status, void *data);
5e1c5ff4
TL		 1937 void *cb_data;
1938
1939 int active;
1940 unsigned long addr, size;
1941 int rotate, data_type, xres, yres;
1942 int vxres;
1943 int mirror;
1944 int xscale, yscale;
1945 int ext_ctrl;
1946 int src_port;
1947 int single_transfer;
1948} lcd_dma;
1949
1950void omap_set_lcd_dma_b1(unsigned long addr, u16 fb_xres, u16 fb_yres,
1951 int data_type)
1952{
1953 lcd_dma.addr = addr;
1954 lcd_dma.data_type = data_type;
1955 lcd_dma.xres = fb_xres;
1956 lcd_dma.yres = fb_yres;
1957}
97b7f715 1958EXPORT_SYMBOL(omap_set_lcd_dma_b1);
5e1c5ff4
TL		 1959
1960void omap_set_lcd_dma_src_port(int port)
1961{
1962 lcd_dma.src_port = port;
1963}
1964
1965void omap_set_lcd_dma_ext_controller(int external)
1966{
1967 lcd_dma.ext_ctrl = external;
1968}
97b7f715 1969EXPORT_SYMBOL(omap_set_lcd_dma_ext_controller);
5e1c5ff4
TL		 1970
1971void omap_set_lcd_dma_single_transfer(int single)
1972{
1973 lcd_dma.single_transfer = single;
1974}
97b7f715 1975EXPORT_SYMBOL(omap_set_lcd_dma_single_transfer);
5e1c5ff4
TL		 1976
1977void omap_set_lcd_dma_b1_rotation(int rotate)
1978{
1979 if (omap_dma_in_1510_mode()) {
1980 printk(KERN_ERR "DMA rotation is not supported in 1510 mode\n");
1981 BUG();
1982 return;
1983 }
1984 lcd_dma.rotate = rotate;
1985}
97b7f715 1986EXPORT_SYMBOL(omap_set_lcd_dma_b1_rotation);
5e1c5ff4
TL		 1987
1988void omap_set_lcd_dma_b1_mirror(int mirror)
1989{
1990 if (omap_dma_in_1510_mode()) {
1991 printk(KERN_ERR "DMA mirror is not supported in 1510 mode\n");
1992 BUG();
1993 }
1994 lcd_dma.mirror = mirror;
1995}
97b7f715 1996EXPORT_SYMBOL(omap_set_lcd_dma_b1_mirror);
5e1c5ff4
TL		 1997
1998void omap_set_lcd_dma_b1_vxres(unsigned long vxres)
1999{
2000 if (omap_dma_in_1510_mode()) {
2001 printk(KERN_ERR "DMA virtual resulotion is not supported "
2002 "in 1510 mode\n");
2003 BUG();
2004 }
2005 lcd_dma.vxres = vxres;
2006}
97b7f715 2007EXPORT_SYMBOL(omap_set_lcd_dma_b1_vxres);
5e1c5ff4
TL		 2008
2009void omap_set_lcd_dma_b1_scale(unsigned int xscale, unsigned int yscale)
2010{
2011 if (omap_dma_in_1510_mode()) {
2012 printk(KERN_ERR "DMA scale is not supported in 1510 mode\n");
2013 BUG();
2014 }
2015 lcd_dma.xscale = xscale;
2016 lcd_dma.yscale = yscale;
2017}
97b7f715 2018EXPORT_SYMBOL(omap_set_lcd_dma_b1_scale);
5e1c5ff4
TL		 2019
2020static void set_b1_regs(void)
2021{
2022 unsigned long top, bottom;
2023 int es;
2024 u16 w;
2025 unsigned long en, fn;
2026 long ei, fi;
2027 unsigned long vxres;
2028 unsigned int xscale, yscale;
2029
2030 switch (lcd_dma.data_type) {
2031 case OMAP_DMA_DATA_TYPE_S8:
2032 es = 1;
2033 break;
2034 case OMAP_DMA_DATA_TYPE_S16:
2035 es = 2;
2036 break;
2037 case OMAP_DMA_DATA_TYPE_S32:
2038 es = 4;
2039 break;
2040 default:
2041 BUG();
2042 return;
2043 }
2044
2045 vxres = lcd_dma.vxres ? lcd_dma.vxres : lcd_dma.xres;
2046 xscale = lcd_dma.xscale ? lcd_dma.xscale : 1;
2047 yscale = lcd_dma.yscale ? lcd_dma.yscale : 1;
2048 BUG_ON(vxres < lcd_dma.xres);
97b7f715
TL		 2049
2050#define PIXADDR(x, y) (lcd_dma.addr + \
2051 ((y) * vxres * yscale + (x) * xscale) * es)
5e1c5ff4 2052#define PIXSTEP(sx, sy, dx, dy) (PIXADDR(dx, dy) - PIXADDR(sx, sy) - es + 1)
97b7f715 2053
5e1c5ff4
TL		 2054 switch (lcd_dma.rotate) {
2055 case 0:
2056 if (!lcd_dma.mirror) {
2057 top = PIXADDR(0, 0);
2058 bottom = PIXADDR(lcd_dma.xres - 1, lcd_dma.yres - 1);
2059 /* 1510 DMA requires the bottom address to be 2 more
2060 * than the actual last memory access location. */
2061 if (omap_dma_in_1510_mode() &&
97b7f715
TL		 2062 lcd_dma.data_type == OMAP_DMA_DATA_TYPE_S32)
2063 bottom += 2;
5e1c5ff4
TL		 2064 ei = PIXSTEP(0, 0, 1, 0);
2065 fi = PIXSTEP(lcd_dma.xres - 1, 0, 0, 1);
2066 } else {
2067 top = PIXADDR(lcd_dma.xres - 1, 0);
2068 bottom = PIXADDR(0, lcd_dma.yres - 1);
2069 ei = PIXSTEP(1, 0, 0, 0);
2070 fi = PIXSTEP(0, 0, lcd_dma.xres - 1, 1);
2071 }
2072 en = lcd_dma.xres;
2073 fn = lcd_dma.yres;
2074 break;
2075 case 90:
2076 if (!lcd_dma.mirror) {
2077 top = PIXADDR(0, lcd_dma.yres - 1);
2078 bottom = PIXADDR(lcd_dma.xres - 1, 0);
2079 ei = PIXSTEP(0, 1, 0, 0);
2080 fi = PIXSTEP(0, 0, 1, lcd_dma.yres - 1);
2081 } else {
2082 top = PIXADDR(lcd_dma.xres - 1, lcd_dma.yres - 1);
2083 bottom = PIXADDR(0, 0);
2084 ei = PIXSTEP(0, 1, 0, 0);
2085 fi = PIXSTEP(1, 0, 0, lcd_dma.yres - 1);
2086 }
2087 en = lcd_dma.yres;
2088 fn = lcd_dma.xres;
2089 break;
2090 case 180:
2091 if (!lcd_dma.mirror) {
2092 top = PIXADDR(lcd_dma.xres - 1, lcd_dma.yres - 1);
2093 bottom = PIXADDR(0, 0);
2094 ei = PIXSTEP(1, 0, 0, 0);
2095 fi = PIXSTEP(0, 1, lcd_dma.xres - 1, 0);
2096 } else {
2097 top = PIXADDR(0, lcd_dma.yres - 1);
2098 bottom = PIXADDR(lcd_dma.xres - 1, 0);
2099 ei = PIXSTEP(0, 0, 1, 0);
2100 fi = PIXSTEP(lcd_dma.xres - 1, 1, 0, 0);
2101 }
2102 en = lcd_dma.xres;
2103 fn = lcd_dma.yres;
2104 break;
2105 case 270:
2106 if (!lcd_dma.mirror) {
2107 top = PIXADDR(lcd_dma.xres - 1, 0);
2108 bottom = PIXADDR(0, lcd_dma.yres - 1);
2109 ei = PIXSTEP(0, 0, 0, 1);
2110 fi = PIXSTEP(1, lcd_dma.yres - 1, 0, 0);
2111 } else {
2112 top = PIXADDR(0, 0);
2113 bottom = PIXADDR(lcd_dma.xres - 1, lcd_dma.yres - 1);
2114 ei = PIXSTEP(0, 0, 0, 1);
2115 fi = PIXSTEP(0, lcd_dma.yres - 1, 1, 0);
2116 }
2117 en = lcd_dma.yres;
2118 fn = lcd_dma.xres;
2119 break;
2120 default:
2121 BUG();
6cbdc8c5 2122 return; /* Suppress warning about uninitialized vars */
5e1c5ff4
TL		 2123 }
2124
2125 if (omap_dma_in_1510_mode()) {
2126 omap_writew(top >> 16, OMAP1510_DMA_LCD_TOP_F1_U);
2127 omap_writew(top, OMAP1510_DMA_LCD_TOP_F1_L);
2128 omap_writew(bottom >> 16, OMAP1510_DMA_LCD_BOT_F1_U);
2129 omap_writew(bottom, OMAP1510_DMA_LCD_BOT_F1_L);
2130
2131 return;
2132 }
2133
2134 /* 1610 regs */
2135 omap_writew(top >> 16, OMAP1610_DMA_LCD_TOP_B1_U);
2136 omap_writew(top, OMAP1610_DMA_LCD_TOP_B1_L);
2137 omap_writew(bottom >> 16, OMAP1610_DMA_LCD_BOT_B1_U);
2138 omap_writew(bottom, OMAP1610_DMA_LCD_BOT_B1_L);
2139
2140 omap_writew(en, OMAP1610_DMA_LCD_SRC_EN_B1);
2141 omap_writew(fn, OMAP1610_DMA_LCD_SRC_FN_B1);
2142
2143 w = omap_readw(OMAP1610_DMA_LCD_CSDP);
2144 w &= ~0x03;
2145 w |= lcd_dma.data_type;
2146 omap_writew(w, OMAP1610_DMA_LCD_CSDP);
2147
2148 w = omap_readw(OMAP1610_DMA_LCD_CTRL);
2149 /* Always set the source port as SDRAM for now*/
2150 w &= ~(0x03 << 6);
5e1c5ff4 2151 if (lcd_dma.callback != NULL)
1a8bfa1e 2152 w |= 1 << 1; /* Block interrupt enable */
5e1c5ff4
TL		 2153 else
2154 w &= ~(1 << 1);
2155 omap_writew(w, OMAP1610_DMA_LCD_CTRL);
2156
2157 if (!(lcd_dma.rotate || lcd_dma.mirror ||
2158 lcd_dma.vxres || lcd_dma.xscale || lcd_dma.yscale))
2159 return;
2160
2161 w = omap_readw(OMAP1610_DMA_LCD_CCR);
2162 /* Set the double-indexed addressing mode */
2163 w |= (0x03 << 12);
2164 omap_writew(w, OMAP1610_DMA_LCD_CCR);
2165
2166 omap_writew(ei, OMAP1610_DMA_LCD_SRC_EI_B1);
2167 omap_writew(fi >> 16, OMAP1610_DMA_LCD_SRC_FI_B1_U);
2168 omap_writew(fi, OMAP1610_DMA_LCD_SRC_FI_B1_L);
2169}
2170
0cd61b68 2171static irqreturn_t lcd_dma_irq_handler(int irq, void *dev_id)
5e1c5ff4
TL		 2172{
2173 u16 w;
2174
2175 w = omap_readw(OMAP1610_DMA_LCD_CTRL);
2176 if (unlikely(!(w & (1 << 3)))) {
2177 printk(KERN_WARNING "Spurious LCD DMA IRQ\n");
2178 return IRQ_NONE;
2179 }
2180 /* Ack the IRQ */
2181 w |= (1 << 3);
2182 omap_writew(w, OMAP1610_DMA_LCD_CTRL);
2183 lcd_dma.active = 0;
2184 if (lcd_dma.callback != NULL)
2185 lcd_dma.callback(w, lcd_dma.cb_data);
2186
2187 return IRQ_HANDLED;
2188}
2189
97b7f715 2190int omap_request_lcd_dma(void (*callback)(u16 status, void *data),
5e1c5ff4
TL		 2191 void *data)
2192{
2193 spin_lock_irq(&lcd_dma.lock);
2194 if (lcd_dma.reserved) {
2195 spin_unlock_irq(&lcd_dma.lock);
2196 printk(KERN_ERR "LCD DMA channel already reserved\n");
2197 BUG();
2198 return -EBUSY;
2199 }
2200 lcd_dma.reserved = 1;
2201 spin_unlock_irq(&lcd_dma.lock);
2202 lcd_dma.callback = callback;
2203 lcd_dma.cb_data = data;
2204 lcd_dma.active = 0;
2205 lcd_dma.single_transfer = 0;
2206 lcd_dma.rotate = 0;
2207 lcd_dma.vxres = 0;
2208 lcd_dma.mirror = 0;
2209 lcd_dma.xscale = 0;
2210 lcd_dma.yscale = 0;
2211 lcd_dma.ext_ctrl = 0;
2212 lcd_dma.src_port = 0;
2213
2214 return 0;
2215}
97b7f715 2216EXPORT_SYMBOL(omap_request_lcd_dma);
5e1c5ff4
TL		 2217
2218void omap_free_lcd_dma(void)
2219{
2220 spin_lock(&lcd_dma.lock);
2221 if (!lcd_dma.reserved) {
2222 spin_unlock(&lcd_dma.lock);
2223 printk(KERN_ERR "LCD DMA is not reserved\n");
2224 BUG();
2225 return;
2226 }
2227 if (!enable_1510_mode)
1a8bfa1e
TL		 2228 omap_writew(omap_readw(OMAP1610_DMA_LCD_CCR) & ~1,
2229 OMAP1610_DMA_LCD_CCR);
5e1c5ff4
TL		 2230 lcd_dma.reserved = 0;
2231 spin_unlock(&lcd_dma.lock);
2232}
97b7f715 2233EXPORT_SYMBOL(omap_free_lcd_dma);
5e1c5ff4
TL		 2234
2235void omap_enable_lcd_dma(void)
2236{
2237 u16 w;
2238
97b7f715
TL		 2239 /*
2240 * Set the Enable bit only if an external controller is
5e1c5ff4
TL		 2241 * connected. Otherwise the OMAP internal controller will
2242 * start the transfer when it gets enabled.
2243 */
2244 if (enable_1510_mode || !lcd_dma.ext_ctrl)
2245 return;
bb13b5fd
TL		 2246
2247 w = omap_readw(OMAP1610_DMA_LCD_CTRL);
2248 w |= 1 << 8;
2249 omap_writew(w, OMAP1610_DMA_LCD_CTRL);
2250
92105bb7
TL		 2251 lcd_dma.active = 1;
2252
5e1c5ff4
TL		 2253 w = omap_readw(OMAP1610_DMA_LCD_CCR);
2254 w |= 1 << 7;
2255 omap_writew(w, OMAP1610_DMA_LCD_CCR);
5e1c5ff4 2256}
97b7f715 2257EXPORT_SYMBOL(omap_enable_lcd_dma);
5e1c5ff4
TL		 2258
2259void omap_setup_lcd_dma(void)
2260{
2261 BUG_ON(lcd_dma.active);
2262 if (!enable_1510_mode) {
2263 /* Set some reasonable defaults */
2264 omap_writew(0x5440, OMAP1610_DMA_LCD_CCR);
2265 omap_writew(0x9102, OMAP1610_DMA_LCD_CSDP);
2266 omap_writew(0x0004, OMAP1610_DMA_LCD_LCH_CTRL);
2267 }
2268 set_b1_regs();
2269 if (!enable_1510_mode) {
2270 u16 w;
2271
2272 w = omap_readw(OMAP1610_DMA_LCD_CCR);
97b7f715
TL		 2273 /*
2274 * If DMA was already active set the end_prog bit to have
5e1c5ff4
TL		 2275 * the programmed register set loaded into the active
2276 * register set.
2277 */
2278 w |= 1 << 11; /* End_prog */
2279 if (!lcd_dma.single_transfer)
97b7f715 2280 w |= (3 << 8); /* Auto_init, repeat */
5e1c5ff4
TL		 2281 omap_writew(w, OMAP1610_DMA_LCD_CCR);
2282 }
2283}
97b7f715 2284EXPORT_SYMBOL(omap_setup_lcd_dma);
5e1c5ff4
TL		 2285
2286void omap_stop_lcd_dma(void)
2287{
bb13b5fd
TL		 2288 u16 w;
2289
5e1c5ff4 2290 lcd_dma.active = 0;
bb13b5fd
TL		 2291 if (enable_1510_mode || !lcd_dma.ext_ctrl)
2292 return;
2293
2294 w = omap_readw(OMAP1610_DMA_LCD_CCR);
2295 w &= ~(1 << 7);
2296 omap_writew(w, OMAP1610_DMA_LCD_CCR);
2297
2298 w = omap_readw(OMAP1610_DMA_LCD_CTRL);
2299 w &= ~(1 << 8);
2300 omap_writew(w, OMAP1610_DMA_LCD_CTRL);
5e1c5ff4 2301}
97b7f715 2302EXPORT_SYMBOL(omap_stop_lcd_dma);
5e1c5ff4 2303
1a8bfa1e 2304/*----------------------------------------------------------------------------*/
bb13b5fd 2305
5e1c5ff4
TL		 2306static int __init omap_init_dma(void)
2307{
2308 int ch, r;
2309
0499bdeb 2310 if (cpu_class_is_omap1()) {
e8a91c95 2311 omap_dma_base = IO_ADDRESS(OMAP1_DMA_BASE);
4d96372e 2312 dma_lch_count = OMAP1_LOGICAL_DMA_CH_COUNT;
0499bdeb 2313 } else if (cpu_is_omap24xx()) {
e8a91c95 2314 omap_dma_base = IO_ADDRESS(OMAP24XX_DMA4_BASE);
4d96372e 2315 dma_lch_count = OMAP_DMA4_LOGICAL_DMA_CH_COUNT;
0499bdeb 2316 } else if (cpu_is_omap34xx()) {
e8a91c95 2317 omap_dma_base = IO_ADDRESS(OMAP34XX_DMA4_BASE);
0499bdeb
TL		 2318 dma_lch_count = OMAP_DMA4_LOGICAL_DMA_CH_COUNT;
2319 } else {
2320 pr_err("DMA init failed for unsupported omap\n");
2321 return -ENODEV;
2322 }
4d96372e
TL		 2323
2324 dma_chan = kzalloc(sizeof(struct omap_dma_lch) * dma_lch_count,
2325 GFP_KERNEL);
2326 if (!dma_chan)
2327 return -ENOMEM;
2328
2329 if (cpu_class_is_omap2()) {
2330 dma_linked_lch = kzalloc(sizeof(struct dma_link_info) *
2331 dma_lch_count, GFP_KERNEL);
2332 if (!dma_linked_lch) {
2333 kfree(dma_chan);
2334 return -ENOMEM;
2335 }
2336 }
2337
1a8bfa1e
TL		 2338 if (cpu_is_omap15xx()) {
2339 printk(KERN_INFO "DMA support for OMAP15xx initialized\n");
5e1c5ff4
TL		 2340 dma_chan_count = 9;
2341 enable_1510_mode = 1;
2342 } else if (cpu_is_omap16xx() || cpu_is_omap730()) {
2343 printk(KERN_INFO "OMAP DMA hardware version %d\n",
0499bdeb 2344 dma_read(HW_ID));
5e1c5ff4 2345 printk(KERN_INFO "DMA capabilities: %08x:%08x:%04x:%04x:%04x\n",
0499bdeb
TL		 2346 (dma_read(CAPS_0_U) << 16) |
2347 dma_read(CAPS_0_L),
2348 (dma_read(CAPS_1_U) << 16) |
2349 dma_read(CAPS_1_L),
2350 dma_read(CAPS_2), dma_read(CAPS_3),
2351 dma_read(CAPS_4));
5e1c5ff4
TL		 2352 if (!enable_1510_mode) {
2353 u16 w;
2354
2355 /* Disable OMAP 3.0/3.1 compatibility mode. */
0499bdeb 2356 w = dma_read(GSCR);
5e1c5ff4 2357 w |= 1 << 3;
0499bdeb 2358 dma_write(w, GSCR);
5e1c5ff4
TL		 2359 dma_chan_count = 16;
2360 } else
2361 dma_chan_count = 9;
b5beef5d
ID		 2362 if (cpu_is_omap16xx()) {
2363 u16 w;
2364
2365 /* this would prevent OMAP sleep */
2366 w = omap_readw(OMAP1610_DMA_LCD_CTRL);
2367 w &= ~(1 << 8);
2368 omap_writew(w, OMAP1610_DMA_LCD_CTRL);
2369 }
f8151e5c 2370 } else if (cpu_class_is_omap2()) {
0499bdeb 2371 u8 revision = dma_read(REVISION) & 0xff;
1a8bfa1e
TL		 2372 printk(KERN_INFO "OMAP DMA hardware revision %d.%d\n",
2373 revision >> 4, revision & 0xf);
4d96372e 2374 dma_chan_count = OMAP_DMA4_LOGICAL_DMA_CH_COUNT;
5e1c5ff4
TL		 2375 } else {
2376 dma_chan_count = 0;
2377 return 0;
2378 }
2379
5e1c5ff4
TL		 2380 spin_lock_init(&lcd_dma.lock);
2381 spin_lock_init(&dma_chan_lock);
5e1c5ff4
TL		 2382
2383 for (ch = 0; ch < dma_chan_count; ch++) {
1a8bfa1e 2384 omap_clear_dma(ch);
5e1c5ff4
TL		 2385 dma_chan[ch].dev_id = -1;
2386 dma_chan[ch].next_lch = -1;
2387
2388 if (ch >= 6 && enable_1510_mode)
2389 continue;
2390
1a8bfa1e 2391 if (cpu_class_is_omap1()) {
97b7f715
TL		 2392 /*
2393 * request_irq() doesn't like dev_id (ie. ch) being
2394 * zero, so we have to kludge around this.
2395 */
1a8bfa1e
TL		 2396 r = request_irq(omap1_dma_irq[ch],
2397 omap1_dma_irq_handler, 0, "DMA",
2398 (void *) (ch + 1));
2399 if (r != 0) {
2400 int i;
2401
2402 printk(KERN_ERR "unable to request IRQ %d "
2403 "for DMA (error %d)\n",
2404 omap1_dma_irq[ch], r);
2405 for (i = 0; i < ch; i++)
2406 free_irq(omap1_dma_irq[i],
2407 (void *) (i + 1));
2408 return r;
2409 }
2410 }
2411 }
2412
f8151e5c
AG		 2413 if (cpu_is_omap2430() || cpu_is_omap34xx())
2414 omap_dma_set_global_params(DMA_DEFAULT_ARB_RATE,
2415 DMA_DEFAULT_FIFO_DEPTH, 0);
2416
2417 if (cpu_class_is_omap2())
1a8bfa1e
TL		 2418 setup_irq(INT_24XX_SDMA_IRQ0, &omap24xx_dma_irq);
2419
2420 /* FIXME: Update LCD DMA to work on 24xx */
2421 if (cpu_class_is_omap1()) {
2422 r = request_irq(INT_DMA_LCD, lcd_dma_irq_handler, 0,
2423 "LCD DMA", NULL);
5e1c5ff4
TL		 2424 if (r != 0) {
2425 int i;
2426
1a8bfa1e
TL		 2427 printk(KERN_ERR "unable to request IRQ for LCD DMA "
2428 "(error %d)\n", r);
2429 for (i = 0; i < dma_chan_count; i++)
2430 free_irq(omap1_dma_irq[i], (void *) (i + 1));
5e1c5ff4
TL		 2431 return r;
2432 }
2433 }
5e1c5ff4 2434
5e1c5ff4
TL		 2435 return 0;
2436}
2437
2438arch_initcall(omap_init_dma);
2439
5e1c5ff4 2440
Linux 6.x block layer and io_uring tree(s)