Commit | Line | Data |
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5e1c5ff4 TL |
1 | /* |
2 | * linux/arch/arm/plat-omap/dma.c | |
3 | * | |
97b7f715 | 4 | * Copyright (C) 2003 - 2008 Nokia Corporation |
96de0e25 | 5 | * Author: Juha Yrjölä <juha.yrjola@nokia.com> |
5e1c5ff4 TL |
6 | * DMA channel linking for 1610 by Samuel Ortiz <samuel.ortiz@nokia.com> |
7 | * Graphics DMA and LCD DMA graphics tranformations | |
8 | * by Imre Deak <imre.deak@nokia.com> | |
f8151e5c | 9 | * OMAP2/3 support Copyright (C) 2004-2007 Texas Instruments, Inc. |
1a8bfa1e | 10 | * Merged to support both OMAP1 and OMAP2 by Tony Lindgren <tony@atomide.com> |
5e1c5ff4 TL |
11 | * Some functions based on earlier dma-omap.c Copyright (C) 2001 RidgeRun, Inc. |
12 | * | |
44169075 SS |
13 | * Copyright (C) 2009 Texas Instruments |
14 | * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com> | |
15 | * | |
5e1c5ff4 TL |
16 | * Support functions for the OMAP internal DMA channels. |
17 | * | |
f31cc962 MK |
18 | * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/ |
19 | * Converted DMA library into DMA platform driver. | |
20 | * - G, Manjunath Kondaiah <manjugk@ti.com> | |
21 | * | |
5e1c5ff4 TL |
22 | * This program is free software; you can redistribute it and/or modify |
23 | * it under the terms of the GNU General Public License version 2 as | |
24 | * published by the Free Software Foundation. | |
25 | * | |
26 | */ | |
27 | ||
28 | #include <linux/module.h> | |
29 | #include <linux/init.h> | |
30 | #include <linux/sched.h> | |
31 | #include <linux/spinlock.h> | |
32 | #include <linux/errno.h> | |
33 | #include <linux/interrupt.h> | |
418ca1f0 | 34 | #include <linux/irq.h> |
97b7f715 | 35 | #include <linux/io.h> |
5a0e3ad6 | 36 | #include <linux/slab.h> |
0e4905c0 | 37 | #include <linux/delay.h> |
5e1c5ff4 | 38 | |
45c3eb7d | 39 | #include <linux/omap-dma.h> |
5e1c5ff4 | 40 | |
685e2d08 TL |
41 | #ifdef CONFIG_ARCH_OMAP1 |
42 | #include <mach/soc.h> | |
43 | #endif | |
44 | ||
bc4d8b5f PW |
45 | /* |
46 | * MAX_LOGICAL_DMA_CH_COUNT: the maximum number of logical DMA | |
47 | * channels that an instance of the SDMA IP block can support. Used | |
48 | * to size arrays. (The actual maximum on a particular SoC may be less | |
49 | * than this -- for example, OMAP1 SDMA instances only support 17 logical | |
50 | * DMA channels.) | |
51 | */ | |
52 | #define MAX_LOGICAL_DMA_CH_COUNT 32 | |
53 | ||
f8151e5c AG |
54 | #undef DEBUG |
55 | ||
56 | #ifndef CONFIG_ARCH_OMAP1 | |
57 | enum { DMA_CH_ALLOC_DONE, DMA_CH_PARAMS_SET_DONE, DMA_CH_STARTED, | |
58 | DMA_CH_QUEUED, DMA_CH_NOTSTARTED, DMA_CH_PAUSED, DMA_CH_LINK_ENABLED | |
59 | }; | |
60 | ||
61 | enum { DMA_CHAIN_STARTED, DMA_CHAIN_NOTSTARTED }; | |
1a8bfa1e | 62 | #endif |
5e1c5ff4 | 63 | |
97b7f715 | 64 | #define OMAP_DMA_ACTIVE 0x01 |
4fb699b4 | 65 | #define OMAP2_DMA_CSR_CLEAR_MASK 0xffffffff |
5e1c5ff4 | 66 | |
97b7f715 | 67 | #define OMAP_FUNC_MUX_ARM_BASE (0xfffe1000 + 0xec) |
5e1c5ff4 | 68 | |
f31cc962 MK |
69 | static struct omap_system_dma_plat_info *p; |
70 | static struct omap_dma_dev_attr *d; | |
175655bd TL |
71 | static void omap_clear_dma(int lch); |
72 | static int omap_dma_set_prio_lch(int lch, unsigned char read_prio, | |
73 | unsigned char write_prio); | |
97b7f715 | 74 | static int enable_1510_mode; |
d3c9be2f | 75 | static u32 errata; |
5e1c5ff4 | 76 | |
f2d11858 TK |
77 | static struct omap_dma_global_context_registers { |
78 | u32 dma_irqenable_l0; | |
9ce2482f | 79 | u32 dma_irqenable_l1; |
f2d11858 TK |
80 | u32 dma_ocp_sysconfig; |
81 | u32 dma_gcr; | |
82 | } omap_dma_global_context; | |
83 | ||
f8151e5c AG |
84 | struct dma_link_info { |
85 | int *linked_dmach_q; | |
86 | int no_of_lchs_linked; | |
87 | ||
88 | int q_count; | |
89 | int q_tail; | |
90 | int q_head; | |
91 | ||
92 | int chain_state; | |
93 | int chain_mode; | |
94 | ||
95 | }; | |
96 | ||
4d96372e TL |
97 | static struct dma_link_info *dma_linked_lch; |
98 | ||
99 | #ifndef CONFIG_ARCH_OMAP1 | |
f8151e5c AG |
100 | |
101 | /* Chain handling macros */ | |
102 | #define OMAP_DMA_CHAIN_QINIT(chain_id) \ | |
103 | do { \ | |
104 | dma_linked_lch[chain_id].q_head = \ | |
105 | dma_linked_lch[chain_id].q_tail = \ | |
106 | dma_linked_lch[chain_id].q_count = 0; \ | |
107 | } while (0) | |
108 | #define OMAP_DMA_CHAIN_QFULL(chain_id) \ | |
109 | (dma_linked_lch[chain_id].no_of_lchs_linked == \ | |
110 | dma_linked_lch[chain_id].q_count) | |
111 | #define OMAP_DMA_CHAIN_QLAST(chain_id) \ | |
112 | do { \ | |
113 | ((dma_linked_lch[chain_id].no_of_lchs_linked-1) == \ | |
114 | dma_linked_lch[chain_id].q_count) \ | |
115 | } while (0) | |
116 | #define OMAP_DMA_CHAIN_QEMPTY(chain_id) \ | |
117 | (0 == dma_linked_lch[chain_id].q_count) | |
118 | #define __OMAP_DMA_CHAIN_INCQ(end) \ | |
119 | ((end) = ((end)+1) % dma_linked_lch[chain_id].no_of_lchs_linked) | |
120 | #define OMAP_DMA_CHAIN_INCQHEAD(chain_id) \ | |
121 | do { \ | |
122 | __OMAP_DMA_CHAIN_INCQ(dma_linked_lch[chain_id].q_head); \ | |
123 | dma_linked_lch[chain_id].q_count--; \ | |
124 | } while (0) | |
125 | ||
126 | #define OMAP_DMA_CHAIN_INCQTAIL(chain_id) \ | |
127 | do { \ | |
128 | __OMAP_DMA_CHAIN_INCQ(dma_linked_lch[chain_id].q_tail); \ | |
129 | dma_linked_lch[chain_id].q_count++; \ | |
130 | } while (0) | |
131 | #endif | |
4d96372e TL |
132 | |
133 | static int dma_lch_count; | |
5e1c5ff4 | 134 | static int dma_chan_count; |
2263f022 | 135 | static int omap_dma_reserve_channels; |
5e1c5ff4 TL |
136 | |
137 | static spinlock_t dma_chan_lock; | |
4d96372e | 138 | static struct omap_dma_lch *dma_chan; |
5e1c5ff4 | 139 | |
f8151e5c AG |
140 | static inline void disable_lnk(int lch); |
141 | static void omap_disable_channel_irq(int lch); | |
142 | static inline void omap_enable_channel_irq(int lch); | |
143 | ||
1a8bfa1e | 144 | #define REVISIT_24XX() printk(KERN_ERR "FIXME: no %s on 24xx\n", \ |
8e86f427 | 145 | __func__); |
1a8bfa1e TL |
146 | |
147 | #ifdef CONFIG_ARCH_OMAP15XX | |
148 | /* Returns 1 if the DMA module is in OMAP1510-compatible mode, 0 otherwise */ | |
c7767582 | 149 | static int omap_dma_in_1510_mode(void) |
1a8bfa1e TL |
150 | { |
151 | return enable_1510_mode; | |
152 | } | |
153 | #else | |
154 | #define omap_dma_in_1510_mode() 0 | |
155 | #endif | |
156 | ||
157 | #ifdef CONFIG_ARCH_OMAP1 | |
5e1c5ff4 TL |
158 | static inline void set_gdma_dev(int req, int dev) |
159 | { | |
160 | u32 reg = OMAP_FUNC_MUX_ARM_BASE + ((req - 1) / 5) * 4; | |
161 | int shift = ((req - 1) % 5) * 6; | |
162 | u32 l; | |
163 | ||
164 | l = omap_readl(reg); | |
165 | l &= ~(0x3f << shift); | |
166 | l |= (dev - 1) << shift; | |
167 | omap_writel(l, reg); | |
168 | } | |
1a8bfa1e TL |
169 | #else |
170 | #define set_gdma_dev(req, dev) do {} while (0) | |
2c799cef TL |
171 | #define omap_readl(reg) 0 |
172 | #define omap_writel(val, reg) do {} while (0) | |
1a8bfa1e | 173 | #endif |
5e1c5ff4 | 174 | |
54b693d4 | 175 | #ifdef CONFIG_ARCH_OMAP1 |
709eb3e5 | 176 | void omap_set_dma_priority(int lch, int dst_port, int priority) |
5e1c5ff4 TL |
177 | { |
178 | unsigned long reg; | |
179 | u32 l; | |
180 | ||
82809601 | 181 | if (dma_omap1()) { |
709eb3e5 TL |
182 | switch (dst_port) { |
183 | case OMAP_DMA_PORT_OCP_T1: /* FFFECC00 */ | |
184 | reg = OMAP_TC_OCPT1_PRIOR; | |
185 | break; | |
186 | case OMAP_DMA_PORT_OCP_T2: /* FFFECCD0 */ | |
187 | reg = OMAP_TC_OCPT2_PRIOR; | |
188 | break; | |
189 | case OMAP_DMA_PORT_EMIFF: /* FFFECC08 */ | |
190 | reg = OMAP_TC_EMIFF_PRIOR; | |
191 | break; | |
192 | case OMAP_DMA_PORT_EMIFS: /* FFFECC04 */ | |
193 | reg = OMAP_TC_EMIFS_PRIOR; | |
194 | break; | |
195 | default: | |
196 | BUG(); | |
197 | return; | |
198 | } | |
199 | l = omap_readl(reg); | |
200 | l &= ~(0xf << 8); | |
201 | l |= (priority & 0xf) << 8; | |
202 | omap_writel(l, reg); | |
203 | } | |
54b693d4 TL |
204 | } |
205 | #endif | |
709eb3e5 | 206 | |
54b693d4 TL |
207 | #ifdef CONFIG_ARCH_OMAP2PLUS |
208 | void omap_set_dma_priority(int lch, int dst_port, int priority) | |
209 | { | |
210 | u32 ccr; | |
211 | ||
212 | ccr = p->dma_read(CCR, lch); | |
213 | if (priority) | |
214 | ccr |= (1 << 6); | |
215 | else | |
216 | ccr &= ~(1 << 6); | |
217 | p->dma_write(ccr, CCR, lch); | |
5e1c5ff4 | 218 | } |
54b693d4 | 219 | #endif |
97b7f715 | 220 | EXPORT_SYMBOL(omap_set_dma_priority); |
5e1c5ff4 TL |
221 | |
222 | void omap_set_dma_transfer_params(int lch, int data_type, int elem_count, | |
1a8bfa1e TL |
223 | int frame_count, int sync_mode, |
224 | int dma_trigger, int src_or_dst_synch) | |
5e1c5ff4 | 225 | { |
0499bdeb TL |
226 | u32 l; |
227 | ||
f31cc962 | 228 | l = p->dma_read(CSDP, lch); |
0499bdeb TL |
229 | l &= ~0x03; |
230 | l |= data_type; | |
f31cc962 | 231 | p->dma_write(l, CSDP, lch); |
5e1c5ff4 | 232 | |
82809601 | 233 | if (dma_omap1()) { |
0499bdeb TL |
234 | u16 ccr; |
235 | ||
f31cc962 | 236 | ccr = p->dma_read(CCR, lch); |
0499bdeb | 237 | ccr &= ~(1 << 5); |
1a8bfa1e | 238 | if (sync_mode == OMAP_DMA_SYNC_FRAME) |
0499bdeb | 239 | ccr |= 1 << 5; |
f31cc962 | 240 | p->dma_write(ccr, CCR, lch); |
1a8bfa1e | 241 | |
f31cc962 | 242 | ccr = p->dma_read(CCR2, lch); |
0499bdeb | 243 | ccr &= ~(1 << 2); |
1a8bfa1e | 244 | if (sync_mode == OMAP_DMA_SYNC_BLOCK) |
0499bdeb | 245 | ccr |= 1 << 2; |
f31cc962 | 246 | p->dma_write(ccr, CCR2, lch); |
1a8bfa1e TL |
247 | } |
248 | ||
82809601 | 249 | if (dma_omap2plus() && dma_trigger) { |
0499bdeb | 250 | u32 val; |
1a8bfa1e | 251 | |
f31cc962 | 252 | val = p->dma_read(CCR, lch); |
4b3cf448 AG |
253 | |
254 | /* DMA_SYNCHRO_CONTROL_UPPER depends on the channel number */ | |
72a1179e | 255 | val &= ~((1 << 23) | (3 << 19) | 0x1f); |
4b3cf448 AG |
256 | val |= (dma_trigger & ~0x1f) << 14; |
257 | val |= dma_trigger & 0x1f; | |
5e1c5ff4 | 258 | |
1a8bfa1e TL |
259 | if (sync_mode & OMAP_DMA_SYNC_FRAME) |
260 | val |= 1 << 5; | |
eca9e56e PU |
261 | else |
262 | val &= ~(1 << 5); | |
5e1c5ff4 | 263 | |
1a8bfa1e TL |
264 | if (sync_mode & OMAP_DMA_SYNC_BLOCK) |
265 | val |= 1 << 18; | |
eca9e56e PU |
266 | else |
267 | val &= ~(1 << 18); | |
5e1c5ff4 | 268 | |
72a1179e SO |
269 | if (src_or_dst_synch == OMAP_DMA_DST_SYNC_PREFETCH) { |
270 | val &= ~(1 << 24); /* dest synch */ | |
271 | val |= (1 << 23); /* Prefetch */ | |
272 | } else if (src_or_dst_synch) { | |
1a8bfa1e | 273 | val |= 1 << 24; /* source synch */ |
72a1179e | 274 | } else { |
1a8bfa1e | 275 | val &= ~(1 << 24); /* dest synch */ |
72a1179e | 276 | } |
f31cc962 | 277 | p->dma_write(val, CCR, lch); |
1a8bfa1e TL |
278 | } |
279 | ||
f31cc962 MK |
280 | p->dma_write(elem_count, CEN, lch); |
281 | p->dma_write(frame_count, CFN, lch); | |
5e1c5ff4 | 282 | } |
97b7f715 | 283 | EXPORT_SYMBOL(omap_set_dma_transfer_params); |
1a8bfa1e | 284 | |
709eb3e5 TL |
285 | void omap_set_dma_write_mode(int lch, enum omap_dma_write_mode mode) |
286 | { | |
82809601 | 287 | if (dma_omap2plus()) { |
0499bdeb TL |
288 | u32 csdp; |
289 | ||
f31cc962 | 290 | csdp = p->dma_read(CSDP, lch); |
0499bdeb TL |
291 | csdp &= ~(0x3 << 16); |
292 | csdp |= (mode << 16); | |
f31cc962 | 293 | p->dma_write(csdp, CSDP, lch); |
709eb3e5 TL |
294 | } |
295 | } | |
97b7f715 | 296 | EXPORT_SYMBOL(omap_set_dma_write_mode); |
709eb3e5 | 297 | |
0499bdeb TL |
298 | void omap_set_dma_channel_mode(int lch, enum omap_dma_channel_mode mode) |
299 | { | |
82809601 | 300 | if (dma_omap1() && !dma_omap15xx()) { |
0499bdeb TL |
301 | u32 l; |
302 | ||
f31cc962 | 303 | l = p->dma_read(LCH_CTRL, lch); |
0499bdeb TL |
304 | l &= ~0x7; |
305 | l |= mode; | |
f31cc962 | 306 | p->dma_write(l, LCH_CTRL, lch); |
0499bdeb TL |
307 | } |
308 | } | |
309 | EXPORT_SYMBOL(omap_set_dma_channel_mode); | |
310 | ||
1a8bfa1e | 311 | /* Note that src_port is only for omap1 */ |
5e1c5ff4 | 312 | void omap_set_dma_src_params(int lch, int src_port, int src_amode, |
1a8bfa1e TL |
313 | unsigned long src_start, |
314 | int src_ei, int src_fi) | |
5e1c5ff4 | 315 | { |
97b7f715 TL |
316 | u32 l; |
317 | ||
82809601 | 318 | if (dma_omap1()) { |
0499bdeb | 319 | u16 w; |
1a8bfa1e | 320 | |
f31cc962 | 321 | w = p->dma_read(CSDP, lch); |
0499bdeb TL |
322 | w &= ~(0x1f << 2); |
323 | w |= src_port << 2; | |
f31cc962 | 324 | p->dma_write(w, CSDP, lch); |
97b7f715 | 325 | } |
1a8bfa1e | 326 | |
f31cc962 | 327 | l = p->dma_read(CCR, lch); |
97b7f715 TL |
328 | l &= ~(0x03 << 12); |
329 | l |= src_amode << 12; | |
f31cc962 | 330 | p->dma_write(l, CCR, lch); |
0499bdeb | 331 | |
f31cc962 | 332 | p->dma_write(src_start, CSSA, lch); |
5e1c5ff4 | 333 | |
f31cc962 MK |
334 | p->dma_write(src_ei, CSEI, lch); |
335 | p->dma_write(src_fi, CSFI, lch); | |
1a8bfa1e | 336 | } |
97b7f715 | 337 | EXPORT_SYMBOL(omap_set_dma_src_params); |
5e1c5ff4 | 338 | |
97b7f715 | 339 | void omap_set_dma_params(int lch, struct omap_dma_channel_params *params) |
1a8bfa1e TL |
340 | { |
341 | omap_set_dma_transfer_params(lch, params->data_type, | |
342 | params->elem_count, params->frame_count, | |
343 | params->sync_mode, params->trigger, | |
344 | params->src_or_dst_synch); | |
345 | omap_set_dma_src_params(lch, params->src_port, | |
346 | params->src_amode, params->src_start, | |
347 | params->src_ei, params->src_fi); | |
348 | ||
349 | omap_set_dma_dest_params(lch, params->dst_port, | |
350 | params->dst_amode, params->dst_start, | |
351 | params->dst_ei, params->dst_fi); | |
f8151e5c AG |
352 | if (params->read_prio || params->write_prio) |
353 | omap_dma_set_prio_lch(lch, params->read_prio, | |
354 | params->write_prio); | |
5e1c5ff4 | 355 | } |
97b7f715 | 356 | EXPORT_SYMBOL(omap_set_dma_params); |
5e1c5ff4 | 357 | |
5e1c5ff4 TL |
358 | void omap_set_dma_src_data_pack(int lch, int enable) |
359 | { | |
0499bdeb TL |
360 | u32 l; |
361 | ||
f31cc962 | 362 | l = p->dma_read(CSDP, lch); |
0499bdeb | 363 | l &= ~(1 << 6); |
1a8bfa1e | 364 | if (enable) |
0499bdeb | 365 | l |= (1 << 6); |
f31cc962 | 366 | p->dma_write(l, CSDP, lch); |
5e1c5ff4 | 367 | } |
97b7f715 | 368 | EXPORT_SYMBOL(omap_set_dma_src_data_pack); |
5e1c5ff4 TL |
369 | |
370 | void omap_set_dma_src_burst_mode(int lch, enum omap_dma_burst_mode burst_mode) | |
371 | { | |
6dc3c8f2 | 372 | unsigned int burst = 0; |
0499bdeb TL |
373 | u32 l; |
374 | ||
f31cc962 | 375 | l = p->dma_read(CSDP, lch); |
0499bdeb | 376 | l &= ~(0x03 << 7); |
5e1c5ff4 | 377 | |
5e1c5ff4 TL |
378 | switch (burst_mode) { |
379 | case OMAP_DMA_DATA_BURST_DIS: | |
380 | break; | |
381 | case OMAP_DMA_DATA_BURST_4: | |
82809601 | 382 | if (dma_omap2plus()) |
6dc3c8f2 KP |
383 | burst = 0x1; |
384 | else | |
385 | burst = 0x2; | |
5e1c5ff4 TL |
386 | break; |
387 | case OMAP_DMA_DATA_BURST_8: | |
82809601 | 388 | if (dma_omap2plus()) { |
6dc3c8f2 KP |
389 | burst = 0x2; |
390 | break; | |
391 | } | |
ea221a6a | 392 | /* |
393 | * not supported by current hardware on OMAP1 | |
5e1c5ff4 TL |
394 | * w |= (0x03 << 7); |
395 | * fall through | |
396 | */ | |
6dc3c8f2 | 397 | case OMAP_DMA_DATA_BURST_16: |
82809601 | 398 | if (dma_omap2plus()) { |
6dc3c8f2 KP |
399 | burst = 0x3; |
400 | break; | |
401 | } | |
ea221a6a | 402 | /* |
403 | * OMAP1 don't support burst 16 | |
6dc3c8f2 KP |
404 | * fall through |
405 | */ | |
5e1c5ff4 TL |
406 | default: |
407 | BUG(); | |
408 | } | |
0499bdeb TL |
409 | |
410 | l |= (burst << 7); | |
f31cc962 | 411 | p->dma_write(l, CSDP, lch); |
5e1c5ff4 | 412 | } |
97b7f715 | 413 | EXPORT_SYMBOL(omap_set_dma_src_burst_mode); |
5e1c5ff4 | 414 | |
1a8bfa1e | 415 | /* Note that dest_port is only for OMAP1 */ |
5e1c5ff4 | 416 | void omap_set_dma_dest_params(int lch, int dest_port, int dest_amode, |
1a8bfa1e TL |
417 | unsigned long dest_start, |
418 | int dst_ei, int dst_fi) | |
5e1c5ff4 | 419 | { |
0499bdeb TL |
420 | u32 l; |
421 | ||
82809601 | 422 | if (dma_omap1()) { |
f31cc962 | 423 | l = p->dma_read(CSDP, lch); |
0499bdeb TL |
424 | l &= ~(0x1f << 9); |
425 | l |= dest_port << 9; | |
f31cc962 | 426 | p->dma_write(l, CSDP, lch); |
1a8bfa1e | 427 | } |
5e1c5ff4 | 428 | |
f31cc962 | 429 | l = p->dma_read(CCR, lch); |
0499bdeb TL |
430 | l &= ~(0x03 << 14); |
431 | l |= dest_amode << 14; | |
f31cc962 | 432 | p->dma_write(l, CCR, lch); |
5e1c5ff4 | 433 | |
f31cc962 | 434 | p->dma_write(dest_start, CDSA, lch); |
5e1c5ff4 | 435 | |
f31cc962 MK |
436 | p->dma_write(dst_ei, CDEI, lch); |
437 | p->dma_write(dst_fi, CDFI, lch); | |
5e1c5ff4 | 438 | } |
97b7f715 | 439 | EXPORT_SYMBOL(omap_set_dma_dest_params); |
5e1c5ff4 | 440 | |
5e1c5ff4 TL |
441 | void omap_set_dma_dest_data_pack(int lch, int enable) |
442 | { | |
0499bdeb TL |
443 | u32 l; |
444 | ||
f31cc962 | 445 | l = p->dma_read(CSDP, lch); |
0499bdeb | 446 | l &= ~(1 << 13); |
1a8bfa1e | 447 | if (enable) |
0499bdeb | 448 | l |= 1 << 13; |
f31cc962 | 449 | p->dma_write(l, CSDP, lch); |
5e1c5ff4 | 450 | } |
97b7f715 | 451 | EXPORT_SYMBOL(omap_set_dma_dest_data_pack); |
5e1c5ff4 TL |
452 | |
453 | void omap_set_dma_dest_burst_mode(int lch, enum omap_dma_burst_mode burst_mode) | |
454 | { | |
6dc3c8f2 | 455 | unsigned int burst = 0; |
0499bdeb TL |
456 | u32 l; |
457 | ||
f31cc962 | 458 | l = p->dma_read(CSDP, lch); |
0499bdeb | 459 | l &= ~(0x03 << 14); |
5e1c5ff4 | 460 | |
5e1c5ff4 TL |
461 | switch (burst_mode) { |
462 | case OMAP_DMA_DATA_BURST_DIS: | |
463 | break; | |
464 | case OMAP_DMA_DATA_BURST_4: | |
82809601 | 465 | if (dma_omap2plus()) |
6dc3c8f2 KP |
466 | burst = 0x1; |
467 | else | |
468 | burst = 0x2; | |
5e1c5ff4 TL |
469 | break; |
470 | case OMAP_DMA_DATA_BURST_8: | |
82809601 | 471 | if (dma_omap2plus()) |
6dc3c8f2 KP |
472 | burst = 0x2; |
473 | else | |
474 | burst = 0x3; | |
5e1c5ff4 | 475 | break; |
6dc3c8f2 | 476 | case OMAP_DMA_DATA_BURST_16: |
82809601 | 477 | if (dma_omap2plus()) { |
6dc3c8f2 KP |
478 | burst = 0x3; |
479 | break; | |
480 | } | |
ea221a6a | 481 | /* |
482 | * OMAP1 don't support burst 16 | |
6dc3c8f2 KP |
483 | * fall through |
484 | */ | |
5e1c5ff4 TL |
485 | default: |
486 | printk(KERN_ERR "Invalid DMA burst mode\n"); | |
487 | BUG(); | |
488 | return; | |
489 | } | |
0499bdeb | 490 | l |= (burst << 14); |
f31cc962 | 491 | p->dma_write(l, CSDP, lch); |
5e1c5ff4 | 492 | } |
97b7f715 | 493 | EXPORT_SYMBOL(omap_set_dma_dest_burst_mode); |
5e1c5ff4 | 494 | |
1a8bfa1e | 495 | static inline void omap_enable_channel_irq(int lch) |
5e1c5ff4 | 496 | { |
7ff879db | 497 | /* Clear CSR */ |
82809601 | 498 | if (dma_omap1()) |
bedfb7ad OM |
499 | p->dma_read(CSR, lch); |
500 | else | |
f31cc962 | 501 | p->dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR, lch); |
1a8bfa1e | 502 | |
5e1c5ff4 | 503 | /* Enable some nice interrupts. */ |
f31cc962 | 504 | p->dma_write(dma_chan[lch].enabled_irqs, CICR, lch); |
5e1c5ff4 TL |
505 | } |
506 | ||
bedfb7ad | 507 | static inline void omap_disable_channel_irq(int lch) |
5e1c5ff4 | 508 | { |
bedfb7ad OM |
509 | /* disable channel interrupts */ |
510 | p->dma_write(0, CICR, lch); | |
511 | /* Clear CSR */ | |
82809601 | 512 | if (dma_omap1()) |
bedfb7ad OM |
513 | p->dma_read(CSR, lch); |
514 | else | |
515 | p->dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR, lch); | |
1a8bfa1e TL |
516 | } |
517 | ||
518 | void omap_enable_dma_irq(int lch, u16 bits) | |
519 | { | |
520 | dma_chan[lch].enabled_irqs |= bits; | |
521 | } | |
97b7f715 | 522 | EXPORT_SYMBOL(omap_enable_dma_irq); |
5e1c5ff4 | 523 | |
1a8bfa1e TL |
524 | void omap_disable_dma_irq(int lch, u16 bits) |
525 | { | |
526 | dma_chan[lch].enabled_irqs &= ~bits; | |
527 | } | |
97b7f715 | 528 | EXPORT_SYMBOL(omap_disable_dma_irq); |
1a8bfa1e TL |
529 | |
530 | static inline void enable_lnk(int lch) | |
531 | { | |
0499bdeb TL |
532 | u32 l; |
533 | ||
f31cc962 | 534 | l = p->dma_read(CLNK_CTRL, lch); |
0499bdeb | 535 | |
82809601 | 536 | if (dma_omap1()) |
0499bdeb | 537 | l &= ~(1 << 14); |
5e1c5ff4 | 538 | |
1a8bfa1e | 539 | /* Set the ENABLE_LNK bits */ |
5e1c5ff4 | 540 | if (dma_chan[lch].next_lch != -1) |
0499bdeb | 541 | l = dma_chan[lch].next_lch | (1 << 15); |
f8151e5c AG |
542 | |
543 | #ifndef CONFIG_ARCH_OMAP1 | |
82809601 | 544 | if (dma_omap2plus()) |
97b7f715 TL |
545 | if (dma_chan[lch].next_linked_ch != -1) |
546 | l = dma_chan[lch].next_linked_ch | (1 << 15); | |
f8151e5c | 547 | #endif |
0499bdeb | 548 | |
f31cc962 | 549 | p->dma_write(l, CLNK_CTRL, lch); |
5e1c5ff4 TL |
550 | } |
551 | ||
552 | static inline void disable_lnk(int lch) | |
553 | { | |
0499bdeb TL |
554 | u32 l; |
555 | ||
f31cc962 | 556 | l = p->dma_read(CLNK_CTRL, lch); |
0499bdeb | 557 | |
5e1c5ff4 | 558 | /* Disable interrupts */ |
bedfb7ad OM |
559 | omap_disable_channel_irq(lch); |
560 | ||
82809601 | 561 | if (dma_omap1()) { |
1a8bfa1e | 562 | /* Set the STOP_LNK bit */ |
0499bdeb | 563 | l |= 1 << 14; |
1a8bfa1e | 564 | } |
5e1c5ff4 | 565 | |
82809601 | 566 | if (dma_omap2plus()) { |
1a8bfa1e | 567 | /* Clear the ENABLE_LNK bit */ |
0499bdeb | 568 | l &= ~(1 << 15); |
1a8bfa1e | 569 | } |
5e1c5ff4 | 570 | |
f31cc962 | 571 | p->dma_write(l, CLNK_CTRL, lch); |
5e1c5ff4 TL |
572 | dma_chan[lch].flags &= ~OMAP_DMA_ACTIVE; |
573 | } | |
574 | ||
1a8bfa1e | 575 | static inline void omap2_enable_irq_lch(int lch) |
5e1c5ff4 | 576 | { |
1a8bfa1e | 577 | u32 val; |
ee907324 | 578 | unsigned long flags; |
1a8bfa1e | 579 | |
82809601 | 580 | if (dma_omap1()) |
1a8bfa1e TL |
581 | return; |
582 | ||
ee907324 | 583 | spin_lock_irqsave(&dma_chan_lock, flags); |
bedfb7ad OM |
584 | /* clear IRQ STATUS */ |
585 | p->dma_write(1 << lch, IRQSTATUS_L0, lch); | |
586 | /* Enable interrupt */ | |
f31cc962 | 587 | val = p->dma_read(IRQENABLE_L0, lch); |
1a8bfa1e | 588 | val |= 1 << lch; |
f31cc962 | 589 | p->dma_write(val, IRQENABLE_L0, lch); |
ee907324 | 590 | spin_unlock_irqrestore(&dma_chan_lock, flags); |
1a8bfa1e TL |
591 | } |
592 | ||
ada8d4a5 MW |
593 | static inline void omap2_disable_irq_lch(int lch) |
594 | { | |
595 | u32 val; | |
596 | unsigned long flags; | |
597 | ||
82809601 | 598 | if (dma_omap1()) |
ada8d4a5 MW |
599 | return; |
600 | ||
601 | spin_lock_irqsave(&dma_chan_lock, flags); | |
bedfb7ad | 602 | /* Disable interrupt */ |
f31cc962 | 603 | val = p->dma_read(IRQENABLE_L0, lch); |
ada8d4a5 | 604 | val &= ~(1 << lch); |
f31cc962 | 605 | p->dma_write(val, IRQENABLE_L0, lch); |
bedfb7ad OM |
606 | /* clear IRQ STATUS */ |
607 | p->dma_write(1 << lch, IRQSTATUS_L0, lch); | |
ada8d4a5 MW |
608 | spin_unlock_irqrestore(&dma_chan_lock, flags); |
609 | } | |
610 | ||
1a8bfa1e | 611 | int omap_request_dma(int dev_id, const char *dev_name, |
97b7f715 | 612 | void (*callback)(int lch, u16 ch_status, void *data), |
1a8bfa1e TL |
613 | void *data, int *dma_ch_out) |
614 | { | |
615 | int ch, free_ch = -1; | |
616 | unsigned long flags; | |
617 | struct omap_dma_lch *chan; | |
618 | ||
5c65c360 RK |
619 | WARN(strcmp(dev_name, "DMA engine"), "Using deprecated platform DMA API - please update to DMA engine"); |
620 | ||
1a8bfa1e TL |
621 | spin_lock_irqsave(&dma_chan_lock, flags); |
622 | for (ch = 0; ch < dma_chan_count; ch++) { | |
623 | if (free_ch == -1 && dma_chan[ch].dev_id == -1) { | |
624 | free_ch = ch; | |
03a6d4a0 S |
625 | /* Exit after first free channel found */ |
626 | break; | |
1a8bfa1e TL |
627 | } |
628 | } | |
629 | if (free_ch == -1) { | |
630 | spin_unlock_irqrestore(&dma_chan_lock, flags); | |
631 | return -EBUSY; | |
632 | } | |
633 | chan = dma_chan + free_ch; | |
634 | chan->dev_id = dev_id; | |
635 | ||
f31cc962 MK |
636 | if (p->clear_lch_regs) |
637 | p->clear_lch_regs(free_ch); | |
5e1c5ff4 | 638 | |
82809601 | 639 | if (dma_omap2plus()) |
1a8bfa1e TL |
640 | omap_clear_dma(free_ch); |
641 | ||
642 | spin_unlock_irqrestore(&dma_chan_lock, flags); | |
643 | ||
644 | chan->dev_name = dev_name; | |
645 | chan->callback = callback; | |
646 | chan->data = data; | |
a92fda19 | 647 | chan->flags = 0; |
97b7f715 | 648 | |
f8151e5c | 649 | #ifndef CONFIG_ARCH_OMAP1 |
82809601 | 650 | if (dma_omap2plus()) { |
97b7f715 TL |
651 | chan->chain_id = -1; |
652 | chan->next_linked_ch = -1; | |
653 | } | |
f8151e5c | 654 | #endif |
97b7f715 | 655 | |
7ff879db | 656 | chan->enabled_irqs = OMAP_DMA_DROP_IRQ | OMAP_DMA_BLOCK_IRQ; |
1a8bfa1e | 657 | |
82809601 | 658 | if (dma_omap1()) |
7ff879db | 659 | chan->enabled_irqs |= OMAP1_DMA_TOUT_IRQ; |
82809601 | 660 | else if (dma_omap2plus()) |
7ff879db TL |
661 | chan->enabled_irqs |= OMAP2_DMA_MISALIGNED_ERR_IRQ | |
662 | OMAP2_DMA_TRANS_ERR_IRQ; | |
1a8bfa1e | 663 | |
82809601 | 664 | if (dma_omap16xx()) { |
1a8bfa1e TL |
665 | /* If the sync device is set, configure it dynamically. */ |
666 | if (dev_id != 0) { | |
667 | set_gdma_dev(free_ch + 1, dev_id); | |
668 | dev_id = free_ch + 1; | |
669 | } | |
97b7f715 TL |
670 | /* |
671 | * Disable the 1510 compatibility mode and set the sync device | |
672 | * id. | |
673 | */ | |
f31cc962 | 674 | p->dma_write(dev_id | (1 << 10), CCR, free_ch); |
82809601 | 675 | } else if (dma_omap1()) { |
f31cc962 | 676 | p->dma_write(dev_id, CCR, free_ch); |
1a8bfa1e TL |
677 | } |
678 | ||
82809601 | 679 | if (dma_omap2plus()) { |
1a8bfa1e | 680 | omap_enable_channel_irq(free_ch); |
bedfb7ad | 681 | omap2_enable_irq_lch(free_ch); |
1a8bfa1e TL |
682 | } |
683 | ||
684 | *dma_ch_out = free_ch; | |
685 | ||
686 | return 0; | |
687 | } | |
97b7f715 | 688 | EXPORT_SYMBOL(omap_request_dma); |
1a8bfa1e TL |
689 | |
690 | void omap_free_dma(int lch) | |
691 | { | |
692 | unsigned long flags; | |
693 | ||
1a8bfa1e | 694 | if (dma_chan[lch].dev_id == -1) { |
97b7f715 | 695 | pr_err("omap_dma: trying to free unallocated DMA channel %d\n", |
1a8bfa1e | 696 | lch); |
1a8bfa1e TL |
697 | return; |
698 | } | |
97b7f715 | 699 | |
bedfb7ad | 700 | /* Disable interrupt for logical channel */ |
82809601 | 701 | if (dma_omap2plus()) |
ada8d4a5 | 702 | omap2_disable_irq_lch(lch); |
1a8bfa1e | 703 | |
bedfb7ad OM |
704 | /* Disable all DMA interrupts for the channel. */ |
705 | omap_disable_channel_irq(lch); | |
1a8bfa1e | 706 | |
bedfb7ad OM |
707 | /* Make sure the DMA transfer is stopped. */ |
708 | p->dma_write(0, CCR, lch); | |
1a8bfa1e | 709 | |
bedfb7ad | 710 | /* Clear registers */ |
82809601 | 711 | if (dma_omap2plus()) |
1a8bfa1e | 712 | omap_clear_dma(lch); |
da1b94e6 SS |
713 | |
714 | spin_lock_irqsave(&dma_chan_lock, flags); | |
715 | dma_chan[lch].dev_id = -1; | |
716 | dma_chan[lch].next_lch = -1; | |
717 | dma_chan[lch].callback = NULL; | |
718 | spin_unlock_irqrestore(&dma_chan_lock, flags); | |
1a8bfa1e | 719 | } |
97b7f715 | 720 | EXPORT_SYMBOL(omap_free_dma); |
1a8bfa1e | 721 | |
f8151e5c AG |
722 | /** |
723 | * @brief omap_dma_set_global_params : Set global priority settings for dma | |
724 | * | |
725 | * @param arb_rate | |
726 | * @param max_fifo_depth | |
70cf644c AA |
727 | * @param tparams - Number of threads to reserve : DMA_THREAD_RESERVE_NORM |
728 | * DMA_THREAD_RESERVE_ONET | |
729 | * DMA_THREAD_RESERVE_TWOT | |
730 | * DMA_THREAD_RESERVE_THREET | |
f8151e5c AG |
731 | */ |
732 | void | |
733 | omap_dma_set_global_params(int arb_rate, int max_fifo_depth, int tparams) | |
734 | { | |
735 | u32 reg; | |
736 | ||
82809601 | 737 | if (dma_omap1()) { |
8e86f427 | 738 | printk(KERN_ERR "FIXME: no %s on 15xx/16xx\n", __func__); |
f8151e5c AG |
739 | return; |
740 | } | |
741 | ||
70cf644c AA |
742 | if (max_fifo_depth == 0) |
743 | max_fifo_depth = 1; | |
f8151e5c AG |
744 | if (arb_rate == 0) |
745 | arb_rate = 1; | |
746 | ||
70cf644c AA |
747 | reg = 0xff & max_fifo_depth; |
748 | reg |= (0x3 & tparams) << 12; | |
749 | reg |= (arb_rate & 0xff) << 16; | |
f8151e5c | 750 | |
f31cc962 | 751 | p->dma_write(reg, GCR, 0); |
f8151e5c AG |
752 | } |
753 | EXPORT_SYMBOL(omap_dma_set_global_params); | |
754 | ||
755 | /** | |
756 | * @brief omap_dma_set_prio_lch : Set channel wise priority settings | |
757 | * | |
758 | * @param lch | |
759 | * @param read_prio - Read priority | |
760 | * @param write_prio - Write priority | |
761 | * Both of the above can be set with one of the following values : | |
762 | * DMA_CH_PRIO_HIGH/DMA_CH_PRIO_LOW | |
763 | */ | |
175655bd | 764 | static int |
f8151e5c AG |
765 | omap_dma_set_prio_lch(int lch, unsigned char read_prio, |
766 | unsigned char write_prio) | |
767 | { | |
0499bdeb | 768 | u32 l; |
f8151e5c | 769 | |
4d96372e | 770 | if (unlikely((lch < 0 || lch >= dma_lch_count))) { |
f8151e5c AG |
771 | printk(KERN_ERR "Invalid channel id\n"); |
772 | return -EINVAL; | |
773 | } | |
f31cc962 | 774 | l = p->dma_read(CCR, lch); |
0499bdeb | 775 | l &= ~((1 << 6) | (1 << 26)); |
82809601 | 776 | if (d->dev_caps & IS_RW_PRIORITY) |
0499bdeb | 777 | l |= ((read_prio & 0x1) << 6) | ((write_prio & 0x1) << 26); |
f8151e5c | 778 | else |
0499bdeb TL |
779 | l |= ((read_prio & 0x1) << 6); |
780 | ||
f31cc962 | 781 | p->dma_write(l, CCR, lch); |
f8151e5c | 782 | |
f8151e5c AG |
783 | return 0; |
784 | } | |
175655bd | 785 | |
f8151e5c | 786 | |
1a8bfa1e TL |
787 | /* |
788 | * Clears any DMA state so the DMA engine is ready to restart with new buffers | |
789 | * through omap_start_dma(). Any buffers in flight are discarded. | |
790 | */ | |
175655bd | 791 | static void omap_clear_dma(int lch) |
1a8bfa1e TL |
792 | { |
793 | unsigned long flags; | |
794 | ||
795 | local_irq_save(flags); | |
f31cc962 | 796 | p->clear_dma(lch); |
1a8bfa1e TL |
797 | local_irq_restore(flags); |
798 | } | |
799 | ||
800 | void omap_start_dma(int lch) | |
801 | { | |
0499bdeb TL |
802 | u32 l; |
803 | ||
519e6166 | 804 | /* |
805 | * The CPC/CDAC register needs to be initialized to zero | |
806 | * before starting dma transfer. | |
807 | */ | |
82809601 | 808 | if (dma_omap15xx()) |
f31cc962 | 809 | p->dma_write(0, CPC, lch); |
519e6166 | 810 | else |
f31cc962 | 811 | p->dma_write(0, CDAC, lch); |
519e6166 | 812 | |
5e1c5ff4 TL |
813 | if (!omap_dma_in_1510_mode() && dma_chan[lch].next_lch != -1) { |
814 | int next_lch, cur_lch; | |
bc4d8b5f | 815 | char dma_chan_link_map[MAX_LOGICAL_DMA_CH_COUNT]; |
5e1c5ff4 | 816 | |
5e1c5ff4 TL |
817 | /* Set the link register of the first channel */ |
818 | enable_lnk(lch); | |
819 | ||
820 | memset(dma_chan_link_map, 0, sizeof(dma_chan_link_map)); | |
f0a3ff27 S |
821 | dma_chan_link_map[lch] = 1; |
822 | ||
5e1c5ff4 TL |
823 | cur_lch = dma_chan[lch].next_lch; |
824 | do { | |
825 | next_lch = dma_chan[cur_lch].next_lch; | |
826 | ||
1a8bfa1e | 827 | /* The loop case: we've been here already */ |
5e1c5ff4 TL |
828 | if (dma_chan_link_map[cur_lch]) |
829 | break; | |
830 | /* Mark the current channel */ | |
831 | dma_chan_link_map[cur_lch] = 1; | |
832 | ||
833 | enable_lnk(cur_lch); | |
1a8bfa1e | 834 | omap_enable_channel_irq(cur_lch); |
5e1c5ff4 TL |
835 | |
836 | cur_lch = next_lch; | |
837 | } while (next_lch != -1); | |
d3c9be2f | 838 | } else if (IS_DMA_ERRATA(DMA_ERRATA_PARALLEL_CHANNELS)) |
f31cc962 | 839 | p->dma_write(lch, CLNK_CTRL, lch); |
5e1c5ff4 | 840 | |
1a8bfa1e TL |
841 | omap_enable_channel_irq(lch); |
842 | ||
f31cc962 | 843 | l = p->dma_read(CCR, lch); |
0499bdeb | 844 | |
d3c9be2f MK |
845 | if (IS_DMA_ERRATA(DMA_ERRATA_IFRAME_BUFFERING)) |
846 | l |= OMAP_DMA_CCR_BUFFERING_DISABLE; | |
0499bdeb | 847 | l |= OMAP_DMA_CCR_EN; |
d3c9be2f | 848 | |
35453584 RK |
849 | /* |
850 | * As dma_write() uses IO accessors which are weakly ordered, there | |
851 | * is no guarantee that data in coherent DMA memory will be visible | |
852 | * to the DMA device. Add a memory barrier here to ensure that any | |
853 | * such data is visible prior to enabling DMA. | |
854 | */ | |
855 | mb(); | |
f31cc962 | 856 | p->dma_write(l, CCR, lch); |
5e1c5ff4 | 857 | |
5e1c5ff4 TL |
858 | dma_chan[lch].flags |= OMAP_DMA_ACTIVE; |
859 | } | |
97b7f715 | 860 | EXPORT_SYMBOL(omap_start_dma); |
5e1c5ff4 TL |
861 | |
862 | void omap_stop_dma(int lch) | |
863 | { | |
0499bdeb TL |
864 | u32 l; |
865 | ||
9da65a99 | 866 | /* Disable all interrupts on the channel */ |
bedfb7ad | 867 | omap_disable_channel_irq(lch); |
9da65a99 | 868 | |
f31cc962 | 869 | l = p->dma_read(CCR, lch); |
d3c9be2f MK |
870 | if (IS_DMA_ERRATA(DMA_ERRATA_i541) && |
871 | (l & OMAP_DMA_CCR_SEL_SRC_DST_SYNC)) { | |
0e4905c0 PU |
872 | int i = 0; |
873 | u32 sys_cf; | |
874 | ||
875 | /* Configure No-Standby */ | |
f31cc962 | 876 | l = p->dma_read(OCP_SYSCONFIG, lch); |
0e4905c0 PU |
877 | sys_cf = l; |
878 | l &= ~DMA_SYSCONFIG_MIDLEMODE_MASK; | |
879 | l |= DMA_SYSCONFIG_MIDLEMODE(DMA_IDLEMODE_NO_IDLE); | |
f31cc962 | 880 | p->dma_write(l , OCP_SYSCONFIG, 0); |
0e4905c0 | 881 | |
f31cc962 | 882 | l = p->dma_read(CCR, lch); |
0e4905c0 | 883 | l &= ~OMAP_DMA_CCR_EN; |
f31cc962 | 884 | p->dma_write(l, CCR, lch); |
0e4905c0 PU |
885 | |
886 | /* Wait for sDMA FIFO drain */ | |
f31cc962 | 887 | l = p->dma_read(CCR, lch); |
0e4905c0 PU |
888 | while (i < 100 && (l & (OMAP_DMA_CCR_RD_ACTIVE | |
889 | OMAP_DMA_CCR_WR_ACTIVE))) { | |
890 | udelay(5); | |
891 | i++; | |
f31cc962 | 892 | l = p->dma_read(CCR, lch); |
0e4905c0 PU |
893 | } |
894 | if (i >= 100) | |
7852ec05 | 895 | pr_err("DMA drain did not complete on lch %d\n", lch); |
0e4905c0 | 896 | /* Restore OCP_SYSCONFIG */ |
f31cc962 | 897 | p->dma_write(sys_cf, OCP_SYSCONFIG, lch); |
0e4905c0 PU |
898 | } else { |
899 | l &= ~OMAP_DMA_CCR_EN; | |
f31cc962 | 900 | p->dma_write(l, CCR, lch); |
0e4905c0 | 901 | } |
9da65a99 | 902 | |
35453584 RK |
903 | /* |
904 | * Ensure that data transferred by DMA is visible to any access | |
905 | * after DMA has been disabled. This is important for coherent | |
906 | * DMA regions. | |
907 | */ | |
908 | mb(); | |
909 | ||
5e1c5ff4 TL |
910 | if (!omap_dma_in_1510_mode() && dma_chan[lch].next_lch != -1) { |
911 | int next_lch, cur_lch = lch; | |
bc4d8b5f | 912 | char dma_chan_link_map[MAX_LOGICAL_DMA_CH_COUNT]; |
5e1c5ff4 TL |
913 | |
914 | memset(dma_chan_link_map, 0, sizeof(dma_chan_link_map)); | |
915 | do { | |
916 | /* The loop case: we've been here already */ | |
917 | if (dma_chan_link_map[cur_lch]) | |
918 | break; | |
919 | /* Mark the current channel */ | |
920 | dma_chan_link_map[cur_lch] = 1; | |
921 | ||
922 | disable_lnk(cur_lch); | |
923 | ||
924 | next_lch = dma_chan[cur_lch].next_lch; | |
925 | cur_lch = next_lch; | |
926 | } while (next_lch != -1); | |
5e1c5ff4 | 927 | } |
1a8bfa1e | 928 | |
5e1c5ff4 TL |
929 | dma_chan[lch].flags &= ~OMAP_DMA_ACTIVE; |
930 | } | |
97b7f715 | 931 | EXPORT_SYMBOL(omap_stop_dma); |
5e1c5ff4 | 932 | |
709eb3e5 TL |
933 | /* |
934 | * Allows changing the DMA callback function or data. This may be needed if | |
935 | * the driver shares a single DMA channel for multiple dma triggers. | |
936 | */ | |
937 | int omap_set_dma_callback(int lch, | |
97b7f715 | 938 | void (*callback)(int lch, u16 ch_status, void *data), |
709eb3e5 TL |
939 | void *data) |
940 | { | |
941 | unsigned long flags; | |
942 | ||
943 | if (lch < 0) | |
944 | return -ENODEV; | |
945 | ||
946 | spin_lock_irqsave(&dma_chan_lock, flags); | |
947 | if (dma_chan[lch].dev_id == -1) { | |
948 | printk(KERN_ERR "DMA callback for not set for free channel\n"); | |
949 | spin_unlock_irqrestore(&dma_chan_lock, flags); | |
950 | return -EINVAL; | |
951 | } | |
952 | dma_chan[lch].callback = callback; | |
953 | dma_chan[lch].data = data; | |
954 | spin_unlock_irqrestore(&dma_chan_lock, flags); | |
955 | ||
956 | return 0; | |
957 | } | |
97b7f715 | 958 | EXPORT_SYMBOL(omap_set_dma_callback); |
709eb3e5 | 959 | |
1a8bfa1e TL |
960 | /* |
961 | * Returns current physical source address for the given DMA channel. | |
962 | * If the channel is running the caller must disable interrupts prior calling | |
963 | * this function and process the returned value before re-enabling interrupt to | |
964 | * prevent races with the interrupt handler. Note that in continuous mode there | |
25985edc | 965 | * is a chance for CSSA_L register overflow between the two reads resulting |
1a8bfa1e TL |
966 | * in incorrect return value. |
967 | */ | |
968 | dma_addr_t omap_get_dma_src_pos(int lch) | |
5e1c5ff4 | 969 | { |
0695de32 | 970 | dma_addr_t offset = 0; |
5e1c5ff4 | 971 | |
82809601 | 972 | if (dma_omap15xx()) |
f31cc962 | 973 | offset = p->dma_read(CPC, lch); |
0499bdeb | 974 | else |
f31cc962 | 975 | offset = p->dma_read(CSAC, lch); |
5e1c5ff4 | 976 | |
d3c9be2f | 977 | if (IS_DMA_ERRATA(DMA_ERRATA_3_3) && offset == 0) |
f31cc962 | 978 | offset = p->dma_read(CSAC, lch); |
0499bdeb | 979 | |
82809601 | 980 | if (!dma_omap15xx()) { |
7ba96680 PU |
981 | /* |
982 | * CDAC == 0 indicates that the DMA transfer on the channel has | |
983 | * not been started (no data has been transferred so far). | |
984 | * Return the programmed source start address in this case. | |
985 | */ | |
986 | if (likely(p->dma_read(CDAC, lch))) | |
987 | offset = p->dma_read(CSAC, lch); | |
988 | else | |
989 | offset = p->dma_read(CSSA, lch); | |
990 | } | |
991 | ||
82809601 | 992 | if (dma_omap1()) |
f31cc962 | 993 | offset |= (p->dma_read(CSSA, lch) & 0xFFFF0000); |
5e1c5ff4 | 994 | |
1a8bfa1e | 995 | return offset; |
5e1c5ff4 | 996 | } |
97b7f715 | 997 | EXPORT_SYMBOL(omap_get_dma_src_pos); |
5e1c5ff4 | 998 | |
1a8bfa1e TL |
999 | /* |
1000 | * Returns current physical destination address for the given DMA channel. | |
1001 | * If the channel is running the caller must disable interrupts prior calling | |
1002 | * this function and process the returned value before re-enabling interrupt to | |
1003 | * prevent races with the interrupt handler. Note that in continuous mode there | |
25985edc | 1004 | * is a chance for CDSA_L register overflow between the two reads resulting |
1a8bfa1e TL |
1005 | * in incorrect return value. |
1006 | */ | |
1007 | dma_addr_t omap_get_dma_dst_pos(int lch) | |
5e1c5ff4 | 1008 | { |
0695de32 | 1009 | dma_addr_t offset = 0; |
5e1c5ff4 | 1010 | |
82809601 | 1011 | if (dma_omap15xx()) |
f31cc962 | 1012 | offset = p->dma_read(CPC, lch); |
0499bdeb | 1013 | else |
f31cc962 | 1014 | offset = p->dma_read(CDAC, lch); |
5e1c5ff4 | 1015 | |
0499bdeb TL |
1016 | /* |
1017 | * omap 3.2/3.3 erratum: sometimes 0 is returned if CSAC/CDAC is | |
1018 | * read before the DMA controller finished disabling the channel. | |
1019 | */ | |
82809601 | 1020 | if (!dma_omap15xx() && offset == 0) { |
f31cc962 | 1021 | offset = p->dma_read(CDAC, lch); |
06e8077b PU |
1022 | /* |
1023 | * CDAC == 0 indicates that the DMA transfer on the channel has | |
1024 | * not been started (no data has been transferred so far). | |
1025 | * Return the programmed destination start address in this case. | |
1026 | */ | |
1027 | if (unlikely(!offset)) | |
1028 | offset = p->dma_read(CDSA, lch); | |
1029 | } | |
0499bdeb | 1030 | |
82809601 | 1031 | if (dma_omap1()) |
f31cc962 | 1032 | offset |= (p->dma_read(CDSA, lch) & 0xFFFF0000); |
5e1c5ff4 | 1033 | |
1a8bfa1e | 1034 | return offset; |
5e1c5ff4 | 1035 | } |
97b7f715 | 1036 | EXPORT_SYMBOL(omap_get_dma_dst_pos); |
0499bdeb TL |
1037 | |
1038 | int omap_get_dma_active_status(int lch) | |
1039 | { | |
f31cc962 | 1040 | return (p->dma_read(CCR, lch) & OMAP_DMA_CCR_EN) != 0; |
5e1c5ff4 | 1041 | } |
0499bdeb | 1042 | EXPORT_SYMBOL(omap_get_dma_active_status); |
5e1c5ff4 | 1043 | |
1a8bfa1e | 1044 | int omap_dma_running(void) |
5e1c5ff4 | 1045 | { |
1a8bfa1e | 1046 | int lch; |
5e1c5ff4 | 1047 | |
82809601 | 1048 | if (dma_omap1()) |
f8e9e984 | 1049 | if (omap_lcd_dma_running()) |
1a8bfa1e | 1050 | return 1; |
5e1c5ff4 | 1051 | |
1a8bfa1e | 1052 | for (lch = 0; lch < dma_chan_count; lch++) |
f31cc962 | 1053 | if (p->dma_read(CCR, lch) & OMAP_DMA_CCR_EN) |
1a8bfa1e | 1054 | return 1; |
5e1c5ff4 | 1055 | |
1a8bfa1e | 1056 | return 0; |
5e1c5ff4 TL |
1057 | } |
1058 | ||
1059 | /* | |
1060 | * lch_queue DMA will start right after lch_head one is finished. | |
1061 | * For this DMA link to start, you still need to start (see omap_start_dma) | |
1062 | * the first one. That will fire up the entire queue. | |
1063 | */ | |
97b7f715 | 1064 | void omap_dma_link_lch(int lch_head, int lch_queue) |
5e1c5ff4 TL |
1065 | { |
1066 | if (omap_dma_in_1510_mode()) { | |
9f0f4ae5 | 1067 | if (lch_head == lch_queue) { |
f31cc962 | 1068 | p->dma_write(p->dma_read(CCR, lch_head) | (3 << 8), |
a4c537c7 | 1069 | CCR, lch_head); |
9f0f4ae5 JK |
1070 | return; |
1071 | } | |
5e1c5ff4 TL |
1072 | printk(KERN_ERR "DMA linking is not supported in 1510 mode\n"); |
1073 | BUG(); | |
1074 | return; | |
1075 | } | |
1076 | ||
1077 | if ((dma_chan[lch_head].dev_id == -1) || | |
1078 | (dma_chan[lch_queue].dev_id == -1)) { | |
7852ec05 | 1079 | pr_err("omap_dma: trying to link non requested channels\n"); |
5e1c5ff4 TL |
1080 | dump_stack(); |
1081 | } | |
1082 | ||
1083 | dma_chan[lch_head].next_lch = lch_queue; | |
1084 | } | |
97b7f715 | 1085 | EXPORT_SYMBOL(omap_dma_link_lch); |
5e1c5ff4 | 1086 | |
1a8bfa1e TL |
1087 | /*----------------------------------------------------------------------------*/ |
1088 | ||
1089 | #ifdef CONFIG_ARCH_OMAP1 | |
1090 | ||
1091 | static int omap1_dma_handle_ch(int ch) | |
1092 | { | |
0499bdeb | 1093 | u32 csr; |
1a8bfa1e TL |
1094 | |
1095 | if (enable_1510_mode && ch >= 6) { | |
1096 | csr = dma_chan[ch].saved_csr; | |
1097 | dma_chan[ch].saved_csr = 0; | |
1098 | } else | |
f31cc962 | 1099 | csr = p->dma_read(CSR, ch); |
1a8bfa1e TL |
1100 | if (enable_1510_mode && ch <= 2 && (csr >> 7) != 0) { |
1101 | dma_chan[ch + 6].saved_csr = csr >> 7; | |
1102 | csr &= 0x7f; | |
1103 | } | |
1104 | if ((csr & 0x3f) == 0) | |
1105 | return 0; | |
1106 | if (unlikely(dma_chan[ch].dev_id == -1)) { | |
7852ec05 PW |
1107 | pr_warn("Spurious interrupt from DMA channel %d (CSR %04x)\n", |
1108 | ch, csr); | |
1a8bfa1e TL |
1109 | return 0; |
1110 | } | |
7ff879db | 1111 | if (unlikely(csr & OMAP1_DMA_TOUT_IRQ)) |
7852ec05 | 1112 | pr_warn("DMA timeout with device %d\n", dma_chan[ch].dev_id); |
1a8bfa1e | 1113 | if (unlikely(csr & OMAP_DMA_DROP_IRQ)) |
7852ec05 PW |
1114 | pr_warn("DMA synchronization event drop occurred with device %d\n", |
1115 | dma_chan[ch].dev_id); | |
1a8bfa1e TL |
1116 | if (likely(csr & OMAP_DMA_BLOCK_IRQ)) |
1117 | dma_chan[ch].flags &= ~OMAP_DMA_ACTIVE; | |
1118 | if (likely(dma_chan[ch].callback != NULL)) | |
1119 | dma_chan[ch].callback(ch, csr, dma_chan[ch].data); | |
97b7f715 | 1120 | |
1a8bfa1e TL |
1121 | return 1; |
1122 | } | |
1123 | ||
0cd61b68 | 1124 | static irqreturn_t omap1_dma_irq_handler(int irq, void *dev_id) |
1a8bfa1e TL |
1125 | { |
1126 | int ch = ((int) dev_id) - 1; | |
1127 | int handled = 0; | |
1128 | ||
1129 | for (;;) { | |
1130 | int handled_now = 0; | |
1131 | ||
1132 | handled_now += omap1_dma_handle_ch(ch); | |
1133 | if (enable_1510_mode && dma_chan[ch + 6].saved_csr) | |
1134 | handled_now += omap1_dma_handle_ch(ch + 6); | |
1135 | if (!handled_now) | |
1136 | break; | |
1137 | handled += handled_now; | |
1138 | } | |
1139 | ||
1140 | return handled ? IRQ_HANDLED : IRQ_NONE; | |
1141 | } | |
1142 | ||
1143 | #else | |
1144 | #define omap1_dma_irq_handler NULL | |
1145 | #endif | |
1146 | ||
140455fa | 1147 | #ifdef CONFIG_ARCH_OMAP2PLUS |
1a8bfa1e TL |
1148 | |
1149 | static int omap2_dma_handle_ch(int ch) | |
1150 | { | |
f31cc962 | 1151 | u32 status = p->dma_read(CSR, ch); |
1a8bfa1e | 1152 | |
3151369d JY |
1153 | if (!status) { |
1154 | if (printk_ratelimit()) | |
7852ec05 | 1155 | pr_warn("Spurious DMA IRQ for lch %d\n", ch); |
f31cc962 | 1156 | p->dma_write(1 << ch, IRQSTATUS_L0, ch); |
1a8bfa1e | 1157 | return 0; |
3151369d JY |
1158 | } |
1159 | if (unlikely(dma_chan[ch].dev_id == -1)) { | |
1160 | if (printk_ratelimit()) | |
7852ec05 PW |
1161 | pr_warn("IRQ %04x for non-allocated DMA channel %d\n", |
1162 | status, ch); | |
1a8bfa1e | 1163 | return 0; |
3151369d | 1164 | } |
1a8bfa1e | 1165 | if (unlikely(status & OMAP_DMA_DROP_IRQ)) |
7852ec05 PW |
1166 | pr_info("DMA synchronization event drop occurred with device %d\n", |
1167 | dma_chan[ch].dev_id); | |
a50f18c7 | 1168 | if (unlikely(status & OMAP2_DMA_TRANS_ERR_IRQ)) { |
1a8bfa1e TL |
1169 | printk(KERN_INFO "DMA transaction error with device %d\n", |
1170 | dma_chan[ch].dev_id); | |
d3c9be2f | 1171 | if (IS_DMA_ERRATA(DMA_ERRATA_i378)) { |
a50f18c7 SS |
1172 | u32 ccr; |
1173 | ||
f31cc962 | 1174 | ccr = p->dma_read(CCR, ch); |
a50f18c7 | 1175 | ccr &= ~OMAP_DMA_CCR_EN; |
f31cc962 | 1176 | p->dma_write(ccr, CCR, ch); |
a50f18c7 SS |
1177 | dma_chan[ch].flags &= ~OMAP_DMA_ACTIVE; |
1178 | } | |
1179 | } | |
7ff879db TL |
1180 | if (unlikely(status & OMAP2_DMA_SECURE_ERR_IRQ)) |
1181 | printk(KERN_INFO "DMA secure error with device %d\n", | |
1182 | dma_chan[ch].dev_id); | |
1183 | if (unlikely(status & OMAP2_DMA_MISALIGNED_ERR_IRQ)) | |
1184 | printk(KERN_INFO "DMA misaligned error with device %d\n", | |
1185 | dma_chan[ch].dev_id); | |
1a8bfa1e | 1186 | |
4fb699b4 | 1187 | p->dma_write(status, CSR, ch); |
f31cc962 | 1188 | p->dma_write(1 << ch, IRQSTATUS_L0, ch); |
e860e6da | 1189 | /* read back the register to flush the write */ |
f31cc962 | 1190 | p->dma_read(IRQSTATUS_L0, ch); |
1a8bfa1e | 1191 | |
f8151e5c AG |
1192 | /* If the ch is not chained then chain_id will be -1 */ |
1193 | if (dma_chan[ch].chain_id != -1) { | |
1194 | int chain_id = dma_chan[ch].chain_id; | |
1195 | dma_chan[ch].state = DMA_CH_NOTSTARTED; | |
f31cc962 | 1196 | if (p->dma_read(CLNK_CTRL, ch) & (1 << 15)) |
f8151e5c AG |
1197 | dma_chan[dma_chan[ch].next_linked_ch].state = |
1198 | DMA_CH_STARTED; | |
1199 | if (dma_linked_lch[chain_id].chain_mode == | |
1200 | OMAP_DMA_DYNAMIC_CHAIN) | |
1201 | disable_lnk(ch); | |
1202 | ||
1203 | if (!OMAP_DMA_CHAIN_QEMPTY(chain_id)) | |
1204 | OMAP_DMA_CHAIN_INCQHEAD(chain_id); | |
1205 | ||
f31cc962 | 1206 | status = p->dma_read(CSR, ch); |
4fb699b4 | 1207 | p->dma_write(status, CSR, ch); |
f8151e5c AG |
1208 | } |
1209 | ||
538528de JN |
1210 | if (likely(dma_chan[ch].callback != NULL)) |
1211 | dma_chan[ch].callback(ch, status, dma_chan[ch].data); | |
f8151e5c | 1212 | |
1a8bfa1e TL |
1213 | return 0; |
1214 | } | |
1215 | ||
1216 | /* STATUS register count is from 1-32 while our is 0-31 */ | |
0cd61b68 | 1217 | static irqreturn_t omap2_dma_irq_handler(int irq, void *dev_id) |
1a8bfa1e | 1218 | { |
52176e70 | 1219 | u32 val, enable_reg; |
1a8bfa1e TL |
1220 | int i; |
1221 | ||
f31cc962 | 1222 | val = p->dma_read(IRQSTATUS_L0, 0); |
3151369d JY |
1223 | if (val == 0) { |
1224 | if (printk_ratelimit()) | |
1225 | printk(KERN_WARNING "Spurious DMA IRQ\n"); | |
1226 | return IRQ_HANDLED; | |
1227 | } | |
f31cc962 | 1228 | enable_reg = p->dma_read(IRQENABLE_L0, 0); |
52176e70 | 1229 | val &= enable_reg; /* Dispatch only relevant interrupts */ |
4d96372e | 1230 | for (i = 0; i < dma_lch_count && val != 0; i++) { |
3151369d JY |
1231 | if (val & 1) |
1232 | omap2_dma_handle_ch(i); | |
1233 | val >>= 1; | |
1a8bfa1e TL |
1234 | } |
1235 | ||
1236 | return IRQ_HANDLED; | |
1237 | } | |
1238 | ||
1239 | static struct irqaction omap24xx_dma_irq = { | |
1240 | .name = "DMA", | |
1241 | .handler = omap2_dma_irq_handler, | |
1a8bfa1e TL |
1242 | }; |
1243 | ||
1244 | #else | |
1245 | static struct irqaction omap24xx_dma_irq; | |
1246 | #endif | |
1247 | ||
1248 | /*----------------------------------------------------------------------------*/ | |
5e1c5ff4 | 1249 | |
9ce2482f TL |
1250 | /* |
1251 | * Note that we are currently using only IRQENABLE_L0 and L1. | |
1252 | * As the DSP may be using IRQENABLE_L2 and L3, let's not | |
1253 | * touch those for now. | |
1254 | */ | |
f2d11858 TK |
1255 | void omap_dma_global_context_save(void) |
1256 | { | |
1257 | omap_dma_global_context.dma_irqenable_l0 = | |
f31cc962 | 1258 | p->dma_read(IRQENABLE_L0, 0); |
9ce2482f TL |
1259 | omap_dma_global_context.dma_irqenable_l1 = |
1260 | p->dma_read(IRQENABLE_L1, 0); | |
f2d11858 | 1261 | omap_dma_global_context.dma_ocp_sysconfig = |
f31cc962 MK |
1262 | p->dma_read(OCP_SYSCONFIG, 0); |
1263 | omap_dma_global_context.dma_gcr = p->dma_read(GCR, 0); | |
f2d11858 TK |
1264 | } |
1265 | ||
1266 | void omap_dma_global_context_restore(void) | |
1267 | { | |
bf07c9f2 AK |
1268 | int ch; |
1269 | ||
f31cc962 MK |
1270 | p->dma_write(omap_dma_global_context.dma_gcr, GCR, 0); |
1271 | p->dma_write(omap_dma_global_context.dma_ocp_sysconfig, | |
a4c537c7 | 1272 | OCP_SYSCONFIG, 0); |
f31cc962 | 1273 | p->dma_write(omap_dma_global_context.dma_irqenable_l0, |
a4c537c7 | 1274 | IRQENABLE_L0, 0); |
9ce2482f TL |
1275 | p->dma_write(omap_dma_global_context.dma_irqenable_l1, |
1276 | IRQENABLE_L1, 0); | |
f2d11858 | 1277 | |
d3c9be2f | 1278 | if (IS_DMA_ERRATA(DMA_ROMCODE_BUG)) |
f31cc962 | 1279 | p->dma_write(0x3 , IRQSTATUS_L0, 0); |
bf07c9f2 AK |
1280 | |
1281 | for (ch = 0; ch < dma_chan_count; ch++) | |
1282 | if (dma_chan[ch].dev_id != -1) | |
1283 | omap_clear_dma(ch); | |
f2d11858 TK |
1284 | } |
1285 | ||
1b416c4b RK |
1286 | struct omap_system_dma_plat_info *omap_get_plat_info(void) |
1287 | { | |
1288 | return p; | |
1289 | } | |
1290 | EXPORT_SYMBOL_GPL(omap_get_plat_info); | |
1291 | ||
351a102d | 1292 | static int omap_system_dma_probe(struct platform_device *pdev) |
d3c9be2f | 1293 | { |
f31cc962 MK |
1294 | int ch, ret = 0; |
1295 | int dma_irq; | |
1296 | char irq_name[4]; | |
1297 | int irq_rel; | |
1298 | ||
1299 | p = pdev->dev.platform_data; | |
1300 | if (!p) { | |
7852ec05 PW |
1301 | dev_err(&pdev->dev, |
1302 | "%s: System DMA initialized without platform data\n", | |
1303 | __func__); | |
f31cc962 | 1304 | return -EINVAL; |
0499bdeb | 1305 | } |
4d96372e | 1306 | |
f31cc962 MK |
1307 | d = p->dma_attr; |
1308 | errata = p->errata; | |
a4c537c7 | 1309 | |
f31cc962 | 1310 | if ((d->dev_caps & RESERVE_CHANNEL) && omap_dma_reserve_channels |
e78f9606 | 1311 | && (omap_dma_reserve_channels < d->lch_count)) |
f31cc962 | 1312 | d->lch_count = omap_dma_reserve_channels; |
2263f022 | 1313 | |
f31cc962 MK |
1314 | dma_lch_count = d->lch_count; |
1315 | dma_chan_count = dma_lch_count; | |
f31cc962 | 1316 | enable_1510_mode = d->dev_caps & ENABLE_1510_MODE; |
4d96372e | 1317 | |
9834f813 | 1318 | dma_chan = devm_kcalloc(&pdev->dev, dma_lch_count, |
16e7ea53 | 1319 | sizeof(*dma_chan), GFP_KERNEL); |
d679950c | 1320 | if (!dma_chan) |
9834f813 | 1321 | return -ENOMEM; |
9834f813 | 1322 | |
82809601 | 1323 | if (dma_omap2plus()) { |
738c985d ME |
1324 | dma_linked_lch = kcalloc(dma_lch_count, |
1325 | sizeof(*dma_linked_lch), | |
1326 | GFP_KERNEL); | |
4d96372e | 1327 | if (!dma_linked_lch) { |
f31cc962 MK |
1328 | ret = -ENOMEM; |
1329 | goto exit_dma_lch_fail; | |
4d96372e TL |
1330 | } |
1331 | } | |
1332 | ||
5e1c5ff4 | 1333 | spin_lock_init(&dma_chan_lock); |
5e1c5ff4 | 1334 | for (ch = 0; ch < dma_chan_count; ch++) { |
1a8bfa1e | 1335 | omap_clear_dma(ch); |
82809601 | 1336 | if (dma_omap2plus()) |
ada8d4a5 MW |
1337 | omap2_disable_irq_lch(ch); |
1338 | ||
5e1c5ff4 TL |
1339 | dma_chan[ch].dev_id = -1; |
1340 | dma_chan[ch].next_lch = -1; | |
1341 | ||
1342 | if (ch >= 6 && enable_1510_mode) | |
1343 | continue; | |
1344 | ||
82809601 | 1345 | if (dma_omap1()) { |
97b7f715 TL |
1346 | /* |
1347 | * request_irq() doesn't like dev_id (ie. ch) being | |
1348 | * zero, so we have to kludge around this. | |
1349 | */ | |
f31cc962 MK |
1350 | sprintf(&irq_name[0], "%d", ch); |
1351 | dma_irq = platform_get_irq_byname(pdev, irq_name); | |
1352 | ||
1353 | if (dma_irq < 0) { | |
1354 | ret = dma_irq; | |
1355 | goto exit_dma_irq_fail; | |
1356 | } | |
1357 | ||
1358 | /* INT_DMA_LCD is handled in lcd_dma.c */ | |
1359 | if (dma_irq == INT_DMA_LCD) | |
1360 | continue; | |
1361 | ||
1362 | ret = request_irq(dma_irq, | |
1a8bfa1e TL |
1363 | omap1_dma_irq_handler, 0, "DMA", |
1364 | (void *) (ch + 1)); | |
f31cc962 MK |
1365 | if (ret != 0) |
1366 | goto exit_dma_irq_fail; | |
1a8bfa1e TL |
1367 | } |
1368 | } | |
1369 | ||
82809601 | 1370 | if (d->dev_caps & IS_RW_PRIORITY) |
f8151e5c AG |
1371 | omap_dma_set_global_params(DMA_DEFAULT_ARB_RATE, |
1372 | DMA_DEFAULT_FIFO_DEPTH, 0); | |
1373 | ||
76be4a54 | 1374 | if (dma_omap2plus() && !(d->dev_caps & DMA_ENGINE_HANDLE_IRQ)) { |
f31cc962 MK |
1375 | strcpy(irq_name, "0"); |
1376 | dma_irq = platform_get_irq_byname(pdev, irq_name); | |
1377 | if (dma_irq < 0) { | |
1378 | dev_err(&pdev->dev, "failed: request IRQ %d", dma_irq); | |
94b1d617 | 1379 | ret = dma_irq; |
f31cc962 MK |
1380 | goto exit_dma_lch_fail; |
1381 | } | |
1382 | ret = setup_irq(dma_irq, &omap24xx_dma_irq); | |
1383 | if (ret) { | |
7852ec05 PW |
1384 | dev_err(&pdev->dev, "set_up failed for IRQ %d for DMA (error %d)\n", |
1385 | dma_irq, ret); | |
f31cc962 | 1386 | goto exit_dma_lch_fail; |
ba50ea7e | 1387 | } |
aecedb94 KJ |
1388 | } |
1389 | ||
82809601 TL |
1390 | /* reserve dma channels 0 and 1 in high security devices on 34xx */ |
1391 | if (d->dev_caps & HS_CHANNELS_RESERVED) { | |
7852ec05 | 1392 | pr_info("Reserving DMA channels 0 and 1 for HS ROM code\n"); |
f31cc962 MK |
1393 | dma_chan[0].dev_id = 0; |
1394 | dma_chan[1].dev_id = 1; | |
1395 | } | |
1396 | p->show_dma_caps(); | |
5e1c5ff4 | 1397 | return 0; |
7e9bf847 | 1398 | |
f31cc962 | 1399 | exit_dma_irq_fail: |
7852ec05 PW |
1400 | dev_err(&pdev->dev, "unable to request IRQ %d for DMA (error %d)\n", |
1401 | dma_irq, ret); | |
f31cc962 MK |
1402 | for (irq_rel = 0; irq_rel < ch; irq_rel++) { |
1403 | dma_irq = platform_get_irq(pdev, irq_rel); | |
1404 | free_irq(dma_irq, (void *)(irq_rel + 1)); | |
1405 | } | |
1406 | ||
1407 | exit_dma_lch_fail: | |
f31cc962 MK |
1408 | return ret; |
1409 | } | |
7e9bf847 | 1410 | |
351a102d | 1411 | static int omap_system_dma_remove(struct platform_device *pdev) |
f31cc962 MK |
1412 | { |
1413 | int dma_irq; | |
7e9bf847 | 1414 | |
82809601 | 1415 | if (dma_omap2plus()) { |
f31cc962 MK |
1416 | char irq_name[4]; |
1417 | strcpy(irq_name, "0"); | |
1418 | dma_irq = platform_get_irq_byname(pdev, irq_name); | |
76be4a54 NM |
1419 | if (dma_irq >= 0) |
1420 | remove_irq(dma_irq, &omap24xx_dma_irq); | |
f31cc962 MK |
1421 | } else { |
1422 | int irq_rel = 0; | |
1423 | for ( ; irq_rel < dma_chan_count; irq_rel++) { | |
1424 | dma_irq = platform_get_irq(pdev, irq_rel); | |
1425 | free_irq(dma_irq, (void *)(irq_rel + 1)); | |
1426 | } | |
1427 | } | |
f31cc962 MK |
1428 | return 0; |
1429 | } | |
1430 | ||
1431 | static struct platform_driver omap_system_dma_driver = { | |
1432 | .probe = omap_system_dma_probe, | |
351a102d | 1433 | .remove = omap_system_dma_remove, |
f31cc962 MK |
1434 | .driver = { |
1435 | .name = "omap_dma_system" | |
1436 | }, | |
1437 | }; | |
1438 | ||
1439 | static int __init omap_system_dma_init(void) | |
1440 | { | |
1441 | return platform_driver_register(&omap_system_dma_driver); | |
1442 | } | |
1443 | arch_initcall(omap_system_dma_init); | |
1444 | ||
1445 | static void __exit omap_system_dma_exit(void) | |
1446 | { | |
1447 | platform_driver_unregister(&omap_system_dma_driver); | |
5e1c5ff4 TL |
1448 | } |
1449 | ||
f31cc962 MK |
1450 | MODULE_DESCRIPTION("OMAP SYSTEM DMA DRIVER"); |
1451 | MODULE_LICENSE("GPL"); | |
f31cc962 | 1452 | MODULE_AUTHOR("Texas Instruments Inc"); |
5e1c5ff4 | 1453 | |
2263f022 SS |
1454 | /* |
1455 | * Reserve the omap SDMA channels using cmdline bootarg | |
1456 | * "omap_dma_reserve_ch=". The valid range is 1 to 32 | |
1457 | */ | |
1458 | static int __init omap_dma_cmdline_reserve_ch(char *str) | |
1459 | { | |
1460 | if (get_option(&str, &omap_dma_reserve_channels) != 1) | |
1461 | omap_dma_reserve_channels = 0; | |
1462 | return 1; | |
1463 | } | |
1464 | ||
1465 | __setup("omap_dma_reserve_ch=", omap_dma_cmdline_reserve_ch); | |
1466 | ||
5e1c5ff4 | 1467 |