Commit | Line | Data |
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5e1c5ff4 TL |
1 | /* |
2 | * linux/arch/arm/plat-omap/dma.c | |
3 | * | |
97b7f715 | 4 | * Copyright (C) 2003 - 2008 Nokia Corporation |
96de0e25 | 5 | * Author: Juha Yrjölä <juha.yrjola@nokia.com> |
5e1c5ff4 TL |
6 | * DMA channel linking for 1610 by Samuel Ortiz <samuel.ortiz@nokia.com> |
7 | * Graphics DMA and LCD DMA graphics tranformations | |
8 | * by Imre Deak <imre.deak@nokia.com> | |
f8151e5c | 9 | * OMAP2/3 support Copyright (C) 2004-2007 Texas Instruments, Inc. |
1a8bfa1e | 10 | * Merged to support both OMAP1 and OMAP2 by Tony Lindgren <tony@atomide.com> |
5e1c5ff4 TL |
11 | * Some functions based on earlier dma-omap.c Copyright (C) 2001 RidgeRun, Inc. |
12 | * | |
44169075 SS |
13 | * Copyright (C) 2009 Texas Instruments |
14 | * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com> | |
15 | * | |
5e1c5ff4 TL |
16 | * Support functions for the OMAP internal DMA channels. |
17 | * | |
f31cc962 MK |
18 | * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/ |
19 | * Converted DMA library into DMA platform driver. | |
20 | * - G, Manjunath Kondaiah <manjugk@ti.com> | |
21 | * | |
5e1c5ff4 TL |
22 | * This program is free software; you can redistribute it and/or modify |
23 | * it under the terms of the GNU General Public License version 2 as | |
24 | * published by the Free Software Foundation. | |
25 | * | |
26 | */ | |
27 | ||
28 | #include <linux/module.h> | |
29 | #include <linux/init.h> | |
30 | #include <linux/sched.h> | |
31 | #include <linux/spinlock.h> | |
32 | #include <linux/errno.h> | |
33 | #include <linux/interrupt.h> | |
418ca1f0 | 34 | #include <linux/irq.h> |
97b7f715 | 35 | #include <linux/io.h> |
5a0e3ad6 | 36 | #include <linux/slab.h> |
0e4905c0 | 37 | #include <linux/delay.h> |
5e1c5ff4 | 38 | |
45c3eb7d | 39 | #include <linux/omap-dma.h> |
5e1c5ff4 | 40 | |
bc4d8b5f PW |
41 | /* |
42 | * MAX_LOGICAL_DMA_CH_COUNT: the maximum number of logical DMA | |
43 | * channels that an instance of the SDMA IP block can support. Used | |
44 | * to size arrays. (The actual maximum on a particular SoC may be less | |
45 | * than this -- for example, OMAP1 SDMA instances only support 17 logical | |
46 | * DMA channels.) | |
47 | */ | |
48 | #define MAX_LOGICAL_DMA_CH_COUNT 32 | |
49 | ||
f8151e5c AG |
50 | #undef DEBUG |
51 | ||
52 | #ifndef CONFIG_ARCH_OMAP1 | |
53 | enum { DMA_CH_ALLOC_DONE, DMA_CH_PARAMS_SET_DONE, DMA_CH_STARTED, | |
54 | DMA_CH_QUEUED, DMA_CH_NOTSTARTED, DMA_CH_PAUSED, DMA_CH_LINK_ENABLED | |
55 | }; | |
56 | ||
57 | enum { DMA_CHAIN_STARTED, DMA_CHAIN_NOTSTARTED }; | |
1a8bfa1e | 58 | #endif |
5e1c5ff4 | 59 | |
97b7f715 | 60 | #define OMAP_DMA_ACTIVE 0x01 |
4fb699b4 | 61 | #define OMAP2_DMA_CSR_CLEAR_MASK 0xffffffff |
5e1c5ff4 | 62 | |
97b7f715 | 63 | #define OMAP_FUNC_MUX_ARM_BASE (0xfffe1000 + 0xec) |
5e1c5ff4 | 64 | |
f31cc962 MK |
65 | static struct omap_system_dma_plat_info *p; |
66 | static struct omap_dma_dev_attr *d; | |
175655bd TL |
67 | static void omap_clear_dma(int lch); |
68 | static int omap_dma_set_prio_lch(int lch, unsigned char read_prio, | |
69 | unsigned char write_prio); | |
97b7f715 | 70 | static int enable_1510_mode; |
d3c9be2f | 71 | static u32 errata; |
5e1c5ff4 | 72 | |
f2d11858 TK |
73 | static struct omap_dma_global_context_registers { |
74 | u32 dma_irqenable_l0; | |
9ce2482f | 75 | u32 dma_irqenable_l1; |
f2d11858 TK |
76 | u32 dma_ocp_sysconfig; |
77 | u32 dma_gcr; | |
78 | } omap_dma_global_context; | |
79 | ||
f8151e5c AG |
80 | struct dma_link_info { |
81 | int *linked_dmach_q; | |
82 | int no_of_lchs_linked; | |
83 | ||
84 | int q_count; | |
85 | int q_tail; | |
86 | int q_head; | |
87 | ||
88 | int chain_state; | |
89 | int chain_mode; | |
90 | ||
91 | }; | |
92 | ||
4d96372e TL |
93 | static struct dma_link_info *dma_linked_lch; |
94 | ||
95 | #ifndef CONFIG_ARCH_OMAP1 | |
f8151e5c AG |
96 | |
97 | /* Chain handling macros */ | |
98 | #define OMAP_DMA_CHAIN_QINIT(chain_id) \ | |
99 | do { \ | |
100 | dma_linked_lch[chain_id].q_head = \ | |
101 | dma_linked_lch[chain_id].q_tail = \ | |
102 | dma_linked_lch[chain_id].q_count = 0; \ | |
103 | } while (0) | |
104 | #define OMAP_DMA_CHAIN_QFULL(chain_id) \ | |
105 | (dma_linked_lch[chain_id].no_of_lchs_linked == \ | |
106 | dma_linked_lch[chain_id].q_count) | |
107 | #define OMAP_DMA_CHAIN_QLAST(chain_id) \ | |
108 | do { \ | |
109 | ((dma_linked_lch[chain_id].no_of_lchs_linked-1) == \ | |
110 | dma_linked_lch[chain_id].q_count) \ | |
111 | } while (0) | |
112 | #define OMAP_DMA_CHAIN_QEMPTY(chain_id) \ | |
113 | (0 == dma_linked_lch[chain_id].q_count) | |
114 | #define __OMAP_DMA_CHAIN_INCQ(end) \ | |
115 | ((end) = ((end)+1) % dma_linked_lch[chain_id].no_of_lchs_linked) | |
116 | #define OMAP_DMA_CHAIN_INCQHEAD(chain_id) \ | |
117 | do { \ | |
118 | __OMAP_DMA_CHAIN_INCQ(dma_linked_lch[chain_id].q_head); \ | |
119 | dma_linked_lch[chain_id].q_count--; \ | |
120 | } while (0) | |
121 | ||
122 | #define OMAP_DMA_CHAIN_INCQTAIL(chain_id) \ | |
123 | do { \ | |
124 | __OMAP_DMA_CHAIN_INCQ(dma_linked_lch[chain_id].q_tail); \ | |
125 | dma_linked_lch[chain_id].q_count++; \ | |
126 | } while (0) | |
127 | #endif | |
4d96372e TL |
128 | |
129 | static int dma_lch_count; | |
5e1c5ff4 | 130 | static int dma_chan_count; |
2263f022 | 131 | static int omap_dma_reserve_channels; |
5e1c5ff4 TL |
132 | |
133 | static spinlock_t dma_chan_lock; | |
4d96372e | 134 | static struct omap_dma_lch *dma_chan; |
5e1c5ff4 | 135 | |
f8151e5c AG |
136 | static inline void disable_lnk(int lch); |
137 | static void omap_disable_channel_irq(int lch); | |
138 | static inline void omap_enable_channel_irq(int lch); | |
139 | ||
1a8bfa1e | 140 | #define REVISIT_24XX() printk(KERN_ERR "FIXME: no %s on 24xx\n", \ |
8e86f427 | 141 | __func__); |
1a8bfa1e TL |
142 | |
143 | #ifdef CONFIG_ARCH_OMAP15XX | |
144 | /* Returns 1 if the DMA module is in OMAP1510-compatible mode, 0 otherwise */ | |
c7767582 | 145 | static int omap_dma_in_1510_mode(void) |
1a8bfa1e TL |
146 | { |
147 | return enable_1510_mode; | |
148 | } | |
149 | #else | |
150 | #define omap_dma_in_1510_mode() 0 | |
151 | #endif | |
152 | ||
153 | #ifdef CONFIG_ARCH_OMAP1 | |
5e1c5ff4 TL |
154 | static inline int get_gdma_dev(int req) |
155 | { | |
156 | u32 reg = OMAP_FUNC_MUX_ARM_BASE + ((req - 1) / 5) * 4; | |
157 | int shift = ((req - 1) % 5) * 6; | |
158 | ||
159 | return ((omap_readl(reg) >> shift) & 0x3f) + 1; | |
160 | } | |
161 | ||
162 | static inline void set_gdma_dev(int req, int dev) | |
163 | { | |
164 | u32 reg = OMAP_FUNC_MUX_ARM_BASE + ((req - 1) / 5) * 4; | |
165 | int shift = ((req - 1) % 5) * 6; | |
166 | u32 l; | |
167 | ||
168 | l = omap_readl(reg); | |
169 | l &= ~(0x3f << shift); | |
170 | l |= (dev - 1) << shift; | |
171 | omap_writel(l, reg); | |
172 | } | |
1a8bfa1e TL |
173 | #else |
174 | #define set_gdma_dev(req, dev) do {} while (0) | |
2c799cef TL |
175 | #define omap_readl(reg) 0 |
176 | #define omap_writel(val, reg) do {} while (0) | |
1a8bfa1e | 177 | #endif |
5e1c5ff4 | 178 | |
54b693d4 | 179 | #ifdef CONFIG_ARCH_OMAP1 |
709eb3e5 | 180 | void omap_set_dma_priority(int lch, int dst_port, int priority) |
5e1c5ff4 TL |
181 | { |
182 | unsigned long reg; | |
183 | u32 l; | |
184 | ||
82809601 | 185 | if (dma_omap1()) { |
709eb3e5 TL |
186 | switch (dst_port) { |
187 | case OMAP_DMA_PORT_OCP_T1: /* FFFECC00 */ | |
188 | reg = OMAP_TC_OCPT1_PRIOR; | |
189 | break; | |
190 | case OMAP_DMA_PORT_OCP_T2: /* FFFECCD0 */ | |
191 | reg = OMAP_TC_OCPT2_PRIOR; | |
192 | break; | |
193 | case OMAP_DMA_PORT_EMIFF: /* FFFECC08 */ | |
194 | reg = OMAP_TC_EMIFF_PRIOR; | |
195 | break; | |
196 | case OMAP_DMA_PORT_EMIFS: /* FFFECC04 */ | |
197 | reg = OMAP_TC_EMIFS_PRIOR; | |
198 | break; | |
199 | default: | |
200 | BUG(); | |
201 | return; | |
202 | } | |
203 | l = omap_readl(reg); | |
204 | l &= ~(0xf << 8); | |
205 | l |= (priority & 0xf) << 8; | |
206 | omap_writel(l, reg); | |
207 | } | |
54b693d4 TL |
208 | } |
209 | #endif | |
709eb3e5 | 210 | |
54b693d4 TL |
211 | #ifdef CONFIG_ARCH_OMAP2PLUS |
212 | void omap_set_dma_priority(int lch, int dst_port, int priority) | |
213 | { | |
214 | u32 ccr; | |
215 | ||
216 | ccr = p->dma_read(CCR, lch); | |
217 | if (priority) | |
218 | ccr |= (1 << 6); | |
219 | else | |
220 | ccr &= ~(1 << 6); | |
221 | p->dma_write(ccr, CCR, lch); | |
5e1c5ff4 | 222 | } |
54b693d4 | 223 | #endif |
97b7f715 | 224 | EXPORT_SYMBOL(omap_set_dma_priority); |
5e1c5ff4 TL |
225 | |
226 | void omap_set_dma_transfer_params(int lch, int data_type, int elem_count, | |
1a8bfa1e TL |
227 | int frame_count, int sync_mode, |
228 | int dma_trigger, int src_or_dst_synch) | |
5e1c5ff4 | 229 | { |
0499bdeb TL |
230 | u32 l; |
231 | ||
f31cc962 | 232 | l = p->dma_read(CSDP, lch); |
0499bdeb TL |
233 | l &= ~0x03; |
234 | l |= data_type; | |
f31cc962 | 235 | p->dma_write(l, CSDP, lch); |
5e1c5ff4 | 236 | |
82809601 | 237 | if (dma_omap1()) { |
0499bdeb TL |
238 | u16 ccr; |
239 | ||
f31cc962 | 240 | ccr = p->dma_read(CCR, lch); |
0499bdeb | 241 | ccr &= ~(1 << 5); |
1a8bfa1e | 242 | if (sync_mode == OMAP_DMA_SYNC_FRAME) |
0499bdeb | 243 | ccr |= 1 << 5; |
f31cc962 | 244 | p->dma_write(ccr, CCR, lch); |
1a8bfa1e | 245 | |
f31cc962 | 246 | ccr = p->dma_read(CCR2, lch); |
0499bdeb | 247 | ccr &= ~(1 << 2); |
1a8bfa1e | 248 | if (sync_mode == OMAP_DMA_SYNC_BLOCK) |
0499bdeb | 249 | ccr |= 1 << 2; |
f31cc962 | 250 | p->dma_write(ccr, CCR2, lch); |
1a8bfa1e TL |
251 | } |
252 | ||
82809601 | 253 | if (dma_omap2plus() && dma_trigger) { |
0499bdeb | 254 | u32 val; |
1a8bfa1e | 255 | |
f31cc962 | 256 | val = p->dma_read(CCR, lch); |
4b3cf448 AG |
257 | |
258 | /* DMA_SYNCHRO_CONTROL_UPPER depends on the channel number */ | |
72a1179e | 259 | val &= ~((1 << 23) | (3 << 19) | 0x1f); |
4b3cf448 AG |
260 | val |= (dma_trigger & ~0x1f) << 14; |
261 | val |= dma_trigger & 0x1f; | |
5e1c5ff4 | 262 | |
1a8bfa1e TL |
263 | if (sync_mode & OMAP_DMA_SYNC_FRAME) |
264 | val |= 1 << 5; | |
eca9e56e PU |
265 | else |
266 | val &= ~(1 << 5); | |
5e1c5ff4 | 267 | |
1a8bfa1e TL |
268 | if (sync_mode & OMAP_DMA_SYNC_BLOCK) |
269 | val |= 1 << 18; | |
eca9e56e PU |
270 | else |
271 | val &= ~(1 << 18); | |
5e1c5ff4 | 272 | |
72a1179e SO |
273 | if (src_or_dst_synch == OMAP_DMA_DST_SYNC_PREFETCH) { |
274 | val &= ~(1 << 24); /* dest synch */ | |
275 | val |= (1 << 23); /* Prefetch */ | |
276 | } else if (src_or_dst_synch) { | |
1a8bfa1e | 277 | val |= 1 << 24; /* source synch */ |
72a1179e | 278 | } else { |
1a8bfa1e | 279 | val &= ~(1 << 24); /* dest synch */ |
72a1179e | 280 | } |
f31cc962 | 281 | p->dma_write(val, CCR, lch); |
1a8bfa1e TL |
282 | } |
283 | ||
f31cc962 MK |
284 | p->dma_write(elem_count, CEN, lch); |
285 | p->dma_write(frame_count, CFN, lch); | |
5e1c5ff4 | 286 | } |
97b7f715 | 287 | EXPORT_SYMBOL(omap_set_dma_transfer_params); |
1a8bfa1e | 288 | |
709eb3e5 TL |
289 | void omap_set_dma_write_mode(int lch, enum omap_dma_write_mode mode) |
290 | { | |
82809601 | 291 | if (dma_omap2plus()) { |
0499bdeb TL |
292 | u32 csdp; |
293 | ||
f31cc962 | 294 | csdp = p->dma_read(CSDP, lch); |
0499bdeb TL |
295 | csdp &= ~(0x3 << 16); |
296 | csdp |= (mode << 16); | |
f31cc962 | 297 | p->dma_write(csdp, CSDP, lch); |
709eb3e5 TL |
298 | } |
299 | } | |
97b7f715 | 300 | EXPORT_SYMBOL(omap_set_dma_write_mode); |
709eb3e5 | 301 | |
0499bdeb TL |
302 | void omap_set_dma_channel_mode(int lch, enum omap_dma_channel_mode mode) |
303 | { | |
82809601 | 304 | if (dma_omap1() && !dma_omap15xx()) { |
0499bdeb TL |
305 | u32 l; |
306 | ||
f31cc962 | 307 | l = p->dma_read(LCH_CTRL, lch); |
0499bdeb TL |
308 | l &= ~0x7; |
309 | l |= mode; | |
f31cc962 | 310 | p->dma_write(l, LCH_CTRL, lch); |
0499bdeb TL |
311 | } |
312 | } | |
313 | EXPORT_SYMBOL(omap_set_dma_channel_mode); | |
314 | ||
1a8bfa1e | 315 | /* Note that src_port is only for omap1 */ |
5e1c5ff4 | 316 | void omap_set_dma_src_params(int lch, int src_port, int src_amode, |
1a8bfa1e TL |
317 | unsigned long src_start, |
318 | int src_ei, int src_fi) | |
5e1c5ff4 | 319 | { |
97b7f715 TL |
320 | u32 l; |
321 | ||
82809601 | 322 | if (dma_omap1()) { |
0499bdeb | 323 | u16 w; |
1a8bfa1e | 324 | |
f31cc962 | 325 | w = p->dma_read(CSDP, lch); |
0499bdeb TL |
326 | w &= ~(0x1f << 2); |
327 | w |= src_port << 2; | |
f31cc962 | 328 | p->dma_write(w, CSDP, lch); |
97b7f715 | 329 | } |
1a8bfa1e | 330 | |
f31cc962 | 331 | l = p->dma_read(CCR, lch); |
97b7f715 TL |
332 | l &= ~(0x03 << 12); |
333 | l |= src_amode << 12; | |
f31cc962 | 334 | p->dma_write(l, CCR, lch); |
0499bdeb | 335 | |
f31cc962 | 336 | p->dma_write(src_start, CSSA, lch); |
5e1c5ff4 | 337 | |
f31cc962 MK |
338 | p->dma_write(src_ei, CSEI, lch); |
339 | p->dma_write(src_fi, CSFI, lch); | |
1a8bfa1e | 340 | } |
97b7f715 | 341 | EXPORT_SYMBOL(omap_set_dma_src_params); |
5e1c5ff4 | 342 | |
97b7f715 | 343 | void omap_set_dma_params(int lch, struct omap_dma_channel_params *params) |
1a8bfa1e TL |
344 | { |
345 | omap_set_dma_transfer_params(lch, params->data_type, | |
346 | params->elem_count, params->frame_count, | |
347 | params->sync_mode, params->trigger, | |
348 | params->src_or_dst_synch); | |
349 | omap_set_dma_src_params(lch, params->src_port, | |
350 | params->src_amode, params->src_start, | |
351 | params->src_ei, params->src_fi); | |
352 | ||
353 | omap_set_dma_dest_params(lch, params->dst_port, | |
354 | params->dst_amode, params->dst_start, | |
355 | params->dst_ei, params->dst_fi); | |
f8151e5c AG |
356 | if (params->read_prio || params->write_prio) |
357 | omap_dma_set_prio_lch(lch, params->read_prio, | |
358 | params->write_prio); | |
5e1c5ff4 | 359 | } |
97b7f715 | 360 | EXPORT_SYMBOL(omap_set_dma_params); |
5e1c5ff4 | 361 | |
5e1c5ff4 TL |
362 | void omap_set_dma_src_data_pack(int lch, int enable) |
363 | { | |
0499bdeb TL |
364 | u32 l; |
365 | ||
f31cc962 | 366 | l = p->dma_read(CSDP, lch); |
0499bdeb | 367 | l &= ~(1 << 6); |
1a8bfa1e | 368 | if (enable) |
0499bdeb | 369 | l |= (1 << 6); |
f31cc962 | 370 | p->dma_write(l, CSDP, lch); |
5e1c5ff4 | 371 | } |
97b7f715 | 372 | EXPORT_SYMBOL(omap_set_dma_src_data_pack); |
5e1c5ff4 TL |
373 | |
374 | void omap_set_dma_src_burst_mode(int lch, enum omap_dma_burst_mode burst_mode) | |
375 | { | |
6dc3c8f2 | 376 | unsigned int burst = 0; |
0499bdeb TL |
377 | u32 l; |
378 | ||
f31cc962 | 379 | l = p->dma_read(CSDP, lch); |
0499bdeb | 380 | l &= ~(0x03 << 7); |
5e1c5ff4 | 381 | |
5e1c5ff4 TL |
382 | switch (burst_mode) { |
383 | case OMAP_DMA_DATA_BURST_DIS: | |
384 | break; | |
385 | case OMAP_DMA_DATA_BURST_4: | |
82809601 | 386 | if (dma_omap2plus()) |
6dc3c8f2 KP |
387 | burst = 0x1; |
388 | else | |
389 | burst = 0x2; | |
5e1c5ff4 TL |
390 | break; |
391 | case OMAP_DMA_DATA_BURST_8: | |
82809601 | 392 | if (dma_omap2plus()) { |
6dc3c8f2 KP |
393 | burst = 0x2; |
394 | break; | |
395 | } | |
ea221a6a | 396 | /* |
397 | * not supported by current hardware on OMAP1 | |
5e1c5ff4 TL |
398 | * w |= (0x03 << 7); |
399 | * fall through | |
400 | */ | |
6dc3c8f2 | 401 | case OMAP_DMA_DATA_BURST_16: |
82809601 | 402 | if (dma_omap2plus()) { |
6dc3c8f2 KP |
403 | burst = 0x3; |
404 | break; | |
405 | } | |
ea221a6a | 406 | /* |
407 | * OMAP1 don't support burst 16 | |
6dc3c8f2 KP |
408 | * fall through |
409 | */ | |
5e1c5ff4 TL |
410 | default: |
411 | BUG(); | |
412 | } | |
0499bdeb TL |
413 | |
414 | l |= (burst << 7); | |
f31cc962 | 415 | p->dma_write(l, CSDP, lch); |
5e1c5ff4 | 416 | } |
97b7f715 | 417 | EXPORT_SYMBOL(omap_set_dma_src_burst_mode); |
5e1c5ff4 | 418 | |
1a8bfa1e | 419 | /* Note that dest_port is only for OMAP1 */ |
5e1c5ff4 | 420 | void omap_set_dma_dest_params(int lch, int dest_port, int dest_amode, |
1a8bfa1e TL |
421 | unsigned long dest_start, |
422 | int dst_ei, int dst_fi) | |
5e1c5ff4 | 423 | { |
0499bdeb TL |
424 | u32 l; |
425 | ||
82809601 | 426 | if (dma_omap1()) { |
f31cc962 | 427 | l = p->dma_read(CSDP, lch); |
0499bdeb TL |
428 | l &= ~(0x1f << 9); |
429 | l |= dest_port << 9; | |
f31cc962 | 430 | p->dma_write(l, CSDP, lch); |
1a8bfa1e | 431 | } |
5e1c5ff4 | 432 | |
f31cc962 | 433 | l = p->dma_read(CCR, lch); |
0499bdeb TL |
434 | l &= ~(0x03 << 14); |
435 | l |= dest_amode << 14; | |
f31cc962 | 436 | p->dma_write(l, CCR, lch); |
5e1c5ff4 | 437 | |
f31cc962 | 438 | p->dma_write(dest_start, CDSA, lch); |
5e1c5ff4 | 439 | |
f31cc962 MK |
440 | p->dma_write(dst_ei, CDEI, lch); |
441 | p->dma_write(dst_fi, CDFI, lch); | |
5e1c5ff4 | 442 | } |
97b7f715 | 443 | EXPORT_SYMBOL(omap_set_dma_dest_params); |
5e1c5ff4 | 444 | |
5e1c5ff4 TL |
445 | void omap_set_dma_dest_data_pack(int lch, int enable) |
446 | { | |
0499bdeb TL |
447 | u32 l; |
448 | ||
f31cc962 | 449 | l = p->dma_read(CSDP, lch); |
0499bdeb | 450 | l &= ~(1 << 13); |
1a8bfa1e | 451 | if (enable) |
0499bdeb | 452 | l |= 1 << 13; |
f31cc962 | 453 | p->dma_write(l, CSDP, lch); |
5e1c5ff4 | 454 | } |
97b7f715 | 455 | EXPORT_SYMBOL(omap_set_dma_dest_data_pack); |
5e1c5ff4 TL |
456 | |
457 | void omap_set_dma_dest_burst_mode(int lch, enum omap_dma_burst_mode burst_mode) | |
458 | { | |
6dc3c8f2 | 459 | unsigned int burst = 0; |
0499bdeb TL |
460 | u32 l; |
461 | ||
f31cc962 | 462 | l = p->dma_read(CSDP, lch); |
0499bdeb | 463 | l &= ~(0x03 << 14); |
5e1c5ff4 | 464 | |
5e1c5ff4 TL |
465 | switch (burst_mode) { |
466 | case OMAP_DMA_DATA_BURST_DIS: | |
467 | break; | |
468 | case OMAP_DMA_DATA_BURST_4: | |
82809601 | 469 | if (dma_omap2plus()) |
6dc3c8f2 KP |
470 | burst = 0x1; |
471 | else | |
472 | burst = 0x2; | |
5e1c5ff4 TL |
473 | break; |
474 | case OMAP_DMA_DATA_BURST_8: | |
82809601 | 475 | if (dma_omap2plus()) |
6dc3c8f2 KP |
476 | burst = 0x2; |
477 | else | |
478 | burst = 0x3; | |
5e1c5ff4 | 479 | break; |
6dc3c8f2 | 480 | case OMAP_DMA_DATA_BURST_16: |
82809601 | 481 | if (dma_omap2plus()) { |
6dc3c8f2 KP |
482 | burst = 0x3; |
483 | break; | |
484 | } | |
ea221a6a | 485 | /* |
486 | * OMAP1 don't support burst 16 | |
6dc3c8f2 KP |
487 | * fall through |
488 | */ | |
5e1c5ff4 TL |
489 | default: |
490 | printk(KERN_ERR "Invalid DMA burst mode\n"); | |
491 | BUG(); | |
492 | return; | |
493 | } | |
0499bdeb | 494 | l |= (burst << 14); |
f31cc962 | 495 | p->dma_write(l, CSDP, lch); |
5e1c5ff4 | 496 | } |
97b7f715 | 497 | EXPORT_SYMBOL(omap_set_dma_dest_burst_mode); |
5e1c5ff4 | 498 | |
1a8bfa1e | 499 | static inline void omap_enable_channel_irq(int lch) |
5e1c5ff4 | 500 | { |
7ff879db | 501 | /* Clear CSR */ |
82809601 | 502 | if (dma_omap1()) |
bedfb7ad OM |
503 | p->dma_read(CSR, lch); |
504 | else | |
f31cc962 | 505 | p->dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR, lch); |
1a8bfa1e | 506 | |
5e1c5ff4 | 507 | /* Enable some nice interrupts. */ |
f31cc962 | 508 | p->dma_write(dma_chan[lch].enabled_irqs, CICR, lch); |
5e1c5ff4 TL |
509 | } |
510 | ||
bedfb7ad | 511 | static inline void omap_disable_channel_irq(int lch) |
5e1c5ff4 | 512 | { |
bedfb7ad OM |
513 | /* disable channel interrupts */ |
514 | p->dma_write(0, CICR, lch); | |
515 | /* Clear CSR */ | |
82809601 | 516 | if (dma_omap1()) |
bedfb7ad OM |
517 | p->dma_read(CSR, lch); |
518 | else | |
519 | p->dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR, lch); | |
1a8bfa1e TL |
520 | } |
521 | ||
522 | void omap_enable_dma_irq(int lch, u16 bits) | |
523 | { | |
524 | dma_chan[lch].enabled_irqs |= bits; | |
525 | } | |
97b7f715 | 526 | EXPORT_SYMBOL(omap_enable_dma_irq); |
5e1c5ff4 | 527 | |
1a8bfa1e TL |
528 | void omap_disable_dma_irq(int lch, u16 bits) |
529 | { | |
530 | dma_chan[lch].enabled_irqs &= ~bits; | |
531 | } | |
97b7f715 | 532 | EXPORT_SYMBOL(omap_disable_dma_irq); |
1a8bfa1e TL |
533 | |
534 | static inline void enable_lnk(int lch) | |
535 | { | |
0499bdeb TL |
536 | u32 l; |
537 | ||
f31cc962 | 538 | l = p->dma_read(CLNK_CTRL, lch); |
0499bdeb | 539 | |
82809601 | 540 | if (dma_omap1()) |
0499bdeb | 541 | l &= ~(1 << 14); |
5e1c5ff4 | 542 | |
1a8bfa1e | 543 | /* Set the ENABLE_LNK bits */ |
5e1c5ff4 | 544 | if (dma_chan[lch].next_lch != -1) |
0499bdeb | 545 | l = dma_chan[lch].next_lch | (1 << 15); |
f8151e5c AG |
546 | |
547 | #ifndef CONFIG_ARCH_OMAP1 | |
82809601 | 548 | if (dma_omap2plus()) |
97b7f715 TL |
549 | if (dma_chan[lch].next_linked_ch != -1) |
550 | l = dma_chan[lch].next_linked_ch | (1 << 15); | |
f8151e5c | 551 | #endif |
0499bdeb | 552 | |
f31cc962 | 553 | p->dma_write(l, CLNK_CTRL, lch); |
5e1c5ff4 TL |
554 | } |
555 | ||
556 | static inline void disable_lnk(int lch) | |
557 | { | |
0499bdeb TL |
558 | u32 l; |
559 | ||
f31cc962 | 560 | l = p->dma_read(CLNK_CTRL, lch); |
0499bdeb | 561 | |
5e1c5ff4 | 562 | /* Disable interrupts */ |
bedfb7ad OM |
563 | omap_disable_channel_irq(lch); |
564 | ||
82809601 | 565 | if (dma_omap1()) { |
1a8bfa1e | 566 | /* Set the STOP_LNK bit */ |
0499bdeb | 567 | l |= 1 << 14; |
1a8bfa1e | 568 | } |
5e1c5ff4 | 569 | |
82809601 | 570 | if (dma_omap2plus()) { |
1a8bfa1e | 571 | /* Clear the ENABLE_LNK bit */ |
0499bdeb | 572 | l &= ~(1 << 15); |
1a8bfa1e | 573 | } |
5e1c5ff4 | 574 | |
f31cc962 | 575 | p->dma_write(l, CLNK_CTRL, lch); |
5e1c5ff4 TL |
576 | dma_chan[lch].flags &= ~OMAP_DMA_ACTIVE; |
577 | } | |
578 | ||
1a8bfa1e | 579 | static inline void omap2_enable_irq_lch(int lch) |
5e1c5ff4 | 580 | { |
1a8bfa1e | 581 | u32 val; |
ee907324 | 582 | unsigned long flags; |
1a8bfa1e | 583 | |
82809601 | 584 | if (dma_omap1()) |
1a8bfa1e TL |
585 | return; |
586 | ||
ee907324 | 587 | spin_lock_irqsave(&dma_chan_lock, flags); |
bedfb7ad OM |
588 | /* clear IRQ STATUS */ |
589 | p->dma_write(1 << lch, IRQSTATUS_L0, lch); | |
590 | /* Enable interrupt */ | |
f31cc962 | 591 | val = p->dma_read(IRQENABLE_L0, lch); |
1a8bfa1e | 592 | val |= 1 << lch; |
f31cc962 | 593 | p->dma_write(val, IRQENABLE_L0, lch); |
ee907324 | 594 | spin_unlock_irqrestore(&dma_chan_lock, flags); |
1a8bfa1e TL |
595 | } |
596 | ||
ada8d4a5 MW |
597 | static inline void omap2_disable_irq_lch(int lch) |
598 | { | |
599 | u32 val; | |
600 | unsigned long flags; | |
601 | ||
82809601 | 602 | if (dma_omap1()) |
ada8d4a5 MW |
603 | return; |
604 | ||
605 | spin_lock_irqsave(&dma_chan_lock, flags); | |
bedfb7ad | 606 | /* Disable interrupt */ |
f31cc962 | 607 | val = p->dma_read(IRQENABLE_L0, lch); |
ada8d4a5 | 608 | val &= ~(1 << lch); |
f31cc962 | 609 | p->dma_write(val, IRQENABLE_L0, lch); |
bedfb7ad OM |
610 | /* clear IRQ STATUS */ |
611 | p->dma_write(1 << lch, IRQSTATUS_L0, lch); | |
ada8d4a5 MW |
612 | spin_unlock_irqrestore(&dma_chan_lock, flags); |
613 | } | |
614 | ||
1a8bfa1e | 615 | int omap_request_dma(int dev_id, const char *dev_name, |
97b7f715 | 616 | void (*callback)(int lch, u16 ch_status, void *data), |
1a8bfa1e TL |
617 | void *data, int *dma_ch_out) |
618 | { | |
619 | int ch, free_ch = -1; | |
620 | unsigned long flags; | |
621 | struct omap_dma_lch *chan; | |
622 | ||
5c65c360 RK |
623 | WARN(strcmp(dev_name, "DMA engine"), "Using deprecated platform DMA API - please update to DMA engine"); |
624 | ||
1a8bfa1e TL |
625 | spin_lock_irqsave(&dma_chan_lock, flags); |
626 | for (ch = 0; ch < dma_chan_count; ch++) { | |
627 | if (free_ch == -1 && dma_chan[ch].dev_id == -1) { | |
628 | free_ch = ch; | |
03a6d4a0 S |
629 | /* Exit after first free channel found */ |
630 | break; | |
1a8bfa1e TL |
631 | } |
632 | } | |
633 | if (free_ch == -1) { | |
634 | spin_unlock_irqrestore(&dma_chan_lock, flags); | |
635 | return -EBUSY; | |
636 | } | |
637 | chan = dma_chan + free_ch; | |
638 | chan->dev_id = dev_id; | |
639 | ||
f31cc962 MK |
640 | if (p->clear_lch_regs) |
641 | p->clear_lch_regs(free_ch); | |
5e1c5ff4 | 642 | |
82809601 | 643 | if (dma_omap2plus()) |
1a8bfa1e TL |
644 | omap_clear_dma(free_ch); |
645 | ||
646 | spin_unlock_irqrestore(&dma_chan_lock, flags); | |
647 | ||
648 | chan->dev_name = dev_name; | |
649 | chan->callback = callback; | |
650 | chan->data = data; | |
a92fda19 | 651 | chan->flags = 0; |
97b7f715 | 652 | |
f8151e5c | 653 | #ifndef CONFIG_ARCH_OMAP1 |
82809601 | 654 | if (dma_omap2plus()) { |
97b7f715 TL |
655 | chan->chain_id = -1; |
656 | chan->next_linked_ch = -1; | |
657 | } | |
f8151e5c | 658 | #endif |
97b7f715 | 659 | |
7ff879db | 660 | chan->enabled_irqs = OMAP_DMA_DROP_IRQ | OMAP_DMA_BLOCK_IRQ; |
1a8bfa1e | 661 | |
82809601 | 662 | if (dma_omap1()) |
7ff879db | 663 | chan->enabled_irqs |= OMAP1_DMA_TOUT_IRQ; |
82809601 | 664 | else if (dma_omap2plus()) |
7ff879db TL |
665 | chan->enabled_irqs |= OMAP2_DMA_MISALIGNED_ERR_IRQ | |
666 | OMAP2_DMA_TRANS_ERR_IRQ; | |
1a8bfa1e | 667 | |
82809601 | 668 | if (dma_omap16xx()) { |
1a8bfa1e TL |
669 | /* If the sync device is set, configure it dynamically. */ |
670 | if (dev_id != 0) { | |
671 | set_gdma_dev(free_ch + 1, dev_id); | |
672 | dev_id = free_ch + 1; | |
673 | } | |
97b7f715 TL |
674 | /* |
675 | * Disable the 1510 compatibility mode and set the sync device | |
676 | * id. | |
677 | */ | |
f31cc962 | 678 | p->dma_write(dev_id | (1 << 10), CCR, free_ch); |
82809601 | 679 | } else if (dma_omap1()) { |
f31cc962 | 680 | p->dma_write(dev_id, CCR, free_ch); |
1a8bfa1e TL |
681 | } |
682 | ||
82809601 | 683 | if (dma_omap2plus()) { |
1a8bfa1e | 684 | omap_enable_channel_irq(free_ch); |
bedfb7ad | 685 | omap2_enable_irq_lch(free_ch); |
1a8bfa1e TL |
686 | } |
687 | ||
688 | *dma_ch_out = free_ch; | |
689 | ||
690 | return 0; | |
691 | } | |
97b7f715 | 692 | EXPORT_SYMBOL(omap_request_dma); |
1a8bfa1e TL |
693 | |
694 | void omap_free_dma(int lch) | |
695 | { | |
696 | unsigned long flags; | |
697 | ||
1a8bfa1e | 698 | if (dma_chan[lch].dev_id == -1) { |
97b7f715 | 699 | pr_err("omap_dma: trying to free unallocated DMA channel %d\n", |
1a8bfa1e | 700 | lch); |
1a8bfa1e TL |
701 | return; |
702 | } | |
97b7f715 | 703 | |
bedfb7ad | 704 | /* Disable interrupt for logical channel */ |
82809601 | 705 | if (dma_omap2plus()) |
ada8d4a5 | 706 | omap2_disable_irq_lch(lch); |
1a8bfa1e | 707 | |
bedfb7ad OM |
708 | /* Disable all DMA interrupts for the channel. */ |
709 | omap_disable_channel_irq(lch); | |
1a8bfa1e | 710 | |
bedfb7ad OM |
711 | /* Make sure the DMA transfer is stopped. */ |
712 | p->dma_write(0, CCR, lch); | |
1a8bfa1e | 713 | |
bedfb7ad | 714 | /* Clear registers */ |
82809601 | 715 | if (dma_omap2plus()) |
1a8bfa1e | 716 | omap_clear_dma(lch); |
da1b94e6 SS |
717 | |
718 | spin_lock_irqsave(&dma_chan_lock, flags); | |
719 | dma_chan[lch].dev_id = -1; | |
720 | dma_chan[lch].next_lch = -1; | |
721 | dma_chan[lch].callback = NULL; | |
722 | spin_unlock_irqrestore(&dma_chan_lock, flags); | |
1a8bfa1e | 723 | } |
97b7f715 | 724 | EXPORT_SYMBOL(omap_free_dma); |
1a8bfa1e | 725 | |
f8151e5c AG |
726 | /** |
727 | * @brief omap_dma_set_global_params : Set global priority settings for dma | |
728 | * | |
729 | * @param arb_rate | |
730 | * @param max_fifo_depth | |
70cf644c AA |
731 | * @param tparams - Number of threads to reserve : DMA_THREAD_RESERVE_NORM |
732 | * DMA_THREAD_RESERVE_ONET | |
733 | * DMA_THREAD_RESERVE_TWOT | |
734 | * DMA_THREAD_RESERVE_THREET | |
f8151e5c AG |
735 | */ |
736 | void | |
737 | omap_dma_set_global_params(int arb_rate, int max_fifo_depth, int tparams) | |
738 | { | |
739 | u32 reg; | |
740 | ||
82809601 | 741 | if (dma_omap1()) { |
8e86f427 | 742 | printk(KERN_ERR "FIXME: no %s on 15xx/16xx\n", __func__); |
f8151e5c AG |
743 | return; |
744 | } | |
745 | ||
70cf644c AA |
746 | if (max_fifo_depth == 0) |
747 | max_fifo_depth = 1; | |
f8151e5c AG |
748 | if (arb_rate == 0) |
749 | arb_rate = 1; | |
750 | ||
70cf644c AA |
751 | reg = 0xff & max_fifo_depth; |
752 | reg |= (0x3 & tparams) << 12; | |
753 | reg |= (arb_rate & 0xff) << 16; | |
f8151e5c | 754 | |
f31cc962 | 755 | p->dma_write(reg, GCR, 0); |
f8151e5c AG |
756 | } |
757 | EXPORT_SYMBOL(omap_dma_set_global_params); | |
758 | ||
759 | /** | |
760 | * @brief omap_dma_set_prio_lch : Set channel wise priority settings | |
761 | * | |
762 | * @param lch | |
763 | * @param read_prio - Read priority | |
764 | * @param write_prio - Write priority | |
765 | * Both of the above can be set with one of the following values : | |
766 | * DMA_CH_PRIO_HIGH/DMA_CH_PRIO_LOW | |
767 | */ | |
175655bd | 768 | static int |
f8151e5c AG |
769 | omap_dma_set_prio_lch(int lch, unsigned char read_prio, |
770 | unsigned char write_prio) | |
771 | { | |
0499bdeb | 772 | u32 l; |
f8151e5c | 773 | |
4d96372e | 774 | if (unlikely((lch < 0 || lch >= dma_lch_count))) { |
f8151e5c AG |
775 | printk(KERN_ERR "Invalid channel id\n"); |
776 | return -EINVAL; | |
777 | } | |
f31cc962 | 778 | l = p->dma_read(CCR, lch); |
0499bdeb | 779 | l &= ~((1 << 6) | (1 << 26)); |
82809601 | 780 | if (d->dev_caps & IS_RW_PRIORITY) |
0499bdeb | 781 | l |= ((read_prio & 0x1) << 6) | ((write_prio & 0x1) << 26); |
f8151e5c | 782 | else |
0499bdeb TL |
783 | l |= ((read_prio & 0x1) << 6); |
784 | ||
f31cc962 | 785 | p->dma_write(l, CCR, lch); |
f8151e5c | 786 | |
f8151e5c AG |
787 | return 0; |
788 | } | |
175655bd | 789 | |
f8151e5c | 790 | |
1a8bfa1e TL |
791 | /* |
792 | * Clears any DMA state so the DMA engine is ready to restart with new buffers | |
793 | * through omap_start_dma(). Any buffers in flight are discarded. | |
794 | */ | |
175655bd | 795 | static void omap_clear_dma(int lch) |
1a8bfa1e TL |
796 | { |
797 | unsigned long flags; | |
798 | ||
799 | local_irq_save(flags); | |
f31cc962 | 800 | p->clear_dma(lch); |
1a8bfa1e TL |
801 | local_irq_restore(flags); |
802 | } | |
803 | ||
804 | void omap_start_dma(int lch) | |
805 | { | |
0499bdeb TL |
806 | u32 l; |
807 | ||
519e6166 | 808 | /* |
809 | * The CPC/CDAC register needs to be initialized to zero | |
810 | * before starting dma transfer. | |
811 | */ | |
82809601 | 812 | if (dma_omap15xx()) |
f31cc962 | 813 | p->dma_write(0, CPC, lch); |
519e6166 | 814 | else |
f31cc962 | 815 | p->dma_write(0, CDAC, lch); |
519e6166 | 816 | |
5e1c5ff4 TL |
817 | if (!omap_dma_in_1510_mode() && dma_chan[lch].next_lch != -1) { |
818 | int next_lch, cur_lch; | |
bc4d8b5f | 819 | char dma_chan_link_map[MAX_LOGICAL_DMA_CH_COUNT]; |
5e1c5ff4 | 820 | |
5e1c5ff4 TL |
821 | /* Set the link register of the first channel */ |
822 | enable_lnk(lch); | |
823 | ||
824 | memset(dma_chan_link_map, 0, sizeof(dma_chan_link_map)); | |
f0a3ff27 S |
825 | dma_chan_link_map[lch] = 1; |
826 | ||
5e1c5ff4 TL |
827 | cur_lch = dma_chan[lch].next_lch; |
828 | do { | |
829 | next_lch = dma_chan[cur_lch].next_lch; | |
830 | ||
1a8bfa1e | 831 | /* The loop case: we've been here already */ |
5e1c5ff4 TL |
832 | if (dma_chan_link_map[cur_lch]) |
833 | break; | |
834 | /* Mark the current channel */ | |
835 | dma_chan_link_map[cur_lch] = 1; | |
836 | ||
837 | enable_lnk(cur_lch); | |
1a8bfa1e | 838 | omap_enable_channel_irq(cur_lch); |
5e1c5ff4 TL |
839 | |
840 | cur_lch = next_lch; | |
841 | } while (next_lch != -1); | |
d3c9be2f | 842 | } else if (IS_DMA_ERRATA(DMA_ERRATA_PARALLEL_CHANNELS)) |
f31cc962 | 843 | p->dma_write(lch, CLNK_CTRL, lch); |
5e1c5ff4 | 844 | |
1a8bfa1e TL |
845 | omap_enable_channel_irq(lch); |
846 | ||
f31cc962 | 847 | l = p->dma_read(CCR, lch); |
0499bdeb | 848 | |
d3c9be2f MK |
849 | if (IS_DMA_ERRATA(DMA_ERRATA_IFRAME_BUFFERING)) |
850 | l |= OMAP_DMA_CCR_BUFFERING_DISABLE; | |
0499bdeb | 851 | l |= OMAP_DMA_CCR_EN; |
d3c9be2f | 852 | |
35453584 RK |
853 | /* |
854 | * As dma_write() uses IO accessors which are weakly ordered, there | |
855 | * is no guarantee that data in coherent DMA memory will be visible | |
856 | * to the DMA device. Add a memory barrier here to ensure that any | |
857 | * such data is visible prior to enabling DMA. | |
858 | */ | |
859 | mb(); | |
f31cc962 | 860 | p->dma_write(l, CCR, lch); |
5e1c5ff4 | 861 | |
5e1c5ff4 TL |
862 | dma_chan[lch].flags |= OMAP_DMA_ACTIVE; |
863 | } | |
97b7f715 | 864 | EXPORT_SYMBOL(omap_start_dma); |
5e1c5ff4 TL |
865 | |
866 | void omap_stop_dma(int lch) | |
867 | { | |
0499bdeb TL |
868 | u32 l; |
869 | ||
9da65a99 | 870 | /* Disable all interrupts on the channel */ |
bedfb7ad | 871 | omap_disable_channel_irq(lch); |
9da65a99 | 872 | |
f31cc962 | 873 | l = p->dma_read(CCR, lch); |
d3c9be2f MK |
874 | if (IS_DMA_ERRATA(DMA_ERRATA_i541) && |
875 | (l & OMAP_DMA_CCR_SEL_SRC_DST_SYNC)) { | |
0e4905c0 PU |
876 | int i = 0; |
877 | u32 sys_cf; | |
878 | ||
879 | /* Configure No-Standby */ | |
f31cc962 | 880 | l = p->dma_read(OCP_SYSCONFIG, lch); |
0e4905c0 PU |
881 | sys_cf = l; |
882 | l &= ~DMA_SYSCONFIG_MIDLEMODE_MASK; | |
883 | l |= DMA_SYSCONFIG_MIDLEMODE(DMA_IDLEMODE_NO_IDLE); | |
f31cc962 | 884 | p->dma_write(l , OCP_SYSCONFIG, 0); |
0e4905c0 | 885 | |
f31cc962 | 886 | l = p->dma_read(CCR, lch); |
0e4905c0 | 887 | l &= ~OMAP_DMA_CCR_EN; |
f31cc962 | 888 | p->dma_write(l, CCR, lch); |
0e4905c0 PU |
889 | |
890 | /* Wait for sDMA FIFO drain */ | |
f31cc962 | 891 | l = p->dma_read(CCR, lch); |
0e4905c0 PU |
892 | while (i < 100 && (l & (OMAP_DMA_CCR_RD_ACTIVE | |
893 | OMAP_DMA_CCR_WR_ACTIVE))) { | |
894 | udelay(5); | |
895 | i++; | |
f31cc962 | 896 | l = p->dma_read(CCR, lch); |
0e4905c0 PU |
897 | } |
898 | if (i >= 100) | |
7852ec05 | 899 | pr_err("DMA drain did not complete on lch %d\n", lch); |
0e4905c0 | 900 | /* Restore OCP_SYSCONFIG */ |
f31cc962 | 901 | p->dma_write(sys_cf, OCP_SYSCONFIG, lch); |
0e4905c0 PU |
902 | } else { |
903 | l &= ~OMAP_DMA_CCR_EN; | |
f31cc962 | 904 | p->dma_write(l, CCR, lch); |
0e4905c0 | 905 | } |
9da65a99 | 906 | |
35453584 RK |
907 | /* |
908 | * Ensure that data transferred by DMA is visible to any access | |
909 | * after DMA has been disabled. This is important for coherent | |
910 | * DMA regions. | |
911 | */ | |
912 | mb(); | |
913 | ||
5e1c5ff4 TL |
914 | if (!omap_dma_in_1510_mode() && dma_chan[lch].next_lch != -1) { |
915 | int next_lch, cur_lch = lch; | |
bc4d8b5f | 916 | char dma_chan_link_map[MAX_LOGICAL_DMA_CH_COUNT]; |
5e1c5ff4 TL |
917 | |
918 | memset(dma_chan_link_map, 0, sizeof(dma_chan_link_map)); | |
919 | do { | |
920 | /* The loop case: we've been here already */ | |
921 | if (dma_chan_link_map[cur_lch]) | |
922 | break; | |
923 | /* Mark the current channel */ | |
924 | dma_chan_link_map[cur_lch] = 1; | |
925 | ||
926 | disable_lnk(cur_lch); | |
927 | ||
928 | next_lch = dma_chan[cur_lch].next_lch; | |
929 | cur_lch = next_lch; | |
930 | } while (next_lch != -1); | |
5e1c5ff4 | 931 | } |
1a8bfa1e | 932 | |
5e1c5ff4 TL |
933 | dma_chan[lch].flags &= ~OMAP_DMA_ACTIVE; |
934 | } | |
97b7f715 | 935 | EXPORT_SYMBOL(omap_stop_dma); |
5e1c5ff4 | 936 | |
709eb3e5 TL |
937 | /* |
938 | * Allows changing the DMA callback function or data. This may be needed if | |
939 | * the driver shares a single DMA channel for multiple dma triggers. | |
940 | */ | |
941 | int omap_set_dma_callback(int lch, | |
97b7f715 | 942 | void (*callback)(int lch, u16 ch_status, void *data), |
709eb3e5 TL |
943 | void *data) |
944 | { | |
945 | unsigned long flags; | |
946 | ||
947 | if (lch < 0) | |
948 | return -ENODEV; | |
949 | ||
950 | spin_lock_irqsave(&dma_chan_lock, flags); | |
951 | if (dma_chan[lch].dev_id == -1) { | |
952 | printk(KERN_ERR "DMA callback for not set for free channel\n"); | |
953 | spin_unlock_irqrestore(&dma_chan_lock, flags); | |
954 | return -EINVAL; | |
955 | } | |
956 | dma_chan[lch].callback = callback; | |
957 | dma_chan[lch].data = data; | |
958 | spin_unlock_irqrestore(&dma_chan_lock, flags); | |
959 | ||
960 | return 0; | |
961 | } | |
97b7f715 | 962 | EXPORT_SYMBOL(omap_set_dma_callback); |
709eb3e5 | 963 | |
1a8bfa1e TL |
964 | /* |
965 | * Returns current physical source address for the given DMA channel. | |
966 | * If the channel is running the caller must disable interrupts prior calling | |
967 | * this function and process the returned value before re-enabling interrupt to | |
968 | * prevent races with the interrupt handler. Note that in continuous mode there | |
25985edc | 969 | * is a chance for CSSA_L register overflow between the two reads resulting |
1a8bfa1e TL |
970 | * in incorrect return value. |
971 | */ | |
972 | dma_addr_t omap_get_dma_src_pos(int lch) | |
5e1c5ff4 | 973 | { |
0695de32 | 974 | dma_addr_t offset = 0; |
5e1c5ff4 | 975 | |
82809601 | 976 | if (dma_omap15xx()) |
f31cc962 | 977 | offset = p->dma_read(CPC, lch); |
0499bdeb | 978 | else |
f31cc962 | 979 | offset = p->dma_read(CSAC, lch); |
5e1c5ff4 | 980 | |
d3c9be2f | 981 | if (IS_DMA_ERRATA(DMA_ERRATA_3_3) && offset == 0) |
f31cc962 | 982 | offset = p->dma_read(CSAC, lch); |
0499bdeb | 983 | |
82809601 | 984 | if (!dma_omap15xx()) { |
7ba96680 PU |
985 | /* |
986 | * CDAC == 0 indicates that the DMA transfer on the channel has | |
987 | * not been started (no data has been transferred so far). | |
988 | * Return the programmed source start address in this case. | |
989 | */ | |
990 | if (likely(p->dma_read(CDAC, lch))) | |
991 | offset = p->dma_read(CSAC, lch); | |
992 | else | |
993 | offset = p->dma_read(CSSA, lch); | |
994 | } | |
995 | ||
82809601 | 996 | if (dma_omap1()) |
f31cc962 | 997 | offset |= (p->dma_read(CSSA, lch) & 0xFFFF0000); |
5e1c5ff4 | 998 | |
1a8bfa1e | 999 | return offset; |
5e1c5ff4 | 1000 | } |
97b7f715 | 1001 | EXPORT_SYMBOL(omap_get_dma_src_pos); |
5e1c5ff4 | 1002 | |
1a8bfa1e TL |
1003 | /* |
1004 | * Returns current physical destination address for the given DMA channel. | |
1005 | * If the channel is running the caller must disable interrupts prior calling | |
1006 | * this function and process the returned value before re-enabling interrupt to | |
1007 | * prevent races with the interrupt handler. Note that in continuous mode there | |
25985edc | 1008 | * is a chance for CDSA_L register overflow between the two reads resulting |
1a8bfa1e TL |
1009 | * in incorrect return value. |
1010 | */ | |
1011 | dma_addr_t omap_get_dma_dst_pos(int lch) | |
5e1c5ff4 | 1012 | { |
0695de32 | 1013 | dma_addr_t offset = 0; |
5e1c5ff4 | 1014 | |
82809601 | 1015 | if (dma_omap15xx()) |
f31cc962 | 1016 | offset = p->dma_read(CPC, lch); |
0499bdeb | 1017 | else |
f31cc962 | 1018 | offset = p->dma_read(CDAC, lch); |
5e1c5ff4 | 1019 | |
0499bdeb TL |
1020 | /* |
1021 | * omap 3.2/3.3 erratum: sometimes 0 is returned if CSAC/CDAC is | |
1022 | * read before the DMA controller finished disabling the channel. | |
1023 | */ | |
82809601 | 1024 | if (!dma_omap15xx() && offset == 0) { |
f31cc962 | 1025 | offset = p->dma_read(CDAC, lch); |
06e8077b PU |
1026 | /* |
1027 | * CDAC == 0 indicates that the DMA transfer on the channel has | |
1028 | * not been started (no data has been transferred so far). | |
1029 | * Return the programmed destination start address in this case. | |
1030 | */ | |
1031 | if (unlikely(!offset)) | |
1032 | offset = p->dma_read(CDSA, lch); | |
1033 | } | |
0499bdeb | 1034 | |
82809601 | 1035 | if (dma_omap1()) |
f31cc962 | 1036 | offset |= (p->dma_read(CDSA, lch) & 0xFFFF0000); |
5e1c5ff4 | 1037 | |
1a8bfa1e | 1038 | return offset; |
5e1c5ff4 | 1039 | } |
97b7f715 | 1040 | EXPORT_SYMBOL(omap_get_dma_dst_pos); |
0499bdeb TL |
1041 | |
1042 | int omap_get_dma_active_status(int lch) | |
1043 | { | |
f31cc962 | 1044 | return (p->dma_read(CCR, lch) & OMAP_DMA_CCR_EN) != 0; |
5e1c5ff4 | 1045 | } |
0499bdeb | 1046 | EXPORT_SYMBOL(omap_get_dma_active_status); |
5e1c5ff4 | 1047 | |
1a8bfa1e | 1048 | int omap_dma_running(void) |
5e1c5ff4 | 1049 | { |
1a8bfa1e | 1050 | int lch; |
5e1c5ff4 | 1051 | |
82809601 | 1052 | if (dma_omap1()) |
f8e9e984 | 1053 | if (omap_lcd_dma_running()) |
1a8bfa1e | 1054 | return 1; |
5e1c5ff4 | 1055 | |
1a8bfa1e | 1056 | for (lch = 0; lch < dma_chan_count; lch++) |
f31cc962 | 1057 | if (p->dma_read(CCR, lch) & OMAP_DMA_CCR_EN) |
1a8bfa1e | 1058 | return 1; |
5e1c5ff4 | 1059 | |
1a8bfa1e | 1060 | return 0; |
5e1c5ff4 TL |
1061 | } |
1062 | ||
1063 | /* | |
1064 | * lch_queue DMA will start right after lch_head one is finished. | |
1065 | * For this DMA link to start, you still need to start (see omap_start_dma) | |
1066 | * the first one. That will fire up the entire queue. | |
1067 | */ | |
97b7f715 | 1068 | void omap_dma_link_lch(int lch_head, int lch_queue) |
5e1c5ff4 TL |
1069 | { |
1070 | if (omap_dma_in_1510_mode()) { | |
9f0f4ae5 | 1071 | if (lch_head == lch_queue) { |
f31cc962 | 1072 | p->dma_write(p->dma_read(CCR, lch_head) | (3 << 8), |
a4c537c7 | 1073 | CCR, lch_head); |
9f0f4ae5 JK |
1074 | return; |
1075 | } | |
5e1c5ff4 TL |
1076 | printk(KERN_ERR "DMA linking is not supported in 1510 mode\n"); |
1077 | BUG(); | |
1078 | return; | |
1079 | } | |
1080 | ||
1081 | if ((dma_chan[lch_head].dev_id == -1) || | |
1082 | (dma_chan[lch_queue].dev_id == -1)) { | |
7852ec05 | 1083 | pr_err("omap_dma: trying to link non requested channels\n"); |
5e1c5ff4 TL |
1084 | dump_stack(); |
1085 | } | |
1086 | ||
1087 | dma_chan[lch_head].next_lch = lch_queue; | |
1088 | } | |
97b7f715 | 1089 | EXPORT_SYMBOL(omap_dma_link_lch); |
5e1c5ff4 | 1090 | |
1a8bfa1e TL |
1091 | /*----------------------------------------------------------------------------*/ |
1092 | ||
1093 | #ifdef CONFIG_ARCH_OMAP1 | |
1094 | ||
1095 | static int omap1_dma_handle_ch(int ch) | |
1096 | { | |
0499bdeb | 1097 | u32 csr; |
1a8bfa1e TL |
1098 | |
1099 | if (enable_1510_mode && ch >= 6) { | |
1100 | csr = dma_chan[ch].saved_csr; | |
1101 | dma_chan[ch].saved_csr = 0; | |
1102 | } else | |
f31cc962 | 1103 | csr = p->dma_read(CSR, ch); |
1a8bfa1e TL |
1104 | if (enable_1510_mode && ch <= 2 && (csr >> 7) != 0) { |
1105 | dma_chan[ch + 6].saved_csr = csr >> 7; | |
1106 | csr &= 0x7f; | |
1107 | } | |
1108 | if ((csr & 0x3f) == 0) | |
1109 | return 0; | |
1110 | if (unlikely(dma_chan[ch].dev_id == -1)) { | |
7852ec05 PW |
1111 | pr_warn("Spurious interrupt from DMA channel %d (CSR %04x)\n", |
1112 | ch, csr); | |
1a8bfa1e TL |
1113 | return 0; |
1114 | } | |
7ff879db | 1115 | if (unlikely(csr & OMAP1_DMA_TOUT_IRQ)) |
7852ec05 | 1116 | pr_warn("DMA timeout with device %d\n", dma_chan[ch].dev_id); |
1a8bfa1e | 1117 | if (unlikely(csr & OMAP_DMA_DROP_IRQ)) |
7852ec05 PW |
1118 | pr_warn("DMA synchronization event drop occurred with device %d\n", |
1119 | dma_chan[ch].dev_id); | |
1a8bfa1e TL |
1120 | if (likely(csr & OMAP_DMA_BLOCK_IRQ)) |
1121 | dma_chan[ch].flags &= ~OMAP_DMA_ACTIVE; | |
1122 | if (likely(dma_chan[ch].callback != NULL)) | |
1123 | dma_chan[ch].callback(ch, csr, dma_chan[ch].data); | |
97b7f715 | 1124 | |
1a8bfa1e TL |
1125 | return 1; |
1126 | } | |
1127 | ||
0cd61b68 | 1128 | static irqreturn_t omap1_dma_irq_handler(int irq, void *dev_id) |
1a8bfa1e TL |
1129 | { |
1130 | int ch = ((int) dev_id) - 1; | |
1131 | int handled = 0; | |
1132 | ||
1133 | for (;;) { | |
1134 | int handled_now = 0; | |
1135 | ||
1136 | handled_now += omap1_dma_handle_ch(ch); | |
1137 | if (enable_1510_mode && dma_chan[ch + 6].saved_csr) | |
1138 | handled_now += omap1_dma_handle_ch(ch + 6); | |
1139 | if (!handled_now) | |
1140 | break; | |
1141 | handled += handled_now; | |
1142 | } | |
1143 | ||
1144 | return handled ? IRQ_HANDLED : IRQ_NONE; | |
1145 | } | |
1146 | ||
1147 | #else | |
1148 | #define omap1_dma_irq_handler NULL | |
1149 | #endif | |
1150 | ||
140455fa | 1151 | #ifdef CONFIG_ARCH_OMAP2PLUS |
1a8bfa1e TL |
1152 | |
1153 | static int omap2_dma_handle_ch(int ch) | |
1154 | { | |
f31cc962 | 1155 | u32 status = p->dma_read(CSR, ch); |
1a8bfa1e | 1156 | |
3151369d JY |
1157 | if (!status) { |
1158 | if (printk_ratelimit()) | |
7852ec05 | 1159 | pr_warn("Spurious DMA IRQ for lch %d\n", ch); |
f31cc962 | 1160 | p->dma_write(1 << ch, IRQSTATUS_L0, ch); |
1a8bfa1e | 1161 | return 0; |
3151369d JY |
1162 | } |
1163 | if (unlikely(dma_chan[ch].dev_id == -1)) { | |
1164 | if (printk_ratelimit()) | |
7852ec05 PW |
1165 | pr_warn("IRQ %04x for non-allocated DMA channel %d\n", |
1166 | status, ch); | |
1a8bfa1e | 1167 | return 0; |
3151369d | 1168 | } |
1a8bfa1e | 1169 | if (unlikely(status & OMAP_DMA_DROP_IRQ)) |
7852ec05 PW |
1170 | pr_info("DMA synchronization event drop occurred with device %d\n", |
1171 | dma_chan[ch].dev_id); | |
a50f18c7 | 1172 | if (unlikely(status & OMAP2_DMA_TRANS_ERR_IRQ)) { |
1a8bfa1e TL |
1173 | printk(KERN_INFO "DMA transaction error with device %d\n", |
1174 | dma_chan[ch].dev_id); | |
d3c9be2f | 1175 | if (IS_DMA_ERRATA(DMA_ERRATA_i378)) { |
a50f18c7 SS |
1176 | u32 ccr; |
1177 | ||
f31cc962 | 1178 | ccr = p->dma_read(CCR, ch); |
a50f18c7 | 1179 | ccr &= ~OMAP_DMA_CCR_EN; |
f31cc962 | 1180 | p->dma_write(ccr, CCR, ch); |
a50f18c7 SS |
1181 | dma_chan[ch].flags &= ~OMAP_DMA_ACTIVE; |
1182 | } | |
1183 | } | |
7ff879db TL |
1184 | if (unlikely(status & OMAP2_DMA_SECURE_ERR_IRQ)) |
1185 | printk(KERN_INFO "DMA secure error with device %d\n", | |
1186 | dma_chan[ch].dev_id); | |
1187 | if (unlikely(status & OMAP2_DMA_MISALIGNED_ERR_IRQ)) | |
1188 | printk(KERN_INFO "DMA misaligned error with device %d\n", | |
1189 | dma_chan[ch].dev_id); | |
1a8bfa1e | 1190 | |
4fb699b4 | 1191 | p->dma_write(status, CSR, ch); |
f31cc962 | 1192 | p->dma_write(1 << ch, IRQSTATUS_L0, ch); |
e860e6da | 1193 | /* read back the register to flush the write */ |
f31cc962 | 1194 | p->dma_read(IRQSTATUS_L0, ch); |
1a8bfa1e | 1195 | |
f8151e5c AG |
1196 | /* If the ch is not chained then chain_id will be -1 */ |
1197 | if (dma_chan[ch].chain_id != -1) { | |
1198 | int chain_id = dma_chan[ch].chain_id; | |
1199 | dma_chan[ch].state = DMA_CH_NOTSTARTED; | |
f31cc962 | 1200 | if (p->dma_read(CLNK_CTRL, ch) & (1 << 15)) |
f8151e5c AG |
1201 | dma_chan[dma_chan[ch].next_linked_ch].state = |
1202 | DMA_CH_STARTED; | |
1203 | if (dma_linked_lch[chain_id].chain_mode == | |
1204 | OMAP_DMA_DYNAMIC_CHAIN) | |
1205 | disable_lnk(ch); | |
1206 | ||
1207 | if (!OMAP_DMA_CHAIN_QEMPTY(chain_id)) | |
1208 | OMAP_DMA_CHAIN_INCQHEAD(chain_id); | |
1209 | ||
f31cc962 | 1210 | status = p->dma_read(CSR, ch); |
4fb699b4 | 1211 | p->dma_write(status, CSR, ch); |
f8151e5c AG |
1212 | } |
1213 | ||
538528de JN |
1214 | if (likely(dma_chan[ch].callback != NULL)) |
1215 | dma_chan[ch].callback(ch, status, dma_chan[ch].data); | |
f8151e5c | 1216 | |
1a8bfa1e TL |
1217 | return 0; |
1218 | } | |
1219 | ||
1220 | /* STATUS register count is from 1-32 while our is 0-31 */ | |
0cd61b68 | 1221 | static irqreturn_t omap2_dma_irq_handler(int irq, void *dev_id) |
1a8bfa1e | 1222 | { |
52176e70 | 1223 | u32 val, enable_reg; |
1a8bfa1e TL |
1224 | int i; |
1225 | ||
f31cc962 | 1226 | val = p->dma_read(IRQSTATUS_L0, 0); |
3151369d JY |
1227 | if (val == 0) { |
1228 | if (printk_ratelimit()) | |
1229 | printk(KERN_WARNING "Spurious DMA IRQ\n"); | |
1230 | return IRQ_HANDLED; | |
1231 | } | |
f31cc962 | 1232 | enable_reg = p->dma_read(IRQENABLE_L0, 0); |
52176e70 | 1233 | val &= enable_reg; /* Dispatch only relevant interrupts */ |
4d96372e | 1234 | for (i = 0; i < dma_lch_count && val != 0; i++) { |
3151369d JY |
1235 | if (val & 1) |
1236 | omap2_dma_handle_ch(i); | |
1237 | val >>= 1; | |
1a8bfa1e TL |
1238 | } |
1239 | ||
1240 | return IRQ_HANDLED; | |
1241 | } | |
1242 | ||
1243 | static struct irqaction omap24xx_dma_irq = { | |
1244 | .name = "DMA", | |
1245 | .handler = omap2_dma_irq_handler, | |
1a8bfa1e TL |
1246 | }; |
1247 | ||
1248 | #else | |
1249 | static struct irqaction omap24xx_dma_irq; | |
1250 | #endif | |
1251 | ||
1252 | /*----------------------------------------------------------------------------*/ | |
5e1c5ff4 | 1253 | |
9ce2482f TL |
1254 | /* |
1255 | * Note that we are currently using only IRQENABLE_L0 and L1. | |
1256 | * As the DSP may be using IRQENABLE_L2 and L3, let's not | |
1257 | * touch those for now. | |
1258 | */ | |
f2d11858 TK |
1259 | void omap_dma_global_context_save(void) |
1260 | { | |
1261 | omap_dma_global_context.dma_irqenable_l0 = | |
f31cc962 | 1262 | p->dma_read(IRQENABLE_L0, 0); |
9ce2482f TL |
1263 | omap_dma_global_context.dma_irqenable_l1 = |
1264 | p->dma_read(IRQENABLE_L1, 0); | |
f2d11858 | 1265 | omap_dma_global_context.dma_ocp_sysconfig = |
f31cc962 MK |
1266 | p->dma_read(OCP_SYSCONFIG, 0); |
1267 | omap_dma_global_context.dma_gcr = p->dma_read(GCR, 0); | |
f2d11858 TK |
1268 | } |
1269 | ||
1270 | void omap_dma_global_context_restore(void) | |
1271 | { | |
bf07c9f2 AK |
1272 | int ch; |
1273 | ||
f31cc962 MK |
1274 | p->dma_write(omap_dma_global_context.dma_gcr, GCR, 0); |
1275 | p->dma_write(omap_dma_global_context.dma_ocp_sysconfig, | |
a4c537c7 | 1276 | OCP_SYSCONFIG, 0); |
f31cc962 | 1277 | p->dma_write(omap_dma_global_context.dma_irqenable_l0, |
a4c537c7 | 1278 | IRQENABLE_L0, 0); |
9ce2482f TL |
1279 | p->dma_write(omap_dma_global_context.dma_irqenable_l1, |
1280 | IRQENABLE_L1, 0); | |
f2d11858 | 1281 | |
d3c9be2f | 1282 | if (IS_DMA_ERRATA(DMA_ROMCODE_BUG)) |
f31cc962 | 1283 | p->dma_write(0x3 , IRQSTATUS_L0, 0); |
bf07c9f2 AK |
1284 | |
1285 | for (ch = 0; ch < dma_chan_count; ch++) | |
1286 | if (dma_chan[ch].dev_id != -1) | |
1287 | omap_clear_dma(ch); | |
f2d11858 TK |
1288 | } |
1289 | ||
1b416c4b RK |
1290 | struct omap_system_dma_plat_info *omap_get_plat_info(void) |
1291 | { | |
1292 | return p; | |
1293 | } | |
1294 | EXPORT_SYMBOL_GPL(omap_get_plat_info); | |
1295 | ||
351a102d | 1296 | static int omap_system_dma_probe(struct platform_device *pdev) |
d3c9be2f | 1297 | { |
f31cc962 MK |
1298 | int ch, ret = 0; |
1299 | int dma_irq; | |
1300 | char irq_name[4]; | |
1301 | int irq_rel; | |
1302 | ||
1303 | p = pdev->dev.platform_data; | |
1304 | if (!p) { | |
7852ec05 PW |
1305 | dev_err(&pdev->dev, |
1306 | "%s: System DMA initialized without platform data\n", | |
1307 | __func__); | |
f31cc962 | 1308 | return -EINVAL; |
0499bdeb | 1309 | } |
4d96372e | 1310 | |
f31cc962 MK |
1311 | d = p->dma_attr; |
1312 | errata = p->errata; | |
a4c537c7 | 1313 | |
f31cc962 | 1314 | if ((d->dev_caps & RESERVE_CHANNEL) && omap_dma_reserve_channels |
e78f9606 | 1315 | && (omap_dma_reserve_channels < d->lch_count)) |
f31cc962 | 1316 | d->lch_count = omap_dma_reserve_channels; |
2263f022 | 1317 | |
f31cc962 MK |
1318 | dma_lch_count = d->lch_count; |
1319 | dma_chan_count = dma_lch_count; | |
f31cc962 | 1320 | enable_1510_mode = d->dev_caps & ENABLE_1510_MODE; |
4d96372e | 1321 | |
9834f813 RK |
1322 | dma_chan = devm_kcalloc(&pdev->dev, dma_lch_count, |
1323 | sizeof(struct omap_dma_lch), GFP_KERNEL); | |
1324 | if (!dma_chan) { | |
1325 | dev_err(&pdev->dev, "%s: kzalloc fail\n", __func__); | |
1326 | return -ENOMEM; | |
1327 | } | |
1328 | ||
1329 | ||
82809601 | 1330 | if (dma_omap2plus()) { |
4d96372e TL |
1331 | dma_linked_lch = kzalloc(sizeof(struct dma_link_info) * |
1332 | dma_lch_count, GFP_KERNEL); | |
1333 | if (!dma_linked_lch) { | |
f31cc962 MK |
1334 | ret = -ENOMEM; |
1335 | goto exit_dma_lch_fail; | |
4d96372e TL |
1336 | } |
1337 | } | |
1338 | ||
5e1c5ff4 | 1339 | spin_lock_init(&dma_chan_lock); |
5e1c5ff4 | 1340 | for (ch = 0; ch < dma_chan_count; ch++) { |
1a8bfa1e | 1341 | omap_clear_dma(ch); |
82809601 | 1342 | if (dma_omap2plus()) |
ada8d4a5 MW |
1343 | omap2_disable_irq_lch(ch); |
1344 | ||
5e1c5ff4 TL |
1345 | dma_chan[ch].dev_id = -1; |
1346 | dma_chan[ch].next_lch = -1; | |
1347 | ||
1348 | if (ch >= 6 && enable_1510_mode) | |
1349 | continue; | |
1350 | ||
82809601 | 1351 | if (dma_omap1()) { |
97b7f715 TL |
1352 | /* |
1353 | * request_irq() doesn't like dev_id (ie. ch) being | |
1354 | * zero, so we have to kludge around this. | |
1355 | */ | |
f31cc962 MK |
1356 | sprintf(&irq_name[0], "%d", ch); |
1357 | dma_irq = platform_get_irq_byname(pdev, irq_name); | |
1358 | ||
1359 | if (dma_irq < 0) { | |
1360 | ret = dma_irq; | |
1361 | goto exit_dma_irq_fail; | |
1362 | } | |
1363 | ||
1364 | /* INT_DMA_LCD is handled in lcd_dma.c */ | |
1365 | if (dma_irq == INT_DMA_LCD) | |
1366 | continue; | |
1367 | ||
1368 | ret = request_irq(dma_irq, | |
1a8bfa1e TL |
1369 | omap1_dma_irq_handler, 0, "DMA", |
1370 | (void *) (ch + 1)); | |
f31cc962 MK |
1371 | if (ret != 0) |
1372 | goto exit_dma_irq_fail; | |
1a8bfa1e TL |
1373 | } |
1374 | } | |
1375 | ||
82809601 | 1376 | if (d->dev_caps & IS_RW_PRIORITY) |
f8151e5c AG |
1377 | omap_dma_set_global_params(DMA_DEFAULT_ARB_RATE, |
1378 | DMA_DEFAULT_FIFO_DEPTH, 0); | |
1379 | ||
76be4a54 | 1380 | if (dma_omap2plus() && !(d->dev_caps & DMA_ENGINE_HANDLE_IRQ)) { |
f31cc962 MK |
1381 | strcpy(irq_name, "0"); |
1382 | dma_irq = platform_get_irq_byname(pdev, irq_name); | |
1383 | if (dma_irq < 0) { | |
1384 | dev_err(&pdev->dev, "failed: request IRQ %d", dma_irq); | |
94b1d617 | 1385 | ret = dma_irq; |
f31cc962 MK |
1386 | goto exit_dma_lch_fail; |
1387 | } | |
1388 | ret = setup_irq(dma_irq, &omap24xx_dma_irq); | |
1389 | if (ret) { | |
7852ec05 PW |
1390 | dev_err(&pdev->dev, "set_up failed for IRQ %d for DMA (error %d)\n", |
1391 | dma_irq, ret); | |
f31cc962 | 1392 | goto exit_dma_lch_fail; |
ba50ea7e | 1393 | } |
aecedb94 KJ |
1394 | } |
1395 | ||
82809601 TL |
1396 | /* reserve dma channels 0 and 1 in high security devices on 34xx */ |
1397 | if (d->dev_caps & HS_CHANNELS_RESERVED) { | |
7852ec05 | 1398 | pr_info("Reserving DMA channels 0 and 1 for HS ROM code\n"); |
f31cc962 MK |
1399 | dma_chan[0].dev_id = 0; |
1400 | dma_chan[1].dev_id = 1; | |
1401 | } | |
1402 | p->show_dma_caps(); | |
5e1c5ff4 | 1403 | return 0; |
7e9bf847 | 1404 | |
f31cc962 | 1405 | exit_dma_irq_fail: |
7852ec05 PW |
1406 | dev_err(&pdev->dev, "unable to request IRQ %d for DMA (error %d)\n", |
1407 | dma_irq, ret); | |
f31cc962 MK |
1408 | for (irq_rel = 0; irq_rel < ch; irq_rel++) { |
1409 | dma_irq = platform_get_irq(pdev, irq_rel); | |
1410 | free_irq(dma_irq, (void *)(irq_rel + 1)); | |
1411 | } | |
1412 | ||
1413 | exit_dma_lch_fail: | |
f31cc962 MK |
1414 | return ret; |
1415 | } | |
7e9bf847 | 1416 | |
351a102d | 1417 | static int omap_system_dma_remove(struct platform_device *pdev) |
f31cc962 MK |
1418 | { |
1419 | int dma_irq; | |
7e9bf847 | 1420 | |
82809601 | 1421 | if (dma_omap2plus()) { |
f31cc962 MK |
1422 | char irq_name[4]; |
1423 | strcpy(irq_name, "0"); | |
1424 | dma_irq = platform_get_irq_byname(pdev, irq_name); | |
76be4a54 NM |
1425 | if (dma_irq >= 0) |
1426 | remove_irq(dma_irq, &omap24xx_dma_irq); | |
f31cc962 MK |
1427 | } else { |
1428 | int irq_rel = 0; | |
1429 | for ( ; irq_rel < dma_chan_count; irq_rel++) { | |
1430 | dma_irq = platform_get_irq(pdev, irq_rel); | |
1431 | free_irq(dma_irq, (void *)(irq_rel + 1)); | |
1432 | } | |
1433 | } | |
f31cc962 MK |
1434 | return 0; |
1435 | } | |
1436 | ||
1437 | static struct platform_driver omap_system_dma_driver = { | |
1438 | .probe = omap_system_dma_probe, | |
351a102d | 1439 | .remove = omap_system_dma_remove, |
f31cc962 MK |
1440 | .driver = { |
1441 | .name = "omap_dma_system" | |
1442 | }, | |
1443 | }; | |
1444 | ||
1445 | static int __init omap_system_dma_init(void) | |
1446 | { | |
1447 | return platform_driver_register(&omap_system_dma_driver); | |
1448 | } | |
1449 | arch_initcall(omap_system_dma_init); | |
1450 | ||
1451 | static void __exit omap_system_dma_exit(void) | |
1452 | { | |
1453 | platform_driver_unregister(&omap_system_dma_driver); | |
5e1c5ff4 TL |
1454 | } |
1455 | ||
f31cc962 MK |
1456 | MODULE_DESCRIPTION("OMAP SYSTEM DMA DRIVER"); |
1457 | MODULE_LICENSE("GPL"); | |
1458 | MODULE_ALIAS("platform:" DRIVER_NAME); | |
1459 | MODULE_AUTHOR("Texas Instruments Inc"); | |
5e1c5ff4 | 1460 | |
2263f022 SS |
1461 | /* |
1462 | * Reserve the omap SDMA channels using cmdline bootarg | |
1463 | * "omap_dma_reserve_ch=". The valid range is 1 to 32 | |
1464 | */ | |
1465 | static int __init omap_dma_cmdline_reserve_ch(char *str) | |
1466 | { | |
1467 | if (get_option(&str, &omap_dma_reserve_channels) != 1) | |
1468 | omap_dma_reserve_channels = 0; | |
1469 | return 1; | |
1470 | } | |
1471 | ||
1472 | __setup("omap_dma_reserve_ch=", omap_dma_cmdline_reserve_ch); | |
1473 | ||
5e1c5ff4 | 1474 |