[linux-2.6-block.git] / arch / arm / plat-omap / devices.c

/*
 * linux/arch/arm/plat-omap/devices.c
 *
 * Common platform device setup/initialization for OMAP1 and OMAP2
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 */

#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/platform_device.h>

#include <asm/hardware.h>
#include <asm/io.h>
#include <asm/mach-types.h>
#include <asm/mach/map.h>

#include <asm/arch/tc.h>
#include <asm/arch/board.h>
#include <asm/arch/mux.h>
#include <asm/arch/gpio.h>
#include <asm/arch/menelaus.h>

#if	defined(CONFIG_OMAP_DSP) || defined(CONFIG_OMAP_DSP_MODULE)

#include "../plat-omap/dsp/dsp_common.h"

static struct dsp_platform_data dsp_pdata = {
	.kdev_list = LIST_HEAD_INIT(dsp_pdata.kdev_list),
};

static struct resource omap_dsp_resources[] = {
	{
		.name	= "dsp_mmu",
		.start	= -1,
		.flags	= IORESOURCE_IRQ,
	},
};

static struct platform_device omap_dsp_device = {
	.name		= "dsp",
	.id		= -1,
	.num_resources	= ARRAY_SIZE(omap_dsp_resources),
	.resource	= omap_dsp_resources,
	.dev = {
		.platform_data = &dsp_pdata,
	},
};

static inline void omap_init_dsp(void)
{
	struct resource *res;
	int irq;

	if (cpu_is_omap15xx())
		irq = INT_1510_DSP_MMU;
	else if (cpu_is_omap16xx())
		irq = INT_1610_DSP_MMU;
	else if (cpu_is_omap24xx())
		irq = INT_24XX_DSP_MMU;

	res = platform_get_resource_byname(&omap_dsp_device,
					   IORESOURCE_IRQ, "dsp_mmu");
	res->start = irq;

	platform_device_register(&omap_dsp_device);
}

int dsp_kfunc_device_register(struct dsp_kfunc_device *kdev)
{
	static DEFINE_MUTEX(dsp_pdata_lock);

	mutex_init(&kdev->lock);

	mutex_lock(&dsp_pdata_lock);
	list_add_tail(&kdev->entry, &dsp_pdata.kdev_list);
	mutex_unlock(&dsp_pdata_lock);

	return 0;
}
EXPORT_SYMBOL(dsp_kfunc_device_register);

#else
static inline void omap_init_dsp(void) { }
#endif	/* CONFIG_OMAP_DSP */

/*-------------------------------------------------------------------------*/
#if	defined(CONFIG_KEYBOARD_OMAP) || defined(CONFIG_KEYBOARD_OMAP_MODULE)

static void omap_init_kp(void)
{
	if (machine_is_omap_h2() || machine_is_omap_h3()) {
		omap_cfg_reg(F18_1610_KBC0);
		omap_cfg_reg(D20_1610_KBC1);
		omap_cfg_reg(D19_1610_KBC2);
		omap_cfg_reg(E18_1610_KBC3);
		omap_cfg_reg(C21_1610_KBC4);

		omap_cfg_reg(G18_1610_KBR0);
		omap_cfg_reg(F19_1610_KBR1);
		omap_cfg_reg(H14_1610_KBR2);
		omap_cfg_reg(E20_1610_KBR3);
		omap_cfg_reg(E19_1610_KBR4);
		omap_cfg_reg(N19_1610_KBR5);
	} else if (machine_is_omap_perseus2() || machine_is_omap_fsample()) {
		omap_cfg_reg(E2_730_KBR0);
		omap_cfg_reg(J7_730_KBR1);
		omap_cfg_reg(E1_730_KBR2);
		omap_cfg_reg(F3_730_KBR3);
		omap_cfg_reg(D2_730_KBR4);

		omap_cfg_reg(C2_730_KBC0);
		omap_cfg_reg(D3_730_KBC1);
		omap_cfg_reg(E4_730_KBC2);
		omap_cfg_reg(F4_730_KBC3);
		omap_cfg_reg(E3_730_KBC4);
	} else if (machine_is_omap_h4()) {
		omap_cfg_reg(T19_24XX_KBR0);
		omap_cfg_reg(R19_24XX_KBR1);
		omap_cfg_reg(V18_24XX_KBR2);
		omap_cfg_reg(M21_24XX_KBR3);
		omap_cfg_reg(E5__24XX_KBR4);
		if (omap_has_menelaus()) {
			omap_cfg_reg(B3__24XX_KBR5);
			omap_cfg_reg(AA4_24XX_KBC2);
			omap_cfg_reg(B13_24XX_KBC6);
		} else {
			omap_cfg_reg(M18_24XX_KBR5);
			omap_cfg_reg(H19_24XX_KBC2);
			omap_cfg_reg(N19_24XX_KBC6);
		}
		omap_cfg_reg(R20_24XX_KBC0);
		omap_cfg_reg(M14_24XX_KBC1);
		omap_cfg_reg(V17_24XX_KBC3);
		omap_cfg_reg(P21_24XX_KBC4);
		omap_cfg_reg(L14_24XX_KBC5);
	}
}
#else
static inline void omap_init_kp(void) {}
#endif

/*-------------------------------------------------------------------------*/

#if	defined(CONFIG_MMC_OMAP) || defined(CONFIG_MMC_OMAP_MODULE)

#ifdef CONFIG_ARCH_OMAP24XX
#define	OMAP_MMC1_BASE		0x4809c000
#define OMAP_MMC1_INT		INT_24XX_MMC_IRQ
#else
#define	OMAP_MMC1_BASE		0xfffb7800
#define OMAP_MMC1_INT		INT_MMC
#endif
#define	OMAP_MMC2_BASE		0xfffb7c00	/* omap16xx only */

static struct omap_mmc_conf mmc1_conf;

static u64 mmc1_dmamask = 0xffffffff;

static struct resource mmc1_resources[] = {
	{
		.start		= OMAP_MMC1_BASE,
		.end		= OMAP_MMC1_BASE + 0x7f,
		.flags		= IORESOURCE_MEM,
	},
	{
		.start		= OMAP_MMC1_INT,
		.flags		= IORESOURCE_IRQ,
	},
};

static struct platform_device mmc_omap_device1 = {
	.name		= "mmci-omap",
	.id		= 1,
	.dev = {
		.dma_mask	= &mmc1_dmamask,
		.platform_data	= &mmc1_conf,
	},
	.num_resources	= ARRAY_SIZE(mmc1_resources),
	.resource	= mmc1_resources,
};

#ifdef	CONFIG_ARCH_OMAP16XX

static struct omap_mmc_conf mmc2_conf;

static u64 mmc2_dmamask = 0xffffffff;

static struct resource mmc2_resources[] = {
	{
		.start		= OMAP_MMC2_BASE,
		.end		= OMAP_MMC2_BASE + 0x7f,
		.flags		= IORESOURCE_MEM,
	},
	{
		.start		= INT_1610_MMC2,
		.flags		= IORESOURCE_IRQ,
	},
};

static struct platform_device mmc_omap_device2 = {
	.name		= "mmci-omap",
	.id		= 2,
	.dev = {
		.dma_mask	= &mmc2_dmamask,
		.platform_data	= &mmc2_conf,
	},
	.num_resources	= ARRAY_SIZE(mmc2_resources),
	.resource	= mmc2_resources,
};
#endif

static void __init omap_init_mmc(void)
{
	const struct omap_mmc_config	*mmc_conf;
	const struct omap_mmc_conf	*mmc;

	/* NOTE:  assumes MMC was never (wrongly) enabled */
	mmc_conf = omap_get_config(OMAP_TAG_MMC, struct omap_mmc_config);
	if (!mmc_conf)
		return;

	/* block 1 is always available and has just one pinout option */
	mmc = &mmc_conf->mmc[0];
	if (mmc->enabled) {
		if (cpu_is_omap24xx()) {
			omap_cfg_reg(H18_24XX_MMC_CMD);
			omap_cfg_reg(H15_24XX_MMC_CLKI);
			omap_cfg_reg(G19_24XX_MMC_CLKO);
			omap_cfg_reg(F20_24XX_MMC_DAT0);
			omap_cfg_reg(F19_24XX_MMC_DAT_DIR0);
			omap_cfg_reg(G18_24XX_MMC_CMD_DIR);
		} else {
			omap_cfg_reg(MMC_CMD);
			omap_cfg_reg(MMC_CLK);
			omap_cfg_reg(MMC_DAT0);
			if (cpu_is_omap1710()) {
				omap_cfg_reg(M15_1710_MMC_CLKI);
				omap_cfg_reg(P19_1710_MMC_CMDDIR);
				omap_cfg_reg(P20_1710_MMC_DATDIR0);
			}
		}
		if (mmc->wire4) {
			if (cpu_is_omap24xx()) {
				omap_cfg_reg(H14_24XX_MMC_DAT1);
				omap_cfg_reg(E19_24XX_MMC_DAT2);
				omap_cfg_reg(D19_24XX_MMC_DAT3);
				omap_cfg_reg(E20_24XX_MMC_DAT_DIR1);
				omap_cfg_reg(F18_24XX_MMC_DAT_DIR2);
				omap_cfg_reg(E18_24XX_MMC_DAT_DIR3);
			} else {
				omap_cfg_reg(MMC_DAT1);
				/* NOTE:  DAT2 can be on W10 (here) or M15 */
				if (!mmc->nomux)
					omap_cfg_reg(MMC_DAT2);
				omap_cfg_reg(MMC_DAT3);
			}
		}
		mmc1_conf = *mmc;
		(void) platform_device_register(&mmc_omap_device1);
	}

#ifdef	CONFIG_ARCH_OMAP16XX
	/* block 2 is on newer chips, and has many pinout options */
	mmc = &mmc_conf->mmc[1];
	if (mmc->enabled) {
		if (!mmc->nomux) {
			omap_cfg_reg(Y8_1610_MMC2_CMD);
			omap_cfg_reg(Y10_1610_MMC2_CLK);
			omap_cfg_reg(R18_1610_MMC2_CLKIN);
			omap_cfg_reg(W8_1610_MMC2_DAT0);
			if (mmc->wire4) {
				omap_cfg_reg(V8_1610_MMC2_DAT1);
				omap_cfg_reg(W15_1610_MMC2_DAT2);
				omap_cfg_reg(R10_1610_MMC2_DAT3);
			}

			/* These are needed for the level shifter */
			omap_cfg_reg(V9_1610_MMC2_CMDDIR);
			omap_cfg_reg(V5_1610_MMC2_DATDIR0);
			omap_cfg_reg(W19_1610_MMC2_DATDIR1);
		}

		/* Feedback clock must be set on OMAP-1710 MMC2 */
		if (cpu_is_omap1710())
			omap_writel(omap_readl(MOD_CONF_CTRL_1) | (1 << 24),
				     MOD_CONF_CTRL_1);
		mmc2_conf = *mmc;
		(void) platform_device_register(&mmc_omap_device2);
	}
#endif
	return;
}
#else
static inline void omap_init_mmc(void) {}
#endif

/*-------------------------------------------------------------------------*/

/* Numbering for the SPI-capable controllers when used for SPI:
 * spi		= 1
 * uwire	= 2
 * mmc1..2	= 3..4
 * mcbsp1..3	= 5..7
 */

#if defined(CONFIG_SPI_OMAP_UWIRE) || defined(CONFIG_SPI_OMAP_UWIRE_MODULE)

#define	OMAP_UWIRE_BASE		0xfffb3000

static struct resource uwire_resources[] = {
	{
		.start		= OMAP_UWIRE_BASE,
		.end		= OMAP_UWIRE_BASE + 0x20,
		.flags		= IORESOURCE_MEM,
	},
};

static struct platform_device omap_uwire_device = {
	.name	   = "omap_uwire",
	.id	     = -1,
	.num_resources	= ARRAY_SIZE(uwire_resources),
	.resource	= uwire_resources,
};

static void omap_init_uwire(void)
{
	/* FIXME define and use a boot tag; not all boards will be hooking
	 * up devices to the microwire controller, and multi-board configs
	 * mean that CONFIG_SPI_OMAP_UWIRE may be configured anyway...
	 */

	/* board-specific code must configure chipselects (only a few
	 * are normally used) and SCLK/SDI/SDO (each has two choices).
	 */
	(void) platform_device_register(&omap_uwire_device);
}
#else
static inline void omap_init_uwire(void) {}
#endif

/*-------------------------------------------------------------------------*/

#if	defined(CONFIG_OMAP_WATCHDOG) || defined(CONFIG_OMAP_WATCHDOG_MODULE)

#ifdef CONFIG_ARCH_OMAP24XX
#define	OMAP_WDT_BASE		0x48022000
#else
#define	OMAP_WDT_BASE		0xfffeb000
#endif

static struct resource wdt_resources[] = {
	{
		.start		= OMAP_WDT_BASE,
		.end		= OMAP_WDT_BASE + 0x4f,
		.flags		= IORESOURCE_MEM,
	},
};

static struct platform_device omap_wdt_device = {
	.name	   = "omap_wdt",
	.id	     = -1,
	.num_resources	= ARRAY_SIZE(wdt_resources),
	.resource	= wdt_resources,
};

static void omap_init_wdt(void)
{
	(void) platform_device_register(&omap_wdt_device);
}
#else
static inline void omap_init_wdt(void) {}
#endif

/*-------------------------------------------------------------------------*/

#if defined(CONFIG_HW_RANDOM_OMAP) || defined(CONFIG_HW_RANDOM_OMAP_MODULE)

#ifdef CONFIG_ARCH_OMAP24XX
#define	OMAP_RNG_BASE		0x480A0000
#else
#define	OMAP_RNG_BASE		0xfffe5000
#endif

static struct resource rng_resources[] = {
	{
		.start		= OMAP_RNG_BASE,
		.end		= OMAP_RNG_BASE + 0x4f,
		.flags		= IORESOURCE_MEM,
	},
};

static struct platform_device omap_rng_device = {
	.name	   = "omap_rng",
	.id	     = -1,
	.num_resources	= ARRAY_SIZE(rng_resources),
	.resource	= rng_resources,
};

static void omap_init_rng(void)
{
	(void) platform_device_register(&omap_rng_device);
}
#else
static inline void omap_init_rng(void) {}
#endif

/*
 * This gets called after board-specific INIT_MACHINE, and initializes most
 * on-chip peripherals accessible on this board (except for few like USB):
 *
 *  (a) Does any "standard config" pin muxing needed.  Board-specific
 *	code will have muxed GPIO pins and done "nonstandard" setup;
 *	that code could live in the boot loader.
 *  (b) Populating board-specific platform_data with the data drivers
 *	rely on to handle wiring variations.
 *  (c) Creating platform devices as meaningful on this board and
 *	with this kernel configuration.
 *
 * Claiming GPIOs, and setting their direction and initial values, is the
 * responsibility of the device drivers.  So is responding to probe().
 *
 * Board-specific knowlege like creating devices or pin setup is to be
 * kept out of drivers as much as possible.  In particular, pin setup
 * may be handled by the boot loader, and drivers should expect it will
 * normally have been done by the time they're probed.
 */
static int __init omap_init_devices(void)
{
/*
 * Need to enable relevant once for 2430 SDP
 */
#ifndef CONFIG_MACH_OMAP_2430SDP
	/* please keep these calls, and their implementations above,
	 * in alphabetical order so they're easier to sort through.
	 */
	omap_init_dsp();
	omap_init_kp();
	omap_init_mmc();
	omap_init_uwire();
	omap_init_wdt();
	omap_init_rng();
#endif
	return 0;
}
arch_initcall(omap_init_devices);
Commit	Line	Data
1a8bfa1e TL	1	/*
	2	* linux/arch/arm/plat-omap/devices.c
	3	*
	4	* Common platform device setup/initialization for OMAP1 and OMAP2
	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License as published by
	8	* the Free Software Foundation; either version 2 of the License, or
	9	* (at your option) any later version.
	10	*/
	11
1a8bfa1e TL	12	#include <linux/module.h>
	13	#include <linux/kernel.h>
	14	#include <linux/init.h>
	15	#include <linux/platform_device.h>
	16
	17	#include <asm/hardware.h>
	18	#include <asm/io.h>
	19	#include <asm/mach-types.h>
	20	#include <asm/mach/map.h>
	21
	22	#include <asm/arch/tc.h>
	23	#include <asm/arch/board.h>
	24	#include <asm/arch/mux.h>
	25	#include <asm/arch/gpio.h>
9b6553cd	26	#include <asm/arch/menelaus.h>
1a8bfa1e	27
c40fae95 TL	28	#if defined(CONFIG_OMAP_DSP) \|\| defined(CONFIG_OMAP_DSP_MODULE)
	29
	30	#include "../plat-omap/dsp/dsp_common.h"
	31
	32	static struct dsp_platform_data dsp_pdata = {
	33	.kdev_list = LIST_HEAD_INIT(dsp_pdata.kdev_list),
	34	};
	35
	36	static struct resource omap_dsp_resources[] = {
	37	{
	38	.name = "dsp_mmu",
	39	.start = -1,
	40	.flags = IORESOURCE_IRQ,
	41	},
	42	};
	43
	44	static struct platform_device omap_dsp_device = {
	45	.name = "dsp",
	46	.id = -1,
	47	.num_resources = ARRAY_SIZE(omap_dsp_resources),
	48	.resource = omap_dsp_resources,
	49	.dev = {
	50	.platform_data = &dsp_pdata,
	51	},
	52	};
	53
	54	static inline void omap_init_dsp(void)
	55	{
	56	struct resource *res;
	57	int irq;
	58
	59	if (cpu_is_omap15xx())
	60	irq = INT_1510_DSP_MMU;
	61	else if (cpu_is_omap16xx())
	62	irq = INT_1610_DSP_MMU;
	63	else if (cpu_is_omap24xx())
	64	irq = INT_24XX_DSP_MMU;
	65
	66	res = platform_get_resource_byname(&omap_dsp_device,
	67	IORESOURCE_IRQ, "dsp_mmu");
	68	res->start = irq;
	69
	70	platform_device_register(&omap_dsp_device);
	71	}
	72
	73	int dsp_kfunc_device_register(struct dsp_kfunc_device *kdev)
	74	{
	75	static DEFINE_MUTEX(dsp_pdata_lock);
	76
	77	mutex_init(&kdev->lock);
	78
	79	mutex_lock(&dsp_pdata_lock);
	80	list_add_tail(&kdev->entry, &dsp_pdata.kdev_list);
	81	mutex_unlock(&dsp_pdata_lock);
	82
	83	return 0;
	84	}
	85	EXPORT_SYMBOL(dsp_kfunc_device_register);
	86
	87	#else
	88	static inline void omap_init_dsp(void) { }
	89	#endif /* CONFIG_OMAP_DSP */
	90
9b6553cd TL	91	/-------------------------------------------------------------------------/
	92	#if defined(CONFIG_KEYBOARD_OMAP) \|\| defined(CONFIG_KEYBOARD_OMAP_MODULE)
	93
	94	static void omap_init_kp(void)
	95	{
	96	if (machine_is_omap_h2() \|\| machine_is_omap_h3()) {
	97	omap_cfg_reg(F18_1610_KBC0);
	98	omap_cfg_reg(D20_1610_KBC1);
	99	omap_cfg_reg(D19_1610_KBC2);
	100	omap_cfg_reg(E18_1610_KBC3);
	101	omap_cfg_reg(C21_1610_KBC4);
	102
	103	omap_cfg_reg(G18_1610_KBR0);
	104	omap_cfg_reg(F19_1610_KBR1);
	105	omap_cfg_reg(H14_1610_KBR2);
	106	omap_cfg_reg(E20_1610_KBR3);
	107	omap_cfg_reg(E19_1610_KBR4);
	108	omap_cfg_reg(N19_1610_KBR5);
495f71db	109	} else if (machine_is_omap_perseus2() \|\| machine_is_omap_fsample()) {
9b6553cd TL	110	omap_cfg_reg(E2_730_KBR0);
	111	omap_cfg_reg(J7_730_KBR1);
	112	omap_cfg_reg(E1_730_KBR2);
	113	omap_cfg_reg(F3_730_KBR3);
	114	omap_cfg_reg(D2_730_KBR4);
	115
	116	omap_cfg_reg(C2_730_KBC0);
	117	omap_cfg_reg(D3_730_KBC1);
	118	omap_cfg_reg(E4_730_KBC2);
	119	omap_cfg_reg(F4_730_KBC3);
	120	omap_cfg_reg(E3_730_KBC4);
	121	} else if (machine_is_omap_h4()) {
	122	omap_cfg_reg(T19_24XX_KBR0);
	123	omap_cfg_reg(R19_24XX_KBR1);
	124	omap_cfg_reg(V18_24XX_KBR2);
	125	omap_cfg_reg(M21_24XX_KBR3);
	126	omap_cfg_reg(E5__24XX_KBR4);
	127	if (omap_has_menelaus()) {
	128	omap_cfg_reg(B3__24XX_KBR5);
	129	omap_cfg_reg(AA4_24XX_KBC2);
	130	omap_cfg_reg(B13_24XX_KBC6);
	131	} else {
	132	omap_cfg_reg(M18_24XX_KBR5);
	133	omap_cfg_reg(H19_24XX_KBC2);
	134	omap_cfg_reg(N19_24XX_KBC6);
	135	}
	136	omap_cfg_reg(R20_24XX_KBC0);
	137	omap_cfg_reg(M14_24XX_KBC1);
	138	omap_cfg_reg(V17_24XX_KBC3);
	139	omap_cfg_reg(P21_24XX_KBC4);
	140	omap_cfg_reg(L14_24XX_KBC5);
	141	}
	142	}
	143	#else
	144	static inline void omap_init_kp(void) {}
	145	#endif
	146
1a8bfa1e TL	147	/-------------------------------------------------------------------------/
	148
	149	#if defined(CONFIG_MMC_OMAP) \|\| defined(CONFIG_MMC_OMAP_MODULE)
	150
	151	#ifdef CONFIG_ARCH_OMAP24XX
	152	#define OMAP_MMC1_BASE 0x4809c000
abc45e1d	153	#define OMAP_MMC1_INT INT_24XX_MMC_IRQ
1a8bfa1e TL	154	#else
	155	#define OMAP_MMC1_BASE 0xfffb7800
	156	#define OMAP_MMC1_INT INT_MMC
	157	#endif
	158	#define OMAP_MMC2_BASE 0xfffb7c00 /* omap16xx only */
	159
	160	static struct omap_mmc_conf mmc1_conf;
	161
	162	static u64 mmc1_dmamask = 0xffffffff;
	163
	164	static struct resource mmc1_resources[] = {
	165	{
ce9c1a83 TL	166	.start = OMAP_MMC1_BASE,
ce9c1a83 TL	167	.end = OMAP_MMC1_BASE + 0x7f,
1a8bfa1e TL	168	.flags = IORESOURCE_MEM,
	169	},
	170	{
	171	.start = OMAP_MMC1_INT,
	172	.flags = IORESOURCE_IRQ,
	173	},
	174	};
	175
	176	static struct platform_device mmc_omap_device1 = {
	177	.name = "mmci-omap",
	178	.id = 1,
	179	.dev = {
1a8bfa1e TL	180	.dma_mask = &mmc1_dmamask,
	181	.platform_data = &mmc1_conf,
	182	},
	183	.num_resources = ARRAY_SIZE(mmc1_resources),
	184	.resource = mmc1_resources,
	185	};
	186
	187	#ifdef CONFIG_ARCH_OMAP16XX
	188
	189	static struct omap_mmc_conf mmc2_conf;
	190
	191	static u64 mmc2_dmamask = 0xffffffff;
	192
	193	static struct resource mmc2_resources[] = {
	194	{
ce9c1a83 TL	195	.start = OMAP_MMC2_BASE,
ce9c1a83 TL	196	.end = OMAP_MMC2_BASE + 0x7f,
1a8bfa1e TL	197	.flags = IORESOURCE_MEM,
	198	},
	199	{
	200	.start = INT_1610_MMC2,
	201	.flags = IORESOURCE_IRQ,
	202	},
	203	};
	204
	205	static struct platform_device mmc_omap_device2 = {
	206	.name = "mmci-omap",
	207	.id = 2,
	208	.dev = {
1a8bfa1e TL	209	.dma_mask = &mmc2_dmamask,
	210	.platform_data = &mmc2_conf,
	211	},
	212	.num_resources = ARRAY_SIZE(mmc2_resources),
	213	.resource = mmc2_resources,
	214	};
	215	#endif
	216
	217	static void __init omap_init_mmc(void)
	218	{
	219	const struct omap_mmc_config *mmc_conf;
	220	const struct omap_mmc_conf *mmc;
	221
	222	/* NOTE: assumes MMC was never (wrongly) enabled */
	223	mmc_conf = omap_get_config(OMAP_TAG_MMC, struct omap_mmc_config);
	224	if (!mmc_conf)
	225	return;
	226
	227	/* block 1 is always available and has just one pinout option */
	228	mmc = &mmc_conf->mmc[0];
	229	if (mmc->enabled) {
abc45e1d KP	230	if (cpu_is_omap24xx()) {
	231	omap_cfg_reg(H18_24XX_MMC_CMD);
	232	omap_cfg_reg(H15_24XX_MMC_CLKI);
	233	omap_cfg_reg(G19_24XX_MMC_CLKO);
	234	omap_cfg_reg(F20_24XX_MMC_DAT0);
	235	omap_cfg_reg(F19_24XX_MMC_DAT_DIR0);
	236	omap_cfg_reg(G18_24XX_MMC_CMD_DIR);
	237	} else {
1a8bfa1e TL	238	omap_cfg_reg(MMC_CMD);
	239	omap_cfg_reg(MMC_CLK);
	240	omap_cfg_reg(MMC_DAT0);
	241	if (cpu_is_omap1710()) {
	242	omap_cfg_reg(M15_1710_MMC_CLKI);
	243	omap_cfg_reg(P19_1710_MMC_CMDDIR);
	244	omap_cfg_reg(P20_1710_MMC_DATDIR0);
	245	}
	246	}
	247	if (mmc->wire4) {
abc45e1d KP	248	if (cpu_is_omap24xx()) {
	249	omap_cfg_reg(H14_24XX_MMC_DAT1);
	250	omap_cfg_reg(E19_24XX_MMC_DAT2);
	251	omap_cfg_reg(D19_24XX_MMC_DAT3);
	252	omap_cfg_reg(E20_24XX_MMC_DAT_DIR1);
	253	omap_cfg_reg(F18_24XX_MMC_DAT_DIR2);
	254	omap_cfg_reg(E18_24XX_MMC_DAT_DIR3);
	255	} else {
1a8bfa1e TL	256	omap_cfg_reg(MMC_DAT1);
	257	/* NOTE: DAT2 can be on W10 (here) or M15 */
	258	if (!mmc->nomux)
	259	omap_cfg_reg(MMC_DAT2);
	260	omap_cfg_reg(MMC_DAT3);
	261	}
	262	}
	263	mmc1_conf = *mmc;
	264	(void) platform_device_register(&mmc_omap_device1);
	265	}
	266
	267	#ifdef CONFIG_ARCH_OMAP16XX
	268	/* block 2 is on newer chips, and has many pinout options */
	269	mmc = &mmc_conf->mmc[1];
	270	if (mmc->enabled) {
	271	if (!mmc->nomux) {
	272	omap_cfg_reg(Y8_1610_MMC2_CMD);
	273	omap_cfg_reg(Y10_1610_MMC2_CLK);
	274	omap_cfg_reg(R18_1610_MMC2_CLKIN);
	275	omap_cfg_reg(W8_1610_MMC2_DAT0);
	276	if (mmc->wire4) {
	277	omap_cfg_reg(V8_1610_MMC2_DAT1);
	278	omap_cfg_reg(W15_1610_MMC2_DAT2);
	279	omap_cfg_reg(R10_1610_MMC2_DAT3);
	280	}
	281
	282	/* These are needed for the level shifter */
	283	omap_cfg_reg(V9_1610_MMC2_CMDDIR);
	284	omap_cfg_reg(V5_1610_MMC2_DATDIR0);
	285	omap_cfg_reg(W19_1610_MMC2_DATDIR1);
	286	}
	287
	288	/* Feedback clock must be set on OMAP-1710 MMC2 */
	289	if (cpu_is_omap1710())
	290	omap_writel(omap_readl(MOD_CONF_CTRL_1) \| (1 << 24),
	291	MOD_CONF_CTRL_1);
	292	mmc2_conf = *mmc;
	293	(void) platform_device_register(&mmc_omap_device2);
	294	}
	295	#endif
	296	return;
	297	}
	298	#else
	299	static inline void omap_init_mmc(void) {}
	300	#endif
	301
9b6553cd TL	302	/-------------------------------------------------------------------------/
	303
	304	/* Numbering for the SPI-capable controllers when used for SPI:
	305	* spi = 1
	306	* uwire = 2
	307	* mmc1..2 = 3..4
	308	* mcbsp1..3 = 5..7
	309	*/
	310
	311	#if defined(CONFIG_SPI_OMAP_UWIRE) \|\| defined(CONFIG_SPI_OMAP_UWIRE_MODULE)
	312
	313	#define OMAP_UWIRE_BASE 0xfffb3000
	314
	315	static struct resource uwire_resources[] = {
	316	{
	317	.start = OMAP_UWIRE_BASE,
	318	.end = OMAP_UWIRE_BASE + 0x20,
	319	.flags = IORESOURCE_MEM,
	320	},
	321	};
	322
	323	static struct platform_device omap_uwire_device = {
	324	.name = "omap_uwire",
	325	.id = -1,
9b6553cd TL	326	.num_resources = ARRAY_SIZE(uwire_resources),
	327	.resource = uwire_resources,
	328	};
	329
	330	static void omap_init_uwire(void)
	331	{
	332	/* FIXME define and use a boot tag; not all boards will be hooking
	333	* up devices to the microwire controller, and multi-board configs
	334	* mean that CONFIG_SPI_OMAP_UWIRE may be configured anyway...
	335	*/
	336
	337	/* board-specific code must configure chipselects (only a few
	338	* are normally used) and SCLK/SDI/SDO (each has two choices).
	339	*/
	340	(void) platform_device_register(&omap_uwire_device);
	341	}
	342	#else
	343	static inline void omap_init_uwire(void) {}
	344	#endif
	345
	346	/-------------------------------------------------------------------------/
	347
1a8bfa1e TL	348	#if defined(CONFIG_OMAP_WATCHDOG) \|\| defined(CONFIG_OMAP_WATCHDOG_MODULE)
	349
	350	#ifdef CONFIG_ARCH_OMAP24XX
	351	#define OMAP_WDT_BASE 0x48022000
	352	#else
	353	#define OMAP_WDT_BASE 0xfffeb000
	354	#endif
	355
	356	static struct resource wdt_resources[] = {
	357	{
	358	.start = OMAP_WDT_BASE,
	359	.end = OMAP_WDT_BASE + 0x4f,
	360	.flags = IORESOURCE_MEM,
	361	},
	362	};
	363
	364	static struct platform_device omap_wdt_device = {
	365	.name = "omap_wdt",
	366	.id = -1,
1a8bfa1e TL	367	.num_resources = ARRAY_SIZE(wdt_resources),
	368	.resource = wdt_resources,
	369	};
	370
	371	static void omap_init_wdt(void)
	372	{
	373	(void) platform_device_register(&omap_wdt_device);
	374	}
	375	#else
	376	static inline void omap_init_wdt(void) {}
	377	#endif
	378
	379	/-------------------------------------------------------------------------/
	380
c40fae95	381	#if defined(CONFIG_HW_RANDOM_OMAP) \|\| defined(CONFIG_HW_RANDOM_OMAP_MODULE)
1a8bfa1e TL	382
	383	#ifdef CONFIG_ARCH_OMAP24XX
	384	#define OMAP_RNG_BASE 0x480A0000
	385	#else
	386	#define OMAP_RNG_BASE 0xfffe5000
	387	#endif
	388
	389	static struct resource rng_resources[] = {
	390	{
	391	.start = OMAP_RNG_BASE,
	392	.end = OMAP_RNG_BASE + 0x4f,
	393	.flags = IORESOURCE_MEM,
	394	},
	395	};
	396
	397	static struct platform_device omap_rng_device = {
	398	.name = "omap_rng",
	399	.id = -1,
1a8bfa1e TL	400	.num_resources = ARRAY_SIZE(rng_resources),
	401	.resource = rng_resources,
	402	};
	403
	404	static void omap_init_rng(void)
	405	{
	406	(void) platform_device_register(&omap_rng_device);
	407	}
	408	#else
	409	static inline void omap_init_rng(void) {}
	410	#endif
	411
1a8bfa1e TL	412	/*
	413	* This gets called after board-specific INIT_MACHINE, and initializes most
	414	* on-chip peripherals accessible on this board (except for few like USB):
	415	*
	416	* (a) Does any "standard config" pin muxing needed. Board-specific
	417	* code will have muxed GPIO pins and done "nonstandard" setup;
	418	* that code could live in the boot loader.
	419	* (b) Populating board-specific platform_data with the data drivers
	420	* rely on to handle wiring variations.
	421	* (c) Creating platform devices as meaningful on this board and
	422	* with this kernel configuration.
	423	*
	424	* Claiming GPIOs, and setting their direction and initial values, is the
	425	* responsibility of the device drivers. So is responding to probe().
	426	*
	427	* Board-specific knowlege like creating devices or pin setup is to be
	428	* kept out of drivers as much as possible. In particular, pin setup
	429	* may be handled by the boot loader, and drivers should expect it will
	430	* normally have been done by the time they're probed.
	431	*/
	432	static int __init omap_init_devices(void)
	433	{
56a25641 SMK	434	/*
	435	* Need to enable relevant once for 2430 SDP
	436	*/
	437	#ifndef CONFIG_MACH_OMAP_2430SDP
1a8bfa1e TL	438	/* please keep these calls, and their implementations above,
	439	* in alphabetical order so they're easier to sort through.
	440	*/
c40fae95	441	omap_init_dsp();
9b6553cd	442	omap_init_kp();
1a8bfa1e	443	omap_init_mmc();
9b6553cd	444	omap_init_uwire();
1a8bfa1e TL	445	omap_init_wdt();
1a8bfa1e TL	446	omap_init_rng();
56a25641	447	#endif
1a8bfa1e TL	448	return 0;
	449	}
	450	arch_initcall(omap_init_devices);