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aa218daf PW |
1 | /* |
2 | * OMAP 32ksynctimer/counter_32k-related code | |
3 | * | |
4 | * Copyright (C) 2009 Texas Instruments | |
5 | * Copyright (C) 2010 Nokia Corporation | |
6 | * Tony Lindgren <tony@atomide.com> | |
7 | * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com> | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License version 2 as | |
11 | * published by the Free Software Foundation. | |
12 | * | |
13 | * NOTE: This timer is not the same timer as the old OMAP1 MPU timer. | |
14 | */ | |
15 | #include <linux/kernel.h> | |
16 | #include <linux/init.h> | |
17 | #include <linux/clk.h> | |
cb9675f3 | 18 | #include <linux/err.h> |
aa218daf | 19 | #include <linux/io.h> |
354a183f | 20 | #include <linux/clocksource.h> |
aa218daf | 21 | |
bd0493ea | 22 | #include <asm/mach/time.h> |
dc548fbb | 23 | #include <asm/sched_clock.h> |
aa218daf | 24 | |
6ccc432f PW |
25 | #include <plat/counter-32k.h> |
26 | ||
1fe97c8f | 27 | /* OMAP2_32KSYNCNT_CR_OFF: offset of 32ksync counter register */ |
b009366f S |
28 | #define OMAP2_32KSYNCNT_REV_OFF 0x0 |
29 | #define OMAP2_32KSYNCNT_REV_SCHEME (0x3 << 30) | |
30 | #define OMAP2_32KSYNCNT_CR_OFF_LOW 0x10 | |
31 | #define OMAP2_32KSYNCNT_CR_OFF_HIGH 0x30 | |
1fe97c8f | 32 | |
aa218daf PW |
33 | /* |
34 | * 32KHz clocksource ... always available, on pretty most chips except | |
35 | * OMAP 730 and 1510. Other timers could be used as clocksources, with | |
36 | * higher resolution in free-running counter modes (e.g. 12 MHz xtal), | |
37 | * but systems won't necessarily want to spend resources that way. | |
38 | */ | |
1fe97c8f | 39 | static void __iomem *sync32k_cnt_reg; |
aa218daf | 40 | |
2f0778af | 41 | static u32 notrace omap_32k_read_sched_clock(void) |
aa218daf | 42 | { |
1fe97c8f | 43 | return sync32k_cnt_reg ? __raw_readl(sync32k_cnt_reg) : 0; |
aa218daf PW |
44 | } |
45 | ||
46 | /** | |
bd0493ea | 47 | * omap_read_persistent_clock - Return time from a persistent clock. |
aa218daf PW |
48 | * |
49 | * Reads the time from a source which isn't disabled during PM, the | |
50 | * 32k sync timer. Convert the cycles elapsed since last read into | |
51 | * nsecs and adds to a monotonically increasing timespec. | |
52 | */ | |
53 | static struct timespec persistent_ts; | |
9d7d6e36 | 54 | static cycles_t cycles; |
354a183f | 55 | static unsigned int persistent_mult, persistent_shift; |
9d7d6e36 CC |
56 | static DEFINE_SPINLOCK(read_persistent_clock_lock); |
57 | ||
bd0493ea | 58 | static void omap_read_persistent_clock(struct timespec *ts) |
aa218daf PW |
59 | { |
60 | unsigned long long nsecs; | |
9d7d6e36 CC |
61 | cycles_t last_cycles; |
62 | unsigned long flags; | |
63 | ||
64 | spin_lock_irqsave(&read_persistent_clock_lock, flags); | |
aa218daf PW |
65 | |
66 | last_cycles = cycles; | |
1fe97c8f | 67 | cycles = sync32k_cnt_reg ? __raw_readl(sync32k_cnt_reg) : 0; |
aa218daf | 68 | |
9d7d6e36 CC |
69 | nsecs = clocksource_cyc2ns(cycles - last_cycles, |
70 | persistent_mult, persistent_shift); | |
71 | ||
72 | timespec_add_ns(&persistent_ts, nsecs); | |
73 | ||
74 | *ts = persistent_ts; | |
aa218daf | 75 | |
9d7d6e36 | 76 | spin_unlock_irqrestore(&read_persistent_clock_lock, flags); |
aa218daf PW |
77 | } |
78 | ||
1fe97c8f VH |
79 | /** |
80 | * omap_init_clocksource_32k - setup and register counter 32k as a | |
81 | * kernel clocksource | |
82 | * @pbase: base addr of counter_32k module | |
83 | * @size: size of counter_32k to map | |
84 | * | |
85 | * Returns 0 upon success or negative error code upon failure. | |
86 | * | |
87 | */ | |
88 | int __init omap_init_clocksource_32k(void __iomem *vbase) | |
aa218daf | 89 | { |
1fe97c8f VH |
90 | int ret; |
91 | ||
92 | /* | |
b009366f S |
93 | * 32k sync Counter IP register offsets vary between the |
94 | * highlander version and the legacy ones. | |
95 | * The 'SCHEME' bits(30-31) of the revision register is used | |
96 | * to identify the version. | |
1fe97c8f | 97 | */ |
b009366f S |
98 | if (__raw_readl(vbase + OMAP2_32KSYNCNT_REV_OFF) & |
99 | OMAP2_32KSYNCNT_REV_SCHEME) | |
100 | sync32k_cnt_reg = vbase + OMAP2_32KSYNCNT_CR_OFF_HIGH; | |
101 | else | |
102 | sync32k_cnt_reg = vbase + OMAP2_32KSYNCNT_CR_OFF_LOW; | |
1fe97c8f VH |
103 | |
104 | /* | |
105 | * 120000 rough estimate from the calculations in | |
106 | * __clocksource_updatefreq_scale. | |
107 | */ | |
108 | clocks_calc_mult_shift(&persistent_mult, &persistent_shift, | |
109 | 32768, NSEC_PER_SEC, 120000); | |
110 | ||
111 | ret = clocksource_mmio_init(sync32k_cnt_reg, "32k_counter", 32768, | |
112 | 250, 32, clocksource_mmio_readl_up); | |
113 | if (ret) { | |
114 | pr_err("32k_counter: can't register clocksource\n"); | |
115 | return ret; | |
aa218daf | 116 | } |
1fe97c8f VH |
117 | |
118 | setup_sched_clock(omap_32k_read_sched_clock, 32, 32768); | |
2c757fd5 | 119 | register_persistent_clock(NULL, omap_read_persistent_clock); |
1fe97c8f VH |
120 | pr_info("OMAP clocksource: 32k_counter at 32768 Hz\n"); |
121 | ||
aa218daf PW |
122 | return 0; |
123 | } |