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aa218daf PW |
1 | /* |
2 | * OMAP 32ksynctimer/counter_32k-related code | |
3 | * | |
4 | * Copyright (C) 2009 Texas Instruments | |
5 | * Copyright (C) 2010 Nokia Corporation | |
6 | * Tony Lindgren <tony@atomide.com> | |
7 | * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com> | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License version 2 as | |
11 | * published by the Free Software Foundation. | |
12 | * | |
13 | * NOTE: This timer is not the same timer as the old OMAP1 MPU timer. | |
14 | */ | |
15 | #include <linux/kernel.h> | |
16 | #include <linux/init.h> | |
17 | #include <linux/clk.h> | |
cb9675f3 | 18 | #include <linux/err.h> |
aa218daf | 19 | #include <linux/io.h> |
354a183f | 20 | #include <linux/clocksource.h> |
aa218daf | 21 | |
bd0493ea | 22 | #include <asm/mach/time.h> |
dc548fbb | 23 | #include <asm/sched_clock.h> |
aa218daf | 24 | |
e6a6e5ad | 25 | #include "common.h" |
aa218daf PW |
26 | #include <plat/clock.h> |
27 | ||
1fe97c8f | 28 | /* OMAP2_32KSYNCNT_CR_OFF: offset of 32ksync counter register */ |
b009366f S |
29 | #define OMAP2_32KSYNCNT_REV_OFF 0x0 |
30 | #define OMAP2_32KSYNCNT_REV_SCHEME (0x3 << 30) | |
31 | #define OMAP2_32KSYNCNT_CR_OFF_LOW 0x10 | |
32 | #define OMAP2_32KSYNCNT_CR_OFF_HIGH 0x30 | |
1fe97c8f | 33 | |
aa218daf PW |
34 | /* |
35 | * 32KHz clocksource ... always available, on pretty most chips except | |
36 | * OMAP 730 and 1510. Other timers could be used as clocksources, with | |
37 | * higher resolution in free-running counter modes (e.g. 12 MHz xtal), | |
38 | * but systems won't necessarily want to spend resources that way. | |
39 | */ | |
1fe97c8f | 40 | static void __iomem *sync32k_cnt_reg; |
aa218daf | 41 | |
2f0778af | 42 | static u32 notrace omap_32k_read_sched_clock(void) |
aa218daf | 43 | { |
1fe97c8f | 44 | return sync32k_cnt_reg ? __raw_readl(sync32k_cnt_reg) : 0; |
aa218daf PW |
45 | } |
46 | ||
47 | /** | |
bd0493ea | 48 | * omap_read_persistent_clock - Return time from a persistent clock. |
aa218daf PW |
49 | * |
50 | * Reads the time from a source which isn't disabled during PM, the | |
51 | * 32k sync timer. Convert the cycles elapsed since last read into | |
52 | * nsecs and adds to a monotonically increasing timespec. | |
53 | */ | |
54 | static struct timespec persistent_ts; | |
9d7d6e36 | 55 | static cycles_t cycles; |
354a183f | 56 | static unsigned int persistent_mult, persistent_shift; |
9d7d6e36 CC |
57 | static DEFINE_SPINLOCK(read_persistent_clock_lock); |
58 | ||
bd0493ea | 59 | static void omap_read_persistent_clock(struct timespec *ts) |
aa218daf PW |
60 | { |
61 | unsigned long long nsecs; | |
9d7d6e36 CC |
62 | cycles_t last_cycles; |
63 | unsigned long flags; | |
64 | ||
65 | spin_lock_irqsave(&read_persistent_clock_lock, flags); | |
aa218daf PW |
66 | |
67 | last_cycles = cycles; | |
1fe97c8f | 68 | cycles = sync32k_cnt_reg ? __raw_readl(sync32k_cnt_reg) : 0; |
aa218daf | 69 | |
9d7d6e36 CC |
70 | nsecs = clocksource_cyc2ns(cycles - last_cycles, |
71 | persistent_mult, persistent_shift); | |
72 | ||
73 | timespec_add_ns(&persistent_ts, nsecs); | |
74 | ||
75 | *ts = persistent_ts; | |
aa218daf | 76 | |
9d7d6e36 | 77 | spin_unlock_irqrestore(&read_persistent_clock_lock, flags); |
aa218daf PW |
78 | } |
79 | ||
1fe97c8f VH |
80 | /** |
81 | * omap_init_clocksource_32k - setup and register counter 32k as a | |
82 | * kernel clocksource | |
83 | * @pbase: base addr of counter_32k module | |
84 | * @size: size of counter_32k to map | |
85 | * | |
86 | * Returns 0 upon success or negative error code upon failure. | |
87 | * | |
88 | */ | |
89 | int __init omap_init_clocksource_32k(void __iomem *vbase) | |
aa218daf | 90 | { |
1fe97c8f VH |
91 | int ret; |
92 | ||
93 | /* | |
b009366f S |
94 | * 32k sync Counter IP register offsets vary between the |
95 | * highlander version and the legacy ones. | |
96 | * The 'SCHEME' bits(30-31) of the revision register is used | |
97 | * to identify the version. | |
1fe97c8f | 98 | */ |
b009366f S |
99 | if (__raw_readl(vbase + OMAP2_32KSYNCNT_REV_OFF) & |
100 | OMAP2_32KSYNCNT_REV_SCHEME) | |
101 | sync32k_cnt_reg = vbase + OMAP2_32KSYNCNT_CR_OFF_HIGH; | |
102 | else | |
103 | sync32k_cnt_reg = vbase + OMAP2_32KSYNCNT_CR_OFF_LOW; | |
1fe97c8f VH |
104 | |
105 | /* | |
106 | * 120000 rough estimate from the calculations in | |
107 | * __clocksource_updatefreq_scale. | |
108 | */ | |
109 | clocks_calc_mult_shift(&persistent_mult, &persistent_shift, | |
110 | 32768, NSEC_PER_SEC, 120000); | |
111 | ||
112 | ret = clocksource_mmio_init(sync32k_cnt_reg, "32k_counter", 32768, | |
113 | 250, 32, clocksource_mmio_readl_up); | |
114 | if (ret) { | |
115 | pr_err("32k_counter: can't register clocksource\n"); | |
116 | return ret; | |
aa218daf | 117 | } |
1fe97c8f VH |
118 | |
119 | setup_sched_clock(omap_32k_read_sched_clock, 32, 32768); | |
2c757fd5 | 120 | register_persistent_clock(NULL, omap_read_persistent_clock); |
1fe97c8f VH |
121 | pr_info("OMAP clocksource: 32k_counter at 32768 Hz\n"); |
122 | ||
aa218daf PW |
123 | return 0; |
124 | } |