[linux-block.git] / arch / arm / plat-nomadik / include / plat / ste_dma40.h

/*
 * Copyright (C) ST-Ericsson SA 2007-2010
 * Author: Per Forlin <per.forlin@stericsson.com> for ST-Ericsson
 * Author: Jonas Aaberg <jonas.aberg@stericsson.com> for ST-Ericsson
 * License terms: GNU General Public License (GPL) version 2
 */


#ifndef STE_DMA40_H
#define STE_DMA40_H

#include <linux/dmaengine.h>
#include <linux/workqueue.h>
#include <linux/interrupt.h>

/* dev types for memcpy */
#define STEDMA40_DEV_DST_MEMORY (-1)
#define	STEDMA40_DEV_SRC_MEMORY (-1)

enum stedma40_mode {
	STEDMA40_MODE_LOGICAL = 0,
	STEDMA40_MODE_PHYSICAL,
	STEDMA40_MODE_OPERATION,
};

enum stedma40_mode_opt {
	STEDMA40_PCHAN_BASIC_MODE = 0,
	STEDMA40_LCHAN_SRC_LOG_DST_LOG = 0,
	STEDMA40_PCHAN_MODULO_MODE,
	STEDMA40_PCHAN_DOUBLE_DST_MODE,
	STEDMA40_LCHAN_SRC_PHY_DST_LOG,
	STEDMA40_LCHAN_SRC_LOG_DST_PHY,
};

#define STEDMA40_ESIZE_8_BIT  0x0
#define STEDMA40_ESIZE_16_BIT 0x1
#define STEDMA40_ESIZE_32_BIT 0x2
#define STEDMA40_ESIZE_64_BIT 0x3

/* The value 4 indicates that PEN-reg shall be set to 0 */
#define STEDMA40_PSIZE_PHY_1  0x4
#define STEDMA40_PSIZE_PHY_2  0x0
#define STEDMA40_PSIZE_PHY_4  0x1
#define STEDMA40_PSIZE_PHY_8  0x2
#define STEDMA40_PSIZE_PHY_16 0x3

/*
 * The number of elements differ in logical and
 * physical mode
 */
#define STEDMA40_PSIZE_LOG_1  STEDMA40_PSIZE_PHY_2
#define STEDMA40_PSIZE_LOG_4  STEDMA40_PSIZE_PHY_4
#define STEDMA40_PSIZE_LOG_8  STEDMA40_PSIZE_PHY_8
#define STEDMA40_PSIZE_LOG_16 STEDMA40_PSIZE_PHY_16

/* Maximum number of possible physical channels */
#define STEDMA40_MAX_PHYS 32

enum stedma40_flow_ctrl {
	STEDMA40_NO_FLOW_CTRL,
	STEDMA40_FLOW_CTRL,
};

enum stedma40_periph_data_width {
	STEDMA40_BYTE_WIDTH = STEDMA40_ESIZE_8_BIT,
	STEDMA40_HALFWORD_WIDTH = STEDMA40_ESIZE_16_BIT,
	STEDMA40_WORD_WIDTH = STEDMA40_ESIZE_32_BIT,
	STEDMA40_DOUBLEWORD_WIDTH = STEDMA40_ESIZE_64_BIT
};

enum stedma40_xfer_dir {
	STEDMA40_MEM_TO_MEM = 1,
	STEDMA40_MEM_TO_PERIPH,
	STEDMA40_PERIPH_TO_MEM,
	STEDMA40_PERIPH_TO_PERIPH
};


/**
 * struct stedma40_chan_cfg - dst/src channel configuration
 *
 * @big_endian: true if the src/dst should be read as big endian
 * @data_width: Data width of the src/dst hardware
 * @p_size: Burst size
 * @flow_ctrl: Flow control on/off.
 */
struct stedma40_half_channel_info {
	bool big_endian;
	enum stedma40_periph_data_width data_width;
	int psize;
	enum stedma40_flow_ctrl flow_ctrl;
};

/**
 * struct stedma40_chan_cfg - Structure to be filled by client drivers.
 *
 * @dir: MEM 2 MEM, PERIPH 2 MEM , MEM 2 PERIPH, PERIPH 2 PERIPH
 * @high_priority: true if high-priority
 * @mode: channel mode: physical, logical, or operation
 * @mode_opt: options for the chosen channel mode
 * @src_dev_type: Src device type
 * @dst_dev_type: Dst device type
 * @src_info: Parameters for dst half channel
 * @dst_info: Parameters for dst half channel
 *
 *
 * This structure has to be filled by the client drivers.
 * It is recommended to do all dma configurations for clients in the machine.
 *
 */
struct stedma40_chan_cfg {
	enum stedma40_xfer_dir			 dir;
	bool					 high_priority;
	enum stedma40_mode			 mode;
	enum stedma40_mode_opt			 mode_opt;
	int					 src_dev_type;
	int					 dst_dev_type;
	struct stedma40_half_channel_info	 src_info;
	struct stedma40_half_channel_info	 dst_info;
};

/**
 * struct stedma40_platform_data - Configuration struct for the dma device.
 *
 * @dev_len: length of dev_tx and dev_rx
 * @dev_tx: mapping between destination event line and io address
 * @dev_rx: mapping between source event line and io address
 * @memcpy: list of memcpy event lines
 * @memcpy_len: length of memcpy
 * @memcpy_conf_phy: default configuration of physical channel memcpy
 * @memcpy_conf_log: default configuration of logical channel memcpy
 * @disabled_channels: A vector, ending with -1, that marks physical channels
 * that are for different reasons not available for the driver.
 */
struct stedma40_platform_data {
	u32				 dev_len;
	const dma_addr_t		*dev_tx;
	const dma_addr_t		*dev_rx;
	int				*memcpy;
	u32				 memcpy_len;
	struct stedma40_chan_cfg	*memcpy_conf_phy;
	struct stedma40_chan_cfg	*memcpy_conf_log;
	int				 disabled_channels[STEDMA40_MAX_PHYS];
};

#ifdef CONFIG_STE_DMA40

/**
 * stedma40_filter() - Provides stedma40_chan_cfg to the
 * ste_dma40 dma driver via the dmaengine framework.
 * does some checking of what's provided.
 *
 * Never directly called by client. It used by dmaengine.
 * @chan: dmaengine handle.
 * @data: Must be of type: struct stedma40_chan_cfg and is
 * the configuration of the framework.
 *
 *
 */

bool stedma40_filter(struct dma_chan *chan, void *data);

/**
 * stedma40_memcpy_sg() - extension of the dma framework, memcpy to/from
 * scattergatter lists.
 *
 * @chan: dmaengine handle
 * @sgl_dst: Destination scatter list
 * @sgl_src: Source scatter list
 * @sgl_len: The length of each scatterlist. Both lists must be of equal length
 * and each element must match the corresponding element in the other scatter
 * list.
 * @flags: is actually enum dma_ctrl_flags. See dmaengine.h
 */

struct dma_async_tx_descriptor *stedma40_memcpy_sg(struct dma_chan *chan,
						   struct scatterlist *sgl_dst,
						   struct scatterlist *sgl_src,
						   unsigned int sgl_len,
						   unsigned long flags);

/**
 * stedma40_slave_mem() - Transfers a raw data buffer to or from a slave
 * (=device)
 *
 * @chan: dmaengine handle
 * @addr: source or destination physicall address.
 * @size: bytes to transfer
 * @direction: direction of transfer
 * @flags: is actually enum dma_ctrl_flags. See dmaengine.h
 */

static inline struct
dma_async_tx_descriptor *stedma40_slave_mem(struct dma_chan *chan,
					    dma_addr_t addr,
					    unsigned int size,
					    enum dma_data_direction direction,
					    unsigned long flags)
{
	struct scatterlist sg;
	sg_init_table(&sg, 1);
	sg.dma_address = addr;
	sg.length = size;

	return chan->device->device_prep_slave_sg(chan, &sg, 1,
						  direction, flags);
}

#else
static inline bool stedma40_filter(struct dma_chan *chan, void *data)
{
	return false;
}

static inline struct
dma_async_tx_descriptor *stedma40_slave_mem(struct dma_chan *chan,
					    dma_addr_t addr,
					    unsigned int size,
					    enum dma_data_direction direction,
					    unsigned long flags)
{
	return NULL;
}
#endif

#endif
Commit	Line	Data
8d318a50	1	/*
767a9675	2	* Copyright (C) ST-Ericsson SA 2007-2010
661385f9	3	* Author: Per Forlin <per.forlin@stericsson.com> for ST-Ericsson
767a9675	4	* Author: Jonas Aaberg <jonas.aberg@stericsson.com> for ST-Ericsson
8d318a50	5	* License terms: GNU General Public License (GPL) version 2
8d318a50 LW	6	*/
	7
	8
	9	#ifndef STE_DMA40_H
	10	#define STE_DMA40_H
	11
	12	#include <linux/dmaengine.h>
	13	#include <linux/workqueue.h>
	14	#include <linux/interrupt.h>
8d318a50 LW	15
	16	/* dev types for memcpy */
	17	#define STEDMA40_DEV_DST_MEMORY (-1)
	18	#define STEDMA40_DEV_SRC_MEMORY (-1)
	19
38bdbf02 RV	20	enum stedma40_mode {
	21	STEDMA40_MODE_LOGICAL = 0,
	22	STEDMA40_MODE_PHYSICAL,
	23	STEDMA40_MODE_OPERATION,
	24	};
8d318a50	25
20a5b6d0 RV	26	enum stedma40_mode_opt {
	27	STEDMA40_PCHAN_BASIC_MODE = 0,
	28	STEDMA40_LCHAN_SRC_LOG_DST_LOG = 0,
	29	STEDMA40_PCHAN_MODULO_MODE,
	30	STEDMA40_PCHAN_DOUBLE_DST_MODE,
	31	STEDMA40_LCHAN_SRC_PHY_DST_LOG,
	32	STEDMA40_LCHAN_SRC_LOG_DST_PHY,
	33	};
8d318a50 LW	34
	35	#define STEDMA40_ESIZE_8_BIT 0x0
	36	#define STEDMA40_ESIZE_16_BIT 0x1
	37	#define STEDMA40_ESIZE_32_BIT 0x2
	38	#define STEDMA40_ESIZE_64_BIT 0x3
	39
	40	/* The value 4 indicates that PEN-reg shall be set to 0 */
	41	#define STEDMA40_PSIZE_PHY_1 0x4
	42	#define STEDMA40_PSIZE_PHY_2 0x0
	43	#define STEDMA40_PSIZE_PHY_4 0x1
	44	#define STEDMA40_PSIZE_PHY_8 0x2
	45	#define STEDMA40_PSIZE_PHY_16 0x3
	46
	47	/*
	48	* The number of elements differ in logical and
	49	* physical mode
	50	*/
	51	#define STEDMA40_PSIZE_LOG_1 STEDMA40_PSIZE_PHY_2
	52	#define STEDMA40_PSIZE_LOG_4 STEDMA40_PSIZE_PHY_4
	53	#define STEDMA40_PSIZE_LOG_8 STEDMA40_PSIZE_PHY_8
	54	#define STEDMA40_PSIZE_LOG_16 STEDMA40_PSIZE_PHY_16
	55
767a9675 JA	56	/* Maximum number of possible physical channels */
	57	#define STEDMA40_MAX_PHYS 32
	58
8d318a50 LW	59	enum stedma40_flow_ctrl {
	60	STEDMA40_NO_FLOW_CTRL,
	61	STEDMA40_FLOW_CTRL,
	62	};
	63
8d318a50 LW	64	enum stedma40_periph_data_width {
	65	STEDMA40_BYTE_WIDTH = STEDMA40_ESIZE_8_BIT,
	66	STEDMA40_HALFWORD_WIDTH = STEDMA40_ESIZE_16_BIT,
	67	STEDMA40_WORD_WIDTH = STEDMA40_ESIZE_32_BIT,
	68	STEDMA40_DOUBLEWORD_WIDTH = STEDMA40_ESIZE_64_BIT
	69	};
	70
8d318a50	71	enum stedma40_xfer_dir {
0747c7ba	72	STEDMA40_MEM_TO_MEM = 1,
8d318a50 LW	73	STEDMA40_MEM_TO_PERIPH,
	74	STEDMA40_PERIPH_TO_MEM,
	75	STEDMA40_PERIPH_TO_PERIPH
	76	};
	77
	78
3c0f2401 JA	79	/**
	80	* struct stedma40_chan_cfg - dst/src channel configuration
	81	*
51f5d744	82	* @big_endian: true if the src/dst should be read as big endian
3c0f2401 JA	83	* @data_width: Data width of the src/dst hardware
	84	* @p_size: Burst size
	85	* @flow_ctrl: Flow control on/off.
	86	*/
	87	struct stedma40_half_channel_info {
51f5d744	88	bool big_endian;
3c0f2401 JA	89	enum stedma40_periph_data_width data_width;
	90	int psize;
	91	enum stedma40_flow_ctrl flow_ctrl;
	92	};
	93
8d318a50 LW	94	/**
	95	* struct stedma40_chan_cfg - Structure to be filled by client drivers.
	96	*
	97	* @dir: MEM 2 MEM, PERIPH 2 MEM , MEM 2 PERIPH, PERIPH 2 PERIPH
730c1871	98	* @high_priority: true if high-priority
38bdbf02	99	* @mode: channel mode: physical, logical, or operation
20a5b6d0	100	* @mode_opt: options for the chosen channel mode
8d318a50 LW	101	* @src_dev_type: Src device type
	102	* @dst_dev_type: Dst device type
	103	* @src_info: Parameters for dst half channel
	104	* @dst_info: Parameters for dst half channel
8d318a50 LW	105	*
	106	*
	107	* This structure has to be filled by the client drivers.
	108	* It is recommended to do all dma configurations for clients in the machine.
	109	*
	110	*/
	111	struct stedma40_chan_cfg {
	112	enum stedma40_xfer_dir dir;
730c1871	113	bool high_priority;
38bdbf02	114	enum stedma40_mode mode;
20a5b6d0	115	enum stedma40_mode_opt mode_opt;
8d318a50 LW	116	int src_dev_type;
	117	int dst_dev_type;
	118	struct stedma40_half_channel_info src_info;
	119	struct stedma40_half_channel_info dst_info;
8d318a50 LW	120	};
	121
	122	/**
	123	* struct stedma40_platform_data - Configuration struct for the dma device.
	124	*
	125	* @dev_len: length of dev_tx and dev_rx
	126	* @dev_tx: mapping between destination event line and io address
	127	* @dev_rx: mapping between source event line and io address
	128	* @memcpy: list of memcpy event lines
	129	* @memcpy_len: length of memcpy
	130	* @memcpy_conf_phy: default configuration of physical channel memcpy
	131	* @memcpy_conf_log: default configuration of logical channel memcpy
59516725 JA	132	* @disabled_channels: A vector, ending with -1, that marks physical channels
59516725 JA	133	* that are for different reasons not available for the driver.
8d318a50 LW	134	*/
	135	struct stedma40_platform_data {
	136	u32 dev_len;
	137	const dma_addr_t *dev_tx;
	138	const dma_addr_t *dev_rx;
	139	int *memcpy;
	140	u32 memcpy_len;
	141	struct stedma40_chan_cfg *memcpy_conf_phy;
	142	struct stedma40_chan_cfg *memcpy_conf_log;
767a9675	143	int disabled_channels[STEDMA40_MAX_PHYS];
8d318a50 LW	144	};
8d318a50 LW	145
9646b798	146	#ifdef CONFIG_STE_DMA40
8d318a50 LW	147
	148	/**
	149	* stedma40_filter() - Provides stedma40_chan_cfg to the
	150	* ste_dma40 dma driver via the dmaengine framework.
	151	* does some checking of what's provided.
	152	*
	153	* Never directly called by client. It used by dmaengine.
	154	* @chan: dmaengine handle.
	155	* @data: Must be of type: struct stedma40_chan_cfg and is
	156	* the configuration of the framework.
	157	*
	158	*
	159	*/
	160
	161	bool stedma40_filter(struct dma_chan chan, void data);
	162
	163	/**
	164	* stedma40_memcpy_sg() - extension of the dma framework, memcpy to/from
	165	* scattergatter lists.
	166	*
	167	* @chan: dmaengine handle
	168	* @sgl_dst: Destination scatter list
	169	* @sgl_src: Source scatter list
	170	* @sgl_len: The length of each scatterlist. Both lists must be of equal length
	171	* and each element must match the corresponding element in the other scatter
	172	* list.
	173	* @flags: is actually enum dma_ctrl_flags. See dmaengine.h
	174	*/
	175
	176	struct dma_async_tx_descriptor stedma40_memcpy_sg(struct dma_chan chan,
	177	struct scatterlist *sgl_dst,
	178	struct scatterlist *sgl_src,
	179	unsigned int sgl_len,
	180	unsigned long flags);
	181
	182	/**
	183	* stedma40_slave_mem() - Transfers a raw data buffer to or from a slave
	184	* (=device)
	185	*
	186	* @chan: dmaengine handle
	187	* @addr: source or destination physicall address.
	188	* @size: bytes to transfer
	189	* @direction: direction of transfer
	190	* @flags: is actually enum dma_ctrl_flags. See dmaengine.h
	191	*/
	192
	193	static inline struct
	194	dma_async_tx_descriptor stedma40_slave_mem(struct dma_chan chan,
	195	dma_addr_t addr,
	196	unsigned int size,
	197	enum dma_data_direction direction,
	198	unsigned long flags)
	199	{
	200	struct scatterlist sg;
	201	sg_init_table(&sg, 1);
	202	sg.dma_address = addr;
	203	sg.length = size;
	204
	205	return chan->device->device_prep_slave_sg(chan, &sg, 1,
	206	direction, flags);
	207	}
	208
9646b798 LW	209	#else
	210	static inline bool stedma40_filter(struct dma_chan chan, void data)
	211	{
	212	return false;
	213	}
	214
	215	static inline struct
	216	dma_async_tx_descriptor stedma40_slave_mem(struct dma_chan chan,
	217	dma_addr_t addr,
	218	unsigned int size,
	219	enum dma_data_direction direction,
	220	unsigned long flags)
	221	{
	222	return NULL;
	223	}
	224	#endif
	225
8d318a50	226	#endif