[linux-2.6-block.git] / arch / arm / plat-nomadik / include / plat / ste_dma40.h

/*
 * Copyright (C) ST-Ericsson SA 2007-2010
 * Author: Per Forlin <per.forlin@stericsson.com> for ST-Ericsson
 * Author: Jonas Aaberg <jonas.aberg@stericsson.com> for ST-Ericsson
 * License terms: GNU General Public License (GPL) version 2
 */


#ifndef STE_DMA40_H
#define STE_DMA40_H

#include <linux/dmaengine.h>
#include <linux/workqueue.h>
#include <linux/interrupt.h>
#include <linux/dmaengine.h>

/* dev types for memcpy */
#define STEDMA40_DEV_DST_MEMORY (-1)
#define	STEDMA40_DEV_SRC_MEMORY (-1)

/*
 * Description of bitfields of channel_type variable is available in
 * the info structure.
 */

enum stedma40_mode {
	STEDMA40_MODE_LOGICAL = 0,
	STEDMA40_MODE_PHYSICAL,
	STEDMA40_MODE_OPERATION,
};

enum stedma40_mode_opt {
	STEDMA40_PCHAN_BASIC_MODE = 0,
	STEDMA40_LCHAN_SRC_LOG_DST_LOG = 0,
	STEDMA40_PCHAN_MODULO_MODE,
	STEDMA40_PCHAN_DOUBLE_DST_MODE,
	STEDMA40_LCHAN_SRC_PHY_DST_LOG,
	STEDMA40_LCHAN_SRC_LOG_DST_PHY,
};

/* End of channel_type configuration */

#define STEDMA40_ESIZE_8_BIT  0x0
#define STEDMA40_ESIZE_16_BIT 0x1
#define STEDMA40_ESIZE_32_BIT 0x2
#define STEDMA40_ESIZE_64_BIT 0x3

/* The value 4 indicates that PEN-reg shall be set to 0 */
#define STEDMA40_PSIZE_PHY_1  0x4
#define STEDMA40_PSIZE_PHY_2  0x0
#define STEDMA40_PSIZE_PHY_4  0x1
#define STEDMA40_PSIZE_PHY_8  0x2
#define STEDMA40_PSIZE_PHY_16 0x3

/*
 * The number of elements differ in logical and
 * physical mode
 */
#define STEDMA40_PSIZE_LOG_1  STEDMA40_PSIZE_PHY_2
#define STEDMA40_PSIZE_LOG_4  STEDMA40_PSIZE_PHY_4
#define STEDMA40_PSIZE_LOG_8  STEDMA40_PSIZE_PHY_8
#define STEDMA40_PSIZE_LOG_16 STEDMA40_PSIZE_PHY_16

/* Maximum number of possible physical channels */
#define STEDMA40_MAX_PHYS 32

enum stedma40_flow_ctrl {
	STEDMA40_NO_FLOW_CTRL,
	STEDMA40_FLOW_CTRL,
};

enum stedma40_endianess {
	STEDMA40_LITTLE_ENDIAN,
	STEDMA40_BIG_ENDIAN
};

enum stedma40_periph_data_width {
	STEDMA40_BYTE_WIDTH = STEDMA40_ESIZE_8_BIT,
	STEDMA40_HALFWORD_WIDTH = STEDMA40_ESIZE_16_BIT,
	STEDMA40_WORD_WIDTH = STEDMA40_ESIZE_32_BIT,
	STEDMA40_DOUBLEWORD_WIDTH = STEDMA40_ESIZE_64_BIT
};

enum stedma40_xfer_dir {
	STEDMA40_MEM_TO_MEM = 1,
	STEDMA40_MEM_TO_PERIPH,
	STEDMA40_PERIPH_TO_MEM,
	STEDMA40_PERIPH_TO_PERIPH
};


/**
 * struct stedma40_chan_cfg - dst/src channel configuration
 *
 * @endianess: Endianess of the src/dst hardware
 * @data_width: Data width of the src/dst hardware
 * @p_size: Burst size
 * @flow_ctrl: Flow control on/off.
 */
struct stedma40_half_channel_info {
	enum stedma40_endianess endianess;
	enum stedma40_periph_data_width data_width;
	int psize;
	enum stedma40_flow_ctrl flow_ctrl;
};

/**
 * struct stedma40_chan_cfg - Structure to be filled by client drivers.
 *
 * @dir: MEM 2 MEM, PERIPH 2 MEM , MEM 2 PERIPH, PERIPH 2 PERIPH
 * @channel_type: priority, mode, mode options and interrupt configuration.
 * @high_priority: true if high-priority
 * @mode: channel mode: physical, logical, or operation
 * @mode_opt: options for the chosen channel mode
 * @src_dev_type: Src device type
 * @dst_dev_type: Dst device type
 * @src_info: Parameters for dst half channel
 * @dst_info: Parameters for dst half channel
 *
 *
 * This structure has to be filled by the client drivers.
 * It is recommended to do all dma configurations for clients in the machine.
 *
 */
struct stedma40_chan_cfg {
	enum stedma40_xfer_dir			 dir;
	unsigned int				 channel_type;
	bool					 high_priority;
	enum stedma40_mode			 mode;
	enum stedma40_mode_opt			 mode_opt;
	int					 src_dev_type;
	int					 dst_dev_type;
	struct stedma40_half_channel_info	 src_info;
	struct stedma40_half_channel_info	 dst_info;
};

/**
 * struct stedma40_platform_data - Configuration struct for the dma device.
 *
 * @dev_len: length of dev_tx and dev_rx
 * @dev_tx: mapping between destination event line and io address
 * @dev_rx: mapping between source event line and io address
 * @memcpy: list of memcpy event lines
 * @memcpy_len: length of memcpy
 * @memcpy_conf_phy: default configuration of physical channel memcpy
 * @memcpy_conf_log: default configuration of logical channel memcpy
 * @disabled_channels: A vector, ending with -1, that marks physical channels
 * that are for different reasons not available for the driver.
 */
struct stedma40_platform_data {
	u32				 dev_len;
	const dma_addr_t		*dev_tx;
	const dma_addr_t		*dev_rx;
	int				*memcpy;
	u32				 memcpy_len;
	struct stedma40_chan_cfg	*memcpy_conf_phy;
	struct stedma40_chan_cfg	*memcpy_conf_log;
	int				 disabled_channels[STEDMA40_MAX_PHYS];
};

#ifdef CONFIG_STE_DMA40

/**
 * stedma40_filter() - Provides stedma40_chan_cfg to the
 * ste_dma40 dma driver via the dmaengine framework.
 * does some checking of what's provided.
 *
 * Never directly called by client. It used by dmaengine.
 * @chan: dmaengine handle.
 * @data: Must be of type: struct stedma40_chan_cfg and is
 * the configuration of the framework.
 *
 *
 */

bool stedma40_filter(struct dma_chan *chan, void *data);

/**
 * stedma40_memcpy_sg() - extension of the dma framework, memcpy to/from
 * scattergatter lists.
 *
 * @chan: dmaengine handle
 * @sgl_dst: Destination scatter list
 * @sgl_src: Source scatter list
 * @sgl_len: The length of each scatterlist. Both lists must be of equal length
 * and each element must match the corresponding element in the other scatter
 * list.
 * @flags: is actually enum dma_ctrl_flags. See dmaengine.h
 */

struct dma_async_tx_descriptor *stedma40_memcpy_sg(struct dma_chan *chan,
						   struct scatterlist *sgl_dst,
						   struct scatterlist *sgl_src,
						   unsigned int sgl_len,
						   unsigned long flags);

/**
 * stedma40_slave_mem() - Transfers a raw data buffer to or from a slave
 * (=device)
 *
 * @chan: dmaengine handle
 * @addr: source or destination physicall address.
 * @size: bytes to transfer
 * @direction: direction of transfer
 * @flags: is actually enum dma_ctrl_flags. See dmaengine.h
 */

static inline struct
dma_async_tx_descriptor *stedma40_slave_mem(struct dma_chan *chan,
					    dma_addr_t addr,
					    unsigned int size,
					    enum dma_data_direction direction,
					    unsigned long flags)
{
	struct scatterlist sg;
	sg_init_table(&sg, 1);
	sg.dma_address = addr;
	sg.length = size;

	return chan->device->device_prep_slave_sg(chan, &sg, 1,
						  direction, flags);
}

#else
static inline bool stedma40_filter(struct dma_chan *chan, void *data)
{
	return false;
}

static inline struct
dma_async_tx_descriptor *stedma40_slave_mem(struct dma_chan *chan,
					    dma_addr_t addr,
					    unsigned int size,
					    enum dma_data_direction direction,
					    unsigned long flags)
{
	return NULL;
}
#endif

#endif
Commit	Line	Data
8d318a50	1	/*
767a9675	2	* Copyright (C) ST-Ericsson SA 2007-2010
661385f9	3	* Author: Per Forlin <per.forlin@stericsson.com> for ST-Ericsson
767a9675	4	* Author: Jonas Aaberg <jonas.aberg@stericsson.com> for ST-Ericsson
8d318a50	5	* License terms: GNU General Public License (GPL) version 2
8d318a50 LW	6	*/
	7
	8
	9	#ifndef STE_DMA40_H
	10	#define STE_DMA40_H
	11
	12	#include <linux/dmaengine.h>
	13	#include <linux/workqueue.h>
	14	#include <linux/interrupt.h>
	15	#include <linux/dmaengine.h>
	16
	17	/* dev types for memcpy */
	18	#define STEDMA40_DEV_DST_MEMORY (-1)
	19	#define STEDMA40_DEV_SRC_MEMORY (-1)
	20
	21	/*
	22	* Description of bitfields of channel_type variable is available in
	23	* the info structure.
	24	*/
	25
38bdbf02 RV	26	enum stedma40_mode {
	27	STEDMA40_MODE_LOGICAL = 0,
	28	STEDMA40_MODE_PHYSICAL,
	29	STEDMA40_MODE_OPERATION,
	30	};
8d318a50	31
20a5b6d0 RV	32	enum stedma40_mode_opt {
	33	STEDMA40_PCHAN_BASIC_MODE = 0,
	34	STEDMA40_LCHAN_SRC_LOG_DST_LOG = 0,
	35	STEDMA40_PCHAN_MODULO_MODE,
	36	STEDMA40_PCHAN_DOUBLE_DST_MODE,
	37	STEDMA40_LCHAN_SRC_PHY_DST_LOG,
	38	STEDMA40_LCHAN_SRC_LOG_DST_PHY,
	39	};
8d318a50	40
8d318a50 LW	41	/* End of channel_type configuration */
	42
	43	#define STEDMA40_ESIZE_8_BIT 0x0
	44	#define STEDMA40_ESIZE_16_BIT 0x1
	45	#define STEDMA40_ESIZE_32_BIT 0x2
	46	#define STEDMA40_ESIZE_64_BIT 0x3
	47
	48	/* The value 4 indicates that PEN-reg shall be set to 0 */
	49	#define STEDMA40_PSIZE_PHY_1 0x4
	50	#define STEDMA40_PSIZE_PHY_2 0x0
	51	#define STEDMA40_PSIZE_PHY_4 0x1
	52	#define STEDMA40_PSIZE_PHY_8 0x2
	53	#define STEDMA40_PSIZE_PHY_16 0x3
	54
	55	/*
	56	* The number of elements differ in logical and
	57	* physical mode
	58	*/
	59	#define STEDMA40_PSIZE_LOG_1 STEDMA40_PSIZE_PHY_2
	60	#define STEDMA40_PSIZE_LOG_4 STEDMA40_PSIZE_PHY_4
	61	#define STEDMA40_PSIZE_LOG_8 STEDMA40_PSIZE_PHY_8
	62	#define STEDMA40_PSIZE_LOG_16 STEDMA40_PSIZE_PHY_16
	63
767a9675 JA	64	/* Maximum number of possible physical channels */
	65	#define STEDMA40_MAX_PHYS 32
	66
8d318a50 LW	67	enum stedma40_flow_ctrl {
	68	STEDMA40_NO_FLOW_CTRL,
	69	STEDMA40_FLOW_CTRL,
	70	};
	71
	72	enum stedma40_endianess {
	73	STEDMA40_LITTLE_ENDIAN,
	74	STEDMA40_BIG_ENDIAN
	75	};
	76
	77	enum stedma40_periph_data_width {
	78	STEDMA40_BYTE_WIDTH = STEDMA40_ESIZE_8_BIT,
	79	STEDMA40_HALFWORD_WIDTH = STEDMA40_ESIZE_16_BIT,
	80	STEDMA40_WORD_WIDTH = STEDMA40_ESIZE_32_BIT,
	81	STEDMA40_DOUBLEWORD_WIDTH = STEDMA40_ESIZE_64_BIT
	82	};
	83
8d318a50	84	enum stedma40_xfer_dir {
0747c7ba	85	STEDMA40_MEM_TO_MEM = 1,
8d318a50 LW	86	STEDMA40_MEM_TO_PERIPH,
	87	STEDMA40_PERIPH_TO_MEM,
	88	STEDMA40_PERIPH_TO_PERIPH
	89	};
	90
	91
3c0f2401 JA	92	/**
	93	* struct stedma40_chan_cfg - dst/src channel configuration
	94	*
	95	* @endianess: Endianess of the src/dst hardware
	96	* @data_width: Data width of the src/dst hardware
	97	* @p_size: Burst size
	98	* @flow_ctrl: Flow control on/off.
	99	*/
	100	struct stedma40_half_channel_info {
	101	enum stedma40_endianess endianess;
	102	enum stedma40_periph_data_width data_width;
	103	int psize;
	104	enum stedma40_flow_ctrl flow_ctrl;
	105	};
	106
8d318a50 LW	107	/**
	108	* struct stedma40_chan_cfg - Structure to be filled by client drivers.
	109	*
	110	* @dir: MEM 2 MEM, PERIPH 2 MEM , MEM 2 PERIPH, PERIPH 2 PERIPH
	111	* @channel_type: priority, mode, mode options and interrupt configuration.
730c1871	112	* @high_priority: true if high-priority
38bdbf02	113	* @mode: channel mode: physical, logical, or operation
20a5b6d0	114	* @mode_opt: options for the chosen channel mode
8d318a50 LW	115	* @src_dev_type: Src device type
	116	* @dst_dev_type: Dst device type
	117	* @src_info: Parameters for dst half channel
	118	* @dst_info: Parameters for dst half channel
8d318a50 LW	119	*
	120	*
	121	* This structure has to be filled by the client drivers.
	122	* It is recommended to do all dma configurations for clients in the machine.
	123	*
	124	*/
	125	struct stedma40_chan_cfg {
	126	enum stedma40_xfer_dir dir;
	127	unsigned int channel_type;
730c1871	128	bool high_priority;
38bdbf02	129	enum stedma40_mode mode;
20a5b6d0	130	enum stedma40_mode_opt mode_opt;
8d318a50 LW	131	int src_dev_type;
	132	int dst_dev_type;
	133	struct stedma40_half_channel_info src_info;
	134	struct stedma40_half_channel_info dst_info;
8d318a50 LW	135	};
	136
	137	/**
	138	* struct stedma40_platform_data - Configuration struct for the dma device.
	139	*
	140	* @dev_len: length of dev_tx and dev_rx
	141	* @dev_tx: mapping between destination event line and io address
	142	* @dev_rx: mapping between source event line and io address
	143	* @memcpy: list of memcpy event lines
	144	* @memcpy_len: length of memcpy
	145	* @memcpy_conf_phy: default configuration of physical channel memcpy
	146	* @memcpy_conf_log: default configuration of logical channel memcpy
59516725 JA	147	* @disabled_channels: A vector, ending with -1, that marks physical channels
59516725 JA	148	* that are for different reasons not available for the driver.
8d318a50 LW	149	*/
	150	struct stedma40_platform_data {
	151	u32 dev_len;
	152	const dma_addr_t *dev_tx;
	153	const dma_addr_t *dev_rx;
	154	int *memcpy;
	155	u32 memcpy_len;
	156	struct stedma40_chan_cfg *memcpy_conf_phy;
	157	struct stedma40_chan_cfg *memcpy_conf_log;
767a9675	158	int disabled_channels[STEDMA40_MAX_PHYS];
8d318a50 LW	159	};
8d318a50 LW	160
9646b798 LW	161	#ifdef CONFIG_STE_DMA40
9646b798 LW	162
8d318a50 LW	163	/**
	164	* stedma40_filter() - Provides stedma40_chan_cfg to the
	165	* ste_dma40 dma driver via the dmaengine framework.
	166	* does some checking of what's provided.
	167	*
	168	* Never directly called by client. It used by dmaengine.
	169	* @chan: dmaengine handle.
	170	* @data: Must be of type: struct stedma40_chan_cfg and is
	171	* the configuration of the framework.
	172	*
	173	*
	174	*/
	175
	176	bool stedma40_filter(struct dma_chan chan, void data);
	177
	178	/**
	179	* stedma40_memcpy_sg() - extension of the dma framework, memcpy to/from
	180	* scattergatter lists.
	181	*
	182	* @chan: dmaengine handle
	183	* @sgl_dst: Destination scatter list
	184	* @sgl_src: Source scatter list
	185	* @sgl_len: The length of each scatterlist. Both lists must be of equal length
	186	* and each element must match the corresponding element in the other scatter
	187	* list.
	188	* @flags: is actually enum dma_ctrl_flags. See dmaengine.h
	189	*/
	190
	191	struct dma_async_tx_descriptor stedma40_memcpy_sg(struct dma_chan chan,
	192	struct scatterlist *sgl_dst,
	193	struct scatterlist *sgl_src,
	194	unsigned int sgl_len,
	195	unsigned long flags);
	196
	197	/**
	198	* stedma40_slave_mem() - Transfers a raw data buffer to or from a slave
	199	* (=device)
	200	*
	201	* @chan: dmaengine handle
	202	* @addr: source or destination physicall address.
	203	* @size: bytes to transfer
	204	* @direction: direction of transfer
	205	* @flags: is actually enum dma_ctrl_flags. See dmaengine.h
	206	*/
	207
	208	static inline struct
	209	dma_async_tx_descriptor stedma40_slave_mem(struct dma_chan chan,
	210	dma_addr_t addr,
	211	unsigned int size,
	212	enum dma_data_direction direction,
	213	unsigned long flags)
	214	{
	215	struct scatterlist sg;
	216	sg_init_table(&sg, 1);
	217	sg.dma_address = addr;
	218	sg.length = size;
	219
	220	return chan->device->device_prep_slave_sg(chan, &sg, 1,
	221	direction, flags);
	222	}
	223
9646b798 LW	224	#else
	225	static inline bool stedma40_filter(struct dma_chan chan, void data)
	226	{
	227	return false;
	228	}
	229
	230	static inline struct
	231	dma_async_tx_descriptor stedma40_slave_mem(struct dma_chan chan,
	232	dma_addr_t addr,
	233	unsigned int size,
	234	enum dma_data_direction direction,
	235	unsigned long flags)
	236	{
	237	return NULL;
	238	}
	239	#endif
	240
8d318a50	241	#endif