Commit | Line | Data |
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2ec1d359 AR |
1 | /* |
2 | * Generic GPIO driver for logic cells found in the Nomadik SoC | |
3 | * | |
4 | * Copyright (C) 2008,2009 STMicroelectronics | |
5 | * Copyright (C) 2009 Alessandro Rubini <rubini@unipv.it> | |
6 | * Rewritten based on work by Prafulla WADASKAR <prafulla.wadaskar@st.com> | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License version 2 as | |
10 | * published by the Free Software Foundation. | |
11 | */ | |
12 | #include <linux/kernel.h> | |
13 | #include <linux/module.h> | |
14 | #include <linux/init.h> | |
15 | #include <linux/device.h> | |
3e3c62ca | 16 | #include <linux/platform_device.h> |
2ec1d359 | 17 | #include <linux/io.h> |
af7dc228 RV |
18 | #include <linux/clk.h> |
19 | #include <linux/err.h> | |
2ec1d359 AR |
20 | #include <linux/gpio.h> |
21 | #include <linux/spinlock.h> | |
22 | #include <linux/interrupt.h> | |
23 | #include <linux/irq.h> | |
5a0e3ad6 | 24 | #include <linux/slab.h> |
2ec1d359 | 25 | |
378be066 | 26 | #include <plat/pincfg.h> |
2ec1d359 AR |
27 | #include <mach/hardware.h> |
28 | #include <mach/gpio.h> | |
29 | ||
30 | /* | |
31 | * The GPIO module in the Nomadik family of Systems-on-Chip is an | |
32 | * AMBA device, managing 32 pins and alternate functions. The logic block | |
33 | * is currently only used in the Nomadik. | |
34 | * | |
35 | * Symbols in this file are called "nmk_gpio" for "nomadik gpio" | |
36 | */ | |
37 | ||
38 | #define NMK_GPIO_PER_CHIP 32 | |
39 | struct nmk_gpio_chip { | |
40 | struct gpio_chip chip; | |
41 | void __iomem *addr; | |
af7dc228 | 42 | struct clk *clk; |
2ec1d359 | 43 | unsigned int parent_irq; |
c0fcb8db | 44 | spinlock_t lock; |
2ec1d359 AR |
45 | /* Keep track of configured edges */ |
46 | u32 edge_rising; | |
47 | u32 edge_falling; | |
48 | }; | |
49 | ||
6f9a974c RV |
50 | static void __nmk_gpio_set_mode(struct nmk_gpio_chip *nmk_chip, |
51 | unsigned offset, int gpio_mode) | |
52 | { | |
53 | u32 bit = 1 << offset; | |
54 | u32 afunc, bfunc; | |
55 | ||
56 | afunc = readl(nmk_chip->addr + NMK_GPIO_AFSLA) & ~bit; | |
57 | bfunc = readl(nmk_chip->addr + NMK_GPIO_AFSLB) & ~bit; | |
58 | if (gpio_mode & NMK_GPIO_ALT_A) | |
59 | afunc |= bit; | |
60 | if (gpio_mode & NMK_GPIO_ALT_B) | |
61 | bfunc |= bit; | |
62 | writel(afunc, nmk_chip->addr + NMK_GPIO_AFSLA); | |
63 | writel(bfunc, nmk_chip->addr + NMK_GPIO_AFSLB); | |
64 | } | |
65 | ||
81a3c298 RV |
66 | static void __nmk_gpio_set_slpm(struct nmk_gpio_chip *nmk_chip, |
67 | unsigned offset, enum nmk_gpio_slpm mode) | |
68 | { | |
69 | u32 bit = 1 << offset; | |
70 | u32 slpm; | |
71 | ||
72 | slpm = readl(nmk_chip->addr + NMK_GPIO_SLPC); | |
73 | if (mode == NMK_GPIO_SLPM_NOCHANGE) | |
74 | slpm |= bit; | |
75 | else | |
76 | slpm &= ~bit; | |
77 | writel(slpm, nmk_chip->addr + NMK_GPIO_SLPC); | |
78 | } | |
79 | ||
5b327edf RV |
80 | static void __nmk_gpio_set_pull(struct nmk_gpio_chip *nmk_chip, |
81 | unsigned offset, enum nmk_gpio_pull pull) | |
82 | { | |
83 | u32 bit = 1 << offset; | |
84 | u32 pdis; | |
85 | ||
86 | pdis = readl(nmk_chip->addr + NMK_GPIO_PDIS); | |
87 | if (pull == NMK_GPIO_PULL_NONE) | |
88 | pdis |= bit; | |
89 | else | |
90 | pdis &= ~bit; | |
91 | writel(pdis, nmk_chip->addr + NMK_GPIO_PDIS); | |
92 | ||
93 | if (pull == NMK_GPIO_PULL_UP) | |
94 | writel(bit, nmk_chip->addr + NMK_GPIO_DATS); | |
95 | else if (pull == NMK_GPIO_PULL_DOWN) | |
96 | writel(bit, nmk_chip->addr + NMK_GPIO_DATC); | |
97 | } | |
98 | ||
378be066 RV |
99 | static void __nmk_gpio_make_input(struct nmk_gpio_chip *nmk_chip, |
100 | unsigned offset) | |
101 | { | |
102 | writel(1 << offset, nmk_chip->addr + NMK_GPIO_DIRC); | |
103 | } | |
104 | ||
6720db7c RV |
105 | static void __nmk_gpio_set_output(struct nmk_gpio_chip *nmk_chip, |
106 | unsigned offset, int val) | |
107 | { | |
108 | if (val) | |
109 | writel(1 << offset, nmk_chip->addr + NMK_GPIO_DATS); | |
110 | else | |
111 | writel(1 << offset, nmk_chip->addr + NMK_GPIO_DATC); | |
112 | } | |
113 | ||
114 | static void __nmk_gpio_make_output(struct nmk_gpio_chip *nmk_chip, | |
115 | unsigned offset, int val) | |
116 | { | |
117 | writel(1 << offset, nmk_chip->addr + NMK_GPIO_DIRS); | |
118 | __nmk_gpio_set_output(nmk_chip, offset, val); | |
119 | } | |
120 | ||
378be066 | 121 | static void __nmk_config_pin(struct nmk_gpio_chip *nmk_chip, unsigned offset, |
dacdc96c | 122 | pin_cfg_t cfg, bool sleep) |
378be066 RV |
123 | { |
124 | static const char *afnames[] = { | |
125 | [NMK_GPIO_ALT_GPIO] = "GPIO", | |
126 | [NMK_GPIO_ALT_A] = "A", | |
127 | [NMK_GPIO_ALT_B] = "B", | |
128 | [NMK_GPIO_ALT_C] = "C" | |
129 | }; | |
130 | static const char *pullnames[] = { | |
131 | [NMK_GPIO_PULL_NONE] = "none", | |
132 | [NMK_GPIO_PULL_UP] = "up", | |
133 | [NMK_GPIO_PULL_DOWN] = "down", | |
134 | [3] /* illegal */ = "??" | |
135 | }; | |
136 | static const char *slpmnames[] = { | |
7e3f7e59 RV |
137 | [NMK_GPIO_SLPM_INPUT] = "input/wakeup", |
138 | [NMK_GPIO_SLPM_NOCHANGE] = "no-change/no-wakeup", | |
378be066 RV |
139 | }; |
140 | ||
141 | int pin = PIN_NUM(cfg); | |
142 | int pull = PIN_PULL(cfg); | |
143 | int af = PIN_ALT(cfg); | |
144 | int slpm = PIN_SLPM(cfg); | |
6720db7c RV |
145 | int output = PIN_DIR(cfg); |
146 | int val = PIN_VAL(cfg); | |
378be066 | 147 | |
dacdc96c RV |
148 | dev_dbg(nmk_chip->chip.dev, "pin %d [%#lx]: af %s, pull %s, slpm %s (%s%s)\n", |
149 | pin, cfg, afnames[af], pullnames[pull], slpmnames[slpm], | |
6720db7c RV |
150 | output ? "output " : "input", |
151 | output ? (val ? "high" : "low") : ""); | |
152 | ||
dacdc96c RV |
153 | if (sleep) { |
154 | int slpm_pull = PIN_SLPM_PULL(cfg); | |
155 | int slpm_output = PIN_SLPM_DIR(cfg); | |
156 | int slpm_val = PIN_SLPM_VAL(cfg); | |
157 | ||
158 | /* | |
159 | * The SLPM_* values are normal values + 1 to allow zero to | |
160 | * mean "same as normal". | |
161 | */ | |
162 | if (slpm_pull) | |
163 | pull = slpm_pull - 1; | |
164 | if (slpm_output) | |
165 | output = slpm_output - 1; | |
166 | if (slpm_val) | |
167 | val = slpm_val - 1; | |
168 | ||
169 | dev_dbg(nmk_chip->chip.dev, "pin %d: sleep pull %s, dir %s, val %s\n", | |
170 | pin, | |
171 | slpm_pull ? pullnames[pull] : "same", | |
172 | slpm_output ? (output ? "output" : "input") : "same", | |
173 | slpm_val ? (val ? "high" : "low") : "same"); | |
174 | } | |
175 | ||
6720db7c RV |
176 | if (output) |
177 | __nmk_gpio_make_output(nmk_chip, offset, val); | |
178 | else { | |
179 | __nmk_gpio_make_input(nmk_chip, offset); | |
180 | __nmk_gpio_set_pull(nmk_chip, offset, pull); | |
181 | } | |
378be066 | 182 | |
378be066 RV |
183 | __nmk_gpio_set_slpm(nmk_chip, offset, slpm); |
184 | __nmk_gpio_set_mode(nmk_chip, offset, af); | |
185 | } | |
186 | ||
187 | /** | |
188 | * nmk_config_pin - configure a pin's mux attributes | |
189 | * @cfg: pin confguration | |
190 | * | |
191 | * Configures a pin's mode (alternate function or GPIO), its pull up status, | |
192 | * and its sleep mode based on the specified configuration. The @cfg is | |
193 | * usually one of the SoC specific macros defined in mach/<soc>-pins.h. These | |
194 | * are constructed using, and can be further enhanced with, the macros in | |
195 | * plat/pincfg.h. | |
196 | * | |
197 | * If a pin's mode is set to GPIO, it is configured as an input to avoid | |
198 | * side-effects. The gpio can be manipulated later using standard GPIO API | |
199 | * calls. | |
200 | */ | |
dacdc96c | 201 | int nmk_config_pin(pin_cfg_t cfg, bool sleep) |
378be066 RV |
202 | { |
203 | struct nmk_gpio_chip *nmk_chip; | |
204 | int gpio = PIN_NUM(cfg); | |
205 | unsigned long flags; | |
206 | ||
207 | nmk_chip = get_irq_chip_data(NOMADIK_GPIO_TO_IRQ(gpio)); | |
208 | if (!nmk_chip) | |
209 | return -EINVAL; | |
210 | ||
211 | spin_lock_irqsave(&nmk_chip->lock, flags); | |
dacdc96c | 212 | __nmk_config_pin(nmk_chip, gpio - nmk_chip->chip.base, cfg, sleep); |
378be066 RV |
213 | spin_unlock_irqrestore(&nmk_chip->lock, flags); |
214 | ||
215 | return 0; | |
216 | } | |
217 | EXPORT_SYMBOL(nmk_config_pin); | |
218 | ||
219 | /** | |
220 | * nmk_config_pins - configure several pins at once | |
221 | * @cfgs: array of pin configurations | |
222 | * @num: number of elments in the array | |
223 | * | |
224 | * Configures several pins using nmk_config_pin(). Refer to that function for | |
225 | * further information. | |
226 | */ | |
227 | int nmk_config_pins(pin_cfg_t *cfgs, int num) | |
228 | { | |
229 | int ret = 0; | |
230 | int i; | |
231 | ||
232 | for (i = 0; i < num; i++) { | |
dacdc96c | 233 | ret = nmk_config_pin(cfgs[i], false); |
378be066 RV |
234 | if (ret) |
235 | break; | |
236 | } | |
237 | ||
238 | return ret; | |
239 | } | |
240 | EXPORT_SYMBOL(nmk_config_pins); | |
241 | ||
dacdc96c RV |
242 | int nmk_config_pins_sleep(pin_cfg_t *cfgs, int num) |
243 | { | |
244 | int ret = 0; | |
245 | int i; | |
246 | ||
247 | for (i = 0; i < num; i++) { | |
248 | ret = nmk_config_pin(cfgs[i], true); | |
249 | if (ret) | |
250 | break; | |
251 | } | |
252 | ||
253 | return ret; | |
254 | } | |
255 | EXPORT_SYMBOL(nmk_config_pins_sleep); | |
256 | ||
81a3c298 RV |
257 | /** |
258 | * nmk_gpio_set_slpm() - configure the sleep mode of a pin | |
259 | * @gpio: pin number | |
260 | * @mode: NMK_GPIO_SLPM_INPUT or NMK_GPIO_SLPM_NOCHANGE, | |
261 | * | |
262 | * Sets the sleep mode of a pin. If @mode is NMK_GPIO_SLPM_INPUT, the pin is | |
263 | * changed to an input (with pullup/down enabled) in sleep and deep sleep. If | |
264 | * @mode is NMK_GPIO_SLPM_NOCHANGE, the pin remains in the state it was | |
265 | * configured even when in sleep and deep sleep. | |
7e3f7e59 RV |
266 | * |
267 | * On DB8500v2 onwards, this setting loses the previous meaning and instead | |
268 | * indicates if wakeup detection is enabled on the pin. Note that | |
269 | * enable_irq_wake() will automatically enable wakeup detection. | |
81a3c298 RV |
270 | */ |
271 | int nmk_gpio_set_slpm(int gpio, enum nmk_gpio_slpm mode) | |
272 | { | |
273 | struct nmk_gpio_chip *nmk_chip; | |
274 | unsigned long flags; | |
275 | ||
276 | nmk_chip = get_irq_chip_data(NOMADIK_GPIO_TO_IRQ(gpio)); | |
277 | if (!nmk_chip) | |
278 | return -EINVAL; | |
279 | ||
280 | spin_lock_irqsave(&nmk_chip->lock, flags); | |
281 | __nmk_gpio_set_slpm(nmk_chip, gpio - nmk_chip->chip.base, mode); | |
282 | spin_unlock_irqrestore(&nmk_chip->lock, flags); | |
283 | ||
284 | return 0; | |
285 | } | |
286 | ||
5b327edf RV |
287 | /** |
288 | * nmk_gpio_set_pull() - enable/disable pull up/down on a gpio | |
289 | * @gpio: pin number | |
290 | * @pull: one of NMK_GPIO_PULL_DOWN, NMK_GPIO_PULL_UP, and NMK_GPIO_PULL_NONE | |
291 | * | |
292 | * Enables/disables pull up/down on a specified pin. This only takes effect if | |
293 | * the pin is configured as an input (either explicitly or by the alternate | |
294 | * function). | |
295 | * | |
296 | * NOTE: If enabling the pull up/down, the caller must ensure that the GPIO is | |
297 | * configured as an input. Otherwise, due to the way the controller registers | |
298 | * work, this function will change the value output on the pin. | |
299 | */ | |
300 | int nmk_gpio_set_pull(int gpio, enum nmk_gpio_pull pull) | |
301 | { | |
302 | struct nmk_gpio_chip *nmk_chip; | |
303 | unsigned long flags; | |
304 | ||
305 | nmk_chip = get_irq_chip_data(NOMADIK_GPIO_TO_IRQ(gpio)); | |
306 | if (!nmk_chip) | |
307 | return -EINVAL; | |
308 | ||
309 | spin_lock_irqsave(&nmk_chip->lock, flags); | |
310 | __nmk_gpio_set_pull(nmk_chip, gpio - nmk_chip->chip.base, pull); | |
311 | spin_unlock_irqrestore(&nmk_chip->lock, flags); | |
312 | ||
313 | return 0; | |
314 | } | |
315 | ||
2ec1d359 AR |
316 | /* Mode functions */ |
317 | int nmk_gpio_set_mode(int gpio, int gpio_mode) | |
318 | { | |
319 | struct nmk_gpio_chip *nmk_chip; | |
320 | unsigned long flags; | |
2ec1d359 AR |
321 | |
322 | nmk_chip = get_irq_chip_data(NOMADIK_GPIO_TO_IRQ(gpio)); | |
323 | if (!nmk_chip) | |
324 | return -EINVAL; | |
325 | ||
2ec1d359 | 326 | spin_lock_irqsave(&nmk_chip->lock, flags); |
6f9a974c | 327 | __nmk_gpio_set_mode(nmk_chip, gpio - nmk_chip->chip.base, gpio_mode); |
2ec1d359 AR |
328 | spin_unlock_irqrestore(&nmk_chip->lock, flags); |
329 | ||
330 | return 0; | |
331 | } | |
332 | EXPORT_SYMBOL(nmk_gpio_set_mode); | |
333 | ||
334 | int nmk_gpio_get_mode(int gpio) | |
335 | { | |
336 | struct nmk_gpio_chip *nmk_chip; | |
337 | u32 afunc, bfunc, bit; | |
338 | ||
339 | nmk_chip = get_irq_chip_data(NOMADIK_GPIO_TO_IRQ(gpio)); | |
340 | if (!nmk_chip) | |
341 | return -EINVAL; | |
342 | ||
343 | bit = 1 << (gpio - nmk_chip->chip.base); | |
344 | ||
345 | afunc = readl(nmk_chip->addr + NMK_GPIO_AFSLA) & bit; | |
346 | bfunc = readl(nmk_chip->addr + NMK_GPIO_AFSLB) & bit; | |
347 | ||
348 | return (afunc ? NMK_GPIO_ALT_A : 0) | (bfunc ? NMK_GPIO_ALT_B : 0); | |
349 | } | |
350 | EXPORT_SYMBOL(nmk_gpio_get_mode); | |
351 | ||
352 | ||
353 | /* IRQ functions */ | |
354 | static inline int nmk_gpio_get_bitmask(int gpio) | |
355 | { | |
356 | return 1 << (gpio % 32); | |
357 | } | |
358 | ||
359 | static void nmk_gpio_irq_ack(unsigned int irq) | |
360 | { | |
361 | int gpio; | |
362 | struct nmk_gpio_chip *nmk_chip; | |
363 | ||
364 | gpio = NOMADIK_IRQ_TO_GPIO(irq); | |
365 | nmk_chip = get_irq_chip_data(irq); | |
366 | if (!nmk_chip) | |
367 | return; | |
368 | writel(nmk_gpio_get_bitmask(gpio), nmk_chip->addr + NMK_GPIO_IC); | |
369 | } | |
370 | ||
4d4e20f7 RV |
371 | enum nmk_gpio_irq_type { |
372 | NORMAL, | |
373 | WAKE, | |
374 | }; | |
375 | ||
040e5ecd | 376 | static void __nmk_gpio_irq_modify(struct nmk_gpio_chip *nmk_chip, |
4d4e20f7 RV |
377 | int gpio, enum nmk_gpio_irq_type which, |
378 | bool enable) | |
2ec1d359 | 379 | { |
4d4e20f7 RV |
380 | u32 rimsc = which == WAKE ? NMK_GPIO_RWIMSC : NMK_GPIO_RIMSC; |
381 | u32 fimsc = which == WAKE ? NMK_GPIO_FWIMSC : NMK_GPIO_FIMSC; | |
040e5ecd RV |
382 | u32 bitmask = nmk_gpio_get_bitmask(gpio); |
383 | u32 reg; | |
2ec1d359 | 384 | |
040e5ecd | 385 | /* we must individually set/clear the two edges */ |
2ec1d359 | 386 | if (nmk_chip->edge_rising & bitmask) { |
4d4e20f7 | 387 | reg = readl(nmk_chip->addr + rimsc); |
040e5ecd RV |
388 | if (enable) |
389 | reg |= bitmask; | |
390 | else | |
391 | reg &= ~bitmask; | |
4d4e20f7 | 392 | writel(reg, nmk_chip->addr + rimsc); |
2ec1d359 AR |
393 | } |
394 | if (nmk_chip->edge_falling & bitmask) { | |
4d4e20f7 | 395 | reg = readl(nmk_chip->addr + fimsc); |
040e5ecd RV |
396 | if (enable) |
397 | reg |= bitmask; | |
398 | else | |
399 | reg &= ~bitmask; | |
4d4e20f7 | 400 | writel(reg, nmk_chip->addr + fimsc); |
2ec1d359 | 401 | } |
040e5ecd | 402 | } |
2ec1d359 | 403 | |
4d4e20f7 RV |
404 | static int nmk_gpio_irq_modify(unsigned int irq, enum nmk_gpio_irq_type which, |
405 | bool enable) | |
2ec1d359 AR |
406 | { |
407 | int gpio; | |
408 | struct nmk_gpio_chip *nmk_chip; | |
409 | unsigned long flags; | |
040e5ecd | 410 | u32 bitmask; |
2ec1d359 AR |
411 | |
412 | gpio = NOMADIK_IRQ_TO_GPIO(irq); | |
413 | nmk_chip = get_irq_chip_data(irq); | |
414 | bitmask = nmk_gpio_get_bitmask(gpio); | |
415 | if (!nmk_chip) | |
4d4e20f7 | 416 | return -EINVAL; |
2ec1d359 | 417 | |
2ec1d359 | 418 | spin_lock_irqsave(&nmk_chip->lock, flags); |
4d4e20f7 | 419 | __nmk_gpio_irq_modify(nmk_chip, gpio, which, enable); |
2ec1d359 | 420 | spin_unlock_irqrestore(&nmk_chip->lock, flags); |
4d4e20f7 RV |
421 | |
422 | return 0; | |
2ec1d359 AR |
423 | } |
424 | ||
040e5ecd RV |
425 | static void nmk_gpio_irq_mask(unsigned int irq) |
426 | { | |
4d4e20f7 RV |
427 | nmk_gpio_irq_modify(irq, NORMAL, false); |
428 | } | |
040e5ecd RV |
429 | |
430 | static void nmk_gpio_irq_unmask(unsigned int irq) | |
431 | { | |
4d4e20f7 RV |
432 | nmk_gpio_irq_modify(irq, NORMAL, true); |
433 | } | |
434 | ||
435 | static int nmk_gpio_irq_set_wake(unsigned int irq, unsigned int on) | |
436 | { | |
7e3f7e59 RV |
437 | struct nmk_gpio_chip *nmk_chip; |
438 | unsigned long flags; | |
439 | int gpio; | |
440 | ||
441 | gpio = NOMADIK_IRQ_TO_GPIO(irq); | |
442 | nmk_chip = get_irq_chip_data(irq); | |
443 | if (!nmk_chip) | |
444 | return -EINVAL; | |
445 | ||
446 | spin_lock_irqsave(&nmk_chip->lock, flags); | |
447 | #ifdef CONFIG_ARCH_U8500 | |
448 | if (cpu_is_u8500v2()) { | |
449 | __nmk_gpio_set_slpm(nmk_chip, gpio, | |
450 | on ? NMK_GPIO_SLPM_WAKEUP_ENABLE | |
451 | : NMK_GPIO_SLPM_WAKEUP_DISABLE); | |
452 | } | |
453 | #endif | |
454 | __nmk_gpio_irq_modify(nmk_chip, gpio, WAKE, on); | |
455 | spin_unlock_irqrestore(&nmk_chip->lock, flags); | |
456 | ||
457 | return 0; | |
040e5ecd RV |
458 | } |
459 | ||
2ec1d359 AR |
460 | static int nmk_gpio_irq_set_type(unsigned int irq, unsigned int type) |
461 | { | |
4d4e20f7 RV |
462 | struct irq_desc *desc = irq_to_desc(irq); |
463 | bool enabled = !(desc->status & IRQ_DISABLED); | |
464 | bool wake = desc->wake_depth; | |
2ec1d359 AR |
465 | int gpio; |
466 | struct nmk_gpio_chip *nmk_chip; | |
467 | unsigned long flags; | |
468 | u32 bitmask; | |
469 | ||
470 | gpio = NOMADIK_IRQ_TO_GPIO(irq); | |
471 | nmk_chip = get_irq_chip_data(irq); | |
472 | bitmask = nmk_gpio_get_bitmask(gpio); | |
473 | if (!nmk_chip) | |
474 | return -EINVAL; | |
475 | ||
476 | if (type & IRQ_TYPE_LEVEL_HIGH) | |
477 | return -EINVAL; | |
478 | if (type & IRQ_TYPE_LEVEL_LOW) | |
479 | return -EINVAL; | |
480 | ||
481 | spin_lock_irqsave(&nmk_chip->lock, flags); | |
482 | ||
7a852d80 | 483 | if (enabled) |
4d4e20f7 RV |
484 | __nmk_gpio_irq_modify(nmk_chip, gpio, NORMAL, false); |
485 | ||
486 | if (wake) | |
487 | __nmk_gpio_irq_modify(nmk_chip, gpio, WAKE, false); | |
7a852d80 | 488 | |
2ec1d359 AR |
489 | nmk_chip->edge_rising &= ~bitmask; |
490 | if (type & IRQ_TYPE_EDGE_RISING) | |
491 | nmk_chip->edge_rising |= bitmask; | |
2ec1d359 AR |
492 | |
493 | nmk_chip->edge_falling &= ~bitmask; | |
494 | if (type & IRQ_TYPE_EDGE_FALLING) | |
495 | nmk_chip->edge_falling |= bitmask; | |
2ec1d359 | 496 | |
7a852d80 | 497 | if (enabled) |
4d4e20f7 RV |
498 | __nmk_gpio_irq_modify(nmk_chip, gpio, NORMAL, true); |
499 | ||
500 | if (wake) | |
501 | __nmk_gpio_irq_modify(nmk_chip, gpio, WAKE, true); | |
2ec1d359 | 502 | |
7a852d80 | 503 | spin_unlock_irqrestore(&nmk_chip->lock, flags); |
2ec1d359 AR |
504 | |
505 | return 0; | |
506 | } | |
507 | ||
508 | static struct irq_chip nmk_gpio_irq_chip = { | |
509 | .name = "Nomadik-GPIO", | |
510 | .ack = nmk_gpio_irq_ack, | |
511 | .mask = nmk_gpio_irq_mask, | |
512 | .unmask = nmk_gpio_irq_unmask, | |
513 | .set_type = nmk_gpio_irq_set_type, | |
4d4e20f7 | 514 | .set_wake = nmk_gpio_irq_set_wake, |
2ec1d359 AR |
515 | }; |
516 | ||
517 | static void nmk_gpio_irq_handler(unsigned int irq, struct irq_desc *desc) | |
518 | { | |
519 | struct nmk_gpio_chip *nmk_chip; | |
aaedaa2b | 520 | struct irq_chip *host_chip = get_irq_chip(irq); |
2ec1d359 AR |
521 | unsigned int gpio_irq; |
522 | u32 pending; | |
523 | unsigned int first_irq; | |
524 | ||
aaedaa2b RV |
525 | if (host_chip->mask_ack) |
526 | host_chip->mask_ack(irq); | |
527 | else { | |
528 | host_chip->mask(irq); | |
529 | if (host_chip->ack) | |
530 | host_chip->ack(irq); | |
531 | } | |
532 | ||
2ec1d359 AR |
533 | nmk_chip = get_irq_data(irq); |
534 | first_irq = NOMADIK_GPIO_TO_IRQ(nmk_chip->chip.base); | |
535 | while ( (pending = readl(nmk_chip->addr + NMK_GPIO_IS)) ) { | |
536 | gpio_irq = first_irq + __ffs(pending); | |
537 | generic_handle_irq(gpio_irq); | |
538 | } | |
aaedaa2b RV |
539 | |
540 | host_chip->unmask(irq); | |
2ec1d359 AR |
541 | } |
542 | ||
543 | static int nmk_gpio_init_irq(struct nmk_gpio_chip *nmk_chip) | |
544 | { | |
545 | unsigned int first_irq; | |
546 | int i; | |
547 | ||
548 | first_irq = NOMADIK_GPIO_TO_IRQ(nmk_chip->chip.base); | |
549 | for (i = first_irq; i < first_irq + NMK_GPIO_PER_CHIP; i++) { | |
550 | set_irq_chip(i, &nmk_gpio_irq_chip); | |
551 | set_irq_handler(i, handle_edge_irq); | |
552 | set_irq_flags(i, IRQF_VALID); | |
553 | set_irq_chip_data(i, nmk_chip); | |
2210d645 | 554 | set_irq_type(i, IRQ_TYPE_EDGE_FALLING); |
2ec1d359 AR |
555 | } |
556 | set_irq_chained_handler(nmk_chip->parent_irq, nmk_gpio_irq_handler); | |
557 | set_irq_data(nmk_chip->parent_irq, nmk_chip); | |
558 | return 0; | |
559 | } | |
560 | ||
561 | /* I/O Functions */ | |
562 | static int nmk_gpio_make_input(struct gpio_chip *chip, unsigned offset) | |
563 | { | |
564 | struct nmk_gpio_chip *nmk_chip = | |
565 | container_of(chip, struct nmk_gpio_chip, chip); | |
566 | ||
567 | writel(1 << offset, nmk_chip->addr + NMK_GPIO_DIRC); | |
568 | return 0; | |
569 | } | |
570 | ||
2ec1d359 AR |
571 | static int nmk_gpio_get_input(struct gpio_chip *chip, unsigned offset) |
572 | { | |
573 | struct nmk_gpio_chip *nmk_chip = | |
574 | container_of(chip, struct nmk_gpio_chip, chip); | |
575 | u32 bit = 1 << offset; | |
576 | ||
577 | return (readl(nmk_chip->addr + NMK_GPIO_DAT) & bit) != 0; | |
578 | } | |
579 | ||
580 | static void nmk_gpio_set_output(struct gpio_chip *chip, unsigned offset, | |
581 | int val) | |
582 | { | |
583 | struct nmk_gpio_chip *nmk_chip = | |
584 | container_of(chip, struct nmk_gpio_chip, chip); | |
2ec1d359 | 585 | |
6720db7c | 586 | __nmk_gpio_set_output(nmk_chip, offset, val); |
2ec1d359 AR |
587 | } |
588 | ||
6647c6c0 RV |
589 | static int nmk_gpio_make_output(struct gpio_chip *chip, unsigned offset, |
590 | int val) | |
591 | { | |
592 | struct nmk_gpio_chip *nmk_chip = | |
593 | container_of(chip, struct nmk_gpio_chip, chip); | |
594 | ||
6720db7c | 595 | __nmk_gpio_make_output(nmk_chip, offset, val); |
6647c6c0 RV |
596 | |
597 | return 0; | |
598 | } | |
599 | ||
0d2aec9c RV |
600 | static int nmk_gpio_to_irq(struct gpio_chip *chip, unsigned offset) |
601 | { | |
602 | struct nmk_gpio_chip *nmk_chip = | |
603 | container_of(chip, struct nmk_gpio_chip, chip); | |
604 | ||
605 | return NOMADIK_GPIO_TO_IRQ(nmk_chip->chip.base) + offset; | |
606 | } | |
607 | ||
2ec1d359 AR |
608 | /* This structure is replicated for each GPIO block allocated at probe time */ |
609 | static struct gpio_chip nmk_gpio_template = { | |
610 | .direction_input = nmk_gpio_make_input, | |
611 | .get = nmk_gpio_get_input, | |
612 | .direction_output = nmk_gpio_make_output, | |
613 | .set = nmk_gpio_set_output, | |
0d2aec9c | 614 | .to_irq = nmk_gpio_to_irq, |
2ec1d359 AR |
615 | .ngpio = NMK_GPIO_PER_CHIP, |
616 | .can_sleep = 0, | |
617 | }; | |
618 | ||
fd0d67d6 | 619 | static int __devinit nmk_gpio_probe(struct platform_device *dev) |
2ec1d359 | 620 | { |
3e3c62ca | 621 | struct nmk_gpio_platform_data *pdata = dev->dev.platform_data; |
2ec1d359 AR |
622 | struct nmk_gpio_chip *nmk_chip; |
623 | struct gpio_chip *chip; | |
3e3c62ca | 624 | struct resource *res; |
af7dc228 | 625 | struct clk *clk; |
3e3c62ca | 626 | int irq; |
2ec1d359 AR |
627 | int ret; |
628 | ||
3e3c62ca RV |
629 | if (!pdata) |
630 | return -ENODEV; | |
631 | ||
632 | res = platform_get_resource(dev, IORESOURCE_MEM, 0); | |
633 | if (!res) { | |
634 | ret = -ENOENT; | |
635 | goto out; | |
636 | } | |
637 | ||
638 | irq = platform_get_irq(dev, 0); | |
639 | if (irq < 0) { | |
640 | ret = irq; | |
641 | goto out; | |
642 | } | |
643 | ||
644 | if (request_mem_region(res->start, resource_size(res), | |
645 | dev_name(&dev->dev)) == NULL) { | |
646 | ret = -EBUSY; | |
647 | goto out; | |
648 | } | |
2ec1d359 | 649 | |
af7dc228 RV |
650 | clk = clk_get(&dev->dev, NULL); |
651 | if (IS_ERR(clk)) { | |
652 | ret = PTR_ERR(clk); | |
653 | goto out_release; | |
654 | } | |
655 | ||
656 | clk_enable(clk); | |
657 | ||
2ec1d359 AR |
658 | nmk_chip = kzalloc(sizeof(*nmk_chip), GFP_KERNEL); |
659 | if (!nmk_chip) { | |
660 | ret = -ENOMEM; | |
af7dc228 | 661 | goto out_clk; |
2ec1d359 AR |
662 | } |
663 | /* | |
664 | * The virt address in nmk_chip->addr is in the nomadik register space, | |
665 | * so we can simply convert the resource address, without remapping | |
666 | */ | |
af7dc228 | 667 | nmk_chip->clk = clk; |
3e3c62ca | 668 | nmk_chip->addr = io_p2v(res->start); |
2ec1d359 | 669 | nmk_chip->chip = nmk_gpio_template; |
3e3c62ca | 670 | nmk_chip->parent_irq = irq; |
c0fcb8db | 671 | spin_lock_init(&nmk_chip->lock); |
2ec1d359 AR |
672 | |
673 | chip = &nmk_chip->chip; | |
674 | chip->base = pdata->first_gpio; | |
8d568ae5 | 675 | chip->label = pdata->name ?: dev_name(&dev->dev); |
2ec1d359 AR |
676 | chip->dev = &dev->dev; |
677 | chip->owner = THIS_MODULE; | |
678 | ||
679 | ret = gpiochip_add(&nmk_chip->chip); | |
680 | if (ret) | |
681 | goto out_free; | |
682 | ||
3e3c62ca | 683 | platform_set_drvdata(dev, nmk_chip); |
2ec1d359 AR |
684 | |
685 | nmk_gpio_init_irq(nmk_chip); | |
686 | ||
687 | dev_info(&dev->dev, "Bits %i-%i at address %p\n", | |
688 | nmk_chip->chip.base, nmk_chip->chip.base+31, nmk_chip->addr); | |
689 | return 0; | |
690 | ||
3e3c62ca | 691 | out_free: |
2ec1d359 | 692 | kfree(nmk_chip); |
af7dc228 RV |
693 | out_clk: |
694 | clk_disable(clk); | |
695 | clk_put(clk); | |
3e3c62ca RV |
696 | out_release: |
697 | release_mem_region(res->start, resource_size(res)); | |
698 | out: | |
2ec1d359 AR |
699 | dev_err(&dev->dev, "Failure %i for GPIO %i-%i\n", ret, |
700 | pdata->first_gpio, pdata->first_gpio+31); | |
701 | return ret; | |
702 | } | |
703 | ||
3e3c62ca RV |
704 | static struct platform_driver nmk_gpio_driver = { |
705 | .driver = { | |
2ec1d359 AR |
706 | .owner = THIS_MODULE, |
707 | .name = "gpio", | |
708 | }, | |
709 | .probe = nmk_gpio_probe, | |
2ec1d359 AR |
710 | .suspend = NULL, /* to be done */ |
711 | .resume = NULL, | |
2ec1d359 AR |
712 | }; |
713 | ||
714 | static int __init nmk_gpio_init(void) | |
715 | { | |
3e3c62ca | 716 | return platform_driver_register(&nmk_gpio_driver); |
2ec1d359 AR |
717 | } |
718 | ||
33f45ea9 | 719 | core_initcall(nmk_gpio_init); |
2ec1d359 AR |
720 | |
721 | MODULE_AUTHOR("Prafulla WADASKAR and Alessandro Rubini"); | |
722 | MODULE_DESCRIPTION("Nomadik GPIO Driver"); | |
723 | MODULE_LICENSE("GPL"); | |
724 | ||
725 |