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2ec1d359 AR |
1 | /* |
2 | * Generic GPIO driver for logic cells found in the Nomadik SoC | |
3 | * | |
4 | * Copyright (C) 2008,2009 STMicroelectronics | |
5 | * Copyright (C) 2009 Alessandro Rubini <rubini@unipv.it> | |
6 | * Rewritten based on work by Prafulla WADASKAR <prafulla.wadaskar@st.com> | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License version 2 as | |
10 | * published by the Free Software Foundation. | |
11 | */ | |
12 | #include <linux/kernel.h> | |
13 | #include <linux/module.h> | |
14 | #include <linux/init.h> | |
15 | #include <linux/device.h> | |
3e3c62ca | 16 | #include <linux/platform_device.h> |
2ec1d359 | 17 | #include <linux/io.h> |
af7dc228 RV |
18 | #include <linux/clk.h> |
19 | #include <linux/err.h> | |
2ec1d359 AR |
20 | #include <linux/gpio.h> |
21 | #include <linux/spinlock.h> | |
22 | #include <linux/interrupt.h> | |
23 | #include <linux/irq.h> | |
5a0e3ad6 | 24 | #include <linux/slab.h> |
2ec1d359 | 25 | |
378be066 | 26 | #include <plat/pincfg.h> |
2ec1d359 AR |
27 | #include <mach/hardware.h> |
28 | #include <mach/gpio.h> | |
29 | ||
30 | /* | |
31 | * The GPIO module in the Nomadik family of Systems-on-Chip is an | |
32 | * AMBA device, managing 32 pins and alternate functions. The logic block | |
9c66ee6f | 33 | * is currently used in the Nomadik and ux500. |
2ec1d359 AR |
34 | * |
35 | * Symbols in this file are called "nmk_gpio" for "nomadik gpio" | |
36 | */ | |
37 | ||
9c66ee6f JA |
38 | static const u32 backup_regs[] = { |
39 | NMK_GPIO_PDIS, | |
40 | NMK_GPIO_DIR, | |
41 | NMK_GPIO_AFSLA, | |
42 | NMK_GPIO_AFSLB, | |
43 | NMK_GPIO_SLPC, | |
44 | NMK_GPIO_RIMSC, | |
45 | NMK_GPIO_FIMSC, | |
46 | NMK_GPIO_RWIMSC, | |
47 | NMK_GPIO_FWIMSC, | |
48 | }; | |
49 | ||
2ec1d359 AR |
50 | struct nmk_gpio_chip { |
51 | struct gpio_chip chip; | |
52 | void __iomem *addr; | |
af7dc228 | 53 | struct clk *clk; |
33b744b3 | 54 | unsigned int bank; |
2ec1d359 | 55 | unsigned int parent_irq; |
2c8bb0eb | 56 | int secondary_parent_irq; |
33b744b3 | 57 | u32 (*get_secondary_status)(unsigned int bank); |
c0fcb8db | 58 | spinlock_t lock; |
2ec1d359 AR |
59 | /* Keep track of configured edges */ |
60 | u32 edge_rising; | |
61 | u32 edge_falling; | |
9c66ee6f JA |
62 | u32 backup[ARRAY_SIZE(backup_regs)]; |
63 | /* Bitmap, 1 = pull up, 0 = pull down */ | |
64 | u32 pull; | |
2ec1d359 AR |
65 | }; |
66 | ||
6f9a974c RV |
67 | static void __nmk_gpio_set_mode(struct nmk_gpio_chip *nmk_chip, |
68 | unsigned offset, int gpio_mode) | |
69 | { | |
70 | u32 bit = 1 << offset; | |
71 | u32 afunc, bfunc; | |
72 | ||
73 | afunc = readl(nmk_chip->addr + NMK_GPIO_AFSLA) & ~bit; | |
74 | bfunc = readl(nmk_chip->addr + NMK_GPIO_AFSLB) & ~bit; | |
75 | if (gpio_mode & NMK_GPIO_ALT_A) | |
76 | afunc |= bit; | |
77 | if (gpio_mode & NMK_GPIO_ALT_B) | |
78 | bfunc |= bit; | |
79 | writel(afunc, nmk_chip->addr + NMK_GPIO_AFSLA); | |
80 | writel(bfunc, nmk_chip->addr + NMK_GPIO_AFSLB); | |
81 | } | |
82 | ||
81a3c298 RV |
83 | static void __nmk_gpio_set_slpm(struct nmk_gpio_chip *nmk_chip, |
84 | unsigned offset, enum nmk_gpio_slpm mode) | |
85 | { | |
86 | u32 bit = 1 << offset; | |
87 | u32 slpm; | |
88 | ||
89 | slpm = readl(nmk_chip->addr + NMK_GPIO_SLPC); | |
90 | if (mode == NMK_GPIO_SLPM_NOCHANGE) | |
91 | slpm |= bit; | |
92 | else | |
93 | slpm &= ~bit; | |
94 | writel(slpm, nmk_chip->addr + NMK_GPIO_SLPC); | |
95 | } | |
96 | ||
5b327edf RV |
97 | static void __nmk_gpio_set_pull(struct nmk_gpio_chip *nmk_chip, |
98 | unsigned offset, enum nmk_gpio_pull pull) | |
99 | { | |
100 | u32 bit = 1 << offset; | |
101 | u32 pdis; | |
102 | ||
103 | pdis = readl(nmk_chip->addr + NMK_GPIO_PDIS); | |
104 | if (pull == NMK_GPIO_PULL_NONE) | |
105 | pdis |= bit; | |
106 | else | |
107 | pdis &= ~bit; | |
108 | writel(pdis, nmk_chip->addr + NMK_GPIO_PDIS); | |
109 | ||
9c66ee6f JA |
110 | if (pull == NMK_GPIO_PULL_UP) { |
111 | nmk_chip->pull |= bit; | |
5b327edf | 112 | writel(bit, nmk_chip->addr + NMK_GPIO_DATS); |
9c66ee6f JA |
113 | } else if (pull == NMK_GPIO_PULL_DOWN) { |
114 | nmk_chip->pull &= ~bit; | |
5b327edf | 115 | writel(bit, nmk_chip->addr + NMK_GPIO_DATC); |
9c66ee6f | 116 | } |
5b327edf RV |
117 | } |
118 | ||
378be066 RV |
119 | static void __nmk_gpio_make_input(struct nmk_gpio_chip *nmk_chip, |
120 | unsigned offset) | |
121 | { | |
122 | writel(1 << offset, nmk_chip->addr + NMK_GPIO_DIRC); | |
123 | } | |
124 | ||
6720db7c RV |
125 | static void __nmk_gpio_set_output(struct nmk_gpio_chip *nmk_chip, |
126 | unsigned offset, int val) | |
127 | { | |
128 | if (val) | |
129 | writel(1 << offset, nmk_chip->addr + NMK_GPIO_DATS); | |
130 | else | |
131 | writel(1 << offset, nmk_chip->addr + NMK_GPIO_DATC); | |
132 | } | |
133 | ||
134 | static void __nmk_gpio_make_output(struct nmk_gpio_chip *nmk_chip, | |
135 | unsigned offset, int val) | |
136 | { | |
137 | writel(1 << offset, nmk_chip->addr + NMK_GPIO_DIRS); | |
138 | __nmk_gpio_set_output(nmk_chip, offset, val); | |
139 | } | |
140 | ||
378be066 | 141 | static void __nmk_config_pin(struct nmk_gpio_chip *nmk_chip, unsigned offset, |
dacdc96c | 142 | pin_cfg_t cfg, bool sleep) |
378be066 RV |
143 | { |
144 | static const char *afnames[] = { | |
145 | [NMK_GPIO_ALT_GPIO] = "GPIO", | |
146 | [NMK_GPIO_ALT_A] = "A", | |
147 | [NMK_GPIO_ALT_B] = "B", | |
148 | [NMK_GPIO_ALT_C] = "C" | |
149 | }; | |
150 | static const char *pullnames[] = { | |
151 | [NMK_GPIO_PULL_NONE] = "none", | |
152 | [NMK_GPIO_PULL_UP] = "up", | |
153 | [NMK_GPIO_PULL_DOWN] = "down", | |
154 | [3] /* illegal */ = "??" | |
155 | }; | |
156 | static const char *slpmnames[] = { | |
7e3f7e59 RV |
157 | [NMK_GPIO_SLPM_INPUT] = "input/wakeup", |
158 | [NMK_GPIO_SLPM_NOCHANGE] = "no-change/no-wakeup", | |
378be066 RV |
159 | }; |
160 | ||
161 | int pin = PIN_NUM(cfg); | |
162 | int pull = PIN_PULL(cfg); | |
163 | int af = PIN_ALT(cfg); | |
164 | int slpm = PIN_SLPM(cfg); | |
6720db7c RV |
165 | int output = PIN_DIR(cfg); |
166 | int val = PIN_VAL(cfg); | |
378be066 | 167 | |
dacdc96c RV |
168 | dev_dbg(nmk_chip->chip.dev, "pin %d [%#lx]: af %s, pull %s, slpm %s (%s%s)\n", |
169 | pin, cfg, afnames[af], pullnames[pull], slpmnames[slpm], | |
6720db7c RV |
170 | output ? "output " : "input", |
171 | output ? (val ? "high" : "low") : ""); | |
172 | ||
dacdc96c RV |
173 | if (sleep) { |
174 | int slpm_pull = PIN_SLPM_PULL(cfg); | |
175 | int slpm_output = PIN_SLPM_DIR(cfg); | |
176 | int slpm_val = PIN_SLPM_VAL(cfg); | |
177 | ||
3546d15c RV |
178 | af = NMK_GPIO_ALT_GPIO; |
179 | ||
dacdc96c RV |
180 | /* |
181 | * The SLPM_* values are normal values + 1 to allow zero to | |
182 | * mean "same as normal". | |
183 | */ | |
184 | if (slpm_pull) | |
185 | pull = slpm_pull - 1; | |
186 | if (slpm_output) | |
187 | output = slpm_output - 1; | |
188 | if (slpm_val) | |
189 | val = slpm_val - 1; | |
190 | ||
191 | dev_dbg(nmk_chip->chip.dev, "pin %d: sleep pull %s, dir %s, val %s\n", | |
192 | pin, | |
193 | slpm_pull ? pullnames[pull] : "same", | |
194 | slpm_output ? (output ? "output" : "input") : "same", | |
195 | slpm_val ? (val ? "high" : "low") : "same"); | |
196 | } | |
197 | ||
6720db7c RV |
198 | if (output) |
199 | __nmk_gpio_make_output(nmk_chip, offset, val); | |
200 | else { | |
201 | __nmk_gpio_make_input(nmk_chip, offset); | |
202 | __nmk_gpio_set_pull(nmk_chip, offset, pull); | |
203 | } | |
378be066 | 204 | |
378be066 RV |
205 | __nmk_gpio_set_slpm(nmk_chip, offset, slpm); |
206 | __nmk_gpio_set_mode(nmk_chip, offset, af); | |
207 | } | |
208 | ||
209 | /** | |
210 | * nmk_config_pin - configure a pin's mux attributes | |
211 | * @cfg: pin confguration | |
212 | * | |
213 | * Configures a pin's mode (alternate function or GPIO), its pull up status, | |
214 | * and its sleep mode based on the specified configuration. The @cfg is | |
215 | * usually one of the SoC specific macros defined in mach/<soc>-pins.h. These | |
216 | * are constructed using, and can be further enhanced with, the macros in | |
217 | * plat/pincfg.h. | |
218 | * | |
219 | * If a pin's mode is set to GPIO, it is configured as an input to avoid | |
220 | * side-effects. The gpio can be manipulated later using standard GPIO API | |
221 | * calls. | |
222 | */ | |
dacdc96c | 223 | int nmk_config_pin(pin_cfg_t cfg, bool sleep) |
378be066 RV |
224 | { |
225 | struct nmk_gpio_chip *nmk_chip; | |
226 | int gpio = PIN_NUM(cfg); | |
227 | unsigned long flags; | |
228 | ||
229 | nmk_chip = get_irq_chip_data(NOMADIK_GPIO_TO_IRQ(gpio)); | |
230 | if (!nmk_chip) | |
231 | return -EINVAL; | |
232 | ||
233 | spin_lock_irqsave(&nmk_chip->lock, flags); | |
dacdc96c | 234 | __nmk_config_pin(nmk_chip, gpio - nmk_chip->chip.base, cfg, sleep); |
378be066 RV |
235 | spin_unlock_irqrestore(&nmk_chip->lock, flags); |
236 | ||
237 | return 0; | |
238 | } | |
239 | EXPORT_SYMBOL(nmk_config_pin); | |
240 | ||
241 | /** | |
242 | * nmk_config_pins - configure several pins at once | |
243 | * @cfgs: array of pin configurations | |
244 | * @num: number of elments in the array | |
245 | * | |
246 | * Configures several pins using nmk_config_pin(). Refer to that function for | |
247 | * further information. | |
248 | */ | |
249 | int nmk_config_pins(pin_cfg_t *cfgs, int num) | |
250 | { | |
251 | int ret = 0; | |
252 | int i; | |
253 | ||
254 | for (i = 0; i < num; i++) { | |
dacdc96c | 255 | ret = nmk_config_pin(cfgs[i], false); |
378be066 RV |
256 | if (ret) |
257 | break; | |
258 | } | |
259 | ||
260 | return ret; | |
261 | } | |
262 | EXPORT_SYMBOL(nmk_config_pins); | |
263 | ||
dacdc96c RV |
264 | int nmk_config_pins_sleep(pin_cfg_t *cfgs, int num) |
265 | { | |
266 | int ret = 0; | |
267 | int i; | |
268 | ||
269 | for (i = 0; i < num; i++) { | |
270 | ret = nmk_config_pin(cfgs[i], true); | |
271 | if (ret) | |
272 | break; | |
273 | } | |
274 | ||
275 | return ret; | |
276 | } | |
277 | EXPORT_SYMBOL(nmk_config_pins_sleep); | |
278 | ||
81a3c298 RV |
279 | /** |
280 | * nmk_gpio_set_slpm() - configure the sleep mode of a pin | |
281 | * @gpio: pin number | |
282 | * @mode: NMK_GPIO_SLPM_INPUT or NMK_GPIO_SLPM_NOCHANGE, | |
283 | * | |
284 | * Sets the sleep mode of a pin. If @mode is NMK_GPIO_SLPM_INPUT, the pin is | |
285 | * changed to an input (with pullup/down enabled) in sleep and deep sleep. If | |
286 | * @mode is NMK_GPIO_SLPM_NOCHANGE, the pin remains in the state it was | |
287 | * configured even when in sleep and deep sleep. | |
7e3f7e59 RV |
288 | * |
289 | * On DB8500v2 onwards, this setting loses the previous meaning and instead | |
290 | * indicates if wakeup detection is enabled on the pin. Note that | |
291 | * enable_irq_wake() will automatically enable wakeup detection. | |
81a3c298 RV |
292 | */ |
293 | int nmk_gpio_set_slpm(int gpio, enum nmk_gpio_slpm mode) | |
294 | { | |
295 | struct nmk_gpio_chip *nmk_chip; | |
296 | unsigned long flags; | |
297 | ||
298 | nmk_chip = get_irq_chip_data(NOMADIK_GPIO_TO_IRQ(gpio)); | |
299 | if (!nmk_chip) | |
300 | return -EINVAL; | |
301 | ||
302 | spin_lock_irqsave(&nmk_chip->lock, flags); | |
303 | __nmk_gpio_set_slpm(nmk_chip, gpio - nmk_chip->chip.base, mode); | |
304 | spin_unlock_irqrestore(&nmk_chip->lock, flags); | |
305 | ||
306 | return 0; | |
307 | } | |
308 | ||
5b327edf RV |
309 | /** |
310 | * nmk_gpio_set_pull() - enable/disable pull up/down on a gpio | |
311 | * @gpio: pin number | |
312 | * @pull: one of NMK_GPIO_PULL_DOWN, NMK_GPIO_PULL_UP, and NMK_GPIO_PULL_NONE | |
313 | * | |
314 | * Enables/disables pull up/down on a specified pin. This only takes effect if | |
315 | * the pin is configured as an input (either explicitly or by the alternate | |
316 | * function). | |
317 | * | |
318 | * NOTE: If enabling the pull up/down, the caller must ensure that the GPIO is | |
319 | * configured as an input. Otherwise, due to the way the controller registers | |
320 | * work, this function will change the value output on the pin. | |
321 | */ | |
322 | int nmk_gpio_set_pull(int gpio, enum nmk_gpio_pull pull) | |
323 | { | |
324 | struct nmk_gpio_chip *nmk_chip; | |
325 | unsigned long flags; | |
326 | ||
327 | nmk_chip = get_irq_chip_data(NOMADIK_GPIO_TO_IRQ(gpio)); | |
328 | if (!nmk_chip) | |
329 | return -EINVAL; | |
330 | ||
331 | spin_lock_irqsave(&nmk_chip->lock, flags); | |
332 | __nmk_gpio_set_pull(nmk_chip, gpio - nmk_chip->chip.base, pull); | |
333 | spin_unlock_irqrestore(&nmk_chip->lock, flags); | |
334 | ||
335 | return 0; | |
336 | } | |
337 | ||
2ec1d359 | 338 | /* Mode functions */ |
9c66ee6f JA |
339 | /** |
340 | * nmk_gpio_set_mode() - set the mux mode of a gpio pin | |
341 | * @gpio: pin number | |
342 | * @gpio_mode: one of NMK_GPIO_ALT_GPIO, NMK_GPIO_ALT_A, | |
343 | * NMK_GPIO_ALT_B, and NMK_GPIO_ALT_C | |
344 | * | |
345 | * Sets the mode of the specified pin to one of the alternate functions or | |
346 | * plain GPIO. | |
347 | */ | |
2ec1d359 AR |
348 | int nmk_gpio_set_mode(int gpio, int gpio_mode) |
349 | { | |
350 | struct nmk_gpio_chip *nmk_chip; | |
351 | unsigned long flags; | |
2ec1d359 AR |
352 | |
353 | nmk_chip = get_irq_chip_data(NOMADIK_GPIO_TO_IRQ(gpio)); | |
354 | if (!nmk_chip) | |
355 | return -EINVAL; | |
356 | ||
2ec1d359 | 357 | spin_lock_irqsave(&nmk_chip->lock, flags); |
6f9a974c | 358 | __nmk_gpio_set_mode(nmk_chip, gpio - nmk_chip->chip.base, gpio_mode); |
2ec1d359 AR |
359 | spin_unlock_irqrestore(&nmk_chip->lock, flags); |
360 | ||
361 | return 0; | |
362 | } | |
363 | EXPORT_SYMBOL(nmk_gpio_set_mode); | |
364 | ||
365 | int nmk_gpio_get_mode(int gpio) | |
366 | { | |
367 | struct nmk_gpio_chip *nmk_chip; | |
368 | u32 afunc, bfunc, bit; | |
369 | ||
370 | nmk_chip = get_irq_chip_data(NOMADIK_GPIO_TO_IRQ(gpio)); | |
371 | if (!nmk_chip) | |
372 | return -EINVAL; | |
373 | ||
374 | bit = 1 << (gpio - nmk_chip->chip.base); | |
375 | ||
376 | afunc = readl(nmk_chip->addr + NMK_GPIO_AFSLA) & bit; | |
377 | bfunc = readl(nmk_chip->addr + NMK_GPIO_AFSLB) & bit; | |
378 | ||
379 | return (afunc ? NMK_GPIO_ALT_A : 0) | (bfunc ? NMK_GPIO_ALT_B : 0); | |
380 | } | |
381 | EXPORT_SYMBOL(nmk_gpio_get_mode); | |
382 | ||
383 | ||
384 | /* IRQ functions */ | |
385 | static inline int nmk_gpio_get_bitmask(int gpio) | |
386 | { | |
387 | return 1 << (gpio % 32); | |
388 | } | |
389 | ||
f272c00e | 390 | static void nmk_gpio_irq_ack(struct irq_data *d) |
2ec1d359 AR |
391 | { |
392 | int gpio; | |
393 | struct nmk_gpio_chip *nmk_chip; | |
394 | ||
f272c00e LB |
395 | gpio = NOMADIK_IRQ_TO_GPIO(d->irq); |
396 | nmk_chip = irq_data_get_irq_chip_data(d); | |
2ec1d359 AR |
397 | if (!nmk_chip) |
398 | return; | |
399 | writel(nmk_gpio_get_bitmask(gpio), nmk_chip->addr + NMK_GPIO_IC); | |
400 | } | |
401 | ||
4d4e20f7 RV |
402 | enum nmk_gpio_irq_type { |
403 | NORMAL, | |
404 | WAKE, | |
405 | }; | |
406 | ||
040e5ecd | 407 | static void __nmk_gpio_irq_modify(struct nmk_gpio_chip *nmk_chip, |
4d4e20f7 RV |
408 | int gpio, enum nmk_gpio_irq_type which, |
409 | bool enable) | |
2ec1d359 | 410 | { |
4d4e20f7 RV |
411 | u32 rimsc = which == WAKE ? NMK_GPIO_RWIMSC : NMK_GPIO_RIMSC; |
412 | u32 fimsc = which == WAKE ? NMK_GPIO_FWIMSC : NMK_GPIO_FIMSC; | |
040e5ecd RV |
413 | u32 bitmask = nmk_gpio_get_bitmask(gpio); |
414 | u32 reg; | |
2ec1d359 | 415 | |
040e5ecd | 416 | /* we must individually set/clear the two edges */ |
2ec1d359 | 417 | if (nmk_chip->edge_rising & bitmask) { |
4d4e20f7 | 418 | reg = readl(nmk_chip->addr + rimsc); |
040e5ecd RV |
419 | if (enable) |
420 | reg |= bitmask; | |
421 | else | |
422 | reg &= ~bitmask; | |
4d4e20f7 | 423 | writel(reg, nmk_chip->addr + rimsc); |
2ec1d359 AR |
424 | } |
425 | if (nmk_chip->edge_falling & bitmask) { | |
4d4e20f7 | 426 | reg = readl(nmk_chip->addr + fimsc); |
040e5ecd RV |
427 | if (enable) |
428 | reg |= bitmask; | |
429 | else | |
430 | reg &= ~bitmask; | |
4d4e20f7 | 431 | writel(reg, nmk_chip->addr + fimsc); |
2ec1d359 | 432 | } |
040e5ecd | 433 | } |
2ec1d359 | 434 | |
f272c00e | 435 | static int nmk_gpio_irq_modify(struct irq_data *d, enum nmk_gpio_irq_type which, |
4d4e20f7 | 436 | bool enable) |
2ec1d359 AR |
437 | { |
438 | int gpio; | |
439 | struct nmk_gpio_chip *nmk_chip; | |
440 | unsigned long flags; | |
040e5ecd | 441 | u32 bitmask; |
2ec1d359 | 442 | |
f272c00e LB |
443 | gpio = NOMADIK_IRQ_TO_GPIO(d->irq); |
444 | nmk_chip = irq_data_get_irq_chip_data(d); | |
2ec1d359 AR |
445 | bitmask = nmk_gpio_get_bitmask(gpio); |
446 | if (!nmk_chip) | |
4d4e20f7 | 447 | return -EINVAL; |
2ec1d359 | 448 | |
2ec1d359 | 449 | spin_lock_irqsave(&nmk_chip->lock, flags); |
4d4e20f7 | 450 | __nmk_gpio_irq_modify(nmk_chip, gpio, which, enable); |
2ec1d359 | 451 | spin_unlock_irqrestore(&nmk_chip->lock, flags); |
4d4e20f7 RV |
452 | |
453 | return 0; | |
2ec1d359 AR |
454 | } |
455 | ||
f272c00e | 456 | static void nmk_gpio_irq_mask(struct irq_data *d) |
040e5ecd | 457 | { |
f272c00e | 458 | nmk_gpio_irq_modify(d, NORMAL, false); |
4d4e20f7 | 459 | } |
040e5ecd | 460 | |
f272c00e | 461 | static void nmk_gpio_irq_unmask(struct irq_data *d) |
040e5ecd | 462 | { |
f272c00e | 463 | nmk_gpio_irq_modify(d, NORMAL, true); |
4d4e20f7 RV |
464 | } |
465 | ||
f272c00e | 466 | static int nmk_gpio_irq_set_wake(struct irq_data *d, unsigned int on) |
4d4e20f7 | 467 | { |
7e3f7e59 RV |
468 | struct nmk_gpio_chip *nmk_chip; |
469 | unsigned long flags; | |
470 | int gpio; | |
471 | ||
f272c00e LB |
472 | gpio = NOMADIK_IRQ_TO_GPIO(d->irq); |
473 | nmk_chip = irq_data_get_irq_chip_data(d); | |
7e3f7e59 RV |
474 | if (!nmk_chip) |
475 | return -EINVAL; | |
476 | ||
477 | spin_lock_irqsave(&nmk_chip->lock, flags); | |
478 | #ifdef CONFIG_ARCH_U8500 | |
479 | if (cpu_is_u8500v2()) { | |
480 | __nmk_gpio_set_slpm(nmk_chip, gpio, | |
481 | on ? NMK_GPIO_SLPM_WAKEUP_ENABLE | |
482 | : NMK_GPIO_SLPM_WAKEUP_DISABLE); | |
483 | } | |
484 | #endif | |
485 | __nmk_gpio_irq_modify(nmk_chip, gpio, WAKE, on); | |
486 | spin_unlock_irqrestore(&nmk_chip->lock, flags); | |
487 | ||
488 | return 0; | |
040e5ecd RV |
489 | } |
490 | ||
f272c00e | 491 | static int nmk_gpio_irq_set_type(struct irq_data *d, unsigned int type) |
2ec1d359 | 492 | { |
f272c00e | 493 | struct irq_desc *desc = irq_to_desc(d->irq); |
4d4e20f7 RV |
494 | bool enabled = !(desc->status & IRQ_DISABLED); |
495 | bool wake = desc->wake_depth; | |
2ec1d359 AR |
496 | int gpio; |
497 | struct nmk_gpio_chip *nmk_chip; | |
498 | unsigned long flags; | |
499 | u32 bitmask; | |
500 | ||
f272c00e LB |
501 | gpio = NOMADIK_IRQ_TO_GPIO(d->irq); |
502 | nmk_chip = irq_data_get_irq_chip_data(d); | |
2ec1d359 AR |
503 | bitmask = nmk_gpio_get_bitmask(gpio); |
504 | if (!nmk_chip) | |
505 | return -EINVAL; | |
506 | ||
507 | if (type & IRQ_TYPE_LEVEL_HIGH) | |
508 | return -EINVAL; | |
509 | if (type & IRQ_TYPE_LEVEL_LOW) | |
510 | return -EINVAL; | |
511 | ||
512 | spin_lock_irqsave(&nmk_chip->lock, flags); | |
513 | ||
7a852d80 | 514 | if (enabled) |
4d4e20f7 RV |
515 | __nmk_gpio_irq_modify(nmk_chip, gpio, NORMAL, false); |
516 | ||
517 | if (wake) | |
518 | __nmk_gpio_irq_modify(nmk_chip, gpio, WAKE, false); | |
7a852d80 | 519 | |
2ec1d359 AR |
520 | nmk_chip->edge_rising &= ~bitmask; |
521 | if (type & IRQ_TYPE_EDGE_RISING) | |
522 | nmk_chip->edge_rising |= bitmask; | |
2ec1d359 AR |
523 | |
524 | nmk_chip->edge_falling &= ~bitmask; | |
525 | if (type & IRQ_TYPE_EDGE_FALLING) | |
526 | nmk_chip->edge_falling |= bitmask; | |
2ec1d359 | 527 | |
7a852d80 | 528 | if (enabled) |
4d4e20f7 RV |
529 | __nmk_gpio_irq_modify(nmk_chip, gpio, NORMAL, true); |
530 | ||
531 | if (wake) | |
532 | __nmk_gpio_irq_modify(nmk_chip, gpio, WAKE, true); | |
2ec1d359 | 533 | |
7a852d80 | 534 | spin_unlock_irqrestore(&nmk_chip->lock, flags); |
2ec1d359 AR |
535 | |
536 | return 0; | |
537 | } | |
538 | ||
539 | static struct irq_chip nmk_gpio_irq_chip = { | |
540 | .name = "Nomadik-GPIO", | |
f272c00e LB |
541 | .irq_ack = nmk_gpio_irq_ack, |
542 | .irq_mask = nmk_gpio_irq_mask, | |
543 | .irq_unmask = nmk_gpio_irq_unmask, | |
544 | .irq_set_type = nmk_gpio_irq_set_type, | |
545 | .irq_set_wake = nmk_gpio_irq_set_wake, | |
2ec1d359 AR |
546 | }; |
547 | ||
33b744b3 RV |
548 | static void __nmk_gpio_irq_handler(unsigned int irq, struct irq_desc *desc, |
549 | u32 status) | |
2ec1d359 AR |
550 | { |
551 | struct nmk_gpio_chip *nmk_chip; | |
aaedaa2b | 552 | struct irq_chip *host_chip = get_irq_chip(irq); |
2ec1d359 AR |
553 | unsigned int first_irq; |
554 | ||
f272c00e LB |
555 | if (host_chip->irq_mask_ack) |
556 | host_chip->irq_mask_ack(&desc->irq_data); | |
aaedaa2b | 557 | else { |
f272c00e LB |
558 | host_chip->irq_mask(&desc->irq_data); |
559 | if (host_chip->irq_ack) | |
560 | host_chip->irq_ack(&desc->irq_data); | |
aaedaa2b RV |
561 | } |
562 | ||
2ec1d359 AR |
563 | nmk_chip = get_irq_data(irq); |
564 | first_irq = NOMADIK_GPIO_TO_IRQ(nmk_chip->chip.base); | |
33b744b3 RV |
565 | while (status) { |
566 | int bit = __ffs(status); | |
567 | ||
568 | generic_handle_irq(first_irq + bit); | |
569 | status &= ~BIT(bit); | |
2ec1d359 | 570 | } |
aaedaa2b | 571 | |
f272c00e | 572 | host_chip->irq_unmask(&desc->irq_data); |
2ec1d359 AR |
573 | } |
574 | ||
33b744b3 RV |
575 | static void nmk_gpio_irq_handler(unsigned int irq, struct irq_desc *desc) |
576 | { | |
577 | struct nmk_gpio_chip *nmk_chip = get_irq_data(irq); | |
578 | u32 status = readl(nmk_chip->addr + NMK_GPIO_IS); | |
579 | ||
580 | __nmk_gpio_irq_handler(irq, desc, status); | |
581 | } | |
582 | ||
583 | static void nmk_gpio_secondary_irq_handler(unsigned int irq, | |
584 | struct irq_desc *desc) | |
585 | { | |
586 | struct nmk_gpio_chip *nmk_chip = get_irq_data(irq); | |
587 | u32 status = nmk_chip->get_secondary_status(nmk_chip->bank); | |
588 | ||
589 | __nmk_gpio_irq_handler(irq, desc, status); | |
590 | } | |
591 | ||
2ec1d359 AR |
592 | static int nmk_gpio_init_irq(struct nmk_gpio_chip *nmk_chip) |
593 | { | |
594 | unsigned int first_irq; | |
595 | int i; | |
596 | ||
597 | first_irq = NOMADIK_GPIO_TO_IRQ(nmk_chip->chip.base); | |
e493e06f | 598 | for (i = first_irq; i < first_irq + nmk_chip->chip.ngpio; i++) { |
2ec1d359 AR |
599 | set_irq_chip(i, &nmk_gpio_irq_chip); |
600 | set_irq_handler(i, handle_edge_irq); | |
601 | set_irq_flags(i, IRQF_VALID); | |
602 | set_irq_chip_data(i, nmk_chip); | |
2210d645 | 603 | set_irq_type(i, IRQ_TYPE_EDGE_FALLING); |
2ec1d359 | 604 | } |
33b744b3 | 605 | |
2ec1d359 AR |
606 | set_irq_chained_handler(nmk_chip->parent_irq, nmk_gpio_irq_handler); |
607 | set_irq_data(nmk_chip->parent_irq, nmk_chip); | |
33b744b3 RV |
608 | |
609 | if (nmk_chip->secondary_parent_irq >= 0) { | |
610 | set_irq_chained_handler(nmk_chip->secondary_parent_irq, | |
611 | nmk_gpio_secondary_irq_handler); | |
612 | set_irq_data(nmk_chip->secondary_parent_irq, nmk_chip); | |
613 | } | |
614 | ||
2ec1d359 AR |
615 | return 0; |
616 | } | |
617 | ||
618 | /* I/O Functions */ | |
619 | static int nmk_gpio_make_input(struct gpio_chip *chip, unsigned offset) | |
620 | { | |
621 | struct nmk_gpio_chip *nmk_chip = | |
622 | container_of(chip, struct nmk_gpio_chip, chip); | |
623 | ||
624 | writel(1 << offset, nmk_chip->addr + NMK_GPIO_DIRC); | |
625 | return 0; | |
626 | } | |
627 | ||
2ec1d359 AR |
628 | static int nmk_gpio_get_input(struct gpio_chip *chip, unsigned offset) |
629 | { | |
630 | struct nmk_gpio_chip *nmk_chip = | |
631 | container_of(chip, struct nmk_gpio_chip, chip); | |
632 | u32 bit = 1 << offset; | |
633 | ||
634 | return (readl(nmk_chip->addr + NMK_GPIO_DAT) & bit) != 0; | |
635 | } | |
636 | ||
637 | static void nmk_gpio_set_output(struct gpio_chip *chip, unsigned offset, | |
638 | int val) | |
639 | { | |
640 | struct nmk_gpio_chip *nmk_chip = | |
641 | container_of(chip, struct nmk_gpio_chip, chip); | |
2ec1d359 | 642 | |
6720db7c | 643 | __nmk_gpio_set_output(nmk_chip, offset, val); |
2ec1d359 AR |
644 | } |
645 | ||
6647c6c0 RV |
646 | static int nmk_gpio_make_output(struct gpio_chip *chip, unsigned offset, |
647 | int val) | |
648 | { | |
649 | struct nmk_gpio_chip *nmk_chip = | |
650 | container_of(chip, struct nmk_gpio_chip, chip); | |
651 | ||
6720db7c | 652 | __nmk_gpio_make_output(nmk_chip, offset, val); |
6647c6c0 RV |
653 | |
654 | return 0; | |
655 | } | |
656 | ||
0d2aec9c RV |
657 | static int nmk_gpio_to_irq(struct gpio_chip *chip, unsigned offset) |
658 | { | |
659 | struct nmk_gpio_chip *nmk_chip = | |
660 | container_of(chip, struct nmk_gpio_chip, chip); | |
661 | ||
662 | return NOMADIK_GPIO_TO_IRQ(nmk_chip->chip.base) + offset; | |
663 | } | |
664 | ||
d0b543c7 RV |
665 | #ifdef CONFIG_DEBUG_FS |
666 | ||
667 | #include <linux/seq_file.h> | |
668 | ||
669 | static void nmk_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip) | |
670 | { | |
671 | int mode; | |
672 | unsigned i; | |
673 | unsigned gpio = chip->base; | |
674 | int is_out; | |
675 | struct nmk_gpio_chip *nmk_chip = | |
676 | container_of(chip, struct nmk_gpio_chip, chip); | |
677 | const char *modes[] = { | |
678 | [NMK_GPIO_ALT_GPIO] = "gpio", | |
679 | [NMK_GPIO_ALT_A] = "altA", | |
680 | [NMK_GPIO_ALT_B] = "altB", | |
681 | [NMK_GPIO_ALT_C] = "altC", | |
682 | }; | |
683 | ||
684 | for (i = 0; i < chip->ngpio; i++, gpio++) { | |
685 | const char *label = gpiochip_is_requested(chip, i); | |
686 | bool pull; | |
687 | u32 bit = 1 << i; | |
688 | ||
689 | if (!label) | |
690 | continue; | |
691 | ||
692 | is_out = readl(nmk_chip->addr + NMK_GPIO_DIR) & bit; | |
693 | pull = !(readl(nmk_chip->addr + NMK_GPIO_PDIS) & bit); | |
694 | mode = nmk_gpio_get_mode(gpio); | |
695 | seq_printf(s, " gpio-%-3d (%-20.20s) %s %s %s %s", | |
696 | gpio, label, | |
697 | is_out ? "out" : "in ", | |
698 | chip->get | |
699 | ? (chip->get(chip, i) ? "hi" : "lo") | |
700 | : "? ", | |
701 | (mode < 0) ? "unknown" : modes[mode], | |
702 | pull ? "pull" : "none"); | |
703 | ||
704 | if (!is_out) { | |
705 | int irq = gpio_to_irq(gpio); | |
706 | struct irq_desc *desc = irq_to_desc(irq); | |
707 | ||
708 | /* This races with request_irq(), set_irq_type(), | |
709 | * and set_irq_wake() ... but those are "rare". | |
710 | * | |
711 | * More significantly, trigger type flags aren't | |
712 | * currently maintained by genirq. | |
713 | */ | |
714 | if (irq >= 0 && desc->action) { | |
715 | char *trigger; | |
716 | ||
717 | switch (desc->status & IRQ_TYPE_SENSE_MASK) { | |
718 | case IRQ_TYPE_NONE: | |
719 | trigger = "(default)"; | |
720 | break; | |
721 | case IRQ_TYPE_EDGE_FALLING: | |
722 | trigger = "edge-falling"; | |
723 | break; | |
724 | case IRQ_TYPE_EDGE_RISING: | |
725 | trigger = "edge-rising"; | |
726 | break; | |
727 | case IRQ_TYPE_EDGE_BOTH: | |
728 | trigger = "edge-both"; | |
729 | break; | |
730 | case IRQ_TYPE_LEVEL_HIGH: | |
731 | trigger = "level-high"; | |
732 | break; | |
733 | case IRQ_TYPE_LEVEL_LOW: | |
734 | trigger = "level-low"; | |
735 | break; | |
736 | default: | |
737 | trigger = "?trigger?"; | |
738 | break; | |
739 | } | |
740 | ||
741 | seq_printf(s, " irq-%d %s%s", | |
742 | irq, trigger, | |
743 | (desc->status & IRQ_WAKEUP) | |
744 | ? " wakeup" : ""); | |
745 | } | |
746 | } | |
747 | ||
748 | seq_printf(s, "\n"); | |
749 | } | |
750 | } | |
751 | ||
752 | #else | |
753 | #define nmk_gpio_dbg_show NULL | |
754 | #endif | |
755 | ||
2ec1d359 AR |
756 | /* This structure is replicated for each GPIO block allocated at probe time */ |
757 | static struct gpio_chip nmk_gpio_template = { | |
758 | .direction_input = nmk_gpio_make_input, | |
759 | .get = nmk_gpio_get_input, | |
760 | .direction_output = nmk_gpio_make_output, | |
761 | .set = nmk_gpio_set_output, | |
0d2aec9c | 762 | .to_irq = nmk_gpio_to_irq, |
d0b543c7 | 763 | .dbg_show = nmk_gpio_dbg_show, |
2ec1d359 AR |
764 | .can_sleep = 0, |
765 | }; | |
766 | ||
fd0d67d6 | 767 | static int __devinit nmk_gpio_probe(struct platform_device *dev) |
2ec1d359 | 768 | { |
3e3c62ca | 769 | struct nmk_gpio_platform_data *pdata = dev->dev.platform_data; |
2ec1d359 AR |
770 | struct nmk_gpio_chip *nmk_chip; |
771 | struct gpio_chip *chip; | |
3e3c62ca | 772 | struct resource *res; |
af7dc228 | 773 | struct clk *clk; |
33b744b3 | 774 | int secondary_irq; |
3e3c62ca | 775 | int irq; |
2ec1d359 AR |
776 | int ret; |
777 | ||
3e3c62ca RV |
778 | if (!pdata) |
779 | return -ENODEV; | |
780 | ||
781 | res = platform_get_resource(dev, IORESOURCE_MEM, 0); | |
782 | if (!res) { | |
783 | ret = -ENOENT; | |
784 | goto out; | |
785 | } | |
786 | ||
787 | irq = platform_get_irq(dev, 0); | |
788 | if (irq < 0) { | |
789 | ret = irq; | |
790 | goto out; | |
791 | } | |
792 | ||
33b744b3 RV |
793 | secondary_irq = platform_get_irq(dev, 1); |
794 | if (secondary_irq >= 0 && !pdata->get_secondary_status) { | |
795 | ret = -EINVAL; | |
796 | goto out; | |
797 | } | |
798 | ||
3e3c62ca RV |
799 | if (request_mem_region(res->start, resource_size(res), |
800 | dev_name(&dev->dev)) == NULL) { | |
801 | ret = -EBUSY; | |
802 | goto out; | |
803 | } | |
2ec1d359 | 804 | |
af7dc228 RV |
805 | clk = clk_get(&dev->dev, NULL); |
806 | if (IS_ERR(clk)) { | |
807 | ret = PTR_ERR(clk); | |
808 | goto out_release; | |
809 | } | |
810 | ||
811 | clk_enable(clk); | |
812 | ||
2ec1d359 AR |
813 | nmk_chip = kzalloc(sizeof(*nmk_chip), GFP_KERNEL); |
814 | if (!nmk_chip) { | |
815 | ret = -ENOMEM; | |
af7dc228 | 816 | goto out_clk; |
2ec1d359 AR |
817 | } |
818 | /* | |
819 | * The virt address in nmk_chip->addr is in the nomadik register space, | |
820 | * so we can simply convert the resource address, without remapping | |
821 | */ | |
33b744b3 | 822 | nmk_chip->bank = dev->id; |
af7dc228 | 823 | nmk_chip->clk = clk; |
3e3c62ca | 824 | nmk_chip->addr = io_p2v(res->start); |
2ec1d359 | 825 | nmk_chip->chip = nmk_gpio_template; |
3e3c62ca | 826 | nmk_chip->parent_irq = irq; |
33b744b3 RV |
827 | nmk_chip->secondary_parent_irq = secondary_irq; |
828 | nmk_chip->get_secondary_status = pdata->get_secondary_status; | |
c0fcb8db | 829 | spin_lock_init(&nmk_chip->lock); |
2ec1d359 AR |
830 | |
831 | chip = &nmk_chip->chip; | |
832 | chip->base = pdata->first_gpio; | |
e493e06f | 833 | chip->ngpio = pdata->num_gpio; |
8d568ae5 | 834 | chip->label = pdata->name ?: dev_name(&dev->dev); |
2ec1d359 AR |
835 | chip->dev = &dev->dev; |
836 | chip->owner = THIS_MODULE; | |
837 | ||
838 | ret = gpiochip_add(&nmk_chip->chip); | |
839 | if (ret) | |
840 | goto out_free; | |
841 | ||
3e3c62ca | 842 | platform_set_drvdata(dev, nmk_chip); |
2ec1d359 AR |
843 | |
844 | nmk_gpio_init_irq(nmk_chip); | |
845 | ||
846 | dev_info(&dev->dev, "Bits %i-%i at address %p\n", | |
847 | nmk_chip->chip.base, nmk_chip->chip.base+31, nmk_chip->addr); | |
848 | return 0; | |
849 | ||
3e3c62ca | 850 | out_free: |
2ec1d359 | 851 | kfree(nmk_chip); |
af7dc228 RV |
852 | out_clk: |
853 | clk_disable(clk); | |
854 | clk_put(clk); | |
3e3c62ca RV |
855 | out_release: |
856 | release_mem_region(res->start, resource_size(res)); | |
857 | out: | |
2ec1d359 AR |
858 | dev_err(&dev->dev, "Failure %i for GPIO %i-%i\n", ret, |
859 | pdata->first_gpio, pdata->first_gpio+31); | |
860 | return ret; | |
861 | } | |
862 | ||
9c66ee6f | 863 | #ifdef CONFIG_NOMADIK_GPIO_PM |
c84c7c08 RV |
864 | static int nmk_gpio_pm(struct platform_device *dev, bool suspend) |
865 | { | |
866 | struct nmk_gpio_chip *nmk_chip = platform_get_drvdata(dev); | |
867 | int i; | |
9c66ee6f JA |
868 | u32 dir; |
869 | u32 dat; | |
c84c7c08 | 870 | |
9c66ee6f | 871 | for (i = 0; i < ARRAY_SIZE(backup_regs); i++) { |
c84c7c08 | 872 | if (suspend) |
9c66ee6f JA |
873 | nmk_chip->backup[i] = readl(nmk_chip->addr + |
874 | backup_regs[i]); | |
c84c7c08 | 875 | else |
9c66ee6f JA |
876 | writel(nmk_chip->backup[i], |
877 | nmk_chip->addr + backup_regs[i]); | |
c84c7c08 RV |
878 | } |
879 | ||
9c66ee6f JA |
880 | if (!suspend) { |
881 | /* | |
882 | * Restore pull-up and pull-down on inputs and | |
883 | * outputs. | |
884 | */ | |
885 | dir = readl(nmk_chip->addr + NMK_GPIO_DIR); | |
886 | dat = readl(nmk_chip->addr + NMK_GPIO_DAT); | |
887 | ||
888 | writel((nmk_chip->pull & ~dir) | | |
889 | (dat & dir), | |
890 | nmk_chip->addr + NMK_GPIO_DATS); | |
891 | ||
892 | writel((~nmk_chip->pull & ~dir) | | |
893 | (~dat & dir), | |
894 | nmk_chip->addr + NMK_GPIO_DATC); | |
895 | } | |
c84c7c08 RV |
896 | return 0; |
897 | } | |
898 | ||
899 | static int nmk_gpio_suspend(struct platform_device *dev, pm_message_t state) | |
900 | { | |
901 | return nmk_gpio_pm(dev, true); | |
902 | } | |
903 | ||
904 | static int nmk_gpio_resume(struct platform_device *dev) | |
905 | { | |
906 | return nmk_gpio_pm(dev, false); | |
907 | } | |
908 | #else | |
909 | #define nmk_gpio_suspend NULL | |
910 | #define nmk_gpio_resume NULL | |
911 | #endif | |
912 | ||
3e3c62ca RV |
913 | static struct platform_driver nmk_gpio_driver = { |
914 | .driver = { | |
2ec1d359 AR |
915 | .owner = THIS_MODULE, |
916 | .name = "gpio", | |
917 | }, | |
918 | .probe = nmk_gpio_probe, | |
c84c7c08 RV |
919 | .suspend = nmk_gpio_suspend, |
920 | .resume = nmk_gpio_resume, | |
2ec1d359 AR |
921 | }; |
922 | ||
923 | static int __init nmk_gpio_init(void) | |
924 | { | |
3e3c62ca | 925 | return platform_driver_register(&nmk_gpio_driver); |
2ec1d359 AR |
926 | } |
927 | ||
33f45ea9 | 928 | core_initcall(nmk_gpio_init); |
2ec1d359 AR |
929 | |
930 | MODULE_AUTHOR("Prafulla WADASKAR and Alessandro Rubini"); | |
931 | MODULE_DESCRIPTION("Nomadik GPIO Driver"); | |
932 | MODULE_LICENSE("GPL"); | |
933 | ||
934 |