[linux-block.git] / arch / arm / plat-mxc / time.c

/*
 *  linux/arch/arm/plat-mxc/time.c
 *
 *  Copyright (C) 2000-2001 Deep Blue Solutions
 *  Copyright (C) 2002 Shane Nay (shane@minirl.com)
 *  Copyright (C) 2006-2007 Pavel Pisa (ppisa@pikron.com)
 *  Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de)
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * as published by the Free Software Foundation; either version 2
 * of the License, or (at your option) any later version.
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
 * MA 02110-1301, USA.
 */

#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/clockchips.h>
#include <linux/clk.h>
#include <linux/err.h>

#include <mach/hardware.h>
#include <asm/sched_clock.h>
#include <asm/mach/time.h>
#include <mach/common.h>

/*
 * There are 2 versions of the timer hardware on Freescale MXC hardware.
 * Version 1: MX1/MXL, MX21, MX27.
 * Version 2: MX25, MX31, MX35, MX37, MX51
 */

/* defines common for all i.MX */
#define MXC_TCTL		0x00
#define MXC_TCTL_TEN		(1 << 0) /* Enable module */
#define MXC_TPRER		0x04

/* MX1, MX21, MX27 */
#define MX1_2_TCTL_CLK_PCLK1	(1 << 1)
#define MX1_2_TCTL_IRQEN	(1 << 4)
#define MX1_2_TCTL_FRR		(1 << 8)
#define MX1_2_TCMP		0x08
#define MX1_2_TCN		0x10
#define MX1_2_TSTAT		0x14

/* MX21, MX27 */
#define MX2_TSTAT_CAPT		(1 << 1)
#define MX2_TSTAT_COMP		(1 << 0)

/* MX31, MX35, MX25, MX5 */
#define V2_TCTL_WAITEN		(1 << 3) /* Wait enable mode */
#define V2_TCTL_CLK_IPG		(1 << 6)
#define V2_TCTL_FRR		(1 << 9)
#define V2_IR			0x0c
#define V2_TSTAT		0x08
#define V2_TSTAT_OF1		(1 << 0)
#define V2_TCN			0x24
#define V2_TCMP			0x10

#define timer_is_v1()	(cpu_is_mx1() || cpu_is_mx21() || cpu_is_mx27())
#define timer_is_v2()	(!timer_is_v1())

static struct clock_event_device clockevent_mxc;
static enum clock_event_mode clockevent_mode = CLOCK_EVT_MODE_UNUSED;

static void __iomem *timer_base;

static inline void gpt_irq_disable(void)
{
	unsigned int tmp;

	if (timer_is_v2())
		__raw_writel(0, timer_base + V2_IR);
	else {
		tmp = __raw_readl(timer_base + MXC_TCTL);
		__raw_writel(tmp & ~MX1_2_TCTL_IRQEN, timer_base + MXC_TCTL);
	}
}

static inline void gpt_irq_enable(void)
{
	if (timer_is_v2())
		__raw_writel(1<<0, timer_base + V2_IR);
	else {
		__raw_writel(__raw_readl(timer_base + MXC_TCTL) | MX1_2_TCTL_IRQEN,
			timer_base + MXC_TCTL);
	}
}

static void gpt_irq_acknowledge(void)
{
	if (timer_is_v1()) {
		if (cpu_is_mx1())
			__raw_writel(0, timer_base + MX1_2_TSTAT);
		else
			__raw_writel(MX2_TSTAT_CAPT | MX2_TSTAT_COMP,
				timer_base + MX1_2_TSTAT);
	} else if (timer_is_v2())
		__raw_writel(V2_TSTAT_OF1, timer_base + V2_TSTAT);
}

static void __iomem *sched_clock_reg;

static u32 notrace mxc_read_sched_clock(void)
{
	return sched_clock_reg ? __raw_readl(sched_clock_reg) : 0;
}

static int __init mxc_clocksource_init(struct clk *timer_clk)
{
	unsigned int c = clk_get_rate(timer_clk);
	void __iomem *reg = timer_base + (timer_is_v2() ? V2_TCN : MX1_2_TCN);

	sched_clock_reg = reg;

	setup_sched_clock(mxc_read_sched_clock, 32, c);
	return clocksource_mmio_init(reg, "mxc_timer1", c, 200, 32,
			clocksource_mmio_readl_up);
}

/* clock event */

static int mx1_2_set_next_event(unsigned long evt,
			      struct clock_event_device *unused)
{
	unsigned long tcmp;

	tcmp = __raw_readl(timer_base + MX1_2_TCN) + evt;

	__raw_writel(tcmp, timer_base + MX1_2_TCMP);

	return (int)(tcmp - __raw_readl(timer_base + MX1_2_TCN)) < 0 ?
				-ETIME : 0;
}

static int v2_set_next_event(unsigned long evt,
			      struct clock_event_device *unused)
{
	unsigned long tcmp;

	tcmp = __raw_readl(timer_base + V2_TCN) + evt;

	__raw_writel(tcmp, timer_base + V2_TCMP);

	return (int)(tcmp - __raw_readl(timer_base + V2_TCN)) < 0 ?
				-ETIME : 0;
}

#ifdef DEBUG
static const char *clock_event_mode_label[] = {
	[CLOCK_EVT_MODE_PERIODIC] = "CLOCK_EVT_MODE_PERIODIC",
	[CLOCK_EVT_MODE_ONESHOT]  = "CLOCK_EVT_MODE_ONESHOT",
	[CLOCK_EVT_MODE_SHUTDOWN] = "CLOCK_EVT_MODE_SHUTDOWN",
	[CLOCK_EVT_MODE_UNUSED]   = "CLOCK_EVT_MODE_UNUSED"
};
#endif /* DEBUG */

static void mxc_set_mode(enum clock_event_mode mode,
				struct clock_event_device *evt)
{
	unsigned long flags;

	/*
	 * The timer interrupt generation is disabled at least
	 * for enough time to call mxc_set_next_event()
	 */
	local_irq_save(flags);

	/* Disable interrupt in GPT module */
	gpt_irq_disable();

	if (mode != clockevent_mode) {
		/* Set event time into far-far future */
		if (timer_is_v2())
			__raw_writel(__raw_readl(timer_base + V2_TCN) - 3,
					timer_base + V2_TCMP);
		else
			__raw_writel(__raw_readl(timer_base + MX1_2_TCN) - 3,
					timer_base + MX1_2_TCMP);

		/* Clear pending interrupt */
		gpt_irq_acknowledge();
	}

#ifdef DEBUG
	printk(KERN_INFO "mxc_set_mode: changing mode from %s to %s\n",
		clock_event_mode_label[clockevent_mode],
		clock_event_mode_label[mode]);
#endif /* DEBUG */

	/* Remember timer mode */
	clockevent_mode = mode;
	local_irq_restore(flags);

	switch (mode) {
	case CLOCK_EVT_MODE_PERIODIC:
		printk(KERN_ERR"mxc_set_mode: Periodic mode is not "
				"supported for i.MX\n");
		break;
	case CLOCK_EVT_MODE_ONESHOT:
	/*
	 * Do not put overhead of interrupt enable/disable into
	 * mxc_set_next_event(), the core has about 4 minutes
	 * to call mxc_set_next_event() or shutdown clock after
	 * mode switching
	 */
		local_irq_save(flags);
		gpt_irq_enable();
		local_irq_restore(flags);
		break;
	case CLOCK_EVT_MODE_SHUTDOWN:
	case CLOCK_EVT_MODE_UNUSED:
	case CLOCK_EVT_MODE_RESUME:
		/* Left event sources disabled, no more interrupts appear */
		break;
	}
}

/*
 * IRQ handler for the timer
 */
static irqreturn_t mxc_timer_interrupt(int irq, void *dev_id)
{
	struct clock_event_device *evt = &clockevent_mxc;
	uint32_t tstat;

	if (timer_is_v2())
		tstat = __raw_readl(timer_base + V2_TSTAT);
	else
		tstat = __raw_readl(timer_base + MX1_2_TSTAT);

	gpt_irq_acknowledge();

	evt->event_handler(evt);

	return IRQ_HANDLED;
}

static struct irqaction mxc_timer_irq = {
	.name		= "i.MX Timer Tick",
	.flags		= IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
	.handler	= mxc_timer_interrupt,
};

static struct clock_event_device clockevent_mxc = {
	.name		= "mxc_timer1",
	.features	= CLOCK_EVT_FEAT_ONESHOT,
	.shift		= 32,
	.set_mode	= mxc_set_mode,
	.set_next_event	= mx1_2_set_next_event,
	.rating		= 200,
};

static int __init mxc_clockevent_init(struct clk *timer_clk)
{
	unsigned int c = clk_get_rate(timer_clk);

	if (timer_is_v2())
		clockevent_mxc.set_next_event = v2_set_next_event;

	clockevent_mxc.mult = div_sc(c, NSEC_PER_SEC,
					clockevent_mxc.shift);
	clockevent_mxc.max_delta_ns =
			clockevent_delta2ns(0xfffffffe, &clockevent_mxc);
	clockevent_mxc.min_delta_ns =
			clockevent_delta2ns(0xff, &clockevent_mxc);

	clockevent_mxc.cpumask = cpumask_of(0);

	clockevents_register_device(&clockevent_mxc);

	return 0;
}

void __init mxc_timer_init(struct clk *timer_clk, void __iomem *base, int irq)
{
	uint32_t tctl_val;
	struct clk *timer_ipg_clk;

	if (!timer_clk) {
		timer_clk = clk_get_sys("imx-gpt.0", "per");
		if (IS_ERR(timer_clk)) {
			pr_err("i.MX timer: unable to get clk\n");
			return;
		}

		timer_ipg_clk = clk_get_sys("imx-gpt.0", "ipg");
		if (!IS_ERR(timer_ipg_clk))
			clk_prepare_enable(timer_ipg_clk);
	}

	clk_prepare_enable(timer_clk);

	timer_base = base;

	/*
	 * Initialise to a known state (all timers off, and timing reset)
	 */

	__raw_writel(0, timer_base + MXC_TCTL);
	__raw_writel(0, timer_base + MXC_TPRER); /* see datasheet note */

	if (timer_is_v2())
		tctl_val = V2_TCTL_CLK_IPG | V2_TCTL_FRR | V2_TCTL_WAITEN | MXC_TCTL_TEN;
	else
		tctl_val = MX1_2_TCTL_FRR | MX1_2_TCTL_CLK_PCLK1 | MXC_TCTL_TEN;

	__raw_writel(tctl_val, timer_base + MXC_TCTL);

	/* init and register the timer to the framework */
	mxc_clocksource_init(timer_clk);
	mxc_clockevent_init(timer_clk);

	/* Make irqs happen */
	setup_irq(irq, &mxc_timer_irq);
}
Commit	Line	Data
d0f349fb JB	1	/*
	2	* linux/arch/arm/plat-mxc/time.c
	3	*
	4	* Copyright (C) 2000-2001 Deep Blue Solutions
	5	* Copyright (C) 2002 Shane Nay (shane@minirl.com)
	6	* Copyright (C) 2006-2007 Pavel Pisa (ppisa@pikron.com)
	7	* Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de)
	8	*
	9	* This program is free software; you can redistribute it and/or
	10	* modify it under the terms of the GNU General Public License
	11	* as published by the Free Software Foundation; either version 2
	12	* of the License, or (at your option) any later version.
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
	18	* You should have received a copy of the GNU General Public License
	19	* along with this program; if not, write to the Free Software
	20	* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
	21	* MA 02110-1301, USA.
	22	*/
	23
	24	#include <linux/interrupt.h>
	25	#include <linux/irq.h>
	26	#include <linux/clockchips.h>
	27	#include <linux/clk.h>
821dc4df	28	#include <linux/err.h>
d0f349fb	29
a09e64fb	30	#include <mach/hardware.h>
c124befc	31	#include <asm/sched_clock.h>
d0f349fb	32	#include <asm/mach/time.h>
a09e64fb	33	#include <mach/common.h>
ec996ba9	34
0f3332c4 SH	35	/*
	36	* There are 2 versions of the timer hardware on Freescale MXC hardware.
	37	* Version 1: MX1/MXL, MX21, MX27.
	38	* Version 2: MX25, MX31, MX35, MX37, MX51
	39	*/
	40
ec996ba9 SH	41	/* defines common for all i.MX */
ec996ba9 SH	42	#define MXC_TCTL 0x00
0f3332c4	43	#define MXC_TCTL_TEN (1 << 0) /* Enable module */
ec996ba9 SH	44	#define MXC_TPRER 0x04
	45
	46	/* MX1, MX21, MX27 */
	47	#define MX1_2_TCTL_CLK_PCLK1 (1 << 1)
	48	#define MX1_2_TCTL_IRQEN (1 << 4)
	49	#define MX1_2_TCTL_FRR (1 << 8)
	50	#define MX1_2_TCMP 0x08
	51	#define MX1_2_TCN 0x10
	52	#define MX1_2_TSTAT 0x14
	53
	54	/* MX21, MX27 */
	55	#define MX2_TSTAT_CAPT (1 << 1)
	56	#define MX2_TSTAT_COMP (1 << 0)
	57
13cf8df9	58	/* MX31, MX35, MX25, MX5 */
38a66f51 AK	59	#define V2_TCTL_WAITEN (1 << 3) /* Wait enable mode */
	60	#define V2_TCTL_CLK_IPG (1 << 6)
	61	#define V2_TCTL_FRR (1 << 9)
	62	#define V2_IR 0x0c
	63	#define V2_TSTAT 0x08
	64	#define V2_TSTAT_OF1 (1 << 0)
	65	#define V2_TCN 0x24
	66	#define V2_TCMP 0x10
d0f349fb	67
0f3332c4 SH	68	#define timer_is_v1() (cpu_is_mx1() \|\| cpu_is_mx21() \|\| cpu_is_mx27())
	69	#define timer_is_v2() (!timer_is_v1())
	70
d0f349fb JB	71	static struct clock_event_device clockevent_mxc;
	72	static enum clock_event_mode clockevent_mode = CLOCK_EVT_MODE_UNUSED;
	73
ec996ba9	74	static void __iomem *timer_base;
d0f349fb	75
ec996ba9	76	static inline void gpt_irq_disable(void)
d0f349fb	77	{
ec996ba9 SH	78	unsigned int tmp;
ec996ba9 SH	79
0f3332c4	80	if (timer_is_v2())
38a66f51	81	__raw_writel(0, timer_base + V2_IR);
ec996ba9 SH	82	else {
	83	tmp = __raw_readl(timer_base + MXC_TCTL);
	84	__raw_writel(tmp & ~MX1_2_TCTL_IRQEN, timer_base + MXC_TCTL);
	85	}
	86	}
	87
	88	static inline void gpt_irq_enable(void)
	89	{
0f3332c4	90	if (timer_is_v2())
38a66f51	91	__raw_writel(1<<0, timer_base + V2_IR);
ec996ba9 SH	92	else {
	93	__raw_writel(__raw_readl(timer_base + MXC_TCTL) \| MX1_2_TCTL_IRQEN,
	94	timer_base + MXC_TCTL);
	95	}
	96	}
	97
	98	static void gpt_irq_acknowledge(void)
	99	{
0f3332c4 SH	100	if (timer_is_v1()) {
	101	if (cpu_is_mx1())
	102	__raw_writel(0, timer_base + MX1_2_TSTAT);
	103	else
	104	__raw_writel(MX2_TSTAT_CAPT \| MX2_TSTAT_COMP,
	105	timer_base + MX1_2_TSTAT);
	106	} else if (timer_is_v2())
d943f2c8	107	__raw_writel(V2_TSTAT_OF1, timer_base + V2_TSTAT);
ec996ba9 SH	108	}
ec996ba9 SH	109
234b6ced	110	static void __iomem *sched_clock_reg;
d0f349fb	111
2f0778af	112	static u32 notrace mxc_read_sched_clock(void)
c124befc	113	{
2f0778af	114	return sched_clock_reg ? __raw_readl(sched_clock_reg) : 0;
c124befc JW	115	}
c124befc JW	116
30c730f8	117	static int __init mxc_clocksource_init(struct clk *timer_clk)
d0f349fb	118	{
058b7a6f	119	unsigned int c = clk_get_rate(timer_clk);
234b6ced	120	void __iomem *reg = timer_base + (timer_is_v2() ? V2_TCN : MX1_2_TCN);
d0f349fb	121
234b6ced	122	sched_clock_reg = reg;
ec996ba9	123
2f0778af	124	setup_sched_clock(mxc_read_sched_clock, 32, c);
234b6ced RK	125	return clocksource_mmio_init(reg, "mxc_timer1", c, 200, 32,
234b6ced RK	126	clocksource_mmio_readl_up);
d0f349fb JB	127	}
	128
	129	/* clock event */
	130
ec996ba9	131	static int mx1_2_set_next_event(unsigned long evt,
d0f349fb JB	132	struct clock_event_device *unused)
	133	{
	134	unsigned long tcmp;
	135
ec996ba9	136	tcmp = __raw_readl(timer_base + MX1_2_TCN) + evt;
d0f349fb	137
ec996ba9 SH	138	__raw_writel(tcmp, timer_base + MX1_2_TCMP);
	139
	140	return (int)(tcmp - __raw_readl(timer_base + MX1_2_TCN)) < 0 ?
	141	-ETIME : 0;
	142	}
	143
38a66f51	144	static int v2_set_next_event(unsigned long evt,
ec996ba9 SH	145	struct clock_event_device *unused)
	146	{
	147	unsigned long tcmp;
	148
38a66f51	149	tcmp = __raw_readl(timer_base + V2_TCN) + evt;
ec996ba9	150
38a66f51	151	__raw_writel(tcmp, timer_base + V2_TCMP);
ec996ba9	152
38a66f51	153	return (int)(tcmp - __raw_readl(timer_base + V2_TCN)) < 0 ?
d0f349fb JB	154	-ETIME : 0;
	155	}
	156
	157	#ifdef DEBUG
	158	static const char *clock_event_mode_label[] = {
	159	[CLOCK_EVT_MODE_PERIODIC] = "CLOCK_EVT_MODE_PERIODIC",
	160	[CLOCK_EVT_MODE_ONESHOT] = "CLOCK_EVT_MODE_ONESHOT",
	161	[CLOCK_EVT_MODE_SHUTDOWN] = "CLOCK_EVT_MODE_SHUTDOWN",
	162	[CLOCK_EVT_MODE_UNUSED] = "CLOCK_EVT_MODE_UNUSED"
	163	};
	164	#endif /* DEBUG */
	165
	166	static void mxc_set_mode(enum clock_event_mode mode,
	167	struct clock_event_device *evt)
	168	{
	169	unsigned long flags;
	170
	171	/*
	172	* The timer interrupt generation is disabled at least
	173	* for enough time to call mxc_set_next_event()
	174	*/
	175	local_irq_save(flags);
	176
	177	/* Disable interrupt in GPT module */
	178	gpt_irq_disable();
	179
	180	if (mode != clockevent_mode) {
	181	/* Set event time into far-far future */
0f3332c4	182	if (timer_is_v2())
38a66f51 AK	183	__raw_writel(__raw_readl(timer_base + V2_TCN) - 3,
38a66f51 AK	184	timer_base + V2_TCMP);
ec996ba9 SH	185	else
	186	__raw_writel(__raw_readl(timer_base + MX1_2_TCN) - 3,
	187	timer_base + MX1_2_TCMP);
	188
d0f349fb JB	189	/* Clear pending interrupt */
	190	gpt_irq_acknowledge();
	191	}
	192
	193	#ifdef DEBUG
	194	printk(KERN_INFO "mxc_set_mode: changing mode from %s to %s\n",
	195	clock_event_mode_label[clockevent_mode],
	196	clock_event_mode_label[mode]);
	197	#endif /* DEBUG */
	198
	199	/* Remember timer mode */
	200	clockevent_mode = mode;
	201	local_irq_restore(flags);
	202
	203	switch (mode) {
	204	case CLOCK_EVT_MODE_PERIODIC:
	205	printk(KERN_ERR"mxc_set_mode: Periodic mode is not "
	206	"supported for i.MX\n");
	207	break;
	208	case CLOCK_EVT_MODE_ONESHOT:
	209	/*
	210	* Do not put overhead of interrupt enable/disable into
	211	* mxc_set_next_event(), the core has about 4 minutes
	212	* to call mxc_set_next_event() or shutdown clock after
	213	* mode switching
	214	*/
	215	local_irq_save(flags);
	216	gpt_irq_enable();
	217	local_irq_restore(flags);
	218	break;
	219	case CLOCK_EVT_MODE_SHUTDOWN:
	220	case CLOCK_EVT_MODE_UNUSED:
	221	case CLOCK_EVT_MODE_RESUME:
	222	/* Left event sources disabled, no more interrupts appear */
	223	break;
	224	}
	225	}
	226
	227	/*
	228	* IRQ handler for the timer
	229	*/
	230	static irqreturn_t mxc_timer_interrupt(int irq, void *dev_id)
	231	{
	232	struct clock_event_device *evt = &clockevent_mxc;
	233	uint32_t tstat;
	234
0f3332c4	235	if (timer_is_v2())
38a66f51	236	tstat = __raw_readl(timer_base + V2_TSTAT);
81ec1f92 SH	237	else
81ec1f92 SH	238	tstat = __raw_readl(timer_base + MX1_2_TSTAT);
d0f349fb JB	239
	240	gpt_irq_acknowledge();
	241
	242	evt->event_handler(evt);
	243
	244	return IRQ_HANDLED;
	245	}
	246
	247	static struct irqaction mxc_timer_irq = {
	248	.name = "i.MX Timer Tick",
	249	.flags = IRQF_DISABLED \| IRQF_TIMER \| IRQF_IRQPOLL,
	250	.handler = mxc_timer_interrupt,
	251	};
	252
	253	static struct clock_event_device clockevent_mxc = {
	254	.name = "mxc_timer1",
	255	.features = CLOCK_EVT_FEAT_ONESHOT,
	256	.shift = 32,
	257	.set_mode = mxc_set_mode,
ec996ba9	258	.set_next_event = mx1_2_set_next_event,
d0f349fb JB	259	.rating = 200,
	260	};
	261
30c730f8	262	static int __init mxc_clockevent_init(struct clk *timer_clk)
d0f349fb	263	{
058b7a6f	264	unsigned int c = clk_get_rate(timer_clk);
d0f349fb	265
0f3332c4	266	if (timer_is_v2())
38a66f51	267	clockevent_mxc.set_next_event = v2_set_next_event;
ec996ba9	268
058b7a6f	269	clockevent_mxc.mult = div_sc(c, NSEC_PER_SEC,
d0f349fb JB	270	clockevent_mxc.shift);
	271	clockevent_mxc.max_delta_ns =
	272	clockevent_delta2ns(0xfffffffe, &clockevent_mxc);
	273	clockevent_mxc.min_delta_ns =
	274	clockevent_delta2ns(0xff, &clockevent_mxc);
	275
320ab2b0	276	clockevent_mxc.cpumask = cpumask_of(0);
d0f349fb JB	277
	278	clockevents_register_device(&clockevent_mxc);
	279
	280	return 0;
	281	}
	282
8db5d1a6	283	void __init mxc_timer_init(struct clk timer_clk, void __iomem base, int irq)
d0f349fb	284	{
ec996ba9	285	uint32_t tctl_val;
821dc4df SH	286	struct clk *timer_ipg_clk;
	287
	288	if (!timer_clk) {
	289	timer_clk = clk_get_sys("imx-gpt.0", "per");
	290	if (IS_ERR(timer_clk)) {
	291	pr_err("i.MX timer: unable to get clk\n");
	292	return;
	293	}
	294
	295	timer_ipg_clk = clk_get_sys("imx-gpt.0", "ipg");
	296	if (!IS_ERR(timer_ipg_clk))
	297	clk_prepare_enable(timer_ipg_clk);
	298	}
ec996ba9	299
46f417de	300	clk_prepare_enable(timer_clk);
d0f349fb	301
8db5d1a6	302	timer_base = base;
ec996ba9	303
d0f349fb JB	304	/*
	305	* Initialise to a known state (all timers off, and timing reset)
	306	*/
d0f349fb	307
ec996ba9 SH	308	__raw_writel(0, timer_base + MXC_TCTL);
	309	__raw_writel(0, timer_base + MXC_TPRER); /* see datasheet note */
	310
0f3332c4	311	if (timer_is_v2())
38a66f51	312	tctl_val = V2_TCTL_CLK_IPG \| V2_TCTL_FRR \| V2_TCTL_WAITEN \| MXC_TCTL_TEN;
ec996ba9 SH	313	else
	314	tctl_val = MX1_2_TCTL_FRR \| MX1_2_TCTL_CLK_PCLK1 \| MXC_TCTL_TEN;
	315
	316	__raw_writel(tctl_val, timer_base + MXC_TCTL);
d0f349fb JB	317
d0f349fb JB	318	/* init and register the timer to the framework */
30c730f8 SH	319	mxc_clocksource_init(timer_clk);
30c730f8 SH	320	mxc_clockevent_init(timer_clk);
d0f349fb JB	321
d0f349fb JB	322	/* Make irqs happen */
ec996ba9	323	setup_irq(irq, &mxc_timer_irq);
d0f349fb	324	}