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52c543f9 | 1 | /* |
259bcaae JB |
2 | * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. |
3 | * Copyright 2008 Juergen Beisert, kernel@pengutronix.de | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or | |
6 | * modify it under the terms of the GNU General Public License | |
7 | * as published by the Free Software Foundation; either version 2 | |
8 | * of the License, or (at your option) any later version. | |
9 | * This program is distributed in the hope that it will be useful, | |
10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
12 | * GNU General Public License for more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License | |
15 | * along with this program; if not, write to the Free Software | |
16 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, | |
17 | * MA 02110-1301, USA. | |
52c543f9 QJ |
18 | */ |
19 | ||
259bcaae | 20 | #include <linux/irq.h> |
52c543f9 | 21 | #include <asm/io.h> |
a09e64fb | 22 | #include <mach/common.h> |
52c543f9 | 23 | |
259bcaae JB |
24 | #define AVIC_BASE IO_ADDRESS(AVIC_BASE_ADDR) |
25 | #define AVIC_INTCNTL (AVIC_BASE + 0x00) /* int control reg */ | |
26 | #define AVIC_NIMASK (AVIC_BASE + 0x04) /* int mask reg */ | |
27 | #define AVIC_INTENNUM (AVIC_BASE + 0x08) /* int enable number reg */ | |
28 | #define AVIC_INTDISNUM (AVIC_BASE + 0x0C) /* int disable number reg */ | |
29 | #define AVIC_INTENABLEH (AVIC_BASE + 0x10) /* int enable reg high */ | |
30 | #define AVIC_INTENABLEL (AVIC_BASE + 0x14) /* int enable reg low */ | |
31 | #define AVIC_INTTYPEH (AVIC_BASE + 0x18) /* int type reg high */ | |
32 | #define AVIC_INTTYPEL (AVIC_BASE + 0x1C) /* int type reg low */ | |
33 | #define AVIC_NIPRIORITY7 (AVIC_BASE + 0x20) /* norm int priority lvl7 */ | |
34 | #define AVIC_NIPRIORITY6 (AVIC_BASE + 0x24) /* norm int priority lvl6 */ | |
35 | #define AVIC_NIPRIORITY5 (AVIC_BASE + 0x28) /* norm int priority lvl5 */ | |
36 | #define AVIC_NIPRIORITY4 (AVIC_BASE + 0x2C) /* norm int priority lvl4 */ | |
37 | #define AVIC_NIPRIORITY3 (AVIC_BASE + 0x30) /* norm int priority lvl3 */ | |
38 | #define AVIC_NIPRIORITY2 (AVIC_BASE + 0x34) /* norm int priority lvl2 */ | |
39 | #define AVIC_NIPRIORITY1 (AVIC_BASE + 0x38) /* norm int priority lvl1 */ | |
40 | #define AVIC_NIPRIORITY0 (AVIC_BASE + 0x3C) /* norm int priority lvl0 */ | |
41 | #define AVIC_NIVECSR (AVIC_BASE + 0x40) /* norm int vector/status */ | |
42 | #define AVIC_FIVECSR (AVIC_BASE + 0x44) /* fast int vector/status */ | |
43 | #define AVIC_INTSRCH (AVIC_BASE + 0x48) /* int source reg high */ | |
44 | #define AVIC_INTSRCL (AVIC_BASE + 0x4C) /* int source reg low */ | |
45 | #define AVIC_INTFRCH (AVIC_BASE + 0x50) /* int force reg high */ | |
46 | #define AVIC_INTFRCL (AVIC_BASE + 0x54) /* int force reg low */ | |
47 | #define AVIC_NIPNDH (AVIC_BASE + 0x58) /* norm int pending high */ | |
48 | #define AVIC_NIPNDL (AVIC_BASE + 0x5C) /* norm int pending low */ | |
49 | #define AVIC_FIPNDH (AVIC_BASE + 0x60) /* fast int pending high */ | |
50 | #define AVIC_FIPNDL (AVIC_BASE + 0x64) /* fast int pending low */ | |
51 | ||
52 | #define SYSTEM_PREV_REG IO_ADDRESS(IIM_BASE_ADDR + 0x20) | |
53 | #define SYSTEM_SREV_REG IO_ADDRESS(IIM_BASE_ADDR + 0x24) | |
54 | #define IIM_PROD_REV_SH 3 | |
55 | #define IIM_PROD_REV_LEN 5 | |
56 | ||
2c130fd5 | 57 | /* Disable interrupt number "irq" in the AVIC */ |
52c543f9 QJ |
58 | static void mxc_mask_irq(unsigned int irq) |
59 | { | |
60 | __raw_writel(irq, AVIC_INTDISNUM); | |
61 | } | |
62 | ||
2c130fd5 | 63 | /* Enable interrupt number "irq" in the AVIC */ |
52c543f9 QJ |
64 | static void mxc_unmask_irq(unsigned int irq) |
65 | { | |
66 | __raw_writel(irq, AVIC_INTENNUM); | |
67 | } | |
68 | ||
69 | static struct irq_chip mxc_avic_chip = { | |
259bcaae | 70 | .ack = mxc_mask_irq, |
52c543f9 QJ |
71 | .mask = mxc_mask_irq, |
72 | .unmask = mxc_unmask_irq, | |
73 | }; | |
74 | ||
2c130fd5 | 75 | /* |
52c543f9 QJ |
76 | * This function initializes the AVIC hardware and disables all the |
77 | * interrupts. It registers the interrupt enable and disable functions | |
78 | * to the kernel for each interrupt source. | |
79 | */ | |
80 | void __init mxc_init_irq(void) | |
81 | { | |
82 | int i; | |
83 | u32 reg; | |
84 | ||
85 | /* put the AVIC into the reset value with | |
86 | * all interrupts disabled | |
87 | */ | |
88 | __raw_writel(0, AVIC_INTCNTL); | |
89 | __raw_writel(0x1f, AVIC_NIMASK); | |
90 | ||
91 | /* disable all interrupts */ | |
92 | __raw_writel(0, AVIC_INTENABLEH); | |
93 | __raw_writel(0, AVIC_INTENABLEL); | |
94 | ||
95 | /* all IRQ no FIQ */ | |
96 | __raw_writel(0, AVIC_INTTYPEH); | |
97 | __raw_writel(0, AVIC_INTTYPEL); | |
98 | for (i = 0; i < MXC_MAX_INT_LINES; i++) { | |
99 | set_irq_chip(i, &mxc_avic_chip); | |
100 | set_irq_handler(i, handle_level_irq); | |
101 | set_irq_flags(i, IRQF_VALID); | |
102 | } | |
103 | ||
104 | /* Set WDOG2's interrupt the highest priority level (bit 28-31) */ | |
105 | reg = __raw_readl(AVIC_NIPRIORITY6); | |
106 | reg |= (0xF << 28); | |
107 | __raw_writel(reg, AVIC_NIPRIORITY6); | |
108 | ||
07bd1a6c JB |
109 | /* init architectures chained interrupt handler */ |
110 | mxc_register_gpios(); | |
111 | ||
52c543f9 QJ |
112 | printk(KERN_INFO "MXC IRQ initialized\n"); |
113 | } |