[linux-2.6-block.git] / arch / arm / plat-mxc / include / mach / mx3x.h

/*
 * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
 */

/*
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#ifndef __ASM_ARCH_MXC_MX31_H__
#define __ASM_ARCH_MXC_MX31_H__

/*
 * MX31 memory map:
 *
 * Virt		Phys		Size	What
 * ---------------------------------------------------------------------------
 * FC000000	43F00000	1M	AIPS 1
 * FC100000	50000000	1M	SPBA
 * FC200000	53F00000	1M	AIPS 2
 * FC500000	60000000	128M	ROMPATCH
 * FC400000	68000000	128M	AVIC
 *         	70000000	256M	IPU (MAX M2)
 *         	80000000	256M	CSD0 SDRAM/DDR
 *         	90000000	256M	CSD1 SDRAM/DDR
 *         	A0000000	128M	CS0 Flash
 *         	A8000000	128M	CS1 Flash
 *         	B0000000	32M	CS2
 *         	B2000000	32M	CS3
 * F4000000	B4000000	32M	CS4
 *         	B6000000	32M	CS5
 * FC320000	B8000000	64K	NAND, SDRAM, WEIM, M3IF, EMI controllers
 *         	C0000000	64M	PCMCIA/CF
 */

/*
 * L2CC
 */
#define MX3x_L2CC_BASE_ADDR		0x30000000
#define MX3x_L2CC_SIZE			SZ_1M

/*
 * AIPS 1
 */
#define MX3x_AIPS1_BASE_ADDR		0x43f00000
#define MX3x_AIPS1_BASE_ADDR_VIRT	0xfc000000
#define MX3x_AIPS1_SIZE			SZ_1M
#define MX3x_MAX_BASE_ADDR			(MX3x_AIPS1_BASE_ADDR + 0x04000)
#define MX3x_EVTMON_BASE_ADDR			(MX3x_AIPS1_BASE_ADDR + 0x08000)
#define MX3x_CLKCTL_BASE_ADDR			(MX3x_AIPS1_BASE_ADDR + 0x0c000)
#define MX3x_ETB_SLOT4_BASE_ADDR		(MX3x_AIPS1_BASE_ADDR + 0x10000)
#define MX3x_ETB_SLOT5_BASE_ADDR		(MX3x_AIPS1_BASE_ADDR + 0x14000)
#define MX3x_ECT_CTIO_BASE_ADDR			(MX3x_AIPS1_BASE_ADDR + 0x18000)
#define MX3x_I2C_BASE_ADDR			(MX3x_AIPS1_BASE_ADDR + 0x80000)
#define MX3x_I2C3_BASE_ADDR			(MX3x_AIPS1_BASE_ADDR + 0x84000)
#define MX3x_UART1_BASE_ADDR			(MX3x_AIPS1_BASE_ADDR + 0x90000)
#define MX3x_UART2_BASE_ADDR			(MX3x_AIPS1_BASE_ADDR + 0x94000)
#define MX3x_I2C2_BASE_ADDR			(MX3x_AIPS1_BASE_ADDR + 0x98000)
#define MX3x_OWIRE_BASE_ADDR			(MX3x_AIPS1_BASE_ADDR + 0x9c000)
#define MX3x_SSI1_BASE_ADDR			(MX3x_AIPS1_BASE_ADDR + 0xa0000)
#define MX3x_CSPI1_BASE_ADDR			(MX3x_AIPS1_BASE_ADDR + 0xa4000)
#define MX3x_KPP_BASE_ADDR			(MX3x_AIPS1_BASE_ADDR + 0xa8000)
#define MX3x_IOMUXC_BASE_ADDR			(MX3x_AIPS1_BASE_ADDR + 0xac000)
#define MX3x_ECT_IP1_BASE_ADDR			(MX3x_AIPS1_BASE_ADDR + 0xb8000)
#define MX3x_ECT_IP2_BASE_ADDR			(MX3x_AIPS1_BASE_ADDR + 0xbc000)

/*
 * SPBA global module enabled #0
 */
#define MX3x_SPBA0_BASE_ADDR		0x50000000
#define MX3x_SPBA0_BASE_ADDR_VIRT	0xfc100000
#define MX3x_SPBA0_SIZE			SZ_1M
#define MX3x_UART3_BASE_ADDR			(MX3x_SPBA0_BASE_ADDR + 0x0c000)
#define MX3x_CSPI2_BASE_ADDR			(MX3x_SPBA0_BASE_ADDR + 0x10000)
#define MX3x_SSI2_BASE_ADDR			(MX3x_SPBA0_BASE_ADDR + 0x14000)
#define MX3x_ATA_DMA_BASE_ADDR			(MX3x_SPBA0_BASE_ADDR + 0x20000)
#define MX3x_MSHC1_BASE_ADDR			(MX3x_SPBA0_BASE_ADDR + 0x24000)
#define MX3x_SPBA_CTRL_BASE_ADDR		(MX3x_SPBA0_BASE_ADDR + 0x3c000)

/*
 * AIPS 2
 */
#define MX3x_AIPS2_BASE_ADDR		0x53f00000
#define MX3x_AIPS2_BASE_ADDR_VIRT	0xfc200000
#define MX3x_AIPS2_SIZE			SZ_1M
#define MX3x_CCM_BASE_ADDR			(MX3x_AIPS2_BASE_ADDR + 0x80000)
#define MX3x_GPT1_BASE_ADDR			(MX3x_AIPS2_BASE_ADDR + 0x90000)
#define MX3x_EPIT1_BASE_ADDR			(MX3x_AIPS2_BASE_ADDR + 0x94000)
#define MX3x_EPIT2_BASE_ADDR			(MX3x_AIPS2_BASE_ADDR + 0x98000)
#define MX3x_GPIO3_BASE_ADDR			(MX3x_AIPS2_BASE_ADDR + 0xa4000)
#define MX3x_SCC_BASE_ADDR			(MX3x_AIPS2_BASE_ADDR + 0xac000)
#define MX3x_RNGA_BASE_ADDR			(MX3x_AIPS2_BASE_ADDR + 0xb0000)
#define MX3x_IPU_CTRL_BASE_ADDR			(MX3x_AIPS2_BASE_ADDR + 0xc0000)
#define MX3x_AUDMUX_BASE_ADDR			(MX3x_AIPS2_BASE_ADDR + 0xc4000)
#define MX3x_GPIO1_BASE_ADDR			(MX3x_AIPS2_BASE_ADDR + 0xcc000)
#define MX3x_GPIO2_BASE_ADDR			(MX3x_AIPS2_BASE_ADDR + 0xd0000)
#define MX3x_SDMA_BASE_ADDR			(MX3x_AIPS2_BASE_ADDR + 0xd4000)
#define MX3x_RTC_BASE_ADDR			(MX3x_AIPS2_BASE_ADDR + 0xd8000)
#define MX3x_WDOG_BASE_ADDR			(MX3x_AIPS2_BASE_ADDR + 0xdc000)
#define MX3x_PWM_BASE_ADDR			(MX3x_AIPS2_BASE_ADDR + 0xe0000)
#define MX3x_RTIC_BASE_ADDR			(MX3x_AIPS2_BASE_ADDR + 0xec000)

/*
 * ROMP and AVIC
 */
#define MX3x_ROMP_BASE_ADDR		0x60000000
#define MX3x_ROMP_BASE_ADDR_VIRT	0xfc500000
#define MX3x_ROMP_SIZE			SZ_1M

#define MX3x_AVIC_BASE_ADDR		0x68000000
#define MX3x_AVIC_BASE_ADDR_VIRT	0xfc400000
#define MX3x_AVIC_SIZE			SZ_1M

/*
 * Memory regions and CS
 */
#define MX3x_IPU_MEM_BASE_ADDR		0x70000000
#define MX3x_CSD0_BASE_ADDR		0x80000000
#define MX3x_CSD1_BASE_ADDR		0x90000000

#define MX3x_CS0_BASE_ADDR		0xa0000000
#define MX3x_CS1_BASE_ADDR		0xa8000000
#define MX3x_CS2_BASE_ADDR		0xb0000000
#define MX3x_CS3_BASE_ADDR		0xb2000000

#define MX3x_CS4_BASE_ADDR		0xb4000000
#define MX3x_CS4_BASE_ADDR_VIRT		0xf4000000
#define MX3x_CS4_SIZE			SZ_32M

#define MX3x_CS5_BASE_ADDR		0xb6000000
#define MX3x_CS5_BASE_ADDR_VIRT		0xf6000000
#define MX3x_CS5_SIZE			SZ_32M

/*
 * NAND, SDRAM, WEIM, M3IF, EMI controllers
 */
#define MX3x_X_MEMC_BASE_ADDR		0xb8000000
#define MX3x_X_MEMC_BASE_ADDR_VIRT	0xfc320000
#define MX3x_X_MEMC_SIZE		SZ_64K
#define MX3x_ESDCTL_BASE_ADDR			(MX3x_X_MEMC_BASE_ADDR + 0x1000)
#define MX3x_WEIM_BASE_ADDR			(MX3x_X_MEMC_BASE_ADDR + 0x2000)
#define MX3x_M3IF_BASE_ADDR			(MX3x_X_MEMC_BASE_ADDR + 0x3000)
#define MX3x_EMI_CTL_BASE_ADDR			(MX3x_X_MEMC_BASE_ADDR + 0x4000)
#define MX3x_PCMCIA_CTL_BASE_ADDR		MX3x_EMI_CTL_BASE_ADDR

#define MX3x_PCMCIA_MEM_BASE_ADDR	0xbc000000

/*!
 * This macro defines the physical to virtual address mapping for all the
 * peripheral modules. It is used by passing in the physical address as x
 * and returning the virtual address. If the physical address is not mapped,
 * it returns 0xDEADBEEF
 */
#define IO_ADDRESS(x)   \
	(void __force __iomem *) \
	(((x >= AIPS1_BASE_ADDR) && (x < (AIPS1_BASE_ADDR + AIPS1_SIZE))) ? AIPS1_IO_ADDRESS(x):\
	((x >= SPBA0_BASE_ADDR) && (x < (SPBA0_BASE_ADDR + SPBA0_SIZE))) ? SPBA0_IO_ADDRESS(x):\
	((x >= AIPS2_BASE_ADDR) && (x < (AIPS2_BASE_ADDR + AIPS2_SIZE))) ? AIPS2_IO_ADDRESS(x):\
	((x >= ROMP_BASE_ADDR) && (x < (ROMP_BASE_ADDR + ROMP_SIZE))) ? ROMP_IO_ADDRESS(x):\
	((x >= AVIC_BASE_ADDR) && (x < (AVIC_BASE_ADDR + AVIC_SIZE))) ? AVIC_IO_ADDRESS(x):\
	((x >= CS4_BASE_ADDR) && (x < (CS4_BASE_ADDR + CS4_SIZE))) ? CS4_IO_ADDRESS(x):\
	((x >= X_MEMC_BASE_ADDR) && (x < (X_MEMC_BASE_ADDR + X_MEMC_SIZE))) ? X_MEMC_IO_ADDRESS(x):\
	0xDEADBEEF)

/*
 * define the address mapping macros: in physical address order
 */
#define L2CC_IO_ADDRESS(x)  \
	(((x) - L2CC_BASE_ADDR) + L2CC_BASE_ADDR_VIRT)

#define AIPS1_IO_ADDRESS(x)  \
	(((x) - AIPS1_BASE_ADDR) + AIPS1_BASE_ADDR_VIRT)

#define SPBA0_IO_ADDRESS(x)  \
	(((x) - SPBA0_BASE_ADDR) + SPBA0_BASE_ADDR_VIRT)

#define AIPS2_IO_ADDRESS(x)  \
	(((x) - AIPS2_BASE_ADDR) + AIPS2_BASE_ADDR_VIRT)

#define ROMP_IO_ADDRESS(x)  \
	(((x) - ROMP_BASE_ADDR) + ROMP_BASE_ADDR_VIRT)

#define AVIC_IO_ADDRESS(x)  \
	(((x) - AVIC_BASE_ADDR) + AVIC_BASE_ADDR_VIRT)

#define CS4_IO_ADDRESS(x)  \
	(((x) - CS4_BASE_ADDR) + CS4_BASE_ADDR_VIRT)

#define CS5_IO_ADDRESS(x)  \
	(((x) - CS5_BASE_ADDR) + CS5_BASE_ADDR_VIRT)

#define X_MEMC_IO_ADDRESS(x)  \
	(((x) - X_MEMC_BASE_ADDR) + X_MEMC_BASE_ADDR_VIRT)

#define PCMCIA_IO_ADDRESS(x) \
	(((x) - X_MEMC_BASE_ADDR) + X_MEMC_BASE_ADDR_VIRT)

/*
 * Interrupt numbers
 */
#define MX3x_INT_I2C3		3
#define MX3x_INT_I2C2		4
#define MX3x_INT_RTIC		6
#define MX3x_INT_I2C		10
#define MX3x_INT_CSPI2		13
#define MX3x_INT_CSPI1		14
#define MX3x_INT_ATA		15
#define MX3x_INT_UART3		18
#define MX3x_INT_IIM		19
#define MX3x_INT_RNGA		22
#define MX3x_INT_EVTMON		23
#define MX3x_INT_KPP		24
#define MX3x_INT_RTC		25
#define MX3x_INT_PWM		26
#define MX3x_INT_EPIT2		27
#define MX3x_INT_EPIT1		28
#define MX3x_INT_GPT		29
#define MX3x_INT_POWER_FAIL	30
#define MX3x_INT_UART2		32
#define MX3x_INT_NANDFC		33
#define MX3x_INT_SDMA		34
#define MX3x_INT_MSHC1		39
#define MX3x_INT_IPU_ERR	41
#define MX3x_INT_IPU_SYN	42
#define MX3x_INT_UART1		45
#define MX3x_INT_ECT		48
#define MX3x_INT_SCC_SCM	49
#define MX3x_INT_SCC_SMN	50
#define MX3x_INT_GPIO2		51
#define MX3x_INT_GPIO1		52
#define MX3x_INT_WDOG		55
#define MX3x_INT_GPIO3		56
#define MX3x_INT_EXT_POWER	58
#define MX3x_INT_EXT_TEMPER	59
#define MX3x_INT_EXT_SENSOR60	60
#define MX3x_INT_EXT_SENSOR61	61
#define MX3x_INT_EXT_WDOG	62
#define MX3x_INT_EXT_TV		63

#define MX3x_PROD_SIGNATURE		0x1	/* For MX31 */

/* silicon revisions specific to i.MX31 */
#define MX3x_CHIP_REV_1_0		0x10
#define MX3x_CHIP_REV_1_1		0x11
#define MX3x_CHIP_REV_1_2		0x12
#define MX3x_CHIP_REV_1_3		0x13
#define MX3x_CHIP_REV_2_0		0x20
#define MX3x_CHIP_REV_2_1		0x21
#define MX3x_CHIP_REV_2_2		0x22
#define MX3x_CHIP_REV_2_3		0x23
#define MX3x_CHIP_REV_3_0		0x30
#define MX3x_CHIP_REV_3_1		0x31
#define MX3x_CHIP_REV_3_2		0x32

#define MX3x_SYSTEM_REV_MIN		MX3x_CHIP_REV_1_0
#define MX3x_SYSTEM_REV_NUM		3

/* Mandatory defines used globally */

#if !defined(__ASSEMBLY__) && !defined(__MXC_BOOT_UNCOMPRESS)

extern unsigned int system_rev;

static inline int mx31_revision(void)
{
	return system_rev;
}
#endif

/* these should go away */
#define L2CC_BASE_ADDR MX3x_L2CC_BASE_ADDR
#define L2CC_SIZE MX3x_L2CC_SIZE
#define AIPS1_BASE_ADDR MX3x_AIPS1_BASE_ADDR
#define AIPS1_BASE_ADDR_VIRT MX3x_AIPS1_BASE_ADDR_VIRT
#define AIPS1_SIZE MX3x_AIPS1_SIZE
#define MAX_BASE_ADDR MX3x_MAX_BASE_ADDR
#define EVTMON_BASE_ADDR MX3x_EVTMON_BASE_ADDR
#define CLKCTL_BASE_ADDR MX3x_CLKCTL_BASE_ADDR
#define ETB_SLOT4_BASE_ADDR MX3x_ETB_SLOT4_BASE_ADDR
#define ETB_SLOT5_BASE_ADDR MX3x_ETB_SLOT5_BASE_ADDR
#define ECT_CTIO_BASE_ADDR MX3x_ECT_CTIO_BASE_ADDR
#define I2C_BASE_ADDR MX3x_I2C_BASE_ADDR
#define I2C3_BASE_ADDR MX3x_I2C3_BASE_ADDR
#define UART1_BASE_ADDR MX3x_UART1_BASE_ADDR
#define UART2_BASE_ADDR MX3x_UART2_BASE_ADDR
#define I2C2_BASE_ADDR MX3x_I2C2_BASE_ADDR
#define OWIRE_BASE_ADDR MX3x_OWIRE_BASE_ADDR
#define SSI1_BASE_ADDR MX3x_SSI1_BASE_ADDR
#define CSPI1_BASE_ADDR MX3x_CSPI1_BASE_ADDR
#define KPP_BASE_ADDR MX3x_KPP_BASE_ADDR
#define IOMUXC_BASE_ADDR MX3x_IOMUXC_BASE_ADDR
#define ECT_IP1_BASE_ADDR MX3x_ECT_IP1_BASE_ADDR
#define ECT_IP2_BASE_ADDR MX3x_ECT_IP2_BASE_ADDR
#define SPBA0_BASE_ADDR MX3x_SPBA0_BASE_ADDR
#define SPBA0_BASE_ADDR_VIRT MX3x_SPBA0_BASE_ADDR_VIRT
#define SPBA0_SIZE MX3x_SPBA0_SIZE
#define UART3_BASE_ADDR MX3x_UART3_BASE_ADDR
#define CSPI2_BASE_ADDR MX3x_CSPI2_BASE_ADDR
#define SSI2_BASE_ADDR MX3x_SSI2_BASE_ADDR
#define ATA_DMA_BASE_ADDR MX3x_ATA_DMA_BASE_ADDR
#define MSHC1_BASE_ADDR MX3x_MSHC1_BASE_ADDR
#define SPBA_CTRL_BASE_ADDR MX3x_SPBA_CTRL_BASE_ADDR
#define AIPS2_BASE_ADDR MX3x_AIPS2_BASE_ADDR
#define AIPS2_BASE_ADDR_VIRT MX3x_AIPS2_BASE_ADDR_VIRT
#define AIPS2_SIZE MX3x_AIPS2_SIZE
#define CCM_BASE_ADDR MX3x_CCM_BASE_ADDR
#define GPT1_BASE_ADDR MX3x_GPT1_BASE_ADDR
#define EPIT1_BASE_ADDR MX3x_EPIT1_BASE_ADDR
#define EPIT2_BASE_ADDR MX3x_EPIT2_BASE_ADDR
#define GPIO3_BASE_ADDR MX3x_GPIO3_BASE_ADDR
#define SCC_BASE_ADDR MX3x_SCC_BASE_ADDR
#define RNGA_BASE_ADDR MX3x_RNGA_BASE_ADDR
#define IPU_CTRL_BASE_ADDR MX3x_IPU_CTRL_BASE_ADDR
#define AUDMUX_BASE_ADDR MX3x_AUDMUX_BASE_ADDR
#define GPIO1_BASE_ADDR MX3x_GPIO1_BASE_ADDR
#define GPIO2_BASE_ADDR MX3x_GPIO2_BASE_ADDR
#define SDMA_BASE_ADDR MX3x_SDMA_BASE_ADDR
#define RTC_BASE_ADDR MX3x_RTC_BASE_ADDR
#define WDOG_BASE_ADDR MX3x_WDOG_BASE_ADDR
#define PWM_BASE_ADDR MX3x_PWM_BASE_ADDR
#define RTIC_BASE_ADDR MX3x_RTIC_BASE_ADDR
#define ROMP_BASE_ADDR MX3x_ROMP_BASE_ADDR
#define ROMP_BASE_ADDR_VIRT MX3x_ROMP_BASE_ADDR_VIRT
#define ROMP_SIZE MX3x_ROMP_SIZE
#define AVIC_BASE_ADDR MX3x_AVIC_BASE_ADDR
#define AVIC_BASE_ADDR_VIRT MX3x_AVIC_BASE_ADDR_VIRT
#define AVIC_SIZE MX3x_AVIC_SIZE
#define IPU_MEM_BASE_ADDR MX3x_IPU_MEM_BASE_ADDR
#define CSD0_BASE_ADDR MX3x_CSD0_BASE_ADDR
#define CSD1_BASE_ADDR MX3x_CSD1_BASE_ADDR
#define CS0_BASE_ADDR MX3x_CS0_BASE_ADDR
#define CS1_BASE_ADDR MX3x_CS1_BASE_ADDR
#define CS2_BASE_ADDR MX3x_CS2_BASE_ADDR
#define CS3_BASE_ADDR MX3x_CS3_BASE_ADDR
#define CS4_BASE_ADDR MX3x_CS4_BASE_ADDR
#define CS4_BASE_ADDR_VIRT MX3x_CS4_BASE_ADDR_VIRT
#define CS4_SIZE MX3x_CS4_SIZE
#define CS5_BASE_ADDR MX3x_CS5_BASE_ADDR
#define CS5_BASE_ADDR_VIRT MX3x_CS5_BASE_ADDR_VIRT
#define CS5_SIZE MX3x_CS5_SIZE
#define X_MEMC_BASE_ADDR MX3x_X_MEMC_BASE_ADDR
#define X_MEMC_BASE_ADDR_VIRT MX3x_X_MEMC_BASE_ADDR_VIRT
#define X_MEMC_SIZE MX3x_X_MEMC_SIZE
#define ESDCTL_BASE_ADDR MX3x_ESDCTL_BASE_ADDR
#define WEIM_BASE_ADDR MX3x_WEIM_BASE_ADDR
#define M3IF_BASE_ADDR MX3x_M3IF_BASE_ADDR
#define EMI_CTL_BASE_ADDR MX3x_EMI_CTL_BASE_ADDR
#define PCMCIA_CTL_BASE_ADDR MX3x_PCMCIA_CTL_BASE_ADDR
#define PCMCIA_MEM_BASE_ADDR MX3x_PCMCIA_MEM_BASE_ADDR
#define MXC_INT_I2C3 MX3x_INT_I2C3
#define MXC_INT_I2C2 MX3x_INT_I2C2
#define MXC_INT_RTIC MX3x_INT_RTIC
#define MXC_INT_I2C MX3x_INT_I2C
#define MXC_INT_CSPI2 MX3x_INT_CSPI2
#define MXC_INT_CSPI1 MX3x_INT_CSPI1
#define MXC_INT_ATA MX3x_INT_ATA
#define MXC_INT_UART3 MX3x_INT_UART3
#define MXC_INT_IIM MX3x_INT_IIM
#define MXC_INT_RNGA MX3x_INT_RNGA
#define MXC_INT_EVTMON MX3x_INT_EVTMON
#define MXC_INT_KPP MX3x_INT_KPP
#define MXC_INT_RTC MX3x_INT_RTC
#define MXC_INT_PWM MX3x_INT_PWM
#define MXC_INT_EPIT2 MX3x_INT_EPIT2
#define MXC_INT_EPIT1 MX3x_INT_EPIT1
#define MXC_INT_GPT MX3x_INT_GPT
#define MXC_INT_POWER_FAIL MX3x_INT_POWER_FAIL
#define MXC_INT_UART2 MX3x_INT_UART2
#define MXC_INT_NANDFC MX3x_INT_NANDFC
#define MXC_INT_SDMA MX3x_INT_SDMA
#define MXC_INT_MSHC1 MX3x_INT_MSHC1
#define MXC_INT_IPU_ERR MX3x_INT_IPU_ERR
#define MXC_INT_IPU_SYN MX3x_INT_IPU_SYN
#define MXC_INT_UART1 MX3x_INT_UART1
#define MXC_INT_ECT MX3x_INT_ECT
#define MXC_INT_SCC_SCM MX3x_INT_SCC_SCM
#define MXC_INT_SCC_SMN MX3x_INT_SCC_SMN
#define MXC_INT_GPIO2 MX3x_INT_GPIO2
#define MXC_INT_GPIO1 MX3x_INT_GPIO1
#define MXC_INT_WDOG MX3x_INT_WDOG
#define MXC_INT_GPIO3 MX3x_INT_GPIO3
#define MXC_INT_EXT_POWER MX3x_INT_EXT_POWER
#define MXC_INT_EXT_TEMPER MX3x_INT_EXT_TEMPER
#define MXC_INT_EXT_SENSOR60 MX3x_INT_EXT_SENSOR60
#define MXC_INT_EXT_SENSOR61 MX3x_INT_EXT_SENSOR61
#define MXC_INT_EXT_WDOG MX3x_INT_EXT_WDOG
#define MXC_INT_EXT_TV MX3x_INT_EXT_TV
#define PROD_SIGNATURE MX3x_PROD_SIGNATURE
#define CHIP_REV_1_0 MX3x_CHIP_REV_1_0
#define CHIP_REV_1_1 MX3x_CHIP_REV_1_1
#define CHIP_REV_1_2 MX3x_CHIP_REV_1_2
#define CHIP_REV_1_3 MX3x_CHIP_REV_1_3
#define CHIP_REV_2_0 MX3x_CHIP_REV_2_0
#define CHIP_REV_2_1 MX3x_CHIP_REV_2_1
#define CHIP_REV_2_2 MX3x_CHIP_REV_2_2
#define CHIP_REV_2_3 MX3x_CHIP_REV_2_3
#define CHIP_REV_3_0 MX3x_CHIP_REV_3_0
#define CHIP_REV_3_1 MX3x_CHIP_REV_3_1
#define CHIP_REV_3_2 MX3x_CHIP_REV_3_2
#define SYSTEM_REV_MIN MX3x_SYSTEM_REV_MIN
#define SYSTEM_REV_NUM MX3x_SYSTEM_REV_NUM

#endif /*  __ASM_ARCH_MXC_MX31_H__ */
Commit	Line	Data
c0a5f855 SH	1	/*
	2	* Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
	3	*/
	4
	5	/*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License version 2 as
	8	* published by the Free Software Foundation.
	9	*/
	10
	11	#ifndef __ASM_ARCH_MXC_MX31_H__
	12	#define __ASM_ARCH_MXC_MX31_H__
	13
c0a5f855 SH	14	/*
	15	* MX31 memory map:
	16	*
	17	* Virt Phys Size What
	18	* ---------------------------------------------------------------------------
	19	* FC000000 43F00000 1M AIPS 1
	20	* FC100000 50000000 1M SPBA
	21	* FC200000 53F00000 1M AIPS 2
	22	* FC500000 60000000 128M ROMPATCH
	23	* FC400000 68000000 128M AVIC
	24	* 70000000 256M IPU (MAX M2)
	25	* 80000000 256M CSD0 SDRAM/DDR
	26	* 90000000 256M CSD1 SDRAM/DDR
	27	* A0000000 128M CS0 Flash
	28	* A8000000 128M CS1 Flash
	29	* B0000000 32M CS2
	30	* B2000000 32M CS3
	31	* F4000000 B4000000 32M CS4
	32	* B6000000 32M CS5
	33	* FC320000 B8000000 64K NAND, SDRAM, WEIM, M3IF, EMI controllers
	34	* C0000000 64M PCMCIA/CF
	35	*/
	36
c0a5f855 SH	37	/*
	38	* L2CC
	39	*/
e4d0f7c7 UKK	40	#define MX3x_L2CC_BASE_ADDR 0x30000000
e4d0f7c7 UKK	41	#define MX3x_L2CC_SIZE SZ_1M
c0a5f855 SH	42
	43	/*
	44	* AIPS 1
	45	*/
e4d0f7c7 UKK	46	#define MX3x_AIPS1_BASE_ADDR 0x43f00000
	47	#define MX3x_AIPS1_BASE_ADDR_VIRT 0xfc000000
	48	#define MX3x_AIPS1_SIZE SZ_1M
	49	#define MX3x_MAX_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x04000)
	50	#define MX3x_EVTMON_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x08000)
	51	#define MX3x_CLKCTL_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x0c000)
	52	#define MX3x_ETB_SLOT4_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x10000)
	53	#define MX3x_ETB_SLOT5_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x14000)
	54	#define MX3x_ECT_CTIO_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x18000)
	55	#define MX3x_I2C_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x80000)
	56	#define MX3x_I2C3_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x84000)
	57	#define MX3x_UART1_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x90000)
	58	#define MX3x_UART2_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x94000)
	59	#define MX3x_I2C2_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x98000)
	60	#define MX3x_OWIRE_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x9c000)
	61	#define MX3x_SSI1_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0xa0000)
	62	#define MX3x_CSPI1_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0xa4000)
	63	#define MX3x_KPP_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0xa8000)
	64	#define MX3x_IOMUXC_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0xac000)
	65	#define MX3x_ECT_IP1_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0xb8000)
	66	#define MX3x_ECT_IP2_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0xbc000)
c0a5f855 SH	67
	68	/*
	69	* SPBA global module enabled #0
	70	*/
e4d0f7c7 UKK	71	#define MX3x_SPBA0_BASE_ADDR 0x50000000
	72	#define MX3x_SPBA0_BASE_ADDR_VIRT 0xfc100000
	73	#define MX3x_SPBA0_SIZE SZ_1M
	74	#define MX3x_UART3_BASE_ADDR (MX3x_SPBA0_BASE_ADDR + 0x0c000)
	75	#define MX3x_CSPI2_BASE_ADDR (MX3x_SPBA0_BASE_ADDR + 0x10000)
	76	#define MX3x_SSI2_BASE_ADDR (MX3x_SPBA0_BASE_ADDR + 0x14000)
	77	#define MX3x_ATA_DMA_BASE_ADDR (MX3x_SPBA0_BASE_ADDR + 0x20000)
	78	#define MX3x_MSHC1_BASE_ADDR (MX3x_SPBA0_BASE_ADDR + 0x24000)
	79	#define MX3x_SPBA_CTRL_BASE_ADDR (MX3x_SPBA0_BASE_ADDR + 0x3c000)
c0a5f855 SH	80
	81	/*
	82	* AIPS 2
	83	*/
e4d0f7c7 UKK	84	#define MX3x_AIPS2_BASE_ADDR 0x53f00000
	85	#define MX3x_AIPS2_BASE_ADDR_VIRT 0xfc200000
	86	#define MX3x_AIPS2_SIZE SZ_1M
	87	#define MX3x_CCM_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0x80000)
	88	#define MX3x_GPT1_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0x90000)
	89	#define MX3x_EPIT1_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0x94000)
	90	#define MX3x_EPIT2_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0x98000)
	91	#define MX3x_GPIO3_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0xa4000)
	92	#define MX3x_SCC_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0xac000)
	93	#define MX3x_RNGA_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0xb0000)
	94	#define MX3x_IPU_CTRL_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0xc0000)
	95	#define MX3x_AUDMUX_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0xc4000)
	96	#define MX3x_GPIO1_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0xcc000)
	97	#define MX3x_GPIO2_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0xd0000)
	98	#define MX3x_SDMA_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0xd4000)
	99	#define MX3x_RTC_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0xd8000)
	100	#define MX3x_WDOG_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0xdc000)
	101	#define MX3x_PWM_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0xe0000)
	102	#define MX3x_RTIC_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0xec000)
c0a5f855 SH	103
	104	/*
	105	* ROMP and AVIC
	106	*/
e4d0f7c7 UKK	107	#define MX3x_ROMP_BASE_ADDR 0x60000000
	108	#define MX3x_ROMP_BASE_ADDR_VIRT 0xfc500000
	109	#define MX3x_ROMP_SIZE SZ_1M
c0a5f855	110
e4d0f7c7 UKK	111	#define MX3x_AVIC_BASE_ADDR 0x68000000
	112	#define MX3x_AVIC_BASE_ADDR_VIRT 0xfc400000
	113	#define MX3x_AVIC_SIZE SZ_1M
c0a5f855	114
e676756f UKK	115	/*
	116	* Memory regions and CS
	117	*/
e4d0f7c7 UKK	118	#define MX3x_IPU_MEM_BASE_ADDR 0x70000000
	119	#define MX3x_CSD0_BASE_ADDR 0x80000000
	120	#define MX3x_CSD1_BASE_ADDR 0x90000000
e676756f	121
e4d0f7c7 UKK	122	#define MX3x_CS0_BASE_ADDR 0xa0000000
	123	#define MX3x_CS1_BASE_ADDR 0xa8000000
	124	#define MX3x_CS2_BASE_ADDR 0xb0000000
	125	#define MX3x_CS3_BASE_ADDR 0xb2000000
e676756f	126
e4d0f7c7 UKK	127	#define MX3x_CS4_BASE_ADDR 0xb4000000
	128	#define MX3x_CS4_BASE_ADDR_VIRT 0xf4000000
	129	#define MX3x_CS4_SIZE SZ_32M
e676756f	130
e4d0f7c7 UKK	131	#define MX3x_CS5_BASE_ADDR 0xb6000000
	132	#define MX3x_CS5_BASE_ADDR_VIRT 0xf6000000
	133	#define MX3x_CS5_SIZE SZ_32M
e676756f	134
c0a5f855 SH	135	/*
	136	* NAND, SDRAM, WEIM, M3IF, EMI controllers
	137	*/
e4d0f7c7 UKK	138	#define MX3x_X_MEMC_BASE_ADDR 0xb8000000
	139	#define MX3x_X_MEMC_BASE_ADDR_VIRT 0xfc320000
	140	#define MX3x_X_MEMC_SIZE SZ_64K
	141	#define MX3x_ESDCTL_BASE_ADDR (MX3x_X_MEMC_BASE_ADDR + 0x1000)
	142	#define MX3x_WEIM_BASE_ADDR (MX3x_X_MEMC_BASE_ADDR + 0x2000)
	143	#define MX3x_M3IF_BASE_ADDR (MX3x_X_MEMC_BASE_ADDR + 0x3000)
	144	#define MX3x_EMI_CTL_BASE_ADDR (MX3x_X_MEMC_BASE_ADDR + 0x4000)
	145	#define MX3x_PCMCIA_CTL_BASE_ADDR MX3x_EMI_CTL_BASE_ADDR
c0a5f855	146
e4d0f7c7	147	#define MX3x_PCMCIA_MEM_BASE_ADDR 0xbc000000
c0a5f855 SH	148
	149	/*!
	150	* This macro defines the physical to virtual address mapping for all the
	151	* peripheral modules. It is used by passing in the physical address as x
	152	* and returning the virtual address. If the physical address is not mapped,
	153	* it returns 0xDEADBEEF
	154	*/
	155	#define IO_ADDRESS(x) \
cc83e409	156	(void __force __iomem *) \
c0a5f855 SH	157	(((x >= AIPS1_BASE_ADDR) && (x < (AIPS1_BASE_ADDR + AIPS1_SIZE))) ? AIPS1_IO_ADDRESS(x):\
	158	((x >= SPBA0_BASE_ADDR) && (x < (SPBA0_BASE_ADDR + SPBA0_SIZE))) ? SPBA0_IO_ADDRESS(x):\
	159	((x >= AIPS2_BASE_ADDR) && (x < (AIPS2_BASE_ADDR + AIPS2_SIZE))) ? AIPS2_IO_ADDRESS(x):\
	160	((x >= ROMP_BASE_ADDR) && (x < (ROMP_BASE_ADDR + ROMP_SIZE))) ? ROMP_IO_ADDRESS(x):\
	161	((x >= AVIC_BASE_ADDR) && (x < (AVIC_BASE_ADDR + AVIC_SIZE))) ? AVIC_IO_ADDRESS(x):\
	162	((x >= CS4_BASE_ADDR) && (x < (CS4_BASE_ADDR + CS4_SIZE))) ? CS4_IO_ADDRESS(x):\
	163	((x >= X_MEMC_BASE_ADDR) && (x < (X_MEMC_BASE_ADDR + X_MEMC_SIZE))) ? X_MEMC_IO_ADDRESS(x):\
	164	0xDEADBEEF)
	165
	166	/*
	167	* define the address mapping macros: in physical address order
	168	*/
	169	#define L2CC_IO_ADDRESS(x) \
	170	(((x) - L2CC_BASE_ADDR) + L2CC_BASE_ADDR_VIRT)
	171
	172	#define AIPS1_IO_ADDRESS(x) \
	173	(((x) - AIPS1_BASE_ADDR) + AIPS1_BASE_ADDR_VIRT)
	174
	175	#define SPBA0_IO_ADDRESS(x) \
	176	(((x) - SPBA0_BASE_ADDR) + SPBA0_BASE_ADDR_VIRT)
	177
	178	#define AIPS2_IO_ADDRESS(x) \
	179	(((x) - AIPS2_BASE_ADDR) + AIPS2_BASE_ADDR_VIRT)
	180
	181	#define ROMP_IO_ADDRESS(x) \
	182	(((x) - ROMP_BASE_ADDR) + ROMP_BASE_ADDR_VIRT)
	183
	184	#define AVIC_IO_ADDRESS(x) \
	185	(((x) - AVIC_BASE_ADDR) + AVIC_BASE_ADDR_VIRT)
	186
	187	#define CS4_IO_ADDRESS(x) \
	188	(((x) - CS4_BASE_ADDR) + CS4_BASE_ADDR_VIRT)
	189
135cad36 ML	190	#define CS5_IO_ADDRESS(x) \
	191	(((x) - CS5_BASE_ADDR) + CS5_BASE_ADDR_VIRT)
	192
c0a5f855 SH	193	#define X_MEMC_IO_ADDRESS(x) \
	194	(((x) - X_MEMC_BASE_ADDR) + X_MEMC_BASE_ADDR_VIRT)
	195
	196	#define PCMCIA_IO_ADDRESS(x) \
	197	(((x) - X_MEMC_BASE_ADDR) + X_MEMC_BASE_ADDR_VIRT)
	198
	199	/*
	200	* Interrupt numbers
	201	*/
e4d0f7c7 UKK	202	#define MX3x_INT_I2C3 3
	203	#define MX3x_INT_I2C2 4
	204	#define MX3x_INT_RTIC 6
	205	#define MX3x_INT_I2C 10
	206	#define MX3x_INT_CSPI2 13
	207	#define MX3x_INT_CSPI1 14
	208	#define MX3x_INT_ATA 15
	209	#define MX3x_INT_UART3 18
	210	#define MX3x_INT_IIM 19
	211	#define MX3x_INT_RNGA 22
	212	#define MX3x_INT_EVTMON 23
	213	#define MX3x_INT_KPP 24
	214	#define MX3x_INT_RTC 25
	215	#define MX3x_INT_PWM 26
	216	#define MX3x_INT_EPIT2 27
	217	#define MX3x_INT_EPIT1 28
	218	#define MX3x_INT_GPT 29
	219	#define MX3x_INT_POWER_FAIL 30
	220	#define MX3x_INT_UART2 32
	221	#define MX3x_INT_NANDFC 33
	222	#define MX3x_INT_SDMA 34
	223	#define MX3x_INT_MSHC1 39
	224	#define MX3x_INT_IPU_ERR 41
	225	#define MX3x_INT_IPU_SYN 42
	226	#define MX3x_INT_UART1 45
	227	#define MX3x_INT_ECT 48
	228	#define MX3x_INT_SCC_SCM 49
	229	#define MX3x_INT_SCC_SMN 50
	230	#define MX3x_INT_GPIO2 51
	231	#define MX3x_INT_GPIO1 52
	232	#define MX3x_INT_WDOG 55
	233	#define MX3x_INT_GPIO3 56
	234	#define MX3x_INT_EXT_POWER 58
	235	#define MX3x_INT_EXT_TEMPER 59
	236	#define MX3x_INT_EXT_SENSOR60 60
	237	#define MX3x_INT_EXT_SENSOR61 61
	238	#define MX3x_INT_EXT_WDOG 62
	239	#define MX3x_INT_EXT_TV 63
	240
	241	#define MX3x_PROD_SIGNATURE 0x1 /* For MX31 */
c0a5f855 SH	242
c0a5f855 SH	243	/* silicon revisions specific to i.MX31 */
e4d0f7c7 UKK	244	#define MX3x_CHIP_REV_1_0 0x10
	245	#define MX3x_CHIP_REV_1_1 0x11
	246	#define MX3x_CHIP_REV_1_2 0x12
	247	#define MX3x_CHIP_REV_1_3 0x13
	248	#define MX3x_CHIP_REV_2_0 0x20
	249	#define MX3x_CHIP_REV_2_1 0x21
	250	#define MX3x_CHIP_REV_2_2 0x22
	251	#define MX3x_CHIP_REV_2_3 0x23
	252	#define MX3x_CHIP_REV_3_0 0x30
	253	#define MX3x_CHIP_REV_3_1 0x31
	254	#define MX3x_CHIP_REV_3_2 0x32
	255
	256	#define MX3x_SYSTEM_REV_MIN MX3x_CHIP_REV_1_0
	257	#define MX3x_SYSTEM_REV_NUM 3
c0a5f855	258
c0a5f855 SH	259	/* Mandatory defines used globally */
c0a5f855 SH	260
c0a5f855 SH	261	#if !defined(__ASSEMBLY__) && !defined(__MXC_BOOT_UNCOMPRESS)
	262
	263	extern unsigned int system_rev;
	264
	265	static inline int mx31_revision(void)
	266	{
	267	return system_rev;
	268	}
	269	#endif
	270
e4d0f7c7 UKK	271	/* these should go away */
	272	#define L2CC_BASE_ADDR MX3x_L2CC_BASE_ADDR
	273	#define L2CC_SIZE MX3x_L2CC_SIZE
	274	#define AIPS1_BASE_ADDR MX3x_AIPS1_BASE_ADDR
	275	#define AIPS1_BASE_ADDR_VIRT MX3x_AIPS1_BASE_ADDR_VIRT
	276	#define AIPS1_SIZE MX3x_AIPS1_SIZE
	277	#define MAX_BASE_ADDR MX3x_MAX_BASE_ADDR
	278	#define EVTMON_BASE_ADDR MX3x_EVTMON_BASE_ADDR
	279	#define CLKCTL_BASE_ADDR MX3x_CLKCTL_BASE_ADDR
	280	#define ETB_SLOT4_BASE_ADDR MX3x_ETB_SLOT4_BASE_ADDR
	281	#define ETB_SLOT5_BASE_ADDR MX3x_ETB_SLOT5_BASE_ADDR
	282	#define ECT_CTIO_BASE_ADDR MX3x_ECT_CTIO_BASE_ADDR
	283	#define I2C_BASE_ADDR MX3x_I2C_BASE_ADDR
	284	#define I2C3_BASE_ADDR MX3x_I2C3_BASE_ADDR
	285	#define UART1_BASE_ADDR MX3x_UART1_BASE_ADDR
	286	#define UART2_BASE_ADDR MX3x_UART2_BASE_ADDR
	287	#define I2C2_BASE_ADDR MX3x_I2C2_BASE_ADDR
	288	#define OWIRE_BASE_ADDR MX3x_OWIRE_BASE_ADDR
	289	#define SSI1_BASE_ADDR MX3x_SSI1_BASE_ADDR
	290	#define CSPI1_BASE_ADDR MX3x_CSPI1_BASE_ADDR
	291	#define KPP_BASE_ADDR MX3x_KPP_BASE_ADDR
	292	#define IOMUXC_BASE_ADDR MX3x_IOMUXC_BASE_ADDR
	293	#define ECT_IP1_BASE_ADDR MX3x_ECT_IP1_BASE_ADDR
	294	#define ECT_IP2_BASE_ADDR MX3x_ECT_IP2_BASE_ADDR
	295	#define SPBA0_BASE_ADDR MX3x_SPBA0_BASE_ADDR
	296	#define SPBA0_BASE_ADDR_VIRT MX3x_SPBA0_BASE_ADDR_VIRT
	297	#define SPBA0_SIZE MX3x_SPBA0_SIZE
	298	#define UART3_BASE_ADDR MX3x_UART3_BASE_ADDR
	299	#define CSPI2_BASE_ADDR MX3x_CSPI2_BASE_ADDR
	300	#define SSI2_BASE_ADDR MX3x_SSI2_BASE_ADDR
	301	#define ATA_DMA_BASE_ADDR MX3x_ATA_DMA_BASE_ADDR
	302	#define MSHC1_BASE_ADDR MX3x_MSHC1_BASE_ADDR
	303	#define SPBA_CTRL_BASE_ADDR MX3x_SPBA_CTRL_BASE_ADDR
	304	#define AIPS2_BASE_ADDR MX3x_AIPS2_BASE_ADDR
	305	#define AIPS2_BASE_ADDR_VIRT MX3x_AIPS2_BASE_ADDR_VIRT
	306	#define AIPS2_SIZE MX3x_AIPS2_SIZE
	307	#define CCM_BASE_ADDR MX3x_CCM_BASE_ADDR
	308	#define GPT1_BASE_ADDR MX3x_GPT1_BASE_ADDR
	309	#define EPIT1_BASE_ADDR MX3x_EPIT1_BASE_ADDR
	310	#define EPIT2_BASE_ADDR MX3x_EPIT2_BASE_ADDR
	311	#define GPIO3_BASE_ADDR MX3x_GPIO3_BASE_ADDR
	312	#define SCC_BASE_ADDR MX3x_SCC_BASE_ADDR
	313	#define RNGA_BASE_ADDR MX3x_RNGA_BASE_ADDR
	314	#define IPU_CTRL_BASE_ADDR MX3x_IPU_CTRL_BASE_ADDR
	315	#define AUDMUX_BASE_ADDR MX3x_AUDMUX_BASE_ADDR
	316	#define GPIO1_BASE_ADDR MX3x_GPIO1_BASE_ADDR
	317	#define GPIO2_BASE_ADDR MX3x_GPIO2_BASE_ADDR
	318	#define SDMA_BASE_ADDR MX3x_SDMA_BASE_ADDR
	319	#define RTC_BASE_ADDR MX3x_RTC_BASE_ADDR
	320	#define WDOG_BASE_ADDR MX3x_WDOG_BASE_ADDR
	321	#define PWM_BASE_ADDR MX3x_PWM_BASE_ADDR
	322	#define RTIC_BASE_ADDR MX3x_RTIC_BASE_ADDR
	323	#define ROMP_BASE_ADDR MX3x_ROMP_BASE_ADDR
	324	#define ROMP_BASE_ADDR_VIRT MX3x_ROMP_BASE_ADDR_VIRT
	325	#define ROMP_SIZE MX3x_ROMP_SIZE
	326	#define AVIC_BASE_ADDR MX3x_AVIC_BASE_ADDR
	327	#define AVIC_BASE_ADDR_VIRT MX3x_AVIC_BASE_ADDR_VIRT
	328	#define AVIC_SIZE MX3x_AVIC_SIZE
	329	#define IPU_MEM_BASE_ADDR MX3x_IPU_MEM_BASE_ADDR
	330	#define CSD0_BASE_ADDR MX3x_CSD0_BASE_ADDR
	331	#define CSD1_BASE_ADDR MX3x_CSD1_BASE_ADDR
	332	#define CS0_BASE_ADDR MX3x_CS0_BASE_ADDR
	333	#define CS1_BASE_ADDR MX3x_CS1_BASE_ADDR
	334	#define CS2_BASE_ADDR MX3x_CS2_BASE_ADDR
335	#define CS3_BASE_ADDR MX3x_CS3_BASE_ADDR
336	#define CS4_BASE_ADDR MX3x_CS4_BASE_ADDR
337	#define CS4_BASE_ADDR_VIRT MX3x_CS4_BASE_ADDR_VIRT
338	#define CS4_SIZE MX3x_CS4_SIZE
339	#define CS5_BASE_ADDR MX3x_CS5_BASE_ADDR
340	#define CS5_BASE_ADDR_VIRT MX3x_CS5_BASE_ADDR_VIRT
341	#define CS5_SIZE MX3x_CS5_SIZE
342	#define X_MEMC_BASE_ADDR MX3x_X_MEMC_BASE_ADDR
343	#define X_MEMC_BASE_ADDR_VIRT MX3x_X_MEMC_BASE_ADDR_VIRT
344	#define X_MEMC_SIZE MX3x_X_MEMC_SIZE
345	#define ESDCTL_BASE_ADDR MX3x_ESDCTL_BASE_ADDR
346	#define WEIM_BASE_ADDR MX3x_WEIM_BASE_ADDR
347	#define M3IF_BASE_ADDR MX3x_M3IF_BASE_ADDR
348	#define EMI_CTL_BASE_ADDR MX3x_EMI_CTL_BASE_ADDR
349	#define PCMCIA_CTL_BASE_ADDR MX3x_PCMCIA_CTL_BASE_ADDR
350	#define PCMCIA_MEM_BASE_ADDR MX3x_PCMCIA_MEM_BASE_ADDR
351	#define MXC_INT_I2C3 MX3x_INT_I2C3
352	#define MXC_INT_I2C2 MX3x_INT_I2C2
353	#define MXC_INT_RTIC MX3x_INT_RTIC
354	#define MXC_INT_I2C MX3x_INT_I2C
355	#define MXC_INT_CSPI2 MX3x_INT_CSPI2
356	#define MXC_INT_CSPI1 MX3x_INT_CSPI1
357	#define MXC_INT_ATA MX3x_INT_ATA
358	#define MXC_INT_UART3 MX3x_INT_UART3
359	#define MXC_INT_IIM MX3x_INT_IIM
360	#define MXC_INT_RNGA MX3x_INT_RNGA
361	#define MXC_INT_EVTMON MX3x_INT_EVTMON
362	#define MXC_INT_KPP MX3x_INT_KPP
363	#define MXC_INT_RTC MX3x_INT_RTC
364	#define MXC_INT_PWM MX3x_INT_PWM
365	#define MXC_INT_EPIT2 MX3x_INT_EPIT2
366	#define MXC_INT_EPIT1 MX3x_INT_EPIT1
367	#define MXC_INT_GPT MX3x_INT_GPT
368	#define MXC_INT_POWER_FAIL MX3x_INT_POWER_FAIL
369	#define MXC_INT_UART2 MX3x_INT_UART2
370	#define MXC_INT_NANDFC MX3x_INT_NANDFC
371	#define MXC_INT_SDMA MX3x_INT_SDMA
372	#define MXC_INT_MSHC1 MX3x_INT_MSHC1
373	#define MXC_INT_IPU_ERR MX3x_INT_IPU_ERR
374	#define MXC_INT_IPU_SYN MX3x_INT_IPU_SYN
375	#define MXC_INT_UART1 MX3x_INT_UART1
376	#define MXC_INT_ECT MX3x_INT_ECT
377	#define MXC_INT_SCC_SCM MX3x_INT_SCC_SCM
378	#define MXC_INT_SCC_SMN MX3x_INT_SCC_SMN
379	#define MXC_INT_GPIO2 MX3x_INT_GPIO2
380	#define MXC_INT_GPIO1 MX3x_INT_GPIO1
381	#define MXC_INT_WDOG MX3x_INT_WDOG
382	#define MXC_INT_GPIO3 MX3x_INT_GPIO3
383	#define MXC_INT_EXT_POWER MX3x_INT_EXT_POWER
384	#define MXC_INT_EXT_TEMPER MX3x_INT_EXT_TEMPER
385	#define MXC_INT_EXT_SENSOR60 MX3x_INT_EXT_SENSOR60
386	#define MXC_INT_EXT_SENSOR61 MX3x_INT_EXT_SENSOR61
387	#define MXC_INT_EXT_WDOG MX3x_INT_EXT_WDOG
388	#define MXC_INT_EXT_TV MX3x_INT_EXT_TV
389	#define PROD_SIGNATURE MX3x_PROD_SIGNATURE
390	#define CHIP_REV_1_0 MX3x_CHIP_REV_1_0
391	#define CHIP_REV_1_1 MX3x_CHIP_REV_1_1
392	#define CHIP_REV_1_2 MX3x_CHIP_REV_1_2
393	#define CHIP_REV_1_3 MX3x_CHIP_REV_1_3
394	#define CHIP_REV_2_0 MX3x_CHIP_REV_2_0
395	#define CHIP_REV_2_1 MX3x_CHIP_REV_2_1
396	#define CHIP_REV_2_2 MX3x_CHIP_REV_2_2
397	#define CHIP_REV_2_3 MX3x_CHIP_REV_2_3
398	#define CHIP_REV_3_0 MX3x_CHIP_REV_3_0
399	#define CHIP_REV_3_1 MX3x_CHIP_REV_3_1
400	#define CHIP_REV_3_2 MX3x_CHIP_REV_3_2
401	#define SYSTEM_REV_MIN MX3x_SYSTEM_REV_MIN
402	#define SYSTEM_REV_NUM MX3x_SYSTEM_REV_NUM
403
c0a5f855	404	#endif /* __ASM_ARCH_MXC_MX31_H__ */