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cfca8b53 PZ |
1 | /* |
2 | * Copyright (C) 1997,1998 Russell King | |
3 | * Copyright (C) 1999 ARM Limited | |
4 | * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. | |
5 | * Copyright (c) 2008 Paulius Zaleckas <paulius.zaleckas@teltonika.lt> | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License version 2 as | |
9 | * published by the Free Software Foundation. | |
10 | */ | |
11 | ||
3cdd5441 UKK |
12 | #ifndef __MACH_MX1_H__ |
13 | #define __MACH_MX1_H__ | |
cfca8b53 | 14 | |
cfca8b53 PZ |
15 | #include <mach/vmalloc.h> |
16 | ||
cfca8b53 PZ |
17 | /* |
18 | * Memory map | |
19 | */ | |
7d58289f UKK |
20 | #define MX1_IO_BASE_ADDR 0x00200000 |
21 | #define MX1_IO_SIZE SZ_1M | |
22 | #define MX1_IO_BASE_ADDR_VIRT VMALLOC_END | |
cfca8b53 | 23 | |
7d58289f UKK |
24 | #define MX1_CS0_PHYS 0x10000000 |
25 | #define MX1_CS0_SIZE 0x02000000 | |
cfca8b53 | 26 | |
7d58289f UKK |
27 | #define MX1_CS1_PHYS 0x12000000 |
28 | #define MX1_CS1_SIZE 0x01000000 | |
cfca8b53 | 29 | |
7d58289f UKK |
30 | #define MX1_CS2_PHYS 0x13000000 |
31 | #define MX1_CS2_SIZE 0x01000000 | |
cfca8b53 | 32 | |
7d58289f UKK |
33 | #define MX1_CS3_PHYS 0x14000000 |
34 | #define MX1_CS3_SIZE 0x01000000 | |
cfca8b53 | 35 | |
7d58289f UKK |
36 | #define MX1_CS4_PHYS 0x15000000 |
37 | #define MX1_CS4_SIZE 0x01000000 | |
cfca8b53 | 38 | |
7d58289f UKK |
39 | #define MX1_CS5_PHYS 0x16000000 |
40 | #define MX1_CS5_SIZE 0x01000000 | |
cfca8b53 PZ |
41 | |
42 | /* | |
43 | * Register BASEs, based on OFFSETs | |
44 | */ | |
7d58289f UKK |
45 | #define MX1_AIPI1_BASE_ADDR (0x00000 + MX1_IO_BASE_ADDR) |
46 | #define MX1_WDT_BASE_ADDR (0x01000 + MX1_IO_BASE_ADDR) | |
47 | #define MX1_TIM1_BASE_ADDR (0x02000 + MX1_IO_BASE_ADDR) | |
48 | #define MX1_TIM2_BASE_ADDR (0x03000 + MX1_IO_BASE_ADDR) | |
49 | #define MX1_RTC_BASE_ADDR (0x04000 + MX1_IO_BASE_ADDR) | |
50 | #define MX1_LCDC_BASE_ADDR (0x05000 + MX1_IO_BASE_ADDR) | |
51 | #define MX1_UART1_BASE_ADDR (0x06000 + MX1_IO_BASE_ADDR) | |
52 | #define MX1_UART2_BASE_ADDR (0x07000 + MX1_IO_BASE_ADDR) | |
53 | #define MX1_PWM_BASE_ADDR (0x08000 + MX1_IO_BASE_ADDR) | |
54 | #define MX1_DMA_BASE_ADDR (0x09000 + MX1_IO_BASE_ADDR) | |
55 | #define MX1_AIPI2_BASE_ADDR (0x10000 + MX1_IO_BASE_ADDR) | |
56 | #define MX1_SIM_BASE_ADDR (0x11000 + MX1_IO_BASE_ADDR) | |
57 | #define MX1_USBD_BASE_ADDR (0x12000 + MX1_IO_BASE_ADDR) | |
58 | #define MX1_SPI1_BASE_ADDR (0x13000 + MX1_IO_BASE_ADDR) | |
59 | #define MX1_MMC_BASE_ADDR (0x14000 + MX1_IO_BASE_ADDR) | |
60 | #define MX1_ASP_BASE_ADDR (0x15000 + MX1_IO_BASE_ADDR) | |
61 | #define MX1_BTA_BASE_ADDR (0x16000 + MX1_IO_BASE_ADDR) | |
62 | #define MX1_I2C_BASE_ADDR (0x17000 + MX1_IO_BASE_ADDR) | |
63 | #define MX1_SSI_BASE_ADDR (0x18000 + MX1_IO_BASE_ADDR) | |
64 | #define MX1_SPI2_BASE_ADDR (0x19000 + MX1_IO_BASE_ADDR) | |
65 | #define MX1_MSHC_BASE_ADDR (0x1A000 + MX1_IO_BASE_ADDR) | |
66 | #define MX1_CCM_BASE_ADDR (0x1B000 + MX1_IO_BASE_ADDR) | |
67 | #define MX1_SCM_BASE_ADDR (0x1B804 + MX1_IO_BASE_ADDR) | |
68 | #define MX1_GPIO_BASE_ADDR (0x1C000 + MX1_IO_BASE_ADDR) | |
69 | #define MX1_EIM_BASE_ADDR (0x20000 + MX1_IO_BASE_ADDR) | |
70 | #define MX1_SDRAMC_BASE_ADDR (0x21000 + MX1_IO_BASE_ADDR) | |
71 | #define MX1_MMA_BASE_ADDR (0x22000 + MX1_IO_BASE_ADDR) | |
72 | #define MX1_AVIC_BASE_ADDR (0x23000 + MX1_IO_BASE_ADDR) | |
73 | #define MX1_CSI_BASE_ADDR (0x24000 + MX1_IO_BASE_ADDR) | |
cfca8b53 PZ |
74 | |
75 | /* macro to get at IO space when running virtually */ | |
7d58289f UKK |
76 | #define MX1_IO_ADDRESS(x) ( \ |
77 | IMX_IO_ADDRESS(x, MX1_IO)) | |
cfca8b53 PZ |
78 | |
79 | /* fixed interrput numbers */ | |
7d58289f UKK |
80 | #define MX1_INT_SOFTINT 0 |
81 | #define MX1_CSI_INT 6 | |
82 | #define MX1_DSPA_MAC_INT 7 | |
83 | #define MX1_DSPA_INT 8 | |
84 | #define MX1_COMP_INT 9 | |
85 | #define MX1_MSHC_XINT 10 | |
86 | #define MX1_GPIO_INT_PORTA 11 | |
87 | #define MX1_GPIO_INT_PORTB 12 | |
88 | #define MX1_GPIO_INT_PORTC 13 | |
89 | #define MX1_LCDC_INT 14 | |
90 | #define MX1_SIM_INT 15 | |
91 | #define MX1_SIM_DATA_INT 16 | |
92 | #define MX1_RTC_INT 17 | |
93 | #define MX1_RTC_SAMINT 18 | |
94 | #define MX1_UART2_MINT_PFERR 19 | |
95 | #define MX1_UART2_MINT_RTS 20 | |
96 | #define MX1_UART2_MINT_DTR 21 | |
97 | #define MX1_UART2_MINT_UARTC 22 | |
98 | #define MX1_UART2_MINT_TX 23 | |
99 | #define MX1_UART2_MINT_RX 24 | |
100 | #define MX1_UART1_MINT_PFERR 25 | |
101 | #define MX1_UART1_MINT_RTS 26 | |
102 | #define MX1_UART1_MINT_DTR 27 | |
103 | #define MX1_UART1_MINT_UARTC 28 | |
104 | #define MX1_UART1_MINT_TX 29 | |
105 | #define MX1_UART1_MINT_RX 30 | |
106 | #define MX1_VOICE_DAC_INT 31 | |
107 | #define MX1_VOICE_ADC_INT 32 | |
108 | #define MX1_PEN_DATA_INT 33 | |
109 | #define MX1_PWM_INT 34 | |
110 | #define MX1_SDHC_INT 35 | |
111 | #define MX1_I2C_INT 39 | |
112 | #define MX1_CSPI_INT 41 | |
113 | #define MX1_SSI_TX_INT 42 | |
114 | #define MX1_SSI_TX_ERR_INT 43 | |
115 | #define MX1_SSI_RX_INT 44 | |
116 | #define MX1_SSI_RX_ERR_INT 45 | |
117 | #define MX1_TOUCH_INT 46 | |
118 | #define MX1_USBD_INT0 47 | |
119 | #define MX1_USBD_INT1 48 | |
120 | #define MX1_USBD_INT2 49 | |
121 | #define MX1_USBD_INT3 50 | |
122 | #define MX1_USBD_INT4 51 | |
123 | #define MX1_USBD_INT5 52 | |
124 | #define MX1_USBD_INT6 53 | |
125 | #define MX1_BTSYS_INT 55 | |
126 | #define MX1_BTTIM_INT 56 | |
127 | #define MX1_BTWUI_INT 57 | |
128 | #define MX1_TIM2_INT 58 | |
129 | #define MX1_TIM1_INT 59 | |
130 | #define MX1_DMA_ERR 60 | |
131 | #define MX1_DMA_INT 61 | |
132 | #define MX1_GPIO_INT_PORTD 62 | |
133 | #define MX1_WDT_INT 63 | |
cfca8b53 | 134 | |
cfca8b53 | 135 | /* DMA */ |
7d58289f UKK |
136 | #define MX1_DMA_REQ_UART3_T 2 |
137 | #define MX1_DMA_REQ_UART3_R 3 | |
138 | #define MX1_DMA_REQ_SSI2_T 4 | |
139 | #define MX1_DMA_REQ_SSI2_R 5 | |
140 | #define MX1_DMA_REQ_CSI_STAT 6 | |
141 | #define MX1_DMA_REQ_CSI_R 7 | |
142 | #define MX1_DMA_REQ_MSHC 8 | |
143 | #define MX1_DMA_REQ_DSPA_DCT_DOUT 9 | |
144 | #define MX1_DMA_REQ_DSPA_DCT_DIN 10 | |
145 | #define MX1_DMA_REQ_DSPA_MAC 11 | |
146 | #define MX1_DMA_REQ_EXT 12 | |
147 | #define MX1_DMA_REQ_SDHC 13 | |
148 | #define MX1_DMA_REQ_SPI1_R 14 | |
149 | #define MX1_DMA_REQ_SPI1_T 15 | |
150 | #define MX1_DMA_REQ_SSI_T 16 | |
151 | #define MX1_DMA_REQ_SSI_R 17 | |
152 | #define MX1_DMA_REQ_ASP_DAC 18 | |
153 | #define MX1_DMA_REQ_ASP_ADC 19 | |
154 | #define MX1_DMA_REQ_USP_EP(x) (20 + (x)) | |
155 | #define MX1_DMA_REQ_SPI2_R 26 | |
156 | #define MX1_DMA_REQ_SPI2_T 27 | |
157 | #define MX1_DMA_REQ_UART2_T 28 | |
158 | #define MX1_DMA_REQ_UART2_R 29 | |
159 | #define MX1_DMA_REQ_UART1_T 30 | |
160 | #define MX1_DMA_REQ_UART1_R 31 | |
161 | ||
162 | /* | |
163 | * This doesn't depend on IMX_NEEDS_DEPRECATED_SYMBOLS | |
164 | * to not break drivers/usb/gadget/imx_udc. Should go | |
165 | * away after this driver uses the new name. | |
166 | */ | |
167 | #define USBD_INT0 MX1_USBD_INT0 | |
168 | ||
169 | #ifdef IMX_NEEDS_DEPRECATED_SYMBOLS | |
170 | /* these should go away */ | |
171 | #define IMX_IO_PHYS MX1_IO_BASE_ADDR | |
172 | #define IMX_IO_SIZE MX1_IO_SIZE | |
173 | #define IMX_IO_BASE MX1_IO_BASE_ADDR_VIRT | |
174 | #define IMX_CS0_PHYS MX1_CS0_PHYS | |
175 | #define IMX_CS0_SIZE MX1_CS0_SIZE | |
176 | #define IMX_CS1_PHYS MX1_CS1_PHYS | |
177 | #define IMX_CS1_SIZE MX1_CS1_SIZE | |
178 | #define IMX_CS2_PHYS MX1_CS2_PHYS | |
179 | #define IMX_CS2_SIZE MX1_CS2_SIZE | |
180 | #define IMX_CS3_PHYS MX1_CS3_PHYS | |
181 | #define IMX_CS3_SIZE MX1_CS3_SIZE | |
182 | #define IMX_CS4_PHYS MX1_CS4_PHYS | |
183 | #define IMX_CS4_SIZE MX1_CS4_SIZE | |
184 | #define IMX_CS5_PHYS MX1_CS5_PHYS | |
185 | #define IMX_CS5_SIZE MX1_CS5_SIZE | |
186 | #define AIPI1_BASE_ADDR MX1_AIPI1_BASE_ADDR | |
187 | #define WDT_BASE_ADDR MX1_WDT_BASE_ADDR | |
188 | #define TIM1_BASE_ADDR MX1_TIM1_BASE_ADDR | |
189 | #define TIM2_BASE_ADDR MX1_TIM2_BASE_ADDR | |
190 | #define RTC_BASE_ADDR MX1_RTC_BASE_ADDR | |
191 | #define LCDC_BASE_ADDR MX1_LCDC_BASE_ADDR | |
192 | #define UART1_BASE_ADDR MX1_UART1_BASE_ADDR | |
193 | #define UART2_BASE_ADDR MX1_UART2_BASE_ADDR | |
194 | #define PWM_BASE_ADDR MX1_PWM_BASE_ADDR | |
195 | #define DMA_BASE_ADDR MX1_DMA_BASE_ADDR | |
196 | #define AIPI2_BASE_ADDR MX1_AIPI2_BASE_ADDR | |
197 | #define SIM_BASE_ADDR MX1_SIM_BASE_ADDR | |
198 | #define USBD_BASE_ADDR MX1_USBD_BASE_ADDR | |
199 | #define SPI1_BASE_ADDR MX1_SPI1_BASE_ADDR | |
200 | #define MMC_BASE_ADDR MX1_MMC_BASE_ADDR | |
201 | #define ASP_BASE_ADDR MX1_ASP_BASE_ADDR | |
202 | #define BTA_BASE_ADDR MX1_BTA_BASE_ADDR | |
203 | #define I2C_BASE_ADDR MX1_I2C_BASE_ADDR | |
204 | #define SSI_BASE_ADDR MX1_SSI_BASE_ADDR | |
205 | #define SPI2_BASE_ADDR MX1_SPI2_BASE_ADDR | |
206 | #define MSHC_BASE_ADDR MX1_MSHC_BASE_ADDR | |
207 | #define CCM_BASE_ADDR MX1_CCM_BASE_ADDR | |
208 | #define SCM_BASE_ADDR MX1_SCM_BASE_ADDR | |
209 | #define GPIO_BASE_ADDR MX1_GPIO_BASE_ADDR | |
210 | #define EIM_BASE_ADDR MX1_EIM_BASE_ADDR | |
211 | #define SDRAMC_BASE_ADDR MX1_SDRAMC_BASE_ADDR | |
212 | #define MMA_BASE_ADDR MX1_MMA_BASE_ADDR | |
213 | #define AVIC_BASE_ADDR MX1_AVIC_BASE_ADDR | |
214 | #define CSI_BASE_ADDR MX1_CSI_BASE_ADDR | |
215 | #define IO_ADDRESS(x) MX1_IO_ADDRESS(x) | |
216 | #define AVIC_IO_ADDRESS(x) IO_ADDRESS(x) | |
217 | #define INT_SOFTINT MX1_INT_SOFTINT | |
218 | #define CSI_INT MX1_CSI_INT | |
219 | #define DSPA_MAC_INT MX1_DSPA_MAC_INT | |
220 | #define DSPA_INT MX1_DSPA_INT | |
221 | #define COMP_INT MX1_COMP_INT | |
222 | #define MSHC_XINT MX1_MSHC_XINT | |
223 | #define GPIO_INT_PORTA MX1_GPIO_INT_PORTA | |
224 | #define GPIO_INT_PORTB MX1_GPIO_INT_PORTB | |
225 | #define GPIO_INT_PORTC MX1_GPIO_INT_PORTC | |
226 | #define LCDC_INT MX1_LCDC_INT | |
227 | #define SIM_INT MX1_SIM_INT | |
228 | #define SIM_DATA_INT MX1_SIM_DATA_INT | |
229 | #define RTC_INT MX1_RTC_INT | |
230 | #define RTC_SAMINT MX1_RTC_SAMINT | |
231 | #define UART2_MINT_PFERR MX1_UART2_MINT_PFERR | |
232 | #define UART2_MINT_RTS MX1_UART2_MINT_RTS | |
233 | #define UART2_MINT_DTR MX1_UART2_MINT_DTR | |
234 | #define UART2_MINT_UARTC MX1_UART2_MINT_UARTC | |
235 | #define UART2_MINT_TX MX1_UART2_MINT_TX | |
236 | #define UART2_MINT_RX MX1_UART2_MINT_RX | |
237 | #define UART1_MINT_PFERR MX1_UART1_MINT_PFERR | |
238 | #define UART1_MINT_RTS MX1_UART1_MINT_RTS | |
239 | #define UART1_MINT_DTR MX1_UART1_MINT_DTR | |
240 | #define UART1_MINT_UARTC MX1_UART1_MINT_UARTC | |
241 | #define UART1_MINT_TX MX1_UART1_MINT_TX | |
242 | #define UART1_MINT_RX MX1_UART1_MINT_RX | |
243 | #define VOICE_DAC_INT MX1_VOICE_DAC_INT | |
244 | #define VOICE_ADC_INT MX1_VOICE_ADC_INT | |
245 | #define PEN_DATA_INT MX1_PEN_DATA_INT | |
246 | #define PWM_INT MX1_PWM_INT | |
247 | #define SDHC_INT MX1_SDHC_INT | |
248 | #define I2C_INT MX1_I2C_INT | |
249 | #define CSPI_INT MX1_CSPI_INT | |
250 | #define SSI_TX_INT MX1_SSI_TX_INT | |
251 | #define SSI_TX_ERR_INT MX1_SSI_TX_ERR_INT | |
252 | #define SSI_RX_INT MX1_SSI_RX_INT | |
253 | #define SSI_RX_ERR_INT MX1_SSI_RX_ERR_INT | |
254 | #define TOUCH_INT MX1_TOUCH_INT | |
255 | #define USBD_INT1 MX1_USBD_INT1 | |
256 | #define USBD_INT2 MX1_USBD_INT2 | |
257 | #define USBD_INT3 MX1_USBD_INT3 | |
258 | #define USBD_INT4 MX1_USBD_INT4 | |
259 | #define USBD_INT5 MX1_USBD_INT5 | |
260 | #define USBD_INT6 MX1_USBD_INT6 | |
261 | #define BTSYS_INT MX1_BTSYS_INT | |
262 | #define BTTIM_INT MX1_BTTIM_INT | |
263 | #define BTWUI_INT MX1_BTWUI_INT | |
264 | #define TIM2_INT MX1_TIM2_INT | |
265 | #define TIM1_INT MX1_TIM1_INT | |
266 | #define DMA_ERR MX1_DMA_ERR | |
267 | #define DMA_INT MX1_DMA_INT | |
268 | #define GPIO_INT_PORTD MX1_GPIO_INT_PORTD | |
269 | #define WDT_INT MX1_WDT_INT | |
270 | #define DMA_REQ_UART3_T MX1_DMA_REQ_UART3_T | |
271 | #define DMA_REQ_UART3_R MX1_DMA_REQ_UART3_R | |
272 | #define DMA_REQ_SSI2_T MX1_DMA_REQ_SSI2_T | |
273 | #define DMA_REQ_SSI2_R MX1_DMA_REQ_SSI2_R | |
274 | #define DMA_REQ_CSI_STAT MX1_DMA_REQ_CSI_STAT | |
275 | #define DMA_REQ_CSI_R MX1_DMA_REQ_CSI_R | |
276 | #define DMA_REQ_MSHC MX1_DMA_REQ_MSHC | |
277 | #define DMA_REQ_DSPA_DCT_DOUT MX1_DMA_REQ_DSPA_DCT_DOUT | |
278 | #define DMA_REQ_DSPA_DCT_DIN MX1_DMA_REQ_DSPA_DCT_DIN | |
279 | #define DMA_REQ_DSPA_MAC MX1_DMA_REQ_DSPA_MAC | |
280 | #define DMA_REQ_EXT MX1_DMA_REQ_EXT | |
281 | #define DMA_REQ_SDHC MX1_DMA_REQ_SDHC | |
282 | #define DMA_REQ_SPI1_R MX1_DMA_REQ_SPI1_R | |
283 | #define DMA_REQ_SPI1_T MX1_DMA_REQ_SPI1_T | |
284 | #define DMA_REQ_SSI_T MX1_DMA_REQ_SSI_T | |
285 | #define DMA_REQ_SSI_R MX1_DMA_REQ_SSI_R | |
286 | #define DMA_REQ_ASP_DAC MX1_DMA_REQ_ASP_DAC | |
287 | #define DMA_REQ_ASP_ADC MX1_DMA_REQ_ASP_ADC | |
288 | #define DMA_REQ_USP_EP(x) MX1_DMA_REQ_USP_EP(x) | |
289 | #define DMA_REQ_SPI2_R MX1_DMA_REQ_SPI2_R | |
290 | #define DMA_REQ_SPI2_T MX1_DMA_REQ_SPI2_T | |
291 | #define DMA_REQ_UART2_T MX1_DMA_REQ_UART2_T | |
292 | #define DMA_REQ_UART2_R MX1_DMA_REQ_UART2_R | |
293 | #define DMA_REQ_UART1_T MX1_DMA_REQ_UART1_T | |
294 | #define DMA_REQ_UART1_R MX1_DMA_REQ_UART1_R | |
295 | #endif /* ifdef IMX_NEEDS_DEPRECATED_SYMBOLS */ | |
cfca8b53 | 296 | |
3cdd5441 | 297 | #endif /* ifndef __MACH_MX1_H__ */ |