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52c543f9 QJ |
1 | /* |
2 | * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. | |
3 | */ | |
4 | ||
5 | /* | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License version 2 as | |
8 | * published by the Free Software Foundation. | |
9 | */ | |
10 | ||
11 | #ifndef __ASM_ARCH_MXC_IRQS_H__ | |
12 | #define __ASM_ARCH_MXC_IRQS_H__ | |
13 | ||
9d631b83 | 14 | /* |
a003708a | 15 | * SoCs with TZIC interrupt controller have 128 IRQs, those with AVIC have 64 |
9d631b83 | 16 | */ |
a003708a AK |
17 | #ifdef CONFIG_MXC_TZIC |
18 | #define MXC_INTERNAL_IRQS 128 | |
19 | #else | |
9d631b83 | 20 | #define MXC_INTERNAL_IRQS 64 |
a003708a | 21 | #endif |
9d631b83 SH |
22 | |
23 | #define MXC_GPIO_IRQ_START MXC_INTERNAL_IRQS | |
24 | ||
abf61632 UKK |
25 | /* these are ordered by size to support multi-SoC kernels */ |
26 | #if defined CONFIG_ARCH_MX2 | |
9d631b83 | 27 | #define MXC_GPIO_IRQS (32 * 6) |
abf61632 UKK |
28 | #elif defined CONFIG_ARCH_MX1 |
29 | #define MXC_GPIO_IRQS (32 * 4) | |
8c25c36f SH |
30 | #elif defined CONFIG_ARCH_MX25 |
31 | #define MXC_GPIO_IRQS (32 * 4) | |
438caa3f AK |
32 | #elif defined CONFIG_ARCH_MX5 |
33 | #define MXC_GPIO_IRQS (32 * 4) | |
fd6ac7bb DT |
34 | #elif defined CONFIG_ARCH_MXC91231 |
35 | #define MXC_GPIO_IRQS (32 * 4) | |
abf61632 UKK |
36 | #elif defined CONFIG_ARCH_MX3 |
37 | #define MXC_GPIO_IRQS (32 * 3) | |
9d631b83 SH |
38 | #endif |
39 | ||
40 | /* | |
41 | * The next 16 interrupts are for board specific purposes. Since | |
42 | * the kernel can only run on one machine at a time, we can re-use | |
43 | * these. If you need more, increase MXC_BOARD_IRQS, but keep it | |
44 | * within sensible limits. | |
45 | */ | |
46 | #define MXC_BOARD_IRQ_START (MXC_INTERNAL_IRQS + MXC_GPIO_IRQS) | |
3d661ac1 MB |
47 | |
48 | #ifdef CONFIG_MACH_MX31ADS_WM1133_EV1 | |
49 | #define MXC_BOARD_IRQS 80 | |
50 | #else | |
9d631b83 | 51 | #define MXC_BOARD_IRQS 16 |
3d661ac1 | 52 | #endif |
9d631b83 | 53 | |
5296b56d GL |
54 | #define MXC_IPU_IRQ_START (MXC_BOARD_IRQ_START + MXC_BOARD_IRQS) |
55 | ||
56 | #ifdef CONFIG_MX3_IPU_IRQS | |
57 | #define MX3_IPU_IRQS CONFIG_MX3_IPU_IRQS | |
58 | #else | |
59 | #define MX3_IPU_IRQS 0 | |
60 | #endif | |
438caa3f | 61 | /* REVISIT: Add IPU irqs on IMX51 */ |
5296b56d GL |
62 | |
63 | #define NR_IRQS (MXC_IPU_IRQ_START + MX3_IPU_IRQS) | |
9d631b83 | 64 | |
3f203016 | 65 | extern int imx_irq_set_priority(unsigned char irq, unsigned char prio); |
52c543f9 | 66 | |
d7927e19 PZ |
67 | /* all normal IRQs can be FIQs */ |
68 | #define FIQ_START 0 | |
69 | /* switch betwean IRQ and FIQ */ | |
70 | extern int mxc_set_irq_fiq(unsigned int irq, unsigned int type); | |
71 | ||
f304fc42 | 72 | #endif /* __ASM_ARCH_MXC_IRQS_H__ */ |