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5296b56d GL |
1 | /* |
2 | * Copyright (C) 2008 | |
3 | * Guennadi Liakhovetski, DENX Software Engineering, <lg@denx.de> | |
4 | * | |
5 | * Copyright (C) 2005-2007 Freescale Semiconductor, Inc. | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License version 2 as | |
9 | * published by the Free Software Foundation. | |
10 | */ | |
11 | ||
12 | #ifndef _IPU_H_ | |
13 | #define _IPU_H_ | |
14 | ||
15 | #include <linux/types.h> | |
16 | #include <linux/dmaengine.h> | |
17 | ||
18 | /* IPU DMA Controller channel definitions. */ | |
19 | enum ipu_channel { | |
20 | IDMAC_IC_0 = 0, /* IC (encoding task) to memory */ | |
21 | IDMAC_IC_1 = 1, /* IC (viewfinder task) to memory */ | |
22 | IDMAC_ADC_0 = 1, | |
23 | IDMAC_IC_2 = 2, | |
24 | IDMAC_ADC_1 = 2, | |
25 | IDMAC_IC_3 = 3, | |
26 | IDMAC_IC_4 = 4, | |
27 | IDMAC_IC_5 = 5, | |
28 | IDMAC_IC_6 = 6, | |
29 | IDMAC_IC_7 = 7, /* IC (sensor data) to memory */ | |
30 | IDMAC_IC_8 = 8, | |
31 | IDMAC_IC_9 = 9, | |
32 | IDMAC_IC_10 = 10, | |
33 | IDMAC_IC_11 = 11, | |
34 | IDMAC_IC_12 = 12, | |
35 | IDMAC_IC_13 = 13, | |
36 | IDMAC_SDC_0 = 14, /* Background synchronous display data */ | |
37 | IDMAC_SDC_1 = 15, /* Foreground data (overlay) */ | |
38 | IDMAC_SDC_2 = 16, | |
39 | IDMAC_SDC_3 = 17, | |
40 | IDMAC_ADC_2 = 18, | |
41 | IDMAC_ADC_3 = 19, | |
42 | IDMAC_ADC_4 = 20, | |
43 | IDMAC_ADC_5 = 21, | |
44 | IDMAC_ADC_6 = 22, | |
45 | IDMAC_ADC_7 = 23, | |
46 | IDMAC_PF_0 = 24, | |
47 | IDMAC_PF_1 = 25, | |
48 | IDMAC_PF_2 = 26, | |
49 | IDMAC_PF_3 = 27, | |
50 | IDMAC_PF_4 = 28, | |
51 | IDMAC_PF_5 = 29, | |
52 | IDMAC_PF_6 = 30, | |
53 | IDMAC_PF_7 = 31, | |
54 | }; | |
55 | ||
56 | /* Order significant! */ | |
57 | enum ipu_channel_status { | |
58 | IPU_CHANNEL_FREE, | |
59 | IPU_CHANNEL_INITIALIZED, | |
60 | IPU_CHANNEL_READY, | |
61 | IPU_CHANNEL_ENABLED, | |
62 | }; | |
63 | ||
64 | #define IPU_CHANNELS_NUM 32 | |
65 | ||
66 | enum pixel_fmt { | |
67 | /* 1 byte */ | |
68 | IPU_PIX_FMT_GENERIC, | |
69 | IPU_PIX_FMT_RGB332, | |
70 | IPU_PIX_FMT_YUV420P, | |
71 | IPU_PIX_FMT_YUV422P, | |
72 | IPU_PIX_FMT_YUV420P2, | |
73 | IPU_PIX_FMT_YVU422P, | |
74 | /* 2 bytes */ | |
75 | IPU_PIX_FMT_RGB565, | |
76 | IPU_PIX_FMT_RGB666, | |
77 | IPU_PIX_FMT_BGR666, | |
78 | IPU_PIX_FMT_YUYV, | |
79 | IPU_PIX_FMT_UYVY, | |
80 | /* 3 bytes */ | |
81 | IPU_PIX_FMT_RGB24, | |
82 | IPU_PIX_FMT_BGR24, | |
83 | /* 4 bytes */ | |
84 | IPU_PIX_FMT_GENERIC_32, | |
85 | IPU_PIX_FMT_RGB32, | |
86 | IPU_PIX_FMT_BGR32, | |
87 | IPU_PIX_FMT_ABGR32, | |
88 | IPU_PIX_FMT_BGRA32, | |
89 | IPU_PIX_FMT_RGBA32, | |
90 | }; | |
91 | ||
92 | enum ipu_color_space { | |
93 | IPU_COLORSPACE_RGB, | |
94 | IPU_COLORSPACE_YCBCR, | |
95 | IPU_COLORSPACE_YUV | |
96 | }; | |
97 | ||
98 | /* | |
99 | * Enumeration of IPU rotation modes | |
100 | */ | |
101 | enum ipu_rotate_mode { | |
102 | /* Note the enum values correspond to BAM value */ | |
103 | IPU_ROTATE_NONE = 0, | |
104 | IPU_ROTATE_VERT_FLIP = 1, | |
105 | IPU_ROTATE_HORIZ_FLIP = 2, | |
106 | IPU_ROTATE_180 = 3, | |
107 | IPU_ROTATE_90_RIGHT = 4, | |
108 | IPU_ROTATE_90_RIGHT_VFLIP = 5, | |
109 | IPU_ROTATE_90_RIGHT_HFLIP = 6, | |
110 | IPU_ROTATE_90_LEFT = 7, | |
111 | }; | |
112 | ||
113 | struct ipu_platform_data { | |
114 | unsigned int irq_base; | |
115 | }; | |
116 | ||
117 | /* | |
118 | * Enumeration of DI ports for ADC. | |
119 | */ | |
120 | enum display_port { | |
121 | DISP0, | |
122 | DISP1, | |
123 | DISP2, | |
124 | DISP3 | |
125 | }; | |
126 | ||
127 | struct idmac_video_param { | |
128 | unsigned short in_width; | |
129 | unsigned short in_height; | |
130 | uint32_t in_pixel_fmt; | |
131 | unsigned short out_width; | |
132 | unsigned short out_height; | |
133 | uint32_t out_pixel_fmt; | |
134 | unsigned short out_stride; | |
135 | bool graphics_combine_en; | |
136 | bool global_alpha_en; | |
137 | bool key_color_en; | |
138 | enum display_port disp; | |
139 | unsigned short out_left; | |
140 | unsigned short out_top; | |
141 | }; | |
142 | ||
143 | /* | |
144 | * Union of initialization parameters for a logical channel. So far only video | |
145 | * parameters are used. | |
146 | */ | |
147 | union ipu_channel_param { | |
148 | struct idmac_video_param video; | |
149 | }; | |
150 | ||
151 | struct idmac_tx_desc { | |
152 | struct dma_async_tx_descriptor txd; | |
153 | struct scatterlist *sg; /* scatterlist for this */ | |
154 | unsigned int sg_len; /* tx-descriptor. */ | |
155 | struct list_head list; | |
156 | }; | |
157 | ||
158 | struct idmac_channel { | |
159 | struct dma_chan dma_chan; | |
160 | dma_cookie_t completed; /* last completed cookie */ | |
161 | union ipu_channel_param params; | |
162 | enum ipu_channel link; /* input channel, linked to the output */ | |
163 | enum ipu_channel_status status; | |
164 | void *client; /* Only one client per channel */ | |
165 | unsigned int n_tx_desc; | |
166 | struct idmac_tx_desc *desc; /* allocated tx-descriptors */ | |
167 | struct scatterlist *sg[2]; /* scatterlist elements in buffer-0 and -1 */ | |
168 | struct list_head free_list; /* free tx-descriptors */ | |
169 | struct list_head queue; /* queued tx-descriptors */ | |
170 | spinlock_t lock; /* protects sg[0,1], queue */ | |
171 | struct mutex chan_mutex; /* protects status, cookie, free_list */ | |
172 | bool sec_chan_en; | |
173 | int active_buffer; | |
174 | unsigned int eof_irq; | |
175 | char eof_name[16]; /* EOF IRQ name for request_irq() */ | |
176 | }; | |
177 | ||
178 | #define to_tx_desc(tx) container_of(tx, struct idmac_tx_desc, txd) | |
179 | #define to_idmac_chan(c) container_of(c, struct idmac_channel, dma_chan) | |
180 | ||
181 | #endif |