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48388b2a LB |
1 | /* |
2 | * arch/arm/plat-iop/time.c | |
3 | * | |
4 | * Timer code for IOP32x and IOP33x based systems | |
5 | * | |
6 | * Author: Deepak Saxena <dsaxena@mvista.com> | |
7 | * | |
8 | * Copyright 2002-2003 MontaVista Software Inc. | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or modify it | |
11 | * under the terms of the GNU General Public License as published by the | |
12 | * Free Software Foundation; either version 2 of the License, or (at your | |
13 | * option) any later version. | |
14 | */ | |
15 | ||
16 | #include <linux/kernel.h> | |
17 | #include <linux/interrupt.h> | |
18 | #include <linux/time.h> | |
19 | #include <linux/init.h> | |
20 | #include <linux/timex.h> | |
fced80c7 | 21 | #include <linux/io.h> |
a91549a8 | 22 | #include <linux/clocksource.h> |
a09e64fb | 23 | #include <mach/hardware.h> |
48388b2a LB |
24 | #include <asm/irq.h> |
25 | #include <asm/uaccess.h> | |
26 | #include <asm/mach/irq.h> | |
27 | #include <asm/mach/time.h> | |
a09e64fb | 28 | #include <mach/time.h> |
48388b2a | 29 | |
a91549a8 MP |
30 | /* |
31 | * IOP clocksource (free-running timer 1). | |
32 | */ | |
33 | static cycle_t iop_clocksource_read(struct clocksource *unused) | |
34 | { | |
35 | return 0xffffffffu - read_tcr1(); | |
36 | } | |
37 | ||
38 | static struct clocksource iop_clocksource = { | |
39 | .name = "iop_timer1", | |
40 | .rating = 300, | |
41 | .read = iop_clocksource_read, | |
42 | .mask = CLOCKSOURCE_MASK(32), | |
43 | .flags = CLOCK_SOURCE_IS_CONTINUOUS, | |
44 | }; | |
45 | ||
46 | static void __init iop_clocksource_set_hz(struct clocksource *cs, unsigned int hz) | |
47 | { | |
48 | u64 temp; | |
49 | u32 shift; | |
50 | ||
51 | /* Find shift and mult values for hz. */ | |
52 | shift = 32; | |
53 | do { | |
54 | temp = (u64) NSEC_PER_SEC << shift; | |
55 | do_div(temp, hz); | |
56 | if ((temp >> 32) == 0) | |
57 | break; | |
58 | } while (--shift != 0); | |
59 | ||
60 | cs->shift = shift; | |
61 | cs->mult = (u32) temp; | |
62 | ||
63 | printk(KERN_INFO "clocksource: %s uses shift %u mult %#x\n", | |
64 | cs->name, cs->shift, cs->mult); | |
65 | } | |
66 | ||
48388b2a LB |
67 | static unsigned long ticks_per_jiffy; |
68 | static unsigned long ticks_per_usec; | |
69 | static unsigned long next_jiffy_time; | |
70 | ||
3668b45d | 71 | unsigned long iop_gettimeoffset(void) |
48388b2a | 72 | { |
8903fcce | 73 | unsigned long offset, temp; |
3668b45d DW |
74 | |
75 | /* enable cp6, if necessary, to avoid taking the overhead of an | |
76 | * undefined instruction trap | |
77 | */ | |
78 | asm volatile ( | |
79 | "mrc p15, 0, %0, c15, c1, 0\n\t" | |
8903fcce | 80 | "tst %0, #(1 << 6)\n\t" |
3668b45d DW |
81 | "orreq %0, %0, #(1 << 6)\n\t" |
82 | "mcreq p15, 0, %0, c15, c1, 0\n\t" | |
8903fcce | 83 | #ifdef CONFIG_CPU_XSCALE |
3668b45d DW |
84 | "mrceq p15, 0, %0, c15, c1, 0\n\t" |
85 | "moveq %0, %0\n\t" | |
86 | "subeq pc, pc, #4\n\t" | |
87 | #endif | |
8903fcce | 88 | : "=r"(temp) : : "cc"); |
48388b2a | 89 | |
3668b45d | 90 | offset = next_jiffy_time - read_tcr1(); |
48388b2a LB |
91 | |
92 | return offset / ticks_per_usec; | |
93 | } | |
94 | ||
95 | static irqreturn_t | |
3668b45d | 96 | iop_timer_interrupt(int irq, void *dev_id) |
48388b2a | 97 | { |
3668b45d | 98 | write_tisr(1); |
48388b2a | 99 | |
3668b45d DW |
100 | while ((signed long)(next_jiffy_time - read_tcr1()) |
101 | >= ticks_per_jiffy) { | |
0cd61b68 | 102 | timer_tick(); |
48388b2a LB |
103 | next_jiffy_time -= ticks_per_jiffy; |
104 | } | |
105 | ||
48388b2a LB |
106 | return IRQ_HANDLED; |
107 | } | |
108 | ||
3668b45d DW |
109 | static struct irqaction iop_timer_irq = { |
110 | .name = "IOP Timer Tick", | |
111 | .handler = iop_timer_interrupt, | |
b30fabad | 112 | .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL, |
48388b2a LB |
113 | }; |
114 | ||
70c14ff0 DW |
115 | static unsigned long iop_tick_rate; |
116 | unsigned long get_iop_tick_rate(void) | |
117 | { | |
118 | return iop_tick_rate; | |
119 | } | |
120 | EXPORT_SYMBOL(get_iop_tick_rate); | |
121 | ||
3668b45d | 122 | void __init iop_init_time(unsigned long tick_rate) |
48388b2a LB |
123 | { |
124 | u32 timer_ctl; | |
125 | ||
a692838d | 126 | ticks_per_jiffy = DIV_ROUND_CLOSEST(tick_rate, HZ); |
48388b2a LB |
127 | ticks_per_usec = tick_rate / 1000000; |
128 | next_jiffy_time = 0xffffffff; | |
70c14ff0 | 129 | iop_tick_rate = tick_rate; |
48388b2a | 130 | |
3668b45d DW |
131 | timer_ctl = IOP_TMR_EN | IOP_TMR_PRIVILEGED | |
132 | IOP_TMR_RELOAD | IOP_TMR_RATIO_1_1; | |
48388b2a LB |
133 | |
134 | /* | |
135 | * We use timer 0 for our timer interrupt, and timer 1 as | |
136 | * monotonic counter for tracking missed jiffies. | |
137 | */ | |
3668b45d DW |
138 | write_trr0(ticks_per_jiffy - 1); |
139 | write_tmr0(timer_ctl); | |
a91549a8 MP |
140 | |
141 | /* | |
142 | * Set up free-running clocksource timer 1. | |
143 | */ | |
3668b45d | 144 | write_trr1(0xffffffff); |
a91549a8 | 145 | write_tcr1(0xffffffff); |
3668b45d | 146 | write_tmr1(timer_ctl); |
a91549a8 MP |
147 | iop_clocksource_set_hz(&iop_clocksource, tick_rate); |
148 | clocksource_register(&iop_clocksource); | |
48388b2a | 149 | |
3668b45d | 150 | setup_irq(IRQ_IOP_TIMER0, &iop_timer_irq); |
48388b2a | 151 | } |