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0cb015f9 LB |
1 | /* |
2 | * arch/arm/plat-iop/pci.c | |
3 | * | |
4 | * PCI support for the Intel IOP32X and IOP33X processors | |
5 | * | |
6 | * Author: Rory Bolt <rorybolt@pacbell.net> | |
7 | * Copyright (C) 2002 Rory Bolt | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License version 2 as | |
11 | * published by the Free Software Foundation. | |
12 | */ | |
13 | ||
14 | #include <linux/kernel.h> | |
15 | #include <linux/pci.h> | |
16 | #include <linux/slab.h> | |
17 | #include <linux/mm.h> | |
18 | #include <linux/init.h> | |
19 | #include <linux/ioport.h> | |
20 | #include <asm/io.h> | |
21 | #include <asm/irq.h> | |
e8edc6e0 | 22 | #include <asm/signal.h> |
0cb015f9 | 23 | #include <asm/system.h> |
a09e64fb | 24 | #include <mach/hardware.h> |
0cb015f9 LB |
25 | #include <asm/mach/pci.h> |
26 | #include <asm/hardware/iop3xx.h> | |
27 | ||
28 | // #define DEBUG | |
29 | ||
30 | #ifdef DEBUG | |
31 | #define DBG(x...) printk(x) | |
32 | #else | |
33 | #define DBG(x...) do { } while (0) | |
34 | #endif | |
35 | ||
36 | /* | |
37 | * This routine builds either a type0 or type1 configuration command. If the | |
38 | * bus is on the 803xx then a type0 made, else a type1 is created. | |
39 | */ | |
40 | static u32 iop3xx_cfg_address(struct pci_bus *bus, int devfn, int where) | |
41 | { | |
42 | struct pci_sys_data *sys = bus->sysdata; | |
43 | u32 addr; | |
44 | ||
45 | if (sys->busnr == bus->number) | |
46 | addr = 1 << (PCI_SLOT(devfn) + 16) | (PCI_SLOT(devfn) << 11); | |
47 | else | |
48 | addr = bus->number << 16 | PCI_SLOT(devfn) << 11 | 1; | |
49 | ||
50 | addr |= PCI_FUNC(devfn) << 8 | (where & ~3); | |
51 | ||
52 | return addr; | |
53 | } | |
54 | ||
55 | /* | |
56 | * This routine checks the status of the last configuration cycle. If an error | |
57 | * was detected it returns a 1, else it returns a 0. The errors being checked | |
58 | * are parity, master abort, target abort (master and target). These types of | |
e90ddd81 | 59 | * errors occur during a config cycle where there is no device, like during |
0cb015f9 LB |
60 | * the discovery stage. |
61 | */ | |
62 | static int iop3xx_pci_status(void) | |
63 | { | |
64 | unsigned int status; | |
65 | int ret = 0; | |
66 | ||
67 | /* | |
68 | * Check the status registers. | |
69 | */ | |
70 | status = *IOP3XX_ATUSR; | |
71 | if (status & 0xf900) { | |
72 | DBG("\t\t\tPCI: P0 - status = 0x%08x\n", status); | |
73 | *IOP3XX_ATUSR = status & 0xf900; | |
74 | ret = 1; | |
75 | } | |
76 | ||
77 | status = *IOP3XX_ATUISR; | |
78 | if (status & 0x679f) { | |
79 | DBG("\t\t\tPCI: P1 - status = 0x%08x\n", status); | |
80 | *IOP3XX_ATUISR = status & 0x679f; | |
81 | ret = 1; | |
82 | } | |
83 | ||
84 | return ret; | |
85 | } | |
86 | ||
87 | /* | |
88 | * Simply write the address register and read the configuration | |
6cbdc8c5 | 89 | * data. Note that the 4 nops ensure that we are able to handle |
0cb015f9 LB |
90 | * a delayed abort (in theory.) |
91 | */ | |
d73d8011 | 92 | static u32 iop3xx_read(unsigned long addr) |
0cb015f9 LB |
93 | { |
94 | u32 val; | |
95 | ||
96 | __asm__ __volatile__( | |
97 | "str %1, [%2]\n\t" | |
98 | "ldr %0, [%3]\n\t" | |
99 | "nop\n\t" | |
100 | "nop\n\t" | |
101 | "nop\n\t" | |
102 | "nop\n\t" | |
103 | : "=r" (val) | |
104 | : "r" (addr), "r" (IOP3XX_OCCAR), "r" (IOP3XX_OCCDR)); | |
105 | ||
106 | return val; | |
107 | } | |
108 | ||
109 | /* | |
110 | * The read routines must check the error status of the last configuration | |
111 | * cycle. If there was an error, the routine returns all hex f's. | |
112 | */ | |
113 | static int | |
114 | iop3xx_read_config(struct pci_bus *bus, unsigned int devfn, int where, | |
115 | int size, u32 *value) | |
116 | { | |
117 | unsigned long addr = iop3xx_cfg_address(bus, devfn, where); | |
118 | u32 val = iop3xx_read(addr) >> ((where & 3) * 8); | |
119 | ||
120 | if (iop3xx_pci_status()) | |
121 | val = 0xffffffff; | |
122 | ||
123 | *value = val; | |
124 | ||
125 | return PCIBIOS_SUCCESSFUL; | |
126 | } | |
127 | ||
128 | static int | |
129 | iop3xx_write_config(struct pci_bus *bus, unsigned int devfn, int where, | |
130 | int size, u32 value) | |
131 | { | |
132 | unsigned long addr = iop3xx_cfg_address(bus, devfn, where); | |
133 | u32 val; | |
134 | ||
135 | if (size != 4) { | |
136 | val = iop3xx_read(addr); | |
137 | if (iop3xx_pci_status()) | |
138 | return PCIBIOS_SUCCESSFUL; | |
139 | ||
140 | where = (where & 3) * 8; | |
141 | ||
142 | if (size == 1) | |
143 | val &= ~(0xff << where); | |
144 | else | |
145 | val &= ~(0xffff << where); | |
146 | ||
147 | *IOP3XX_OCCDR = val | value << where; | |
148 | } else { | |
149 | asm volatile( | |
150 | "str %1, [%2]\n\t" | |
151 | "str %0, [%3]\n\t" | |
152 | "nop\n\t" | |
153 | "nop\n\t" | |
154 | "nop\n\t" | |
155 | "nop\n\t" | |
156 | : | |
157 | : "r" (value), "r" (addr), | |
158 | "r" (IOP3XX_OCCAR), "r" (IOP3XX_OCCDR)); | |
159 | } | |
160 | ||
161 | return PCIBIOS_SUCCESSFUL; | |
162 | } | |
163 | ||
164 | static struct pci_ops iop3xx_ops = { | |
165 | .read = iop3xx_read_config, | |
166 | .write = iop3xx_write_config, | |
167 | }; | |
168 | ||
169 | /* | |
170 | * When a PCI device does not exist during config cycles, the 80200 gets a | |
171 | * bus error instead of returning 0xffffffff. This handler simply returns. | |
172 | */ | |
173 | static int | |
174 | iop3xx_pci_abort(unsigned long addr, unsigned int fsr, struct pt_regs *regs) | |
175 | { | |
176 | DBG("PCI abort: address = 0x%08lx fsr = 0x%03x PC = 0x%08lx LR = 0x%08lx\n", | |
177 | addr, fsr, regs->ARM_pc, regs->ARM_lr); | |
178 | ||
179 | /* | |
180 | * If it was an imprecise abort, then we need to correct the | |
181 | * return address to be _after_ the instruction. | |
182 | */ | |
183 | if (fsr & (1 << 10)) | |
184 | regs->ARM_pc += 4; | |
185 | ||
186 | return 0; | |
187 | } | |
188 | ||
189 | int iop3xx_pci_setup(int nr, struct pci_sys_data *sys) | |
190 | { | |
191 | struct resource *res; | |
192 | ||
193 | if (nr != 0) | |
194 | return 0; | |
195 | ||
196 | res = kzalloc(2 * sizeof(struct resource), GFP_KERNEL); | |
197 | if (!res) | |
198 | panic("PCI: unable to alloc resources"); | |
199 | ||
6df26700 DW |
200 | res[0].start = IOP3XX_PCI_LOWER_IO_PA; |
201 | res[0].end = IOP3XX_PCI_LOWER_IO_PA + IOP3XX_PCI_IO_WINDOW_SIZE - 1; | |
0cb015f9 LB |
202 | res[0].name = "IOP3XX PCI I/O Space"; |
203 | res[0].flags = IORESOURCE_IO; | |
204 | request_resource(&ioport_resource, &res[0]); | |
205 | ||
206 | res[1].start = IOP3XX_PCI_LOWER_MEM_PA; | |
207 | res[1].end = IOP3XX_PCI_LOWER_MEM_PA + IOP3XX_PCI_MEM_WINDOW_SIZE - 1; | |
208 | res[1].name = "IOP3XX PCI Memory Space"; | |
209 | res[1].flags = IORESOURCE_MEM; | |
210 | request_resource(&iomem_resource, &res[1]); | |
211 | ||
27eedbf5 RK |
212 | /* |
213 | * Use whatever translation is already setup. | |
214 | */ | |
215 | sys->mem_offset = IOP3XX_PCI_LOWER_MEM_PA - *IOP3XX_OMWTVR0; | |
216 | sys->io_offset = IOP3XX_PCI_LOWER_IO_PA - *IOP3XX_OIOWTVR; | |
0cb015f9 LB |
217 | |
218 | sys->resource[0] = &res[0]; | |
219 | sys->resource[1] = &res[1]; | |
220 | sys->resource[2] = NULL; | |
221 | ||
222 | return 1; | |
223 | } | |
224 | ||
225 | struct pci_bus *iop3xx_pci_scan_bus(int nr, struct pci_sys_data *sys) | |
226 | { | |
227 | return pci_scan_bus(sys->busnr, &iop3xx_ops, sys); | |
228 | } | |
229 | ||
e90ddd81 DW |
230 | void __init iop3xx_atu_setup(void) |
231 | { | |
232 | /* BAR 0 ( Disabled ) */ | |
233 | *IOP3XX_IAUBAR0 = 0x0; | |
234 | *IOP3XX_IABAR0 = 0x0; | |
235 | *IOP3XX_IATVR0 = 0x0; | |
236 | *IOP3XX_IALR0 = 0x0; | |
237 | ||
238 | /* BAR 1 ( Disabled ) */ | |
239 | *IOP3XX_IAUBAR1 = 0x0; | |
240 | *IOP3XX_IABAR1 = 0x0; | |
241 | *IOP3XX_IALR1 = 0x0; | |
242 | ||
243 | /* BAR 2 (1:1 mapping with Physical RAM) */ | |
244 | /* Set limit and enable */ | |
245 | *IOP3XX_IALR2 = ~((u32)IOP3XX_MAX_RAM_SIZE - 1) & ~0x1; | |
246 | *IOP3XX_IAUBAR2 = 0x0; | |
247 | ||
248 | /* Align the inbound bar with the base of memory */ | |
249 | *IOP3XX_IABAR2 = PHYS_OFFSET | | |
250 | PCI_BASE_ADDRESS_MEM_TYPE_64 | | |
251 | PCI_BASE_ADDRESS_MEM_PREFETCH; | |
252 | ||
253 | *IOP3XX_IATVR2 = PHYS_OFFSET; | |
254 | ||
255 | /* Outbound window 0 */ | |
97c46048 | 256 | *IOP3XX_OMWTVR0 = IOP3XX_PCI_LOWER_MEM_BA; |
e90ddd81 DW |
257 | *IOP3XX_OUMWTVR0 = 0; |
258 | ||
259 | /* Outbound window 1 */ | |
97c46048 | 260 | *IOP3XX_OMWTVR1 = IOP3XX_PCI_LOWER_MEM_BA + IOP3XX_PCI_MEM_WINDOW_SIZE; |
e90ddd81 DW |
261 | *IOP3XX_OUMWTVR1 = 0; |
262 | ||
263 | /* BAR 3 ( Disabled ) */ | |
264 | *IOP3XX_IAUBAR3 = 0x0; | |
265 | *IOP3XX_IABAR3 = 0x0; | |
266 | *IOP3XX_IATVR3 = 0x0; | |
267 | *IOP3XX_IALR3 = 0x0; | |
268 | ||
269 | /* Setup the I/O Bar | |
270 | */ | |
97c46048 | 271 | *IOP3XX_OIOWTVR = IOP3XX_PCI_LOWER_IO_BA; |
e90ddd81 DW |
272 | |
273 | /* Enable inbound and outbound cycles | |
274 | */ | |
275 | *IOP3XX_ATUCMD |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | | |
276 | PCI_COMMAND_PARITY | PCI_COMMAND_SERR; | |
277 | *IOP3XX_ATUCR |= IOP3XX_ATUCR_OUT_EN; | |
278 | } | |
279 | ||
280 | void __init iop3xx_atu_disable(void) | |
281 | { | |
282 | *IOP3XX_ATUCMD = 0; | |
283 | *IOP3XX_ATUCR = 0; | |
284 | ||
285 | /* wait for cycles to quiesce */ | |
286 | while (*IOP3XX_PCSR & (IOP3XX_PCSR_OUT_Q_BUSY | | |
287 | IOP3XX_PCSR_IN_Q_BUSY)) | |
288 | cpu_relax(); | |
289 | ||
290 | /* BAR 0 ( Disabled ) */ | |
291 | *IOP3XX_IAUBAR0 = 0x0; | |
292 | *IOP3XX_IABAR0 = 0x0; | |
293 | *IOP3XX_IATVR0 = 0x0; | |
294 | *IOP3XX_IALR0 = 0x0; | |
295 | ||
296 | /* BAR 1 ( Disabled ) */ | |
297 | *IOP3XX_IAUBAR1 = 0x0; | |
298 | *IOP3XX_IABAR1 = 0x0; | |
299 | *IOP3XX_IALR1 = 0x0; | |
300 | ||
301 | /* BAR 2 ( Disabled ) */ | |
302 | *IOP3XX_IAUBAR2 = 0x0; | |
303 | *IOP3XX_IABAR2 = 0x0; | |
304 | *IOP3XX_IATVR2 = 0x0; | |
305 | *IOP3XX_IALR2 = 0x0; | |
306 | ||
307 | /* BAR 3 ( Disabled ) */ | |
308 | *IOP3XX_IAUBAR3 = 0x0; | |
309 | *IOP3XX_IABAR3 = 0x0; | |
310 | *IOP3XX_IATVR3 = 0x0; | |
311 | *IOP3XX_IALR3 = 0x0; | |
312 | ||
313 | /* Clear the outbound windows */ | |
314 | *IOP3XX_OIOWTVR = 0; | |
315 | ||
316 | /* Outbound window 0 */ | |
317 | *IOP3XX_OMWTVR0 = 0; | |
318 | *IOP3XX_OUMWTVR0 = 0; | |
319 | ||
320 | /* Outbound window 1 */ | |
321 | *IOP3XX_OMWTVR1 = 0; | |
322 | *IOP3XX_OUMWTVR1 = 0; | |
323 | } | |
324 | ||
325 | /* Flag to determine whether the ATU is initialized and the PCI bus scanned */ | |
326 | int init_atu; | |
327 | ||
c34002c1 DW |
328 | int iop3xx_get_init_atu(void) { |
329 | /* check if default has been overridden */ | |
330 | if (init_atu != IOP3XX_INIT_ATU_DEFAULT) | |
331 | return init_atu; | |
332 | else | |
333 | return IOP3XX_INIT_ATU_DISABLE; | |
334 | } | |
e90ddd81 | 335 | |
c34002c1 DW |
336 | static void __init iop3xx_atu_debug(void) |
337 | { | |
c3a1c9c7 RK |
338 | DBG("PCI: Intel IOP3xx PCI init.\n"); |
339 | DBG("PCI: Outbound memory window 0: PCI 0x%08x%08x\n", | |
340 | *IOP3XX_OUMWTVR0, *IOP3XX_OMWTVR0); | |
341 | DBG("PCI: Outbound memory window 1: PCI 0x%08x%08x\n", | |
342 | *IOP3XX_OUMWTVR1, *IOP3XX_OMWTVR1); | |
343 | DBG("PCI: Outbound IO window: PCI 0x%08x\n", | |
344 | *IOP3XX_OIOWTVR); | |
345 | ||
346 | DBG("PCI: Inbound memory window 0: PCI 0x%08x%08x 0x%08x -> 0x%08x\n", | |
347 | *IOP3XX_IAUBAR0, *IOP3XX_IABAR0, *IOP3XX_IALR0, *IOP3XX_IATVR0); | |
348 | DBG("PCI: Inbound memory window 1: PCI 0x%08x%08x 0x%08x\n", | |
349 | *IOP3XX_IAUBAR1, *IOP3XX_IABAR1, *IOP3XX_IALR1); | |
350 | DBG("PCI: Inbound memory window 2: PCI 0x%08x%08x 0x%08x -> 0x%08x\n", | |
351 | *IOP3XX_IAUBAR2, *IOP3XX_IABAR2, *IOP3XX_IALR2, *IOP3XX_IATVR2); | |
352 | DBG("PCI: Inbound memory window 3: PCI 0x%08x%08x 0x%08x -> 0x%08x\n", | |
353 | *IOP3XX_IAUBAR3, *IOP3XX_IABAR3, *IOP3XX_IALR3, *IOP3XX_IATVR3); | |
354 | ||
355 | DBG("PCI: Expansion ROM window: PCI 0x%08x%08x 0x%08x -> 0x%08x\n", | |
356 | 0, *IOP3XX_ERBAR, *IOP3XX_ERLR, *IOP3XX_ERTVR); | |
357 | ||
0cb015f9 | 358 | DBG("ATU: IOP3XX_ATUCMD=0x%04x\n", *IOP3XX_ATUCMD); |
0cb015f9 | 359 | DBG("ATU: IOP3XX_ATUCR=0x%08x\n", *IOP3XX_ATUCR); |
0cb015f9 LB |
360 | |
361 | hook_fault_code(16+6, iop3xx_pci_abort, SIGBUS, "imprecise external abort"); | |
362 | } | |
e90ddd81 | 363 | |
c34002c1 DW |
364 | /* for platforms that might be host-bus-adapters */ |
365 | void __init iop3xx_pci_preinit_cond(void) | |
366 | { | |
367 | if (iop3xx_get_init_atu() == IOP3XX_INIT_ATU_ENABLE) { | |
368 | iop3xx_atu_disable(); | |
369 | iop3xx_atu_setup(); | |
370 | iop3xx_atu_debug(); | |
371 | } | |
372 | } | |
373 | ||
374 | void __init iop3xx_pci_preinit(void) | |
375 | { | |
376 | iop3xx_atu_disable(); | |
377 | iop3xx_atu_setup(); | |
378 | iop3xx_atu_debug(); | |
379 | } | |
380 | ||
e90ddd81 DW |
381 | /* allow init_atu to be user overridden */ |
382 | static int __init iop3xx_init_atu_setup(char *str) | |
383 | { | |
384 | init_atu = IOP3XX_INIT_ATU_DEFAULT; | |
385 | if (str) { | |
386 | while (*str != '\0') { | |
387 | switch (*str) { | |
388 | case 'y': | |
389 | case 'Y': | |
390 | init_atu = IOP3XX_INIT_ATU_ENABLE; | |
391 | break; | |
392 | case 'n': | |
393 | case 'N': | |
394 | init_atu = IOP3XX_INIT_ATU_DISABLE; | |
395 | break; | |
396 | case ',': | |
397 | case '=': | |
398 | break; | |
399 | default: | |
400 | printk(KERN_DEBUG "\"%s\" malformed at " | |
401 | "character: \'%c\'", | |
8e86f427 | 402 | __func__, |
e90ddd81 DW |
403 | *str); |
404 | *(str + 1) = '\0'; | |
405 | } | |
406 | str++; | |
407 | } | |
408 | } | |
409 | ||
410 | return 1; | |
411 | } | |
412 | ||
413 | __setup("iop3xx_init_atu", iop3xx_init_atu_setup); | |
414 |