projects / linux-block.git / blame
| Commit | Line | Data |
|---|---|---|
| d2912cb1 | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
| 2ccdd1e7 CM |
2 | /* |
| 3 | * linux/arch/arm/mm/tlb-v7.S | |
| 4 | * | |
| 5 | * Copyright (C) 1997-2002 Russell King | |
| 6 | * Modified for ARMv7 by Catalin Marinas | |
| 7 | * | |
| 2ccdd1e7 CM |
8 | * ARM architecture version 6 TLB handling functions. |
| 9 | * These assume a split I/D TLB. | |
| 10 | */ | |
| 991da17e | 11 | #include <linux/init.h> |
| 2ccdd1e7 | 12 | #include <linux/linkage.h> |
| 6b0ef279 | 13 | #include <linux/cfi_types.h> |
| f00ec48f | 14 | #include <asm/assembler.h> |
| 2ccdd1e7 CM |
15 | #include <asm/asm-offsets.h> |
| 16 | #include <asm/page.h> | |
| 17 | #include <asm/tlbflush.h> | |
| 18 | #include "proc-macros.S" | |
| 19 | ||
| a2faac39 ND |
20 | .arch armv7-a |
| 21 | ||
| 2ccdd1e7 CM |
22 | /* |
| 23 | * v7wbi_flush_user_tlb_range(start, end, vma) | |
| 24 | * | |
| 25 | * Invalidate a range of TLB entries in the specified address space. | |
| 26 | * | |
| 27 | * - start - start address (may not be aligned) | |
| 28 | * - end - end address (exclusive, may not be aligned) | |
| 5673a60b | 29 | * - vma - vm_area_struct describing address range |
| 2ccdd1e7 CM |
30 | * |
| 31 | * It is assumed that: | |
| 32 | * - the "Invalidate single entry" instruction will invalidate | |
| 33 | * both the I and the D TLBs on Harvard-style TLBs | |
| 34 | */ | |
| 6b0ef279 | 35 | SYM_TYPED_FUNC_START(v7wbi_flush_user_tlb_range) |
| 2ccdd1e7 CM |
36 | vma_vm_mm r3, r2 @ get vma->vm_mm |
| 37 | mmid r3, r3 @ get vm_mm->context.id | |
| 6abdd491 | 38 | dsb ish |
| 2ccdd1e7 CM |
39 | mov r0, r0, lsr #PAGE_SHIFT @ align address |
| 40 | mov r1, r1, lsr #PAGE_SHIFT | |
| 41 | asid r3, r3 @ mask ASID | |
| 730a8128 WD |
42 | #ifdef CONFIG_ARM_ERRATA_720789 |
| 43 | ALT_SMP(W(mov) r3, #0 ) | |
| 44 | ALT_UP(W(nop) ) | |
| 5a783cbc | 45 | #endif |
| 2ccdd1e7 CM |
46 | orr r0, r3, r0, lsl #PAGE_SHIFT @ Create initial MVA |
| 47 | mov r1, r1, lsl #PAGE_SHIFT | |
| 2ccdd1e7 | 48 | 1: |
| 5a783cbc WD |
49 | #ifdef CONFIG_ARM_ERRATA_720789 |
| 50 | ALT_SMP(mcr p15, 0, r0, c8, c3, 3) @ TLB invalidate U MVA all ASID (shareable) | |
| 51 | #else | |
| f00ec48f | 52 | ALT_SMP(mcr p15, 0, r0, c8, c3, 1) @ TLB invalidate U MVA (shareable) |
| 5a783cbc | 53 | #endif |
| f00ec48f RK |
54 | ALT_UP(mcr p15, 0, r0, c8, c7, 1) @ TLB invalidate U MVA |
| 55 | ||
| 2ccdd1e7 CM |
56 | add r0, r0, #PAGE_SZ |
| 57 | cmp r0, r1 | |
| 58 | blo 1b | |
| 6abdd491 | 59 | dsb ish |
| 6ebbf2ce | 60 | ret lr |
| 6b0ef279 | 61 | SYM_FUNC_END(v7wbi_flush_user_tlb_range) |
| 2ccdd1e7 CM |
62 | |
| 63 | /* | |
| 64 | * v7wbi_flush_kern_tlb_range(start,end) | |
| 65 | * | |
| 66 | * Invalidate a range of kernel TLB entries | |
| 67 | * | |
| 68 | * - start - start address (may not be aligned) | |
| 69 | * - end - end address (exclusive, may not be aligned) | |
| 70 | */ | |
| 6b0ef279 | 71 | SYM_TYPED_FUNC_START(v7wbi_flush_kern_tlb_range) |
| 6abdd491 | 72 | dsb ish |
| 2ccdd1e7 CM |
73 | mov r0, r0, lsr #PAGE_SHIFT @ align address |
| 74 | mov r1, r1, lsr #PAGE_SHIFT | |
| 75 | mov r0, r0, lsl #PAGE_SHIFT | |
| 76 | mov r1, r1, lsl #PAGE_SHIFT | |
| 77 | 1: | |
| 5a783cbc WD |
78 | #ifdef CONFIG_ARM_ERRATA_720789 |
| 79 | ALT_SMP(mcr p15, 0, r0, c8, c3, 3) @ TLB invalidate U MVA all ASID (shareable) | |
| 80 | #else | |
| f00ec48f | 81 | ALT_SMP(mcr p15, 0, r0, c8, c3, 1) @ TLB invalidate U MVA (shareable) |
| 5a783cbc | 82 | #endif |
| f00ec48f | 83 | ALT_UP(mcr p15, 0, r0, c8, c7, 1) @ TLB invalidate U MVA |
| 2ccdd1e7 CM |
84 | add r0, r0, #PAGE_SZ |
| 85 | cmp r0, r1 | |
| 86 | blo 1b | |
| 6abdd491 | 87 | dsb ish |
| 2ccdd1e7 | 88 | isb |
| 6ebbf2ce | 89 | ret lr |
| 6b0ef279 | 90 | SYM_FUNC_END(v7wbi_flush_kern_tlb_range) |