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d2912cb1 | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
1da177e4 LT |
2 | /* |
3 | * linux/arch/arm/mm/tlbv4wb.S | |
4 | * | |
5 | * Copyright (C) 1997-2002 Russell King | |
6 | * | |
1da177e4 LT |
7 | * ARM architecture version 4 TLB handling functions. |
8 | * These assume a split I/D TLBs w/o I TLB entry, with a write buffer. | |
9 | * | |
10 | * Processors: SA110 SA1100 SA1110 | |
11 | */ | |
12 | #include <linux/linkage.h> | |
13 | #include <linux/init.h> | |
6b0ef279 | 14 | #include <linux/cfi_types.h> |
6ebbf2ce | 15 | #include <asm/assembler.h> |
e6ae744d | 16 | #include <asm/asm-offsets.h> |
1da177e4 LT |
17 | #include <asm/tlbflush.h> |
18 | #include "proc-macros.S" | |
19 | ||
20 | .align 5 | |
21 | /* | |
22 | * v4wb_flush_user_tlb_range(start, end, mm) | |
23 | * | |
24 | * Invalidate a range of TLB entries in the specified address space. | |
25 | * | |
26 | * - start - range start address | |
27 | * - end - range end address | |
28 | * - mm - mm_struct describing address space | |
29 | */ | |
30 | .align 5 | |
6b0ef279 | 31 | SYM_TYPED_FUNC_START(v4wb_flush_user_tlb_range) |
1da177e4 LT |
32 | vma_vm_mm ip, r2 |
33 | act_mm r3 @ get current->active_mm | |
34 | eors r3, ip, r3 @ == mm ? | |
6ebbf2ce | 35 | retne lr @ no, we dont do anything |
1da177e4 LT |
36 | vma_vm_flags r2, r2 |
37 | mcr p15, 0, r3, c7, c10, 4 @ drain WB | |
38 | tst r2, #VM_EXEC | |
39 | mcrne p15, 0, r3, c8, c5, 0 @ invalidate I TLB | |
40 | bic r0, r0, #0x0ff | |
41 | bic r0, r0, #0xf00 | |
42 | 1: mcr p15, 0, r0, c8, c6, 1 @ invalidate D TLB entry | |
43 | add r0, r0, #PAGE_SZ | |
44 | cmp r0, r1 | |
45 | blo 1b | |
6ebbf2ce | 46 | ret lr |
6b0ef279 | 47 | SYM_FUNC_END(v4wb_flush_user_tlb_range) |
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48 | |
49 | /* | |
50 | * v4_flush_kern_tlb_range(start, end) | |
51 | * | |
52 | * Invalidate a range of TLB entries in the specified kernel | |
53 | * address range. | |
54 | * | |
55 | * - start - virtual address (may not be aligned) | |
56 | * - end - virtual address (may not be aligned) | |
57 | */ | |
6b0ef279 | 58 | SYM_TYPED_FUNC_START(v4wb_flush_kern_tlb_range) |
1da177e4 LT |
59 | mov r3, #0 |
60 | mcr p15, 0, r3, c7, c10, 4 @ drain WB | |
61 | bic r0, r0, #0x0ff | |
62 | bic r0, r0, #0xf00 | |
63 | mcr p15, 0, r3, c8, c5, 0 @ invalidate I TLB | |
64 | 1: mcr p15, 0, r0, c8, c6, 1 @ invalidate D TLB entry | |
65 | add r0, r0, #PAGE_SZ | |
66 | cmp r0, r1 | |
67 | blo 1b | |
6ebbf2ce | 68 | ret lr |
6b0ef279 | 69 | SYM_FUNC_END(v4wb_flush_kern_tlb_range) |