[linux-2.6-block.git] / arch / arm / mm / proc-xsc3.S

/* SPDX-License-Identifier: GPL-2.0-only */
/*
 * linux/arch/arm/mm/proc-xsc3.S
 *
 * Original Author: Matthew Gilbert
 * Current Maintainer: Lennert Buytenhek <buytenh@wantstofly.org>
 *
 * Copyright 2004 (C) Intel Corp.
 * Copyright 2005 (C) MontaVista Software, Inc.
 *
 * MMU functions for the Intel XScale3 Core (XSC3).  The XSC3 core is
 * an extension to Intel's original XScale core that adds the following
 * features:
 *
 * - ARMv6 Supersections
 * - Low Locality Reference pages (replaces mini-cache)
 * - 36-bit addressing
 * - L2 cache
 * - Cache coherency if chipset supports it
 *
 * Based on original XScale code by Nicolas Pitre.
 */

#include <linux/linkage.h>
#include <linux/init.h>
#include <linux/cfi_types.h>
#include <linux/pgtable.h>
#include <asm/assembler.h>
#include <asm/hwcap.h>
#include <asm/pgtable-hwdef.h>
#include <asm/page.h>
#include <asm/ptrace.h>
#include "proc-macros.S"

/*
 * This is the maximum size of an area which will be flushed.  If the
 * area is larger than this, then we flush the whole cache.
 */
#define MAX_AREA_SIZE	32768

/*
 * The cache line size of the L1 I, L1 D and unified L2 cache.
 */
#define CACHELINESIZE	32

/*
 * The size of the L1 D cache.
 */
#define CACHESIZE	32768

/*
 * This macro is used to wait for a CP15 write and is needed when we
 * have to ensure that the last operation to the coprocessor was
 * completed before continuing with operation.
 */
	.macro	cpwait_ret, lr, rd
	mrc	p15, 0, \rd, c2, c0, 0		@ arbitrary read of cp15
	sub	pc, \lr, \rd, LSR #32		@ wait for completion and
						@ flush instruction pipeline
	.endm

/*
 * This macro cleans and invalidates the entire L1 D cache.
 */

 	.macro  clean_d_cache rd, rs
	mov	\rd, #0x1f00
	orr	\rd, \rd, #0x00e0
1:	mcr	p15, 0, \rd, c7, c14, 2		@ clean/invalidate L1 D line
	adds	\rd, \rd, #0x40000000
	bcc	1b
	subs	\rd, \rd, #0x20
	bpl	1b
	.endm

	.text

/*
 * cpu_xsc3_proc_init()
 *
 * Nothing too exciting at the moment
 */
SYM_TYPED_FUNC_START(cpu_xsc3_proc_init)
	ret	lr
SYM_FUNC_END(cpu_xsc3_proc_init)

/*
 * cpu_xsc3_proc_fin()
 */
SYM_TYPED_FUNC_START(cpu_xsc3_proc_fin)
	mrc	p15, 0, r0, c1, c0, 0		@ ctrl register
	bic	r0, r0, #0x1800			@ ...IZ...........
	bic	r0, r0, #0x0006			@ .............CA.
	mcr	p15, 0, r0, c1, c0, 0		@ disable caches
	ret	lr
SYM_FUNC_END(cpu_xsc3_proc_fin)

/*
 * cpu_xsc3_reset(loc)
 *
 * Perform a soft reset of the system.  Put the CPU into the
 * same state as it would be if it had been reset, and branch
 * to what would be the reset vector.
 *
 * loc: location to jump to for soft reset
 */
	.align	5
	.pushsection	.idmap.text, "ax"
SYM_TYPED_FUNC_START(cpu_xsc3_reset)
	mov	r1, #PSR_F_BIT|PSR_I_BIT|SVC_MODE
	msr	cpsr_c, r1			@ reset CPSR
	mrc	p15, 0, r1, c1, c0, 0		@ ctrl register
	bic	r1, r1, #0x3900			@ ..VIZ..S........
	bic	r1, r1, #0x0086			@ ........B....CA.
	mcr	p15, 0, r1, c1, c0, 0		@ ctrl register
	mcr	p15, 0, ip, c7, c7, 0		@ invalidate L1 caches and BTB
	bic	r1, r1, #0x0001			@ ...............M
	mcr	p15, 0, r1, c1, c0, 0		@ ctrl register
	@ CAUTION: MMU turned off from this point.  We count on the pipeline
	@ already containing those two last instructions to survive.
	mcr	p15, 0, ip, c8, c7, 0		@ invalidate I and D TLBs
	ret	r0
SYM_FUNC_END(cpu_xsc3_reset)
	.popsection

/*
 * cpu_xsc3_do_idle()
 *
 * Cause the processor to idle
 *
 * For now we do nothing but go to idle mode for every case
 *
 * XScale supports clock switching, but using idle mode support
 * allows external hardware to react to system state changes.
 */
	.align	5

SYM_TYPED_FUNC_START(cpu_xsc3_do_idle)
	mov	r0, #1
	mcr	p14, 0, r0, c7, c0, 0		@ go to idle
	ret	lr
SYM_FUNC_END(cpu_xsc3_do_idle)

/* ================================= CACHE ================================ */

/*
 *	flush_icache_all()
 *
 *	Unconditionally clean and invalidate the entire icache.
 */
SYM_TYPED_FUNC_START(xsc3_flush_icache_all)
	mov	r0, #0
	mcr	p15, 0, r0, c7, c5, 0		@ invalidate I cache
	ret	lr
SYM_FUNC_END(xsc3_flush_icache_all)

/*
 *	flush_user_cache_all()
 *
 *	Invalidate all cache entries in a particular address
 *	space.
 */
SYM_FUNC_ALIAS(xsc3_flush_user_cache_all, xsc3_flush_kern_cache_all)

/*
 *	flush_kern_cache_all()
 *
 *	Clean and invalidate the entire cache.
 */
SYM_TYPED_FUNC_START(xsc3_flush_kern_cache_all)
	mov	r2, #VM_EXEC
	mov	ip, #0
__flush_whole_cache:
	clean_d_cache r0, r1
	tst	r2, #VM_EXEC
	mcrne	p15, 0, ip, c7, c5, 0		@ invalidate L1 I cache and BTB
	mcrne	p15, 0, ip, c7, c10, 4		@ data write barrier
	mcrne	p15, 0, ip, c7, c5, 4		@ prefetch flush
	ret	lr
SYM_FUNC_END(xsc3_flush_kern_cache_all)

/*
 *	flush_user_cache_range(start, end, vm_flags)
 *
 *	Invalidate a range of cache entries in the specified
 *	address space.
 *
 *	- start - start address (may not be aligned)
 *	- end	- end address (exclusive, may not be aligned)
 *	- vma	- vma_area_struct describing address space
 */
	.align	5
SYM_TYPED_FUNC_START(xsc3_flush_user_cache_range)
	mov	ip, #0
	sub	r3, r1, r0			@ calculate total size
	cmp	r3, #MAX_AREA_SIZE
	bhs	__flush_whole_cache

1:	tst	r2, #VM_EXEC
	mcrne	p15, 0, r0, c7, c5, 1		@ invalidate L1 I line
	mcr	p15, 0, r0, c7, c14, 1		@ clean/invalidate L1 D line
	add	r0, r0, #CACHELINESIZE
	cmp	r0, r1
	blo	1b
	tst	r2, #VM_EXEC
	mcrne	p15, 0, ip, c7, c5, 6		@ invalidate BTB
	mcrne	p15, 0, ip, c7, c10, 4		@ data write barrier
	mcrne	p15, 0, ip, c7, c5, 4		@ prefetch flush
	ret	lr
SYM_FUNC_END(xsc3_flush_user_cache_range)

/*
 *	coherent_kern_range(start, end)
 *
 *	Ensure coherency between the I cache and the D cache in the
 *	region described by start.  If you have non-snooping
 *	Harvard caches, you need to implement this function.
 *
 *	- start  - virtual start address
 *	- end	 - virtual end address
 *
 *	Note: single I-cache line invalidation isn't used here since
 *	it also trashes the mini I-cache used by JTAG debuggers.
 */
SYM_TYPED_FUNC_START(xsc3_coherent_kern_range)
#ifdef CONFIG_CFI_CLANG /* Fallthrough if !CFI */
	b	xsc3_coherent_user_range
#endif
SYM_FUNC_END(xsc3_coherent_kern_range)

SYM_TYPED_FUNC_START(xsc3_coherent_user_range)
	bic	r0, r0, #CACHELINESIZE - 1
1:	mcr	p15, 0, r0, c7, c10, 1		@ clean L1 D line
	add	r0, r0, #CACHELINESIZE
	cmp	r0, r1
	blo	1b
	mov	r0, #0
	mcr	p15, 0, r0, c7, c5, 0		@ invalidate L1 I cache and BTB
	mcr	p15, 0, r0, c7, c10, 4		@ data write barrier
	mcr	p15, 0, r0, c7, c5, 4		@ prefetch flush
	ret	lr
SYM_FUNC_END(xsc3_coherent_user_range)

/*
 *	flush_kern_dcache_area(void *addr, size_t size)
 *
 *	Ensure no D cache aliasing occurs, either with itself or
 *	the I cache.
 *
 *	- addr	- kernel address
 *	- size	- region size
 */
SYM_TYPED_FUNC_START(xsc3_flush_kern_dcache_area)
	add	r1, r0, r1
1:	mcr	p15, 0, r0, c7, c14, 1		@ clean/invalidate L1 D line
	add	r0, r0, #CACHELINESIZE
	cmp	r0, r1
	blo	1b
	mov	r0, #0
	mcr	p15, 0, r0, c7, c5, 0		@ invalidate L1 I cache and BTB
	mcr	p15, 0, r0, c7, c10, 4		@ data write barrier
	mcr	p15, 0, r0, c7, c5, 4		@ prefetch flush
	ret	lr
SYM_FUNC_END(xsc3_flush_kern_dcache_area)

/*
 *	dma_inv_range(start, end)
 *
 *	Invalidate (discard) the specified virtual address range.
 *	May not write back any entries.  If 'start' or 'end'
 *	are not cache line aligned, those lines must be written
 *	back.
 *
 *	- start  - virtual start address
 *	- end	 - virtual end address
 */
xsc3_dma_inv_range:
	tst	r0, #CACHELINESIZE - 1
	bic	r0, r0, #CACHELINESIZE - 1
	mcrne	p15, 0, r0, c7, c10, 1		@ clean L1 D line
	tst	r1, #CACHELINESIZE - 1
	mcrne	p15, 0, r1, c7, c10, 1		@ clean L1 D line
1:	mcr	p15, 0, r0, c7, c6, 1		@ invalidate L1 D line
	add	r0, r0, #CACHELINESIZE
	cmp	r0, r1
	blo	1b
	mcr	p15, 0, r0, c7, c10, 4		@ data write barrier
	ret	lr

/*
 *	dma_clean_range(start, end)
 *
 *	Clean the specified virtual address range.
 *
 *	- start  - virtual start address
 *	- end	 - virtual end address
 */
xsc3_dma_clean_range:
	bic	r0, r0, #CACHELINESIZE - 1
1:	mcr	p15, 0, r0, c7, c10, 1		@ clean L1 D line
	add	r0, r0, #CACHELINESIZE
	cmp	r0, r1
	blo	1b
	mcr	p15, 0, r0, c7, c10, 4		@ data write barrier
	ret	lr

/*
 *	dma_flush_range(start, end)
 *
 *	Clean and invalidate the specified virtual address range.
 *
 *	- start  - virtual start address
 *	- end	 - virtual end address
 */
SYM_TYPED_FUNC_START(xsc3_dma_flush_range)
	bic	r0, r0, #CACHELINESIZE - 1
1:	mcr	p15, 0, r0, c7, c14, 1		@ clean/invalidate L1 D line
	add	r0, r0, #CACHELINESIZE
	cmp	r0, r1
	blo	1b
	mcr	p15, 0, r0, c7, c10, 4		@ data write barrier
	ret	lr
SYM_FUNC_END(xsc3_dma_flush_range)

/*
 *	dma_map_area(start, size, dir)
 *	- start	- kernel virtual start address
 *	- size	- size of region
 *	- dir	- DMA direction
 */
SYM_TYPED_FUNC_START(xsc3_dma_map_area)
	add	r1, r1, r0
	cmp	r2, #DMA_TO_DEVICE
	beq	xsc3_dma_clean_range
	bcs	xsc3_dma_inv_range
	b	xsc3_dma_flush_range
SYM_FUNC_END(xsc3_dma_map_area)

/*
 *	dma_unmap_area(start, size, dir)
 *	- start	- kernel virtual start address
 *	- size	- size of region
 *	- dir	- DMA direction
 */
SYM_TYPED_FUNC_START(xsc3_dma_unmap_area)
	ret	lr
SYM_FUNC_END(xsc3_dma_unmap_area)

SYM_TYPED_FUNC_START(cpu_xsc3_dcache_clean_area)
1:	mcr	p15, 0, r0, c7, c10, 1		@ clean L1 D line
	add	r0, r0, #CACHELINESIZE
	subs	r1, r1, #CACHELINESIZE
	bhi	1b
	ret	lr
SYM_FUNC_END(cpu_xsc3_dcache_clean_area)

/* =============================== PageTable ============================== */

/*
 * cpu_xsc3_switch_mm(pgd)
 *
 * Set the translation base pointer to be as described by pgd.
 *
 * pgd: new page tables
 */
	.align	5
SYM_TYPED_FUNC_START(cpu_xsc3_switch_mm)
	clean_d_cache r1, r2
	mcr	p15, 0, ip, c7, c5, 0		@ invalidate L1 I cache and BTB
	mcr	p15, 0, ip, c7, c10, 4		@ data write barrier
	mcr	p15, 0, ip, c7, c5, 4		@ prefetch flush
	orr	r0, r0, #0x18			@ cache the page table in L2
	mcr	p15, 0, r0, c2, c0, 0		@ load page table pointer
	mcr	p15, 0, ip, c8, c7, 0		@ invalidate I and D TLBs
	cpwait_ret lr, ip
SYM_FUNC_END(cpu_xsc3_switch_mm)

/*
 * cpu_xsc3_set_pte_ext(ptep, pte, ext)
 *
 * Set a PTE and flush it out
 */
cpu_xsc3_mt_table:
	.long	0x00						@ L_PTE_MT_UNCACHED
	.long	PTE_EXT_TEX(1)					@ L_PTE_MT_BUFFERABLE
	.long	PTE_EXT_TEX(5) | PTE_CACHEABLE			@ L_PTE_MT_WRITETHROUGH
	.long	PTE_CACHEABLE | PTE_BUFFERABLE			@ L_PTE_MT_WRITEBACK
	.long	PTE_EXT_TEX(1) | PTE_BUFFERABLE			@ L_PTE_MT_DEV_SHARED
	.long	0x00						@ unused
	.long	0x00						@ L_PTE_MT_MINICACHE (not present)
	.long	PTE_EXT_TEX(5) | PTE_CACHEABLE | PTE_BUFFERABLE	@ L_PTE_MT_WRITEALLOC (not present?)
	.long	0x00						@ unused
	.long	PTE_EXT_TEX(1)					@ L_PTE_MT_DEV_WC
	.long	0x00						@ unused
	.long	PTE_CACHEABLE | PTE_BUFFERABLE			@ L_PTE_MT_DEV_CACHED
	.long	PTE_EXT_TEX(2)					@ L_PTE_MT_DEV_NONSHARED
	.long	0x00						@ unused
	.long	0x00						@ unused
	.long	0x00						@ unused

	.align	5
SYM_TYPED_FUNC_START(cpu_xsc3_set_pte_ext)
	xscale_set_pte_ext_prologue

	tst	r1, #L_PTE_SHARED		@ shared?
	and	r1, r1, #L_PTE_MT_MASK
	adr	ip, cpu_xsc3_mt_table
	ldr	ip, [ip, r1]
	orrne	r2, r2, #PTE_EXT_COHERENT	@ interlock: mask in coherent bit
	bic	r2, r2, #0x0c			@ clear old C,B bits
	orr	r2, r2, ip

	xscale_set_pte_ext_epilogue
	ret	lr
SYM_FUNC_END(cpu_xsc3_set_pte_ext)

	.ltorg
	.align

.globl	cpu_xsc3_suspend_size
.equ	cpu_xsc3_suspend_size, 4 * 6
#ifdef CONFIG_ARM_CPU_SUSPEND
SYM_TYPED_FUNC_START(cpu_xsc3_do_suspend)
	stmfd	sp!, {r4 - r9, lr}
	mrc	p14, 0, r4, c6, c0, 0	@ clock configuration, for turbo mode
	mrc	p15, 0, r5, c15, c1, 0	@ CP access reg
	mrc	p15, 0, r6, c13, c0, 0	@ PID
	mrc 	p15, 0, r7, c3, c0, 0	@ domain ID
	mrc	p15, 0, r8, c1, c0, 1	@ auxiliary control reg
	mrc 	p15, 0, r9, c1, c0, 0	@ control reg
	bic	r4, r4, #2		@ clear frequency change bit
	stmia	r0, {r4 - r9}		@ store cp regs
	ldmia	sp!, {r4 - r9, pc}
SYM_FUNC_END(cpu_xsc3_do_suspend)

SYM_TYPED_FUNC_START(cpu_xsc3_do_resume)
	ldmia	r0, {r4 - r9}		@ load cp regs
	mov	ip, #0
	mcr	p15, 0, ip, c7, c7, 0	@ invalidate I & D caches, BTB
	mcr	p15, 0, ip, c7, c10, 4	@ drain write (&fill) buffer
	mcr	p15, 0, ip, c7, c5, 4	@ flush prefetch buffer
	mcr	p15, 0, ip, c8, c7, 0	@ invalidate I & D TLBs
	mcr	p14, 0, r4, c6, c0, 0	@ clock configuration, turbo mode.
	mcr	p15, 0, r5, c15, c1, 0	@ CP access reg
	mcr	p15, 0, r6, c13, c0, 0	@ PID
	mcr	p15, 0, r7, c3, c0, 0	@ domain ID
	orr	r1, r1, #0x18		@ cache the page table in L2
	mcr	p15, 0, r1, c2, c0, 0	@ translation table base addr
	mcr	p15, 0, r8, c1, c0, 1	@ auxiliary control reg
	mov	r0, r9			@ control register
	b	cpu_resume_mmu
SYM_FUNC_END(cpu_xsc3_do_resume)
#endif

	.type	__xsc3_setup, #function
__xsc3_setup:
	mov	r0, #PSR_F_BIT|PSR_I_BIT|SVC_MODE
	msr	cpsr_c, r0
	mcr	p15, 0, ip, c7, c7, 0		@ invalidate L1 caches and BTB
	mcr	p15, 0, ip, c7, c10, 4		@ data write barrier
	mcr	p15, 0, ip, c7, c5, 4		@ prefetch flush
	mcr	p15, 0, ip, c8, c7, 0		@ invalidate I and D TLBs
	orr	r4, r4, #0x18			@ cache the page table in L2
	mcr	p15, 0, r4, c2, c0, 0		@ load page table pointer

	mov	r0, #1 << 6			@ cp6 access for early sched_clock
	mcr	p15, 0, r0, c15, c1, 0		@ write CP access register

	mrc	p15, 0, r0, c1, c0, 1		@ get auxiliary control reg
	and	r0, r0, #2			@ preserve bit P bit setting
	orr	r0, r0, #(1 << 10)		@ enable L2 for LLR cache
	mcr	p15, 0, r0, c1, c0, 1		@ set auxiliary control reg

	adr	r5, xsc3_crval
	ldmia	r5, {r5, r6}

#ifdef CONFIG_CACHE_XSC3L2
	mrc	p15, 1, r0, c0, c0, 1		@ get L2 present information
	ands	r0, r0, #0xf8
	orrne	r6, r6, #(1 << 26)		@ enable L2 if present
#endif

	mrc	p15, 0, r0, c1, c0, 0		@ get control register
	bic	r0, r0, r5			@ ..V. ..R. .... ..A.
	orr	r0, r0, r6			@ ..VI Z..S .... .C.M (mmu)
						@ ...I Z..S .... .... (uc)
	ret	lr

	.size	__xsc3_setup, . - __xsc3_setup

	.type	xsc3_crval, #object
xsc3_crval:
	crval	clear=0x04002202, mmuset=0x00003905, ucset=0x00001900

	__INITDATA

	@ define struct processor (see <asm/proc-fns.h> and proc-macros.S)
	define_processor_functions xsc3, dabort=v5t_early_abort, pabort=legacy_pabort, suspend=1

	.section ".rodata"

	string	cpu_arch_name, "armv5te"
	string	cpu_elf_name, "v5"
	string	cpu_xsc3_name, "XScale-V3 based processor"

	.align

	.section ".proc.info.init", "a"

.macro xsc3_proc_info name:req, cpu_val:req, cpu_mask:req
	.type	__\name\()_proc_info,#object
__\name\()_proc_info:
	.long	\cpu_val
	.long	\cpu_mask
	.long	PMD_TYPE_SECT | \
		PMD_SECT_BUFFERABLE | \
		PMD_SECT_CACHEABLE | \
		PMD_SECT_AP_WRITE | \
		PMD_SECT_AP_READ
	.long	PMD_TYPE_SECT | \
		PMD_SECT_AP_WRITE | \
		PMD_SECT_AP_READ
	initfn	__xsc3_setup, __\name\()_proc_info
	.long	cpu_arch_name
	.long	cpu_elf_name
	.long	HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
	.long	cpu_xsc3_name
	.long	xsc3_processor_functions
	.long	v4wbi_tlb_fns
	.long	xsc3_mc_user_fns
	.long	xsc3_cache_fns
	.size	__\name\()_proc_info, . - __\name\()_proc_info
.endm

	xsc3_proc_info xsc3, 0x69056000, 0xffffe000

/* Note: PXA935 changed its implementor ID from Intel to Marvell */
	xsc3_proc_info xsc3_pxa935, 0x56056000, 0xffffe000
Commit	Line	Data
d2912cb1	1	/* SPDX-License-Identifier: GPL-2.0-only */
23bdf86a LB	2	/*
	3	* linux/arch/arm/mm/proc-xsc3.S
	4	*
	5	* Original Author: Matthew Gilbert
57fee39f	6	* Current Maintainer: Lennert Buytenhek <buytenh@wantstofly.org>
23bdf86a LB	7	*
23bdf86a LB	8	* Copyright 2004 (C) Intel Corp.
850b4293	9	* Copyright 2005 (C) MontaVista Software, Inc.
23bdf86a	10	*
850b4293 LB	11	* MMU functions for the Intel XScale3 Core (XSC3). The XSC3 core is
850b4293 LB	12	* an extension to Intel's original XScale core that adds the following
23bdf86a LB	13	* features:
	14	*
	15	* - ARMv6 Supersections
	16	* - Low Locality Reference pages (replaces mini-cache)
	17	* - 36-bit addressing
	18	* - L2 cache
850b4293	19	* - Cache coherency if chipset supports it
23bdf86a	20	*
850b4293	21	* Based on original XScale code by Nicolas Pitre.
23bdf86a LB	22	*/
	23
	24	#include <linux/linkage.h>
	25	#include <linux/init.h>
1036b895	26	#include <linux/cfi_types.h>
65fddcfc	27	#include <linux/pgtable.h>
23bdf86a	28	#include <asm/assembler.h>
5ec9407d	29	#include <asm/hwcap.h>
b48340af	30	#include <asm/pgtable-hwdef.h>
23bdf86a LB	31	#include <asm/page.h>
	32	#include <asm/ptrace.h>
	33	#include "proc-macros.S"
	34
	35	/*
	36	* This is the maximum size of an area which will be flushed. If the
	37	* area is larger than this, then we flush the whole cache.
	38	*/
	39	#define MAX_AREA_SIZE 32768
	40
	41	/*
850b4293	42	* The cache line size of the L1 I, L1 D and unified L2 cache.
23bdf86a LB	43	*/
	44	#define CACHELINESIZE 32
	45
	46	/*
850b4293	47	* The size of the L1 D cache.
23bdf86a LB	48	*/
	49	#define CACHESIZE 32768
	50
23bdf86a	51	/*
850b4293 LB	52	* This macro is used to wait for a CP15 write and is needed when we
	53	* have to ensure that the last operation to the coprocessor was
	54	* completed before continuing with operation.
23bdf86a LB	55	*/
	56	.macro cpwait_ret, lr, rd
	57	mrc p15, 0, \rd, c2, c0, 0 @ arbitrary read of cp15
	58	sub pc, \lr, \rd, LSR #32 @ wait for completion and
	59	@ flush instruction pipeline
	60	.endm
	61
	62	/*
850b4293	63	* This macro cleans and invalidates the entire L1 D cache.
23bdf86a LB	64	*/
	65
	66	.macro clean_d_cache rd, rs
	67	mov \rd, #0x1f00
	68	orr \rd, \rd, #0x00e0
850b4293	69	1: mcr p15, 0, \rd, c7, c14, 2 @ clean/invalidate L1 D line
23bdf86a LB	70	adds \rd, \rd, #0x40000000
	71	bcc 1b
	72	subs \rd, \rd, #0x20
	73	bpl 1b
	74	.endm
	75
	76	.text
	77
	78	/*
	79	* cpu_xsc3_proc_init()
	80	*
	81	* Nothing too exciting at the moment
	82	*/
51db13aa	83	SYM_TYPED_FUNC_START(cpu_xsc3_proc_init)
6ebbf2ce	84	ret lr
51db13aa	85	SYM_FUNC_END(cpu_xsc3_proc_init)
23bdf86a LB	86
	87	/*
	88	* cpu_xsc3_proc_fin()
	89	*/
51db13aa	90	SYM_TYPED_FUNC_START(cpu_xsc3_proc_fin)
23bdf86a LB	91	mrc p15, 0, r0, c1, c0, 0 @ ctrl register
	92	bic r0, r0, #0x1800 @ ...IZ...........
	93	bic r0, r0, #0x0006 @ .............CA.
	94	mcr p15, 0, r0, c1, c0, 0 @ disable caches
6ebbf2ce	95	ret lr
51db13aa	96	SYM_FUNC_END(cpu_xsc3_proc_fin)
23bdf86a LB	97
	98	/*
	99	* cpu_xsc3_reset(loc)
	100	*
	101	* Perform a soft reset of the system. Put the CPU into the
	102	* same state as it would be if it had been reset, and branch
	103	* to what would be the reset vector.
	104	*
	105	* loc: location to jump to for soft reset
	106	*/
	107	.align 5
1a4baafa	108	.pushsection .idmap.text, "ax"
51db13aa	109	SYM_TYPED_FUNC_START(cpu_xsc3_reset)
23bdf86a LB	110	mov r1, #PSR_F_BIT\|PSR_I_BIT\|SVC_MODE
	111	msr cpsr_c, r1 @ reset CPSR
	112	mrc p15, 0, r1, c1, c0, 0 @ ctrl register
23bdf86a	113	bic r1, r1, #0x3900 @ ..VIZ..S........
850b4293	114	bic r1, r1, #0x0086 @ ........B....CA.
23bdf86a	115	mcr p15, 0, r1, c1, c0, 0 @ ctrl register
850b4293	116	mcr p15, 0, ip, c7, c7, 0 @ invalidate L1 caches and BTB
23bdf86a LB	117	bic r1, r1, #0x0001 @ ...............M
	118	mcr p15, 0, r1, c1, c0, 0 @ ctrl register
	119	@ CAUTION: MMU turned off from this point. We count on the pipeline
	120	@ already containing those two last instructions to survive.
850b4293	121	mcr p15, 0, ip, c8, c7, 0 @ invalidate I and D TLBs
6ebbf2ce	122	ret r0
51db13aa	123	SYM_FUNC_END(cpu_xsc3_reset)
1a4baafa	124	.popsection
23bdf86a LB	125
	126	/*
	127	* cpu_xsc3_do_idle()
	128	*
	129	* Cause the processor to idle
	130	*
	131	* For now we do nothing but go to idle mode for every case
	132	*
	133	* XScale supports clock switching, but using idle mode support
	134	* allows external hardware to react to system state changes.
23bdf86a LB	135	*/
	136	.align 5
	137
51db13aa	138	SYM_TYPED_FUNC_START(cpu_xsc3_do_idle)
23bdf86a	139	mov r0, #1
850b4293	140	mcr p14, 0, r0, c7, c0, 0 @ go to idle
6ebbf2ce	141	ret lr
51db13aa	142	SYM_FUNC_END(cpu_xsc3_do_idle)
23bdf86a LB	143
	144	/* ================================= CACHE ================================ */
	145
c8c90860 MW	146	/*
	147	* flush_icache_all()
	148	*
	149	* Unconditionally clean and invalidate the entire icache.
	150	*/
1036b895	151	SYM_TYPED_FUNC_START(xsc3_flush_icache_all)
c8c90860 MW	152	mov r0, #0
c8c90860 MW	153	mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
6ebbf2ce	154	ret lr
1036b895	155	SYM_FUNC_END(xsc3_flush_icache_all)
c8c90860	156
23bdf86a LB	157	/*
	158	* flush_user_cache_all()
	159	*
	160	* Invalidate all cache entries in a particular address
	161	* space.
	162	*/
2074beeb	163	SYM_FUNC_ALIAS(xsc3_flush_user_cache_all, xsc3_flush_kern_cache_all)
23bdf86a LB	164
	165	/*
	166	* flush_kern_cache_all()
	167	*
	168	* Clean and invalidate the entire cache.
	169	*/
1036b895	170	SYM_TYPED_FUNC_START(xsc3_flush_kern_cache_all)
23bdf86a LB	171	mov r2, #VM_EXEC
	172	mov ip, #0
	173	__flush_whole_cache:
	174	clean_d_cache r0, r1
	175	tst r2, #VM_EXEC
850b4293 LB	176	mcrne p15, 0, ip, c7, c5, 0 @ invalidate L1 I cache and BTB
	177	mcrne p15, 0, ip, c7, c10, 4 @ data write barrier
	178	mcrne p15, 0, ip, c7, c5, 4 @ prefetch flush
6ebbf2ce	179	ret lr
1036b895	180	SYM_FUNC_END(xsc3_flush_kern_cache_all)
23bdf86a LB	181
	182	/*
	183	* flush_user_cache_range(start, end, vm_flags)
	184	*
	185	* Invalidate a range of cache entries in the specified
	186	* address space.
	187	*
	188	* - start - start address (may not be aligned)
	189	* - end - end address (exclusive, may not be aligned)
	190	* - vma - vma_area_struct describing address space
	191	*/
	192	.align 5
1036b895	193	SYM_TYPED_FUNC_START(xsc3_flush_user_cache_range)
23bdf86a LB	194	mov ip, #0
	195	sub r3, r1, r0 @ calculate total size
	196	cmp r3, #MAX_AREA_SIZE
	197	bhs __flush_whole_cache
	198
	199	1: tst r2, #VM_EXEC
850b4293 LB	200	mcrne p15, 0, r0, c7, c5, 1 @ invalidate L1 I line
850b4293 LB	201	mcr p15, 0, r0, c7, c14, 1 @ clean/invalidate L1 D line
23bdf86a LB	202	add r0, r0, #CACHELINESIZE
	203	cmp r0, r1
	204	blo 1b
	205	tst r2, #VM_EXEC
850b4293 LB	206	mcrne p15, 0, ip, c7, c5, 6 @ invalidate BTB
	207	mcrne p15, 0, ip, c7, c10, 4 @ data write barrier
	208	mcrne p15, 0, ip, c7, c5, 4 @ prefetch flush
6ebbf2ce	209	ret lr
1036b895	210	SYM_FUNC_END(xsc3_flush_user_cache_range)
23bdf86a LB	211
	212	/*
	213	* coherent_kern_range(start, end)
	214	*
850b4293	215	* Ensure coherency between the I cache and the D cache in the
23bdf86a LB	216	* region described by start. If you have non-snooping
	217	* Harvard caches, you need to implement this function.
	218	*
	219	* - start - virtual start address
	220	* - end - virtual end address
	221	*
	222	* Note: single I-cache line invalidation isn't used here since
	223	* it also trashes the mini I-cache used by JTAG debuggers.
	224	*/
1036b895	225	SYM_TYPED_FUNC_START(xsc3_coherent_kern_range)
7b749aad	226	#ifdef CONFIG_CFI_CLANG /* Fallthrough if !CFI */
1036b895	227	b xsc3_coherent_user_range
7b749aad	228	#endif
1036b895 LW	229	SYM_FUNC_END(xsc3_coherent_kern_range)
	230
	231	SYM_TYPED_FUNC_START(xsc3_coherent_user_range)
23bdf86a	232	bic r0, r0, #CACHELINESIZE - 1
850b4293	233	1: mcr p15, 0, r0, c7, c10, 1 @ clean L1 D line
23bdf86a LB	234	add r0, r0, #CACHELINESIZE
	235	cmp r0, r1
	236	blo 1b
	237	mov r0, #0
850b4293 LB	238	mcr p15, 0, r0, c7, c5, 0 @ invalidate L1 I cache and BTB
	239	mcr p15, 0, r0, c7, c10, 4 @ data write barrier
	240	mcr p15, 0, r0, c7, c5, 4 @ prefetch flush
6ebbf2ce	241	ret lr
1036b895	242	SYM_FUNC_END(xsc3_coherent_user_range)
23bdf86a LB	243
23bdf86a LB	244	/*
2c9b9c84	245	* flush_kern_dcache_area(void *addr, size_t size)
23bdf86a LB	246	*
23bdf86a LB	247	* Ensure no D cache aliasing occurs, either with itself or
850b4293	248	* the I cache.
23bdf86a	249	*
2c9b9c84 RK	250	* - addr - kernel address
2c9b9c84 RK	251	* - size - region size
23bdf86a	252	*/
1036b895	253	SYM_TYPED_FUNC_START(xsc3_flush_kern_dcache_area)
2c9b9c84	254	add r1, r0, r1
850b4293	255	1: mcr p15, 0, r0, c7, c14, 1 @ clean/invalidate L1 D line
23bdf86a LB	256	add r0, r0, #CACHELINESIZE
	257	cmp r0, r1
	258	blo 1b
	259	mov r0, #0
850b4293 LB	260	mcr p15, 0, r0, c7, c5, 0 @ invalidate L1 I cache and BTB
	261	mcr p15, 0, r0, c7, c10, 4 @ data write barrier
	262	mcr p15, 0, r0, c7, c5, 4 @ prefetch flush
6ebbf2ce	263	ret lr
1036b895	264	SYM_FUNC_END(xsc3_flush_kern_dcache_area)
23bdf86a LB	265
	266	/*
	267	* dma_inv_range(start, end)
	268	*
	269	* Invalidate (discard) the specified virtual address range.
	270	* May not write back any entries. If 'start' or 'end'
	271	* are not cache line aligned, those lines must be written
	272	* back.
	273	*
	274	* - start - virtual start address
	275	* - end - virtual end address
	276	*/
702b94bf	277	xsc3_dma_inv_range:
23bdf86a LB	278	tst r0, #CACHELINESIZE - 1
23bdf86a LB	279	bic r0, r0, #CACHELINESIZE - 1
850b4293	280	mcrne p15, 0, r0, c7, c10, 1 @ clean L1 D line
23bdf86a	281	tst r1, #CACHELINESIZE - 1
850b4293	282	mcrne p15, 0, r1, c7, c10, 1 @ clean L1 D line
850b4293	283	1: mcr p15, 0, r0, c7, c6, 1 @ invalidate L1 D line
23bdf86a LB	284	add r0, r0, #CACHELINESIZE
	285	cmp r0, r1
	286	blo 1b
850b4293	287	mcr p15, 0, r0, c7, c10, 4 @ data write barrier
6ebbf2ce	288	ret lr
23bdf86a LB	289
	290	/*
	291	* dma_clean_range(start, end)
	292	*
	293	* Clean the specified virtual address range.
	294	*
	295	* - start - virtual start address
	296	* - end - virtual end address
	297	*/
702b94bf	298	xsc3_dma_clean_range:
23bdf86a	299	bic r0, r0, #CACHELINESIZE - 1
850b4293	300	1: mcr p15, 0, r0, c7, c10, 1 @ clean L1 D line
23bdf86a LB	301	add r0, r0, #CACHELINESIZE
	302	cmp r0, r1
	303	blo 1b
850b4293	304	mcr p15, 0, r0, c7, c10, 4 @ data write barrier
6ebbf2ce	305	ret lr
23bdf86a LB	306
	307	/*
	308	* dma_flush_range(start, end)
	309	*
	310	* Clean and invalidate the specified virtual address range.
	311	*
	312	* - start - virtual start address
	313	* - end - virtual end address
	314	*/
1036b895	315	SYM_TYPED_FUNC_START(xsc3_dma_flush_range)
23bdf86a	316	bic r0, r0, #CACHELINESIZE - 1
850b4293	317	1: mcr p15, 0, r0, c7, c14, 1 @ clean/invalidate L1 D line
23bdf86a LB	318	add r0, r0, #CACHELINESIZE
	319	cmp r0, r1
	320	blo 1b
850b4293	321	mcr p15, 0, r0, c7, c10, 4 @ data write barrier
6ebbf2ce	322	ret lr
1036b895	323	SYM_FUNC_END(xsc3_dma_flush_range)
23bdf86a	324
a9c9147e RK	325	/*
	326	* dma_map_area(start, size, dir)
	327	* - start - kernel virtual start address
	328	* - size - size of region
	329	* - dir - DMA direction
	330	*/
1036b895	331	SYM_TYPED_FUNC_START(xsc3_dma_map_area)
a9c9147e RK	332	add r1, r1, r0
	333	cmp r2, #DMA_TO_DEVICE
	334	beq xsc3_dma_clean_range
	335	bcs xsc3_dma_inv_range
	336	b xsc3_dma_flush_range
1036b895	337	SYM_FUNC_END(xsc3_dma_map_area)
a9c9147e RK	338
	339	/*
	340	* dma_unmap_area(start, size, dir)
	341	* - start - kernel virtual start address
	342	* - size - size of region
	343	* - dir - DMA direction
	344	*/
1036b895	345	SYM_TYPED_FUNC_START(xsc3_dma_unmap_area)
6ebbf2ce	346	ret lr
1036b895	347	SYM_FUNC_END(xsc3_dma_unmap_area)
a9c9147e	348
51db13aa	349	SYM_TYPED_FUNC_START(cpu_xsc3_dcache_clean_area)
850b4293	350	1: mcr p15, 0, r0, c7, c10, 1 @ clean L1 D line
23bdf86a LB	351	add r0, r0, #CACHELINESIZE
	352	subs r1, r1, #CACHELINESIZE
	353	bhi 1b
6ebbf2ce	354	ret lr
51db13aa	355	SYM_FUNC_END(cpu_xsc3_dcache_clean_area)
23bdf86a LB	356
	357	/* =============================== PageTable ============================== */
	358
	359	/*
	360	* cpu_xsc3_switch_mm(pgd)
	361	*
	362	* Set the translation base pointer to be as described by pgd.
	363	*
	364	* pgd: new page tables
	365	*/
	366	.align 5
51db13aa	367	SYM_TYPED_FUNC_START(cpu_xsc3_switch_mm)
23bdf86a	368	clean_d_cache r1, r2
850b4293 LB	369	mcr p15, 0, ip, c7, c5, 0 @ invalidate L1 I cache and BTB
	370	mcr p15, 0, ip, c7, c10, 4 @ data write barrier
	371	mcr p15, 0, ip, c7, c5, 4 @ prefetch flush
23bdf86a	372	orr r0, r0, #0x18 @ cache the page table in L2
23bdf86a	373	mcr p15, 0, r0, c2, c0, 0 @ load page table pointer
850b4293	374	mcr p15, 0, ip, c8, c7, 0 @ invalidate I and D TLBs
23bdf86a	375	cpwait_ret lr, ip
51db13aa	376	SYM_FUNC_END(cpu_xsc3_switch_mm)
23bdf86a LB	377
23bdf86a LB	378	/*
ad1ae2fe	379	* cpu_xsc3_set_pte_ext(ptep, pte, ext)
23bdf86a LB	380	*
23bdf86a LB	381	* Set a PTE and flush it out
23bdf86a	382	*/
9e8b5199 RK	383	cpu_xsc3_mt_table:
9e8b5199 RK	384	.long 0x00 @ L_PTE_MT_UNCACHED
40df2d1d	385	.long PTE_EXT_TEX(1) @ L_PTE_MT_BUFFERABLE
6bee00db	386	.long PTE_EXT_TEX(5) \| PTE_CACHEABLE @ L_PTE_MT_WRITETHROUGH
40df2d1d RK	387	.long PTE_CACHEABLE \| PTE_BUFFERABLE @ L_PTE_MT_WRITEBACK
40df2d1d RK	388	.long PTE_EXT_TEX(1) \| PTE_BUFFERABLE @ L_PTE_MT_DEV_SHARED
639b0ae7	389	.long 0x00 @ unused
9e8b5199 RK	390	.long 0x00 @ L_PTE_MT_MINICACHE (not present)
9e8b5199 RK	391	.long PTE_EXT_TEX(5) \| PTE_CACHEABLE \| PTE_BUFFERABLE @ L_PTE_MT_WRITEALLOC (not present?)
639b0ae7	392	.long 0x00 @ unused
9e8b5199 RK	393	.long PTE_EXT_TEX(1) @ L_PTE_MT_DEV_WC
9e8b5199 RK	394	.long 0x00 @ unused
40df2d1d RK	395	.long PTE_CACHEABLE \| PTE_BUFFERABLE @ L_PTE_MT_DEV_CACHED
40df2d1d RK	396	.long PTE_EXT_TEX(2) @ L_PTE_MT_DEV_NONSHARED
db5b7169	397	.long 0x00 @ unused
9e8b5199 RK	398	.long 0x00 @ unused
	399	.long 0x00 @ unused
	400
23bdf86a	401	.align 5
51db13aa	402	SYM_TYPED_FUNC_START(cpu_xsc3_set_pte_ext)
da091653	403	xscale_set_pte_ext_prologue
23bdf86a	404
da091653	405	tst r1, #L_PTE_SHARED @ shared?
9e8b5199 RK	406	and r1, r1, #L_PTE_MT_MASK
	407	adr ip, cpu_xsc3_mt_table
	408	ldr ip, [ip, r1]
	409	orrne r2, r2, #PTE_EXT_COHERENT @ interlock: mask in coherent bit
	410	bic r2, r2, #0x0c @ clear old C,B bits
	411	orr r2, r2, ip
23bdf86a	412
da091653	413	xscale_set_pte_ext_epilogue
6ebbf2ce	414	ret lr
51db13aa	415	SYM_FUNC_END(cpu_xsc3_set_pte_ext)
23bdf86a LB	416
23bdf86a LB	417	.ltorg
23bdf86a LB	418	.align
23bdf86a LB	419
f6b0fa02	420	.globl cpu_xsc3_suspend_size
de8e71ca	421	.equ cpu_xsc3_suspend_size, 4 * 6
b6c7aabd	422	#ifdef CONFIG_ARM_CPU_SUSPEND
51db13aa	423	SYM_TYPED_FUNC_START(cpu_xsc3_do_suspend)
de8e71ca	424	stmfd sp!, {r4 - r9, lr}
f6b0fa02 RK	425	mrc p14, 0, r4, c6, c0, 0 @ clock configuration, for turbo mode
	426	mrc p15, 0, r5, c15, c1, 0 @ CP access reg
	427	mrc p15, 0, r6, c13, c0, 0 @ PID
	428	mrc p15, 0, r7, c3, c0, 0 @ domain ID
de8e71ca RK	429	mrc p15, 0, r8, c1, c0, 1 @ auxiliary control reg
de8e71ca RK	430	mrc p15, 0, r9, c1, c0, 0 @ control reg
f6b0fa02	431	bic r4, r4, #2 @ clear frequency change bit
de8e71ca RK	432	stmia r0, {r4 - r9} @ store cp regs
de8e71ca RK	433	ldmia sp!, {r4 - r9, pc}
51db13aa	434	SYM_FUNC_END(cpu_xsc3_do_suspend)
f6b0fa02	435
51db13aa	436	SYM_TYPED_FUNC_START(cpu_xsc3_do_resume)
de8e71ca	437	ldmia r0, {r4 - r9} @ load cp regs
f6b0fa02 RK	438	mov ip, #0
	439	mcr p15, 0, ip, c7, c7, 0 @ invalidate I & D caches, BTB
	440	mcr p15, 0, ip, c7, c10, 4 @ drain write (&fill) buffer
	441	mcr p15, 0, ip, c7, c5, 4 @ flush prefetch buffer
	442	mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
	443	mcr p14, 0, r4, c6, c0, 0 @ clock configuration, turbo mode.
	444	mcr p15, 0, r5, c15, c1, 0 @ CP access reg
	445	mcr p15, 0, r6, c13, c0, 0 @ PID
	446	mcr p15, 0, r7, c3, c0, 0 @ domain ID
de8e71ca RK	447	orr r1, r1, #0x18 @ cache the page table in L2
	448	mcr p15, 0, r1, c2, c0, 0 @ translation table base addr
	449	mcr p15, 0, r8, c1, c0, 1 @ auxiliary control reg
	450	mov r0, r9 @ control register
f6b0fa02	451	b cpu_resume_mmu
51db13aa	452	SYM_FUNC_END(cpu_xsc3_do_resume)
f6b0fa02 RK	453	#endif
f6b0fa02 RK	454
23bdf86a LB	455	.type __xsc3_setup, #function
	456	__xsc3_setup:
	457	mov r0, #PSR_F_BIT\|PSR_I_BIT\|SVC_MODE
	458	msr cpsr_c, r0
850b4293 LB	459	mcr p15, 0, ip, c7, c7, 0 @ invalidate L1 caches and BTB
	460	mcr p15, 0, ip, c7, c10, 4 @ data write barrier
	461	mcr p15, 0, ip, c7, c5, 4 @ prefetch flush
	462	mcr p15, 0, ip, c8, c7, 0 @ invalidate I and D TLBs
23bdf86a	463	orr r4, r4, #0x18 @ cache the page table in L2
23bdf86a	464	mcr p15, 0, r4, c2, c0, 0 @ load page table pointer
850b4293	465
345a3229	466	mov r0, #1 << 6 @ cp6 access for early sched_clock
850b4293 LB	467	mcr p15, 0, r0, c15, c1, 0 @ write CP access register
850b4293 LB	468
23bdf86a LB	469	mrc p15, 0, r0, c1, c0, 1 @ get auxiliary control reg
23bdf86a LB	470	and r0, r0, #2 @ preserve bit P bit setting
23bdf86a	471	orr r0, r0, #(1 << 10) @ enable L2 for LLR cache
23bdf86a	472	mcr p15, 0, r0, c1, c0, 1 @ set auxiliary control reg
22b19086 RK	473
	474	adr r5, xsc3_crval
	475	ldmia r5, {r5, r6}
548c6af4 HZ	476
	477	#ifdef CONFIG_CACHE_XSC3L2
	478	mrc p15, 1, r0, c0, c0, 1 @ get L2 present information
	479	ands r0, r0, #0xf8
	480	orrne r6, r6, #(1 << 26) @ enable L2 if present
	481	#endif
	482
23bdf86a	483	mrc p15, 0, r0, c1, c0, 0 @ get control register
850b4293 LB	484	bic r0, r0, r5 @ ..V. ..R. .... ..A.
	485	orr r0, r0, r6 @ ..VI Z..S .... .C.M (mmu)
	486	@ ...I Z..S .... .... (uc)
6ebbf2ce	487	ret lr
23bdf86a LB	488
	489	.size __xsc3_setup, . - __xsc3_setup
	490
22b19086 RK	491	.type xsc3_crval, #object
22b19086 RK	492	xsc3_crval:
850b4293	493	crval clear=0x04002202, mmuset=0x00003905, ucset=0x00001900
22b19086	494
23bdf86a LB	495	__INITDATA
23bdf86a LB	496
c21898f9 DM	497	@ define struct processor (see <asm/proc-fns.h> and proc-macros.S)
c21898f9 DM	498	define_processor_functions xsc3, dabort=v5t_early_abort, pabort=legacy_pabort, suspend=1
23bdf86a LB	499
	500	.section ".rodata"
	501
c21898f9 DM	502	string cpu_arch_name, "armv5te"
	503	string cpu_elf_name, "v5"
	504	string cpu_xsc3_name, "XScale-V3 based processor"
23bdf86a LB	505
	506	.align
	507
790756c7	508	.section ".proc.info.init", "a"
23bdf86a	509
c21898f9 DM	510	.macro xsc3_proc_info name:req, cpu_val:req, cpu_mask:req
	511	.type __\name\()_proc_info,#object
	512	__\name\()_proc_info:
	513	.long \cpu_val
	514	.long \cpu_mask
8799ee9f RK	515	.long PMD_TYPE_SECT \| \
	516	PMD_SECT_BUFFERABLE \| \
	517	PMD_SECT_CACHEABLE \| \
	518	PMD_SECT_AP_WRITE \| \
	519	PMD_SECT_AP_READ
850b4293	520	.long PMD_TYPE_SECT \| \
8799ee9f RK	521	PMD_SECT_AP_WRITE \| \
8799ee9f RK	522	PMD_SECT_AP_READ
bf35706f	523	initfn __xsc3_setup, __\name\()_proc_info
23bdf86a LB	524	.long cpu_arch_name
	525	.long cpu_elf_name
	526	.long HWCAP_SWP\|HWCAP_HALF\|HWCAP_THUMB\|HWCAP_FAST_MULT\|HWCAP_EDSP
	527	.long cpu_xsc3_name
	528	.long xsc3_processor_functions
	529	.long v4wbi_tlb_fns
	530	.long xsc3_mc_user_fns
	531	.long xsc3_cache_fns
c21898f9 DM	532	.size __\name\()_proc_info, . - __\name\()_proc_info
c21898f9 DM	533	.endm
59c7bcd4	534
c21898f9	535	xsc3_proc_info xsc3, 0x69056000, 0xffffe000
59c7bcd4	536
c21898f9 DM	537	/* Note: PXA935 changed its implementor ID from Intel to Marvell */
c21898f9 DM	538	xsc3_proc_info xsc3_pxa935, 0x56056000, 0xffffe000