[linux-2.6-block.git] / arch / arm / mm / proc-v7m.S

/* SPDX-License-Identifier: GPL-2.0-only */
/*
 *  linux/arch/arm/mm/proc-v7m.S
 *
 *  Copyright (C) 2008 ARM Ltd.
 *  Copyright (C) 2001 Deep Blue Solutions Ltd.
 *
 *  This is the "shell" of the ARMv7-M processor support.
 */
#include <linux/linkage.h>
#include <asm/assembler.h>
#include <asm/memory.h>
#include <asm/v7m.h>
#include "proc-macros.S"

ENTRY(cpu_v7m_proc_init)
	ret	lr
ENDPROC(cpu_v7m_proc_init)

ENTRY(cpu_v7m_proc_fin)
	ret	lr
ENDPROC(cpu_v7m_proc_fin)

/*
 *	cpu_v7m_reset(loc)
 *
 *	Perform a soft reset of the system.  Put the CPU into the
 *	same state as it would be if it had been reset, and branch
 *	to what would be the reset vector.
 *
 *	- loc   - location to jump to for soft reset
 */
	.align	5
ENTRY(cpu_v7m_reset)
	ret	r0
ENDPROC(cpu_v7m_reset)

/*
 *	cpu_v7m_do_idle()
 *
 *	Idle the processor (eg, wait for interrupt).
 *
 *	IRQs are already disabled.
 */
ENTRY(cpu_v7m_do_idle)
	wfi
	ret	lr
ENDPROC(cpu_v7m_do_idle)

ENTRY(cpu_v7m_dcache_clean_area)
	ret	lr
ENDPROC(cpu_v7m_dcache_clean_area)

/*
 * There is no MMU, so here is nothing to do.
 */
ENTRY(cpu_v7m_switch_mm)
	ret	lr
ENDPROC(cpu_v7m_switch_mm)

.globl	cpu_v7m_suspend_size
.equ	cpu_v7m_suspend_size, 0

#ifdef CONFIG_ARM_CPU_SUSPEND
ENTRY(cpu_v7m_do_suspend)
	ret	lr
ENDPROC(cpu_v7m_do_suspend)

ENTRY(cpu_v7m_do_resume)
	ret	lr
ENDPROC(cpu_v7m_do_resume)
#endif

ENTRY(cpu_cm7_dcache_clean_area)
	dcache_line_size r2, r3
	movw	r3, #:lower16:BASEADDR_V7M_SCB + V7M_SCB_DCCMVAC
	movt	r3, #:upper16:BASEADDR_V7M_SCB + V7M_SCB_DCCMVAC

1:	str	r0, [r3]		@ clean D entry
	add	r0, r0, r2
	subs	r1, r1, r2
	bhi	1b
	dsb
	ret	lr
ENDPROC(cpu_cm7_dcache_clean_area)

ENTRY(cpu_cm7_proc_fin)
	movw	r2, #:lower16:(BASEADDR_V7M_SCB + V7M_SCB_CCR)
	movt	r2, #:upper16:(BASEADDR_V7M_SCB + V7M_SCB_CCR)
	ldr	r0, [r2]
	bic	r0, r0, #(V7M_SCB_CCR_DC | V7M_SCB_CCR_IC)
	str	r0, [r2]
	ret	lr
ENDPROC(cpu_cm7_proc_fin)

	.section ".init.text", #alloc, #execinstr

__v7m_cm7_setup:
	mov	r8, #(V7M_SCB_CCR_DC | V7M_SCB_CCR_IC| V7M_SCB_CCR_BP)
	b	__v7m_setup_cont
/*
 *	__v7m_setup
 *
 *	This should be able to cover all ARMv7-M cores.
 */
__v7m_setup:
	mov	r8, 0

__v7m_setup_cont:
	@ Configure the vector table base address
	ldr	r0, =BASEADDR_V7M_SCB
	ldr	r12, =vector_table
	str	r12, [r0, V7M_SCB_VTOR]

	@ enable UsageFault, BusFault and MemManage fault.
	ldr	r5, [r0, #V7M_SCB_SHCSR]
	orr	r5, #(V7M_SCB_SHCSR_USGFAULTENA | V7M_SCB_SHCSR_BUSFAULTENA | V7M_SCB_SHCSR_MEMFAULTENA)
	str	r5, [r0, #V7M_SCB_SHCSR]

	@ Lower the priority of the SVC and PendSV exceptions
	mov	r5, #0x80000000
	str	r5, [r0, V7M_SCB_SHPR2]	@ set SVC priority
	mov	r5, #0x00800000
	str	r5, [r0, V7M_SCB_SHPR3]	@ set PendSV priority

	@ SVC to switch to handler mode. Notice that this requires sp to
	@ point to writeable memory because the processor saves
	@ some registers to the stack.
	badr	r1, 1f
	ldr	r5, [r12, #11 * 4]	@ read the SVC vector entry
	str	r1, [r12, #11 * 4]	@ write the temporary SVC vector entry
	dsb
	mov	r6, lr			@ save LR
	ldr	sp, =init_thread_union + THREAD_START_SP
	stmia	sp, {r0-r3, r12}
	cpsie	i
	svc	#0
1:	cpsid	i
	ldr	r0, =exc_ret
	orr	lr, lr, #EXC_RET_THREADMODE_PROCESSSTACK
	str	lr, [r0]
	ldmia	sp, {r0-r3, r12}
	str	r5, [r12, #11 * 4]	@ restore the original SVC vector entry
	mov	lr, r6			@ restore LR

	@ Special-purpose control register
	mov	r1, #1
	msr	control, r1		@ Thread mode has unpriviledged access

	@ Configure caches (if implemented)
	teq     r8, #0
	stmiane	sp, {r0-r6, lr}		@ v7m_invalidate_l1 touches r0-r6
	blne	v7m_invalidate_l1
	teq     r8, #0			@ re-evalutae condition
	ldmiane	sp, {r0-r6, lr}

	@ Configure the System Control Register to ensure 8-byte stack alignment
	@ Note the STKALIGN bit is either RW or RAO.
	ldr	r0, [r0, V7M_SCB_CCR]   @ system control register
	orr	r0, #V7M_SCB_CCR_STKALIGN
	orr	r0, r0, r8

	ret	lr
ENDPROC(__v7m_setup)

/*
 * Cortex-M7 processor functions
 */
	globl_equ	cpu_cm7_proc_init,	cpu_v7m_proc_init
	globl_equ	cpu_cm7_reset,		cpu_v7m_reset
	globl_equ	cpu_cm7_do_idle,	cpu_v7m_do_idle
	globl_equ	cpu_cm7_switch_mm,	cpu_v7m_switch_mm

	define_processor_functions v7m, dabort=nommu_early_abort, pabort=legacy_pabort, nommu=1
	define_processor_functions cm7, dabort=nommu_early_abort, pabort=legacy_pabort, nommu=1

	.section ".rodata"
	string cpu_arch_name, "armv7m"
	string cpu_elf_name "v7m"
	string cpu_v7m_name "ARMv7-M"

	.section ".proc.info.init", #alloc

.macro __v7m_proc name, initfunc, cache_fns = nop_cache_fns, hwcaps = 0,  proc_fns = v7m_processor_functions
	.long	0			/* proc_info_list.__cpu_mm_mmu_flags */
	.long	0			/* proc_info_list.__cpu_io_mmu_flags */
	initfn	\initfunc, \name
	.long	cpu_arch_name
	.long	cpu_elf_name
	.long	HWCAP_HALF | HWCAP_THUMB | HWCAP_FAST_MULT | \hwcaps
	.long	cpu_v7m_name
	.long   \proc_fns
	.long	0			/* proc_info_list.tlb */
	.long	0			/* proc_info_list.user */
	.long	\cache_fns
.endm

	/*
	 * Match ARM Cortex-M7 processor.
	 */
	.type	__v7m_cm7_proc_info, #object
__v7m_cm7_proc_info:
	.long	0x410fc270		/* ARM Cortex-M7 0xC27 */
	.long	0xff0ffff0		/* Mask off revision, patch release */
	__v7m_proc __v7m_cm7_proc_info, __v7m_cm7_setup, hwcaps = HWCAP_EDSP, cache_fns = v7m_cache_fns, proc_fns = cm7_processor_functions
	.size	__v7m_cm7_proc_info, . - __v7m_cm7_proc_info

	/*
	 * Match ARM Cortex-M4 processor.
	 */
	.type	__v7m_cm4_proc_info, #object
__v7m_cm4_proc_info:
	.long	0x410fc240		/* ARM Cortex-M4 0xC24 */
	.long	0xff0ffff0		/* Mask off revision, patch release */
	__v7m_proc __v7m_cm4_proc_info, __v7m_setup, hwcaps = HWCAP_EDSP
	.size	__v7m_cm4_proc_info, . - __v7m_cm4_proc_info

	/*
	 * Match ARM Cortex-M3 processor.
	 */
	.type	__v7m_cm3_proc_info, #object
__v7m_cm3_proc_info:
	.long	0x410fc230		/* ARM Cortex-M3 0xC23 */
	.long	0xff0ffff0		/* Mask off revision, patch release */
	__v7m_proc __v7m_cm3_proc_info, __v7m_setup
	.size	__v7m_cm3_proc_info, . - __v7m_cm3_proc_info

	/*
	 * Match any ARMv7-M processor core.
	 */
	.type	__v7m_proc_info, #object
__v7m_proc_info:
	.long	0x000f0000		@ Required ID value
	.long	0x000f0000		@ Mask for ID
	__v7m_proc __v7m_proc_info, __v7m_setup
	.size	__v7m_proc_info, . - __v7m_proc_info
Commit	Line	Data
d2912cb1	1	/* SPDX-License-Identifier: GPL-2.0-only */
55bdd694 CM	2	/*
	3	* linux/arch/arm/mm/proc-v7m.S
	4	*
	5	* Copyright (C) 2008 ARM Ltd.
	6	* Copyright (C) 2001 Deep Blue Solutions Ltd.
	7	*
55bdd694 CM	8	* This is the "shell" of the ARMv7-M processor support.
	9	*/
	10	#include <linux/linkage.h>
	11	#include <asm/assembler.h>
a4124e72	12	#include <asm/memory.h>
55bdd694 CM	13	#include <asm/v7m.h>
	14	#include "proc-macros.S"
	15
	16	ENTRY(cpu_v7m_proc_init)
6ebbf2ce	17	ret lr
55bdd694 CM	18	ENDPROC(cpu_v7m_proc_init)
	19
	20	ENTRY(cpu_v7m_proc_fin)
6ebbf2ce	21	ret lr
55bdd694 CM	22	ENDPROC(cpu_v7m_proc_fin)
	23
	24	/*
	25	* cpu_v7m_reset(loc)
	26	*
	27	* Perform a soft reset of the system. Put the CPU into the
	28	* same state as it would be if it had been reset, and branch
	29	* to what would be the reset vector.
	30	*
	31	* - loc - location to jump to for soft reset
	32	*/
	33	.align 5
	34	ENTRY(cpu_v7m_reset)
6ebbf2ce	35	ret r0
55bdd694 CM	36	ENDPROC(cpu_v7m_reset)
	37
	38	/*
	39	* cpu_v7m_do_idle()
	40	*
	41	* Idle the processor (eg, wait for interrupt).
	42	*
	43	* IRQs are already disabled.
	44	*/
	45	ENTRY(cpu_v7m_do_idle)
	46	wfi
6ebbf2ce	47	ret lr
55bdd694 CM	48	ENDPROC(cpu_v7m_do_idle)
	49
	50	ENTRY(cpu_v7m_dcache_clean_area)
6ebbf2ce	51	ret lr
55bdd694 CM	52	ENDPROC(cpu_v7m_dcache_clean_area)
	53
	54	/*
	55	* There is no MMU, so here is nothing to do.
	56	*/
	57	ENTRY(cpu_v7m_switch_mm)
6ebbf2ce	58	ret lr
55bdd694 CM	59	ENDPROC(cpu_v7m_switch_mm)
	60
	61	.globl cpu_v7m_suspend_size
	62	.equ cpu_v7m_suspend_size, 0
	63
	64	#ifdef CONFIG_ARM_CPU_SUSPEND
	65	ENTRY(cpu_v7m_do_suspend)
6ebbf2ce	66	ret lr
55bdd694 CM	67	ENDPROC(cpu_v7m_do_suspend)
	68
	69	ENTRY(cpu_v7m_do_resume)
6ebbf2ce	70	ret lr
55bdd694 CM	71	ENDPROC(cpu_v7m_do_resume)
	72	#endif
	73
6a8146f4 JA	74	ENTRY(cpu_cm7_dcache_clean_area)
	75	dcache_line_size r2, r3
	76	movw r3, #:lower16:BASEADDR_V7M_SCB + V7M_SCB_DCCMVAC
	77	movt r3, #:upper16:BASEADDR_V7M_SCB + V7M_SCB_DCCMVAC
	78
	79	1: str r0, [r3] @ clean D entry
	80	add r0, r0, r2
	81	subs r1, r1, r2
	82	bhi 1b
	83	dsb
	84	ret lr
	85	ENDPROC(cpu_cm7_dcache_clean_area)
	86
	87	ENTRY(cpu_cm7_proc_fin)
	88	movw r2, #:lower16:(BASEADDR_V7M_SCB + V7M_SCB_CCR)
	89	movt r2, #:upper16:(BASEADDR_V7M_SCB + V7M_SCB_CCR)
	90	ldr r0, [r2]
	91	bic r0, r0, #(V7M_SCB_CCR_DC \| V7M_SCB_CCR_IC)
	92	str r0, [r2]
	93	ret lr
	94	ENDPROC(cpu_cm7_proc_fin)
	95
544457fa	96	.section ".init.text", #alloc, #execinstr
55bdd694	97
6a8146f4 JA	98	__v7m_cm7_setup:
	99	mov r8, #(V7M_SCB_CCR_DC \| V7M_SCB_CCR_IC\| V7M_SCB_CCR_BP)
	100	b __v7m_setup_cont
55bdd694 CM	101	/*
	102	* __v7m_setup
	103	*
	104	* This should be able to cover all ARMv7-M cores.
	105	*/
	106	__v7m_setup:
6a8146f4 JA	107	mov r8, 0
	108
	109	__v7m_setup_cont:
55bdd694 CM	110	@ Configure the vector table base address
	111	ldr r0, =BASEADDR_V7M_SCB
	112	ldr r12, =vector_table
	113	str r12, [r0, V7M_SCB_VTOR]
	114
	115	@ enable UsageFault, BusFault and MemManage fault.
	116	ldr r5, [r0, #V7M_SCB_SHCSR]
	117	orr r5, #(V7M_SCB_SHCSR_USGFAULTENA \| V7M_SCB_SHCSR_BUSFAULTENA \| V7M_SCB_SHCSR_MEMFAULTENA)
	118	str r5, [r0, #V7M_SCB_SHCSR]
	119
	120	@ Lower the priority of the SVC and PendSV exceptions
	121	mov r5, #0x80000000
	122	str r5, [r0, V7M_SCB_SHPR2] @ set SVC priority
	123	mov r5, #0x00800000
	124	str r5, [r0, V7M_SCB_SHPR3] @ set PendSV priority
	125
a4124e72 EG	126	@ SVC to switch to handler mode. Notice that this requires sp to
	127	@ point to writeable memory because the processor saves
	128	@ some registers to the stack.
14327c66	129	badr r1, 1f
55bdd694 CM	130	ldr r5, [r12, #11 * 4] @ read the SVC vector entry
55bdd694 CM	131	str r1, [r12, #11 * 4] @ write the temporary SVC vector entry
8e02676f	132	dsb
55bdd694	133	mov r6, lr @ save LR
a4124e72	134	ldr sp, =init_thread_union + THREAD_START_SP
b70cd406	135	stmia sp, {r0-r3, r12}
55bdd694 CM	136	cpsie i
	137	svc #0
	138	1: cpsid i
72cd4064 VM	139	ldr r0, =exc_ret
	140	orr lr, lr, #EXC_RET_THREADMODE_PROCESSSTACK
	141	str lr, [r0]
b70cd406	142	ldmia sp, {r0-r3, r12}
55bdd694 CM	143	str r5, [r12, #11 * 4] @ restore the original SVC vector entry
55bdd694 CM	144	mov lr, r6 @ restore LR
55bdd694 CM	145
	146	@ Special-purpose control register
	147	mov r1, #1
	148	msr control, r1 @ Thread mode has unpriviledged access
	149
6a8146f4 JA	150	@ Configure caches (if implemented)
6a8146f4 JA	151	teq r8, #0
e44fc388	152	stmiane sp, {r0-r6, lr} @ v7m_invalidate_l1 touches r0-r6
6a8146f4 JA	153	blne v7m_invalidate_l1
6a8146f4 JA	154	teq r8, #0 @ re-evalutae condition
e44fc388	155	ldmiane sp, {r0-r6, lr}
6a8146f4	156
55bdd694 CM	157	@ Configure the System Control Register to ensure 8-byte stack alignment
55bdd694 CM	158	@ Note the STKALIGN bit is either RW or RAO.
bc0ee9d2 JA	159	ldr r0, [r0, V7M_SCB_CCR] @ system control register
bc0ee9d2 JA	160	orr r0, #V7M_SCB_CCR_STKALIGN
6a8146f4 JA	161	orr r0, r0, r8
6a8146f4 JA	162
6ebbf2ce	163	ret lr
55bdd694 CM	164	ENDPROC(__v7m_setup)
55bdd694 CM	165
6a8146f4 JA	166	/*
	167	* Cortex-M7 processor functions
	168	*/
	169	globl_equ cpu_cm7_proc_init, cpu_v7m_proc_init
	170	globl_equ cpu_cm7_reset, cpu_v7m_reset
	171	globl_equ cpu_cm7_do_idle, cpu_v7m_do_idle
	172	globl_equ cpu_cm7_switch_mm, cpu_v7m_switch_mm
	173
55bdd694	174	define_processor_functions v7m, dabort=nommu_early_abort, pabort=legacy_pabort, nommu=1
6a8146f4	175	define_processor_functions cm7, dabort=nommu_early_abort, pabort=legacy_pabort, nommu=1
55bdd694 CM	176
	177	.section ".rodata"
	178	string cpu_arch_name, "armv7m"
	179	string cpu_elf_name "v7m"
	180	string cpu_v7m_name "ARMv7-M"
	181
bf35706f	182	.section ".proc.info.init", #alloc
55bdd694	183
c3a6bcbe JA	184	.macro __v7m_proc name, initfunc, cache_fns = nop_cache_fns, hwcaps = 0, proc_fns = v7m_processor_functions
	185	.long 0 /* proc_info_list.__cpu_mm_mmu_flags */
	186	.long 0 /* proc_info_list.__cpu_io_mmu_flags */
	187	initfn \initfunc, \name
	188	.long cpu_arch_name
	189	.long cpu_elf_name
	190	.long HWCAP_HALF \| HWCAP_THUMB \| HWCAP_FAST_MULT \| \hwcaps
	191	.long cpu_v7m_name
	192	.long \proc_fns
	193	.long 0 /* proc_info_list.tlb */
	194	.long 0 /* proc_info_list.user */
	195	.long \cache_fns
	196	.endm
	197
6a8146f4 JA	198	/*
	199	* Match ARM Cortex-M7 processor.
	200	*/
	201	.type __v7m_cm7_proc_info, #object
	202	__v7m_cm7_proc_info:
	203	.long 0x410fc270 /* ARM Cortex-M7 0xC27 */
	204	.long 0xff0ffff0 /* Mask off revision, patch release */
	205	__v7m_proc __v7m_cm7_proc_info, __v7m_cm7_setup, hwcaps = HWCAP_EDSP, cache_fns = v7m_cache_fns, proc_fns = cm7_processor_functions
	206	.size __v7m_cm7_proc_info, . - __v7m_cm7_proc_info
	207
c3a6bcbe JA	208	/*
	209	* Match ARM Cortex-M4 processor.
	210	*/
	211	.type __v7m_cm4_proc_info, #object
	212	__v7m_cm4_proc_info:
	213	.long 0x410fc240 /* ARM Cortex-M4 0xC24 */
	214	.long 0xff0ffff0 /* Mask off revision, patch release */
	215	__v7m_proc __v7m_cm4_proc_info, __v7m_setup, hwcaps = HWCAP_EDSP
	216	.size __v7m_cm4_proc_info, . - __v7m_cm4_proc_info
	217
	218	/*
	219	* Match ARM Cortex-M3 processor.
	220	*/
	221	.type __v7m_cm3_proc_info, #object
	222	__v7m_cm3_proc_info:
	223	.long 0x410fc230 /* ARM Cortex-M3 0xC23 */
	224	.long 0xff0ffff0 /* Mask off revision, patch release */
	225	__v7m_proc __v7m_cm3_proc_info, __v7m_setup
	226	.size __v7m_cm3_proc_info, . - __v7m_cm3_proc_info
	227
55bdd694 CM	228	/*
	229	* Match any ARMv7-M processor core.
	230	*/
	231	.type __v7m_proc_info, #object
	232	__v7m_proc_info:
	233	.long 0x000f0000 @ Required ID value
	234	.long 0x000f0000 @ Mask for ID
c3a6bcbe	235	__v7m_proc __v7m_proc_info, __v7m_setup
55bdd694 CM	236	.size __v7m_proc_info, . - __v7m_proc_info
55bdd694 CM	237