Commit | Line | Data |
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bbe88886 CM |
1 | /* |
2 | * linux/arch/arm/mm/proc-v7.S | |
3 | * | |
4 | * Copyright (C) 2001 Deep Blue Solutions Ltd. | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License version 2 as | |
8 | * published by the Free Software Foundation. | |
9 | * | |
10 | * This is the "shell" of the ARMv7 processor support. | |
11 | */ | |
991da17e | 12 | #include <linux/init.h> |
bbe88886 CM |
13 | #include <linux/linkage.h> |
14 | #include <asm/assembler.h> | |
15 | #include <asm/asm-offsets.h> | |
5ec9407d | 16 | #include <asm/hwcap.h> |
bbe88886 CM |
17 | #include <asm/pgtable-hwdef.h> |
18 | #include <asm/pgtable.h> | |
19 | ||
20 | #include "proc-macros.S" | |
21 | ||
1b6ba46b CM |
22 | #ifdef CONFIG_ARM_LPAE |
23 | #include "proc-v7-3level.S" | |
24 | #else | |
8d2cd3a3 | 25 | #include "proc-v7-2level.S" |
1b6ba46b | 26 | #endif |
73b63efa | 27 | |
bbe88886 CM |
28 | ENTRY(cpu_v7_proc_init) |
29 | mov pc, lr | |
93ed3970 | 30 | ENDPROC(cpu_v7_proc_init) |
bbe88886 CM |
31 | |
32 | ENTRY(cpu_v7_proc_fin) | |
1f667c69 TL |
33 | mrc p15, 0, r0, c1, c0, 0 @ ctrl register |
34 | bic r0, r0, #0x1000 @ ...i............ | |
35 | bic r0, r0, #0x0006 @ .............ca. | |
36 | mcr p15, 0, r0, c1, c0, 0 @ disable caches | |
9ca03a21 | 37 | mov pc, lr |
93ed3970 | 38 | ENDPROC(cpu_v7_proc_fin) |
bbe88886 CM |
39 | |
40 | /* | |
41 | * cpu_v7_reset(loc) | |
42 | * | |
43 | * Perform a soft reset of the system. Put the CPU into the | |
44 | * same state as it would be if it had been reset, and branch | |
45 | * to what would be the reset vector. | |
46 | * | |
47 | * - loc - location to jump to for soft reset | |
f4daf06f WD |
48 | * |
49 | * This code must be executed using a flat identity mapping with | |
50 | * caches disabled. | |
bbe88886 CM |
51 | */ |
52 | .align 5 | |
1a4baafa | 53 | .pushsection .idmap.text, "ax" |
bbe88886 | 54 | ENTRY(cpu_v7_reset) |
f4daf06f WD |
55 | mrc p15, 0, r1, c1, c0, 0 @ ctrl register |
56 | bic r1, r1, #0x1 @ ...............m | |
0f81bb6b | 57 | THUMB( bic r1, r1, #1 << 30 ) @ SCTLR.TE (Thumb exceptions) |
f4daf06f WD |
58 | mcr p15, 0, r1, c1, c0, 0 @ disable MMU |
59 | isb | |
153cd8e8 | 60 | bx r0 |
93ed3970 | 61 | ENDPROC(cpu_v7_reset) |
1a4baafa | 62 | .popsection |
bbe88886 CM |
63 | |
64 | /* | |
65 | * cpu_v7_do_idle() | |
66 | * | |
67 | * Idle the processor (eg, wait for interrupt). | |
68 | * | |
69 | * IRQs are already disabled. | |
70 | */ | |
71 | ENTRY(cpu_v7_do_idle) | |
8553cb67 | 72 | dsb @ WFI may enter a low-power mode |
000b5025 | 73 | wfi |
bbe88886 | 74 | mov pc, lr |
93ed3970 | 75 | ENDPROC(cpu_v7_do_idle) |
bbe88886 CM |
76 | |
77 | ENTRY(cpu_v7_dcache_clean_area) | |
78 | #ifndef TLB_CAN_READ_FROM_L1_CACHE | |
79 | dcache_line_size r2, r3 | |
80 | 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry | |
81 | add r0, r0, r2 | |
82 | subs r1, r1, r2 | |
83 | bhi 1b | |
84 | dsb | |
85 | #endif | |
86 | mov pc, lr | |
93ed3970 | 87 | ENDPROC(cpu_v7_dcache_clean_area) |
bbe88886 | 88 | |
78a8f3c3 | 89 | string cpu_v7_name, "ARMv7 Processor" |
bbe88886 CM |
90 | .align |
91 | ||
f6b0fa02 RK |
92 | /* Suspend/resume support: derived from arch/arm/mach-s5pv210/sleep.S */ |
93 | .globl cpu_v7_suspend_size | |
1b6ba46b | 94 | .equ cpu_v7_suspend_size, 4 * 8 |
15e0d9e3 | 95 | #ifdef CONFIG_ARM_CPU_SUSPEND |
f6b0fa02 | 96 | ENTRY(cpu_v7_do_suspend) |
de8e71ca | 97 | stmfd sp!, {r4 - r10, lr} |
f6b0fa02 | 98 | mrc p15, 0, r4, c13, c0, 0 @ FCSE/PID |
1aede681 RK |
99 | mrc p15, 0, r5, c13, c0, 3 @ User r/o thread ID |
100 | stmia r0!, {r4 - r5} | |
f6b0fa02 | 101 | mrc p15, 0, r6, c3, c0, 0 @ Domain ID |
de8e71ca | 102 | mrc p15, 0, r7, c2, c0, 1 @ TTB 1 |
1b6ba46b | 103 | mrc p15, 0, r11, c2, c0, 2 @ TTB control register |
de8e71ca RK |
104 | mrc p15, 0, r8, c1, c0, 0 @ Control register |
105 | mrc p15, 0, r9, c1, c0, 1 @ Auxiliary control register | |
106 | mrc p15, 0, r10, c1, c0, 2 @ Co-processor access control | |
1b6ba46b | 107 | stmia r0, {r6 - r11} |
de8e71ca | 108 | ldmfd sp!, {r4 - r10, pc} |
f6b0fa02 RK |
109 | ENDPROC(cpu_v7_do_suspend) |
110 | ||
111 | ENTRY(cpu_v7_do_resume) | |
112 | mov ip, #0 | |
113 | mcr p15, 0, ip, c8, c7, 0 @ invalidate TLBs | |
114 | mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache | |
1aede681 RK |
115 | mcr p15, 0, ip, c13, c0, 1 @ set reserved context ID |
116 | ldmia r0!, {r4 - r5} | |
f6b0fa02 | 117 | mcr p15, 0, r4, c13, c0, 0 @ FCSE/PID |
1aede681 | 118 | mcr p15, 0, r5, c13, c0, 3 @ User r/o thread ID |
1b6ba46b | 119 | ldmia r0, {r6 - r11} |
f6b0fa02 | 120 | mcr p15, 0, r6, c3, c0, 0 @ Domain ID |
1b6ba46b | 121 | #ifndef CONFIG_ARM_LPAE |
de8e71ca RK |
122 | ALT_SMP(orr r1, r1, #TTB_FLAGS_SMP) |
123 | ALT_UP(orr r1, r1, #TTB_FLAGS_UP) | |
1b6ba46b | 124 | #endif |
de8e71ca RK |
125 | mcr p15, 0, r1, c2, c0, 0 @ TTB 0 |
126 | mcr p15, 0, r7, c2, c0, 1 @ TTB 1 | |
1b6ba46b | 127 | mcr p15, 0, r11, c2, c0, 2 @ TTB control register |
25904157 | 128 | mrc p15, 0, r4, c1, c0, 1 @ Read Auxiliary control register |
de8e71ca RK |
129 | teq r4, r9 @ Is it already set? |
130 | mcrne p15, 0, r9, c1, c0, 1 @ No, so write it | |
131 | mcr p15, 0, r10, c1, c0, 2 @ Co-processor access control | |
f6b0fa02 RK |
132 | ldr r4, =PRRR @ PRRR |
133 | ldr r5, =NMRR @ NMRR | |
134 | mcr p15, 0, r4, c10, c2, 0 @ write PRRR | |
135 | mcr p15, 0, r5, c10, c2, 1 @ write NMRR | |
136 | isb | |
f35235a3 | 137 | dsb |
de8e71ca | 138 | mov r0, r8 @ control register |
f6b0fa02 RK |
139 | b cpu_resume_mmu |
140 | ENDPROC(cpu_v7_do_resume) | |
f6b0fa02 RK |
141 | #endif |
142 | ||
5085f3ff | 143 | __CPUINIT |
bbe88886 CM |
144 | |
145 | /* | |
146 | * __v7_setup | |
147 | * | |
148 | * Initialise TLB, Caches, and MMU state ready to switch the MMU | |
149 | * on. Return in r0 the new CP15 C1 control register setting. | |
150 | * | |
bbe88886 CM |
151 | * This should be able to cover all ARMv7 cores. |
152 | * | |
153 | * It is assumed that: | |
154 | * - cache type register is implemented | |
155 | */ | |
15eb169b | 156 | __v7_ca5mp_setup: |
14eff181 | 157 | __v7_ca9mp_setup: |
7665d9d2 WD |
158 | mov r10, #(1 << 0) @ TLB ops broadcasting |
159 | b 1f | |
b4244738 | 160 | __v7_ca7mp_setup: |
7665d9d2 WD |
161 | __v7_ca15mp_setup: |
162 | mov r10, #0 | |
163 | 1: | |
73b63efa | 164 | #ifdef CONFIG_SMP |
f00ec48f RK |
165 | ALT_SMP(mrc p15, 0, r0, c1, c0, 1) |
166 | ALT_UP(mov r0, #(1 << 6)) @ fake it for UP | |
1b3a02eb | 167 | tst r0, #(1 << 6) @ SMP/nAMP mode enabled? |
7665d9d2 WD |
168 | orreq r0, r0, #(1 << 6) @ Enable SMP/nAMP mode |
169 | orreq r0, r0, r10 @ Enable CPU-specific SMP bits | |
170 | mcreq p15, 0, r0, c1, c0, 1 | |
73b63efa | 171 | #endif |
d106de38 | 172 | b __v7_setup |
de490193 GC |
173 | |
174 | __v7_pj4b_setup: | |
175 | #ifdef CONFIG_CPU_PJ4B | |
176 | ||
177 | /* Auxiliary Debug Modes Control 1 Register */ | |
178 | #define PJ4B_STATIC_BP (1 << 2) /* Enable Static BP */ | |
179 | #define PJ4B_INTER_PARITY (1 << 8) /* Disable Internal Parity Handling */ | |
180 | #define PJ4B_BCK_OFF_STREX (1 << 5) /* Enable the back off of STREX instr */ | |
181 | #define PJ4B_CLEAN_LINE (1 << 16) /* Disable data transfer for clean line */ | |
182 | ||
183 | /* Auxiliary Debug Modes Control 2 Register */ | |
184 | #define PJ4B_FAST_LDR (1 << 23) /* Disable fast LDR */ | |
185 | #define PJ4B_SNOOP_DATA (1 << 25) /* Do not interleave write and snoop data */ | |
186 | #define PJ4B_CWF (1 << 27) /* Disable Critical Word First feature */ | |
187 | #define PJ4B_OUTSDNG_NC (1 << 29) /* Disable outstanding non cacheable rqst */ | |
188 | #define PJ4B_L1_REP_RR (1 << 30) /* L1 replacement - Strict round robin */ | |
189 | #define PJ4B_AUX_DBG_CTRL2 (PJ4B_SNOOP_DATA | PJ4B_CWF |\ | |
190 | PJ4B_OUTSDNG_NC | PJ4B_L1_REP_RR) | |
191 | ||
192 | /* Auxiliary Functional Modes Control Register 0 */ | |
193 | #define PJ4B_SMP_CFB (1 << 1) /* Set SMP mode. Join the coherency fabric */ | |
194 | #define PJ4B_L1_PAR_CHK (1 << 2) /* Support L1 parity checking */ | |
195 | #define PJ4B_BROADCAST_CACHE (1 << 8) /* Broadcast Cache and TLB maintenance */ | |
196 | ||
197 | /* Auxiliary Debug Modes Control 0 Register */ | |
198 | #define PJ4B_WFI_WFE (1 << 22) /* WFI/WFE - serve the DVM and back to idle */ | |
199 | ||
200 | /* Auxiliary Debug Modes Control 1 Register */ | |
201 | mrc p15, 1, r0, c15, c1, 1 | |
202 | orr r0, r0, #PJ4B_CLEAN_LINE | |
203 | orr r0, r0, #PJ4B_BCK_OFF_STREX | |
204 | orr r0, r0, #PJ4B_INTER_PARITY | |
205 | bic r0, r0, #PJ4B_STATIC_BP | |
206 | mcr p15, 1, r0, c15, c1, 1 | |
207 | ||
208 | /* Auxiliary Debug Modes Control 2 Register */ | |
209 | mrc p15, 1, r0, c15, c1, 2 | |
210 | bic r0, r0, #PJ4B_FAST_LDR | |
211 | orr r0, r0, #PJ4B_AUX_DBG_CTRL2 | |
212 | mcr p15, 1, r0, c15, c1, 2 | |
213 | ||
214 | /* Auxiliary Functional Modes Control Register 0 */ | |
215 | mrc p15, 1, r0, c15, c2, 0 | |
216 | #ifdef CONFIG_SMP | |
217 | orr r0, r0, #PJ4B_SMP_CFB | |
218 | #endif | |
219 | orr r0, r0, #PJ4B_L1_PAR_CHK | |
220 | orr r0, r0, #PJ4B_BROADCAST_CACHE | |
221 | mcr p15, 1, r0, c15, c2, 0 | |
222 | ||
223 | /* Auxiliary Debug Modes Control 0 Register */ | |
224 | mrc p15, 1, r0, c15, c1, 0 | |
225 | orr r0, r0, #PJ4B_WFI_WFE | |
226 | mcr p15, 1, r0, c15, c1, 0 | |
227 | ||
228 | #endif /* CONFIG_CPU_PJ4B */ | |
229 | ||
14eff181 | 230 | __v7_setup: |
bbe88886 CM |
231 | adr r12, __v7_setup_stack @ the local stack |
232 | stmia r12, {r0-r5, r7, r9, r11, lr} | |
6323fa22 | 233 | bl v7_flush_dcache_louis |
bbe88886 | 234 | ldmia r12, {r0-r5, r7, r9, r11, lr} |
1946d6ef RK |
235 | |
236 | mrc p15, 0, r0, c0, c0, 0 @ read main ID register | |
237 | and r10, r0, #0xff000000 @ ARM? | |
238 | teq r10, #0x41000000 | |
9f05027c | 239 | bne 3f |
1946d6ef RK |
240 | and r5, r0, #0x00f00000 @ variant |
241 | and r6, r0, #0x0000000f @ revision | |
6491848d WD |
242 | orr r6, r6, r5, lsr #20-4 @ combine variant and revision |
243 | ubfx r0, r0, #4, #12 @ primary part number | |
1946d6ef | 244 | |
6491848d WD |
245 | /* Cortex-A8 Errata */ |
246 | ldr r10, =0x00000c08 @ Cortex-A8 primary part number | |
247 | teq r0, r10 | |
248 | bne 2f | |
62e4d357 RH |
249 | #if defined(CONFIG_ARM_ERRATA_430973) && !defined(CONFIG_ARCH_MULTIPLATFORM) |
250 | ||
1946d6ef RK |
251 | teq r5, #0x00100000 @ only present in r1p* |
252 | mrceq p15, 0, r10, c1, c0, 1 @ read aux control register | |
253 | orreq r10, r10, #(1 << 6) @ set IBE to 1 | |
254 | mcreq p15, 0, r10, c1, c0, 1 @ write aux control register | |
855c551f CM |
255 | #endif |
256 | #ifdef CONFIG_ARM_ERRATA_458693 | |
6491848d | 257 | teq r6, #0x20 @ only present in r2p0 |
1946d6ef RK |
258 | mrceq p15, 0, r10, c1, c0, 1 @ read aux control register |
259 | orreq r10, r10, #(1 << 5) @ set L1NEON to 1 | |
260 | orreq r10, r10, #(1 << 9) @ set PLDNOP to 1 | |
261 | mcreq p15, 0, r10, c1, c0, 1 @ write aux control register | |
0516e464 CM |
262 | #endif |
263 | #ifdef CONFIG_ARM_ERRATA_460075 | |
6491848d | 264 | teq r6, #0x20 @ only present in r2p0 |
1946d6ef RK |
265 | mrceq p15, 1, r10, c9, c0, 2 @ read L2 cache aux ctrl register |
266 | tsteq r10, #1 << 22 | |
267 | orreq r10, r10, #(1 << 22) @ set the Write Allocate disable bit | |
268 | mcreq p15, 1, r10, c9, c0, 2 @ write the L2 cache aux ctrl register | |
7ce236fc | 269 | #endif |
9f05027c WD |
270 | b 3f |
271 | ||
272 | /* Cortex-A9 Errata */ | |
273 | 2: ldr r10, =0x00000c09 @ Cortex-A9 primary part number | |
274 | teq r0, r10 | |
275 | bne 3f | |
276 | #ifdef CONFIG_ARM_ERRATA_742230 | |
277 | cmp r6, #0x22 @ only present up to r2p2 | |
278 | mrcle p15, 0, r10, c15, c0, 1 @ read diagnostic register | |
279 | orrle r10, r10, #1 << 4 @ set bit #4 | |
280 | mcrle p15, 0, r10, c15, c0, 1 @ write diagnostic register | |
281 | #endif | |
a672e99b WD |
282 | #ifdef CONFIG_ARM_ERRATA_742231 |
283 | teq r6, #0x20 @ present in r2p0 | |
284 | teqne r6, #0x21 @ present in r2p1 | |
285 | teqne r6, #0x22 @ present in r2p2 | |
286 | mrceq p15, 0, r10, c15, c0, 1 @ read diagnostic register | |
287 | orreq r10, r10, #1 << 12 @ set bit #12 | |
288 | orreq r10, r10, #1 << 22 @ set bit #22 | |
289 | mcreq p15, 0, r10, c15, c0, 1 @ write diagnostic register | |
290 | #endif | |
475d92fc | 291 | #ifdef CONFIG_ARM_ERRATA_743622 |
efbc74ac | 292 | teq r5, #0x00200000 @ only present in r2p* |
475d92fc WD |
293 | mrceq p15, 0, r10, c15, c0, 1 @ read diagnostic register |
294 | orreq r10, r10, #1 << 6 @ set bit #6 | |
295 | mcreq p15, 0, r10, c15, c0, 1 @ write diagnostic register | |
296 | #endif | |
ba90c516 DM |
297 | #if defined(CONFIG_ARM_ERRATA_751472) && defined(CONFIG_SMP) |
298 | ALT_SMP(cmp r6, #0x30) @ present prior to r3p0 | |
299 | ALT_UP_B(1f) | |
9a27c27c WD |
300 | mrclt p15, 0, r10, c15, c0, 1 @ read diagnostic register |
301 | orrlt r10, r10, #1 << 11 @ set bit #11 | |
302 | mcrlt p15, 0, r10, c15, c0, 1 @ write diagnostic register | |
ba90c516 | 303 | 1: |
9a27c27c | 304 | #endif |
1946d6ef | 305 | |
9f05027c | 306 | 3: mov r10, #0 |
bbe88886 | 307 | mcr p15, 0, r10, c7, c5, 0 @ I+BTB cache invalidate |
bbe88886 | 308 | dsb |
2eb8c82b | 309 | #ifdef CONFIG_MMU |
bbe88886 | 310 | mcr p15, 0, r10, c8, c7, 0 @ invalidate I + D TLBs |
8d2cd3a3 | 311 | v7_ttb_setup r10, r4, r8, r5 @ TTBCR, TTBRx setup |
f6b0fa02 RK |
312 | ldr r5, =PRRR @ PRRR |
313 | ldr r6, =NMRR @ NMRR | |
3f69c0c1 RK |
314 | mcr p15, 0, r5, c10, c2, 0 @ write PRRR |
315 | mcr p15, 0, r6, c10, c2, 1 @ write NMRR | |
078c0454 JA |
316 | #endif |
317 | #ifndef CONFIG_ARM_THUMBEE | |
318 | mrc p15, 0, r0, c0, c1, 0 @ read ID_PFR0 for ThumbEE | |
319 | and r0, r0, #(0xf << 12) @ ThumbEE enabled field | |
320 | teq r0, #(1 << 12) @ check if ThumbEE is present | |
321 | bne 1f | |
322 | mov r5, #0 | |
323 | mcr p14, 6, r5, c1, c0, 0 @ Initialize TEEHBR to 0 | |
324 | mrc p14, 6, r0, c0, c0, 0 @ load TEECR | |
325 | orr r0, r0, #1 @ set the 1st bit in order to | |
326 | mcr p14, 6, r0, c0, c0, 0 @ stop userspace TEEHBR access | |
327 | 1: | |
bdaaaec3 | 328 | #endif |
2eb8c82b CM |
329 | adr r5, v7_crval |
330 | ldmia r5, {r5, r6} | |
26584853 CM |
331 | #ifdef CONFIG_CPU_ENDIAN_BE8 |
332 | orr r6, r6, #1 << 25 @ big-endian page tables | |
64d2dc38 LL |
333 | #endif |
334 | #ifdef CONFIG_SWP_EMULATE | |
335 | orr r5, r5, #(1 << 10) @ set SW bit in "clear" | |
336 | bic r6, r6, #(1 << 10) @ clear it in "mmuset" | |
26584853 | 337 | #endif |
2eb8c82b CM |
338 | mrc p15, 0, r0, c1, c0, 0 @ read control register |
339 | bic r0, r0, r5 @ clear bits them | |
340 | orr r0, r0, r6 @ set them | |
347c8b70 | 341 | THUMB( orr r0, r0, #1 << 30 ) @ Thumb exceptions |
bbe88886 | 342 | mov pc, lr @ return to head.S:__ret |
93ed3970 | 343 | ENDPROC(__v7_setup) |
bbe88886 | 344 | |
8d2cd3a3 | 345 | .align 2 |
bbe88886 CM |
346 | __v7_setup_stack: |
347 | .space 4 * 11 @ 11 registers | |
348 | ||
5085f3ff RK |
349 | __INITDATA |
350 | ||
78a8f3c3 DM |
351 | @ define struct processor (see <asm/proc-fns.h> and proc-macros.S) |
352 | define_processor_functions v7, dabort=v7_early_abort, pabort=v7_pabort, suspend=1 | |
bbe88886 | 353 | |
5085f3ff RK |
354 | .section ".rodata" |
355 | ||
78a8f3c3 DM |
356 | string cpu_arch_name, "armv7" |
357 | string cpu_elf_name, "v7" | |
bbe88886 CM |
358 | .align |
359 | ||
360 | .section ".proc.info.init", #alloc, #execinstr | |
361 | ||
dc939cd8 PM |
362 | /* |
363 | * Standard v7 proc info content | |
364 | */ | |
365 | .macro __v7_proc initfunc, mm_mmuflags = 0, io_mmuflags = 0, hwcaps = 0 | |
366 | ALT_SMP(.long PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_SECT_AP_READ | \ | |
1b6ba46b | 367 | PMD_SECT_AF | PMD_FLAGS_SMP | \mm_mmuflags) |
dc939cd8 | 368 | ALT_UP(.long PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_SECT_AP_READ | \ |
1b6ba46b CM |
369 | PMD_SECT_AF | PMD_FLAGS_UP | \mm_mmuflags) |
370 | .long PMD_TYPE_SECT | PMD_SECT_AP_WRITE | \ | |
371 | PMD_SECT_AP_READ | PMD_SECT_AF | \io_mmuflags | |
dc939cd8 | 372 | W(b) \initfunc |
14eff181 DW |
373 | .long cpu_arch_name |
374 | .long cpu_elf_name | |
dc939cd8 PM |
375 | .long HWCAP_SWP | HWCAP_HALF | HWCAP_THUMB | HWCAP_FAST_MULT | \ |
376 | HWCAP_EDSP | HWCAP_TLS | \hwcaps | |
14eff181 DW |
377 | .long cpu_v7_name |
378 | .long v7_processor_functions | |
379 | .long v7wbi_tlb_fns | |
380 | .long v6_user_fns | |
381 | .long v7_cache_fns | |
dc939cd8 PM |
382 | .endm |
383 | ||
1b6ba46b | 384 | #ifndef CONFIG_ARM_LPAE |
15eb169b PM |
385 | /* |
386 | * ARM Ltd. Cortex A5 processor. | |
387 | */ | |
388 | .type __v7_ca5mp_proc_info, #object | |
389 | __v7_ca5mp_proc_info: | |
390 | .long 0x410fc050 | |
391 | .long 0xff0ffff0 | |
392 | __v7_proc __v7_ca5mp_setup | |
393 | .size __v7_ca5mp_proc_info, . - __v7_ca5mp_proc_info | |
394 | ||
dc939cd8 PM |
395 | /* |
396 | * ARM Ltd. Cortex A9 processor. | |
397 | */ | |
398 | .type __v7_ca9mp_proc_info, #object | |
399 | __v7_ca9mp_proc_info: | |
400 | .long 0x410fc090 | |
401 | .long 0xff0ffff0 | |
402 | __v7_proc __v7_ca9mp_setup | |
14eff181 | 403 | .size __v7_ca9mp_proc_info, . - __v7_ca9mp_proc_info |
de490193 GC |
404 | |
405 | /* | |
406 | * Marvell PJ4B processor. | |
407 | */ | |
408 | .type __v7_pj4b_proc_info, #object | |
409 | __v7_pj4b_proc_info: | |
410 | .long 0x562f5840 | |
411 | .long 0xfffffff0 | |
412 | __v7_proc __v7_pj4b_setup | |
413 | .size __v7_pj4b_proc_info, . - __v7_pj4b_proc_info | |
1b6ba46b | 414 | #endif /* CONFIG_ARM_LPAE */ |
14eff181 | 415 | |
868dbf90 WD |
416 | /* |
417 | * ARM Ltd. Cortex A7 processor. | |
418 | */ | |
419 | .type __v7_ca7mp_proc_info, #object | |
420 | __v7_ca7mp_proc_info: | |
421 | .long 0x410fc070 | |
422 | .long 0xff0ffff0 | |
8164f7af | 423 | __v7_proc __v7_ca7mp_setup |
868dbf90 WD |
424 | .size __v7_ca7mp_proc_info, . - __v7_ca7mp_proc_info |
425 | ||
7665d9d2 WD |
426 | /* |
427 | * ARM Ltd. Cortex A15 processor. | |
428 | */ | |
429 | .type __v7_ca15mp_proc_info, #object | |
430 | __v7_ca15mp_proc_info: | |
431 | .long 0x410fc0f0 | |
432 | .long 0xff0ffff0 | |
8164f7af | 433 | __v7_proc __v7_ca15mp_setup |
7665d9d2 WD |
434 | .size __v7_ca15mp_proc_info, . - __v7_ca15mp_proc_info |
435 | ||
120ecfaf SM |
436 | /* |
437 | * Qualcomm Inc. Krait processors. | |
438 | */ | |
439 | .type __krait_proc_info, #object | |
440 | __krait_proc_info: | |
441 | .long 0x510f0400 @ Required ID value | |
442 | .long 0xff0ffc00 @ Mask for ID | |
443 | /* | |
444 | * Some Krait processors don't indicate support for SDIV and UDIV | |
445 | * instructions in the ARM instruction set, even though they actually | |
446 | * do support them. | |
447 | */ | |
448 | __v7_proc __v7_setup, hwcaps = HWCAP_IDIV | |
449 | .size __krait_proc_info, . - __krait_proc_info | |
450 | ||
bbe88886 CM |
451 | /* |
452 | * Match any ARMv7 processor core. | |
453 | */ | |
454 | .type __v7_proc_info, #object | |
455 | __v7_proc_info: | |
456 | .long 0x000f0000 @ Required ID value | |
457 | .long 0x000f0000 @ Mask for ID | |
dc939cd8 | 458 | __v7_proc __v7_setup |
bbe88886 | 459 | .size __v7_proc_info, . - __v7_proc_info |