[linux-2.6-block.git] / arch / arm / mm / proc-v7.S

/*
 *  linux/arch/arm/mm/proc-v7.S
 *
 *  Copyright (C) 2001 Deep Blue Solutions Ltd.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 *  This is the "shell" of the ARMv7 processor support.
 */
#include <linux/init.h>
#include <linux/linkage.h>
#include <asm/assembler.h>
#include <asm/asm-offsets.h>
#include <asm/hwcap.h>
#include <asm/pgtable-hwdef.h>
#include <asm/pgtable.h>

#include "proc-macros.S"

#ifdef CONFIG_ARM_LPAE
#include "proc-v7-3level.S"
#else
#include "proc-v7-2level.S"
#endif

ENTRY(cpu_v7_proc_init)
	mov	pc, lr
ENDPROC(cpu_v7_proc_init)

ENTRY(cpu_v7_proc_fin)
	mrc	p15, 0, r0, c1, c0, 0		@ ctrl register
	bic	r0, r0, #0x1000			@ ...i............
	bic	r0, r0, #0x0006			@ .............ca.
	mcr	p15, 0, r0, c1, c0, 0		@ disable caches
	mov	pc, lr
ENDPROC(cpu_v7_proc_fin)

/*
 *	cpu_v7_reset(loc)
 *
 *	Perform a soft reset of the system.  Put the CPU into the
 *	same state as it would be if it had been reset, and branch
 *	to what would be the reset vector.
 *
 *	- loc   - location to jump to for soft reset
 *
 *	This code must be executed using a flat identity mapping with
 *      caches disabled.
 */
	.align	5
	.pushsection	.idmap.text, "ax"
ENTRY(cpu_v7_reset)
	mrc	p15, 0, r1, c1, c0, 0		@ ctrl register
	bic	r1, r1, #0x1			@ ...............m
 THUMB(	bic	r1, r1, #1 << 30 )		@ SCTLR.TE (Thumb exceptions)
	mcr	p15, 0, r1, c1, c0, 0		@ disable MMU
	isb
	mov	pc, r0
ENDPROC(cpu_v7_reset)
	.popsection

/*
 *	cpu_v7_do_idle()
 *
 *	Idle the processor (eg, wait for interrupt).
 *
 *	IRQs are already disabled.
 */
ENTRY(cpu_v7_do_idle)
	dsb					@ WFI may enter a low-power mode
	wfi
	mov	pc, lr
ENDPROC(cpu_v7_do_idle)

ENTRY(cpu_v7_dcache_clean_area)
#ifndef TLB_CAN_READ_FROM_L1_CACHE
	dcache_line_size r2, r3
1:	mcr	p15, 0, r0, c7, c10, 1		@ clean D entry
	add	r0, r0, r2
	subs	r1, r1, r2
	bhi	1b
	dsb
#endif
	mov	pc, lr
ENDPROC(cpu_v7_dcache_clean_area)

	string	cpu_v7_name, "ARMv7 Processor"
	.align

/* Suspend/resume support: derived from arch/arm/mach-s5pv210/sleep.S */
.globl	cpu_v7_suspend_size
.equ	cpu_v7_suspend_size, 4 * 8
#ifdef CONFIG_ARM_CPU_SUSPEND
ENTRY(cpu_v7_do_suspend)
	stmfd	sp!, {r4 - r10, lr}
	mrc	p15, 0, r4, c13, c0, 0	@ FCSE/PID
	mrc	p15, 0, r5, c13, c0, 3	@ User r/o thread ID
	stmia	r0!, {r4 - r5}
	mrc	p15, 0, r6, c3, c0, 0	@ Domain ID
	mrc	p15, 0, r7, c2, c0, 1	@ TTB 1
	mrc	p15, 0, r11, c2, c0, 2	@ TTB control register
	mrc	p15, 0, r8, c1, c0, 0	@ Control register
	mrc	p15, 0, r9, c1, c0, 1	@ Auxiliary control register
	mrc	p15, 0, r10, c1, c0, 2	@ Co-processor access control
	stmia	r0, {r6 - r11}
	ldmfd	sp!, {r4 - r10, pc}
ENDPROC(cpu_v7_do_suspend)

ENTRY(cpu_v7_do_resume)
	mov	ip, #0
	mcr	p15, 0, ip, c8, c7, 0	@ invalidate TLBs
	mcr	p15, 0, ip, c7, c5, 0	@ invalidate I cache
	mcr	p15, 0, ip, c13, c0, 1	@ set reserved context ID
	ldmia	r0!, {r4 - r5}
	mcr	p15, 0, r4, c13, c0, 0	@ FCSE/PID
	mcr	p15, 0, r5, c13, c0, 3	@ User r/o thread ID
	ldmia	r0, {r6 - r11}
	mcr	p15, 0, r6, c3, c0, 0	@ Domain ID
#ifndef CONFIG_ARM_LPAE
	ALT_SMP(orr	r1, r1, #TTB_FLAGS_SMP)
	ALT_UP(orr	r1, r1, #TTB_FLAGS_UP)
#endif
	mcr	p15, 0, r1, c2, c0, 0	@ TTB 0
	mcr	p15, 0, r7, c2, c0, 1	@ TTB 1
	mcr	p15, 0, r11, c2, c0, 2	@ TTB control register
	mrc	p15, 0, r4, c1, c0, 1	@ Read Auxiliary control register
	teq	r4, r9			@ Is it already set?
	mcrne	p15, 0, r9, c1, c0, 1	@ No, so write it
	mcr	p15, 0, r10, c1, c0, 2	@ Co-processor access control
	ldr	r4, =PRRR		@ PRRR
	ldr	r5, =NMRR		@ NMRR
	mcr	p15, 0, r4, c10, c2, 0	@ write PRRR
	mcr	p15, 0, r5, c10, c2, 1	@ write NMRR
	isb
	dsb
	mov	r0, r8			@ control register
	b	cpu_resume_mmu
ENDPROC(cpu_v7_do_resume)
#endif

	__CPUINIT

/*
 *	__v7_setup
 *
 *	Initialise TLB, Caches, and MMU state ready to switch the MMU
 *	on.  Return in r0 the new CP15 C1 control register setting.
 *
 *	This should be able to cover all ARMv7 cores.
 *
 *	It is assumed that:
 *	- cache type register is implemented
 */
__v7_ca5mp_setup:
__v7_ca9mp_setup:
	mov	r10, #(1 << 0)			@ TLB ops broadcasting
	b	1f
__v7_ca7mp_setup:
__v7_ca15mp_setup:
	mov	r10, #0
1:
#ifdef CONFIG_SMP
	ALT_SMP(mrc	p15, 0, r0, c1, c0, 1)
	ALT_UP(mov	r0, #(1 << 6))		@ fake it for UP
	tst	r0, #(1 << 6)			@ SMP/nAMP mode enabled?
	orreq	r0, r0, #(1 << 6)		@ Enable SMP/nAMP mode
	orreq	r0, r0, r10			@ Enable CPU-specific SMP bits
	mcreq	p15, 0, r0, c1, c0, 1
#endif
__v7_setup:
	adr	r12, __v7_setup_stack		@ the local stack
	stmia	r12, {r0-r5, r7, r9, r11, lr}
	bl	v7_flush_dcache_all
	ldmia	r12, {r0-r5, r7, r9, r11, lr}

	mrc	p15, 0, r0, c0, c0, 0		@ read main ID register
	and	r10, r0, #0xff000000		@ ARM?
	teq	r10, #0x41000000
	bne	3f
	and	r5, r0, #0x00f00000		@ variant
	and	r6, r0, #0x0000000f		@ revision
	orr	r6, r6, r5, lsr #20-4		@ combine variant and revision
	ubfx	r0, r0, #4, #12			@ primary part number

	/* Cortex-A8 Errata */
	ldr	r10, =0x00000c08		@ Cortex-A8 primary part number
	teq	r0, r10
	bne	2f
#ifdef CONFIG_ARM_ERRATA_430973
	teq	r5, #0x00100000			@ only present in r1p*
	mrceq	p15, 0, r10, c1, c0, 1		@ read aux control register
	orreq	r10, r10, #(1 << 6)		@ set IBE to 1
	mcreq	p15, 0, r10, c1, c0, 1		@ write aux control register
#endif
#ifdef CONFIG_ARM_ERRATA_458693
	teq	r6, #0x20			@ only present in r2p0
	mrceq	p15, 0, r10, c1, c0, 1		@ read aux control register
	orreq	r10, r10, #(1 << 5)		@ set L1NEON to 1
	orreq	r10, r10, #(1 << 9)		@ set PLDNOP to 1
	mcreq	p15, 0, r10, c1, c0, 1		@ write aux control register
#endif
#ifdef CONFIG_ARM_ERRATA_460075
	teq	r6, #0x20			@ only present in r2p0
	mrceq	p15, 1, r10, c9, c0, 2		@ read L2 cache aux ctrl register
	tsteq	r10, #1 << 22
	orreq	r10, r10, #(1 << 22)		@ set the Write Allocate disable bit
	mcreq	p15, 1, r10, c9, c0, 2		@ write the L2 cache aux ctrl register
#endif
	b	3f

	/* Cortex-A9 Errata */
2:	ldr	r10, =0x00000c09		@ Cortex-A9 primary part number
	teq	r0, r10
	bne	3f
#ifdef CONFIG_ARM_ERRATA_742230
	cmp	r6, #0x22			@ only present up to r2p2
	mrcle	p15, 0, r10, c15, c0, 1		@ read diagnostic register
	orrle	r10, r10, #1 << 4		@ set bit #4
	mcrle	p15, 0, r10, c15, c0, 1		@ write diagnostic register
#endif
#ifdef CONFIG_ARM_ERRATA_742231
	teq	r6, #0x20			@ present in r2p0
	teqne	r6, #0x21			@ present in r2p1
	teqne	r6, #0x22			@ present in r2p2
	mrceq	p15, 0, r10, c15, c0, 1		@ read diagnostic register
	orreq	r10, r10, #1 << 12		@ set bit #12
	orreq	r10, r10, #1 << 22		@ set bit #22
	mcreq	p15, 0, r10, c15, c0, 1		@ write diagnostic register
#endif
#ifdef CONFIG_ARM_ERRATA_743622
	teq	r6, #0x20			@ present in r2p0
	teqne	r6, #0x21			@ present in r2p1
	teqne	r6, #0x22			@ present in r2p2
	mrceq	p15, 0, r10, c15, c0, 1		@ read diagnostic register
	orreq	r10, r10, #1 << 6		@ set bit #6
	mcreq	p15, 0, r10, c15, c0, 1		@ write diagnostic register
#endif
#if defined(CONFIG_ARM_ERRATA_751472) && defined(CONFIG_SMP)
	ALT_SMP(cmp r6, #0x30)			@ present prior to r3p0
	ALT_UP_B(1f)
	mrclt	p15, 0, r10, c15, c0, 1		@ read diagnostic register
	orrlt	r10, r10, #1 << 11		@ set bit #11
	mcrlt	p15, 0, r10, c15, c0, 1		@ write diagnostic register
1:
#endif

3:	mov	r10, #0
	mcr	p15, 0, r10, c7, c5, 0		@ I+BTB cache invalidate
	dsb
#ifdef CONFIG_MMU
	mcr	p15, 0, r10, c8, c7, 0		@ invalidate I + D TLBs
	v7_ttb_setup r10, r4, r8, r5		@ TTBCR, TTBRx setup
	ldr	r5, =PRRR			@ PRRR
	ldr	r6, =NMRR			@ NMRR
	mcr	p15, 0, r5, c10, c2, 0		@ write PRRR
	mcr	p15, 0, r6, c10, c2, 1		@ write NMRR
#endif
	adr	r5, v7_crval
	ldmia	r5, {r5, r6}
#ifdef CONFIG_CPU_ENDIAN_BE8
	orr	r6, r6, #1 << 25		@ big-endian page tables
#endif
#ifdef CONFIG_SWP_EMULATE
	orr     r5, r5, #(1 << 10)              @ set SW bit in "clear"
	bic     r6, r6, #(1 << 10)              @ clear it in "mmuset"
#endif
   	mrc	p15, 0, r0, c1, c0, 0		@ read control register
	bic	r0, r0, r5			@ clear bits them
	orr	r0, r0, r6			@ set them
 THUMB(	orr	r0, r0, #1 << 30	)	@ Thumb exceptions
	mov	pc, lr				@ return to head.S:__ret
ENDPROC(__v7_setup)

	.align	2
__v7_setup_stack:
	.space	4 * 11				@ 11 registers

	__INITDATA

	@ define struct processor (see <asm/proc-fns.h> and proc-macros.S)
	define_processor_functions v7, dabort=v7_early_abort, pabort=v7_pabort, suspend=1

	.section ".rodata"

	string	cpu_arch_name, "armv7"
	string	cpu_elf_name, "v7"
	.align

	.section ".proc.info.init", #alloc, #execinstr

	/*
	 * Standard v7 proc info content
	 */
.macro __v7_proc initfunc, mm_mmuflags = 0, io_mmuflags = 0, hwcaps = 0
	ALT_SMP(.long	PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_SECT_AP_READ | \
			PMD_SECT_AF | PMD_FLAGS_SMP | \mm_mmuflags)
	ALT_UP(.long	PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_SECT_AP_READ | \
			PMD_SECT_AF | PMD_FLAGS_UP | \mm_mmuflags)
	.long	PMD_TYPE_SECT | PMD_SECT_AP_WRITE | \
		PMD_SECT_AP_READ | PMD_SECT_AF | \io_mmuflags
	W(b)	\initfunc
	.long	cpu_arch_name
	.long	cpu_elf_name
	.long	HWCAP_SWP | HWCAP_HALF | HWCAP_THUMB | HWCAP_FAST_MULT | \
		HWCAP_EDSP | HWCAP_TLS | \hwcaps
	.long	cpu_v7_name
	.long	v7_processor_functions
	.long	v7wbi_tlb_fns
	.long	v6_user_fns
	.long	v7_cache_fns
.endm

#ifndef CONFIG_ARM_LPAE
	/*
	 * ARM Ltd. Cortex A5 processor.
	 */
	.type   __v7_ca5mp_proc_info, #object
__v7_ca5mp_proc_info:
	.long	0x410fc050
	.long	0xff0ffff0
	__v7_proc __v7_ca5mp_setup
	.size	__v7_ca5mp_proc_info, . - __v7_ca5mp_proc_info

	/*
	 * ARM Ltd. Cortex A9 processor.
	 */
	.type   __v7_ca9mp_proc_info, #object
__v7_ca9mp_proc_info:
	.long	0x410fc090
	.long	0xff0ffff0
	__v7_proc __v7_ca9mp_setup
	.size	__v7_ca9mp_proc_info, . - __v7_ca9mp_proc_info
#endif	/* CONFIG_ARM_LPAE */

	/*
	 * ARM Ltd. Cortex A7 processor.
	 */
	.type	__v7_ca7mp_proc_info, #object
__v7_ca7mp_proc_info:
	.long	0x410fc070
	.long	0xff0ffff0
	__v7_proc __v7_ca7mp_setup, hwcaps = HWCAP_IDIV
	.size	__v7_ca7mp_proc_info, . - __v7_ca7mp_proc_info

	/*
	 * ARM Ltd. Cortex A15 processor.
	 */
	.type	__v7_ca15mp_proc_info, #object
__v7_ca15mp_proc_info:
	.long	0x410fc0f0
	.long	0xff0ffff0
	__v7_proc __v7_ca15mp_setup, hwcaps = HWCAP_IDIV
	.size	__v7_ca15mp_proc_info, . - __v7_ca15mp_proc_info

	/*
	 * Match any ARMv7 processor core.
	 */
	.type	__v7_proc_info, #object
__v7_proc_info:
	.long	0x000f0000		@ Required ID value
	.long	0x000f0000		@ Mask for ID
	__v7_proc __v7_setup
	.size	__v7_proc_info, . - __v7_proc_info
Commit	Line	Data
bbe88886 CM	1	/*
	2	* linux/arch/arm/mm/proc-v7.S
	3	*
	4	* Copyright (C) 2001 Deep Blue Solutions Ltd.
	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License version 2 as
	8	* published by the Free Software Foundation.
	9	*
	10	* This is the "shell" of the ARMv7 processor support.
	11	*/
991da17e	12	#include <linux/init.h>
bbe88886 CM	13	#include <linux/linkage.h>
	14	#include <asm/assembler.h>
	15	#include <asm/asm-offsets.h>
5ec9407d	16	#include <asm/hwcap.h>
bbe88886 CM	17	#include <asm/pgtable-hwdef.h>
	18	#include <asm/pgtable.h>
	19
	20	#include "proc-macros.S"
	21
1b6ba46b CM	22	#ifdef CONFIG_ARM_LPAE
	23	#include "proc-v7-3level.S"
	24	#else
8d2cd3a3	25	#include "proc-v7-2level.S"
1b6ba46b	26	#endif
73b63efa	27
bbe88886 CM	28	ENTRY(cpu_v7_proc_init)
bbe88886 CM	29	mov pc, lr
93ed3970	30	ENDPROC(cpu_v7_proc_init)
bbe88886 CM	31
bbe88886 CM	32	ENTRY(cpu_v7_proc_fin)
1f667c69 TL	33	mrc p15, 0, r0, c1, c0, 0 @ ctrl register
	34	bic r0, r0, #0x1000 @ ...i............
	35	bic r0, r0, #0x0006 @ .............ca.
	36	mcr p15, 0, r0, c1, c0, 0 @ disable caches
9ca03a21	37	mov pc, lr
93ed3970	38	ENDPROC(cpu_v7_proc_fin)
bbe88886 CM	39
	40	/*
	41	* cpu_v7_reset(loc)
	42	*
	43	* Perform a soft reset of the system. Put the CPU into the
	44	* same state as it would be if it had been reset, and branch
	45	* to what would be the reset vector.
	46	*
	47	* - loc - location to jump to for soft reset
f4daf06f WD	48	*
	49	* This code must be executed using a flat identity mapping with
	50	* caches disabled.
bbe88886 CM	51	*/
bbe88886 CM	52	.align 5
1a4baafa	53	.pushsection .idmap.text, "ax"
bbe88886	54	ENTRY(cpu_v7_reset)
f4daf06f WD	55	mrc p15, 0, r1, c1, c0, 0 @ ctrl register
f4daf06f WD	56	bic r1, r1, #0x1 @ ...............m
0f81bb6b	57	THUMB( bic r1, r1, #1 << 30 ) @ SCTLR.TE (Thumb exceptions)
f4daf06f WD	58	mcr p15, 0, r1, c1, c0, 0 @ disable MMU
f4daf06f WD	59	isb
bbe88886	60	mov pc, r0
93ed3970	61	ENDPROC(cpu_v7_reset)
1a4baafa	62	.popsection
bbe88886 CM	63
	64	/*
	65	* cpu_v7_do_idle()
	66	*
	67	* Idle the processor (eg, wait for interrupt).
	68	*
	69	* IRQs are already disabled.
	70	*/
	71	ENTRY(cpu_v7_do_idle)
8553cb67	72	dsb @ WFI may enter a low-power mode
000b5025	73	wfi
bbe88886	74	mov pc, lr
93ed3970	75	ENDPROC(cpu_v7_do_idle)
bbe88886 CM	76
	77	ENTRY(cpu_v7_dcache_clean_area)
	78	#ifndef TLB_CAN_READ_FROM_L1_CACHE
	79	dcache_line_size r2, r3
	80	1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
	81	add r0, r0, r2
	82	subs r1, r1, r2
	83	bhi 1b
	84	dsb
	85	#endif
	86	mov pc, lr
93ed3970	87	ENDPROC(cpu_v7_dcache_clean_area)
bbe88886	88
78a8f3c3	89	string cpu_v7_name, "ARMv7 Processor"
bbe88886 CM	90	.align
bbe88886 CM	91
f6b0fa02 RK	92	/* Suspend/resume support: derived from arch/arm/mach-s5pv210/sleep.S */
f6b0fa02 RK	93	.globl cpu_v7_suspend_size
1b6ba46b	94	.equ cpu_v7_suspend_size, 4 * 8
15e0d9e3	95	#ifdef CONFIG_ARM_CPU_SUSPEND
f6b0fa02	96	ENTRY(cpu_v7_do_suspend)
de8e71ca	97	stmfd sp!, {r4 - r10, lr}
f6b0fa02	98	mrc p15, 0, r4, c13, c0, 0 @ FCSE/PID
1aede681 RK	99	mrc p15, 0, r5, c13, c0, 3 @ User r/o thread ID
1aede681 RK	100	stmia r0!, {r4 - r5}
f6b0fa02	101	mrc p15, 0, r6, c3, c0, 0 @ Domain ID
de8e71ca	102	mrc p15, 0, r7, c2, c0, 1 @ TTB 1
1b6ba46b	103	mrc p15, 0, r11, c2, c0, 2 @ TTB control register
de8e71ca RK	104	mrc p15, 0, r8, c1, c0, 0 @ Control register
	105	mrc p15, 0, r9, c1, c0, 1 @ Auxiliary control register
	106	mrc p15, 0, r10, c1, c0, 2 @ Co-processor access control
1b6ba46b	107	stmia r0, {r6 - r11}
de8e71ca	108	ldmfd sp!, {r4 - r10, pc}
f6b0fa02 RK	109	ENDPROC(cpu_v7_do_suspend)
	110
	111	ENTRY(cpu_v7_do_resume)
	112	mov ip, #0
	113	mcr p15, 0, ip, c8, c7, 0 @ invalidate TLBs
	114	mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache
1aede681 RK	115	mcr p15, 0, ip, c13, c0, 1 @ set reserved context ID
1aede681 RK	116	ldmia r0!, {r4 - r5}
f6b0fa02	117	mcr p15, 0, r4, c13, c0, 0 @ FCSE/PID
1aede681	118	mcr p15, 0, r5, c13, c0, 3 @ User r/o thread ID
1b6ba46b	119	ldmia r0, {r6 - r11}
f6b0fa02	120	mcr p15, 0, r6, c3, c0, 0 @ Domain ID
1b6ba46b	121	#ifndef CONFIG_ARM_LPAE
de8e71ca RK	122	ALT_SMP(orr r1, r1, #TTB_FLAGS_SMP)
de8e71ca RK	123	ALT_UP(orr r1, r1, #TTB_FLAGS_UP)
1b6ba46b	124	#endif
de8e71ca RK	125	mcr p15, 0, r1, c2, c0, 0 @ TTB 0
de8e71ca RK	126	mcr p15, 0, r7, c2, c0, 1 @ TTB 1
1b6ba46b	127	mcr p15, 0, r11, c2, c0, 2 @ TTB control register
25904157	128	mrc p15, 0, r4, c1, c0, 1 @ Read Auxiliary control register
de8e71ca RK	129	teq r4, r9 @ Is it already set?
	130	mcrne p15, 0, r9, c1, c0, 1 @ No, so write it
	131	mcr p15, 0, r10, c1, c0, 2 @ Co-processor access control
f6b0fa02 RK	132	ldr r4, =PRRR @ PRRR
	133	ldr r5, =NMRR @ NMRR
	134	mcr p15, 0, r4, c10, c2, 0 @ write PRRR
	135	mcr p15, 0, r5, c10, c2, 1 @ write NMRR
	136	isb
f35235a3	137	dsb
de8e71ca	138	mov r0, r8 @ control register
f6b0fa02 RK	139	b cpu_resume_mmu
f6b0fa02 RK	140	ENDPROC(cpu_v7_do_resume)
f6b0fa02 RK	141	#endif
f6b0fa02 RK	142
5085f3ff	143	__CPUINIT
bbe88886 CM	144
	145	/*
	146	* __v7_setup
	147	*
	148	* Initialise TLB, Caches, and MMU state ready to switch the MMU
	149	* on. Return in r0 the new CP15 C1 control register setting.
	150	*
bbe88886 CM	151	* This should be able to cover all ARMv7 cores.
	152	*
	153	* It is assumed that:
	154	* - cache type register is implemented
	155	*/
15eb169b	156	__v7_ca5mp_setup:
14eff181	157	__v7_ca9mp_setup:
7665d9d2 WD	158	mov r10, #(1 << 0) @ TLB ops broadcasting
7665d9d2 WD	159	b 1f
b4244738	160	__v7_ca7mp_setup:
7665d9d2 WD	161	__v7_ca15mp_setup:
	162	mov r10, #0
	163	1:
73b63efa	164	#ifdef CONFIG_SMP
f00ec48f RK	165	ALT_SMP(mrc p15, 0, r0, c1, c0, 1)
f00ec48f RK	166	ALT_UP(mov r0, #(1 << 6)) @ fake it for UP
1b3a02eb	167	tst r0, #(1 << 6) @ SMP/nAMP mode enabled?
7665d9d2 WD	168	orreq r0, r0, #(1 << 6) @ Enable SMP/nAMP mode
	169	orreq r0, r0, r10 @ Enable CPU-specific SMP bits
	170	mcreq p15, 0, r0, c1, c0, 1
73b63efa	171	#endif
14eff181	172	__v7_setup:
bbe88886 CM	173	adr r12, __v7_setup_stack @ the local stack
	174	stmia r12, {r0-r5, r7, r9, r11, lr}
	175	bl v7_flush_dcache_all
	176	ldmia r12, {r0-r5, r7, r9, r11, lr}
1946d6ef RK	177
	178	mrc p15, 0, r0, c0, c0, 0 @ read main ID register
	179	and r10, r0, #0xff000000 @ ARM?
	180	teq r10, #0x41000000
9f05027c	181	bne 3f
1946d6ef RK	182	and r5, r0, #0x00f00000 @ variant
1946d6ef RK	183	and r6, r0, #0x0000000f @ revision
6491848d WD	184	orr r6, r6, r5, lsr #20-4 @ combine variant and revision
6491848d WD	185	ubfx r0, r0, #4, #12 @ primary part number
1946d6ef	186
6491848d WD	187	/* Cortex-A8 Errata */
	188	ldr r10, =0x00000c08 @ Cortex-A8 primary part number
	189	teq r0, r10
	190	bne 2f
7ce236fc	191	#ifdef CONFIG_ARM_ERRATA_430973
1946d6ef RK	192	teq r5, #0x00100000 @ only present in r1p*
	193	mrceq p15, 0, r10, c1, c0, 1 @ read aux control register
	194	orreq r10, r10, #(1 << 6) @ set IBE to 1
	195	mcreq p15, 0, r10, c1, c0, 1 @ write aux control register
855c551f CM	196	#endif
855c551f CM	197	#ifdef CONFIG_ARM_ERRATA_458693
6491848d	198	teq r6, #0x20 @ only present in r2p0
1946d6ef RK	199	mrceq p15, 0, r10, c1, c0, 1 @ read aux control register
	200	orreq r10, r10, #(1 << 5) @ set L1NEON to 1
	201	orreq r10, r10, #(1 << 9) @ set PLDNOP to 1
	202	mcreq p15, 0, r10, c1, c0, 1 @ write aux control register
0516e464 CM	203	#endif
0516e464 CM	204	#ifdef CONFIG_ARM_ERRATA_460075
6491848d	205	teq r6, #0x20 @ only present in r2p0
1946d6ef RK	206	mrceq p15, 1, r10, c9, c0, 2 @ read L2 cache aux ctrl register
	207	tsteq r10, #1 << 22
	208	orreq r10, r10, #(1 << 22) @ set the Write Allocate disable bit
	209	mcreq p15, 1, r10, c9, c0, 2 @ write the L2 cache aux ctrl register
7ce236fc	210	#endif
9f05027c WD	211	b 3f
	212
	213	/* Cortex-A9 Errata */
	214	2: ldr r10, =0x00000c09 @ Cortex-A9 primary part number
	215	teq r0, r10
	216	bne 3f
	217	#ifdef CONFIG_ARM_ERRATA_742230
	218	cmp r6, #0x22 @ only present up to r2p2
	219	mrcle p15, 0, r10, c15, c0, 1 @ read diagnostic register
	220	orrle r10, r10, #1 << 4 @ set bit #4
	221	mcrle p15, 0, r10, c15, c0, 1 @ write diagnostic register
	222	#endif
a672e99b WD	223	#ifdef CONFIG_ARM_ERRATA_742231
	224	teq r6, #0x20 @ present in r2p0
	225	teqne r6, #0x21 @ present in r2p1
	226	teqne r6, #0x22 @ present in r2p2
	227	mrceq p15, 0, r10, c15, c0, 1 @ read diagnostic register
	228	orreq r10, r10, #1 << 12 @ set bit #12
	229	orreq r10, r10, #1 << 22 @ set bit #22
	230	mcreq p15, 0, r10, c15, c0, 1 @ write diagnostic register
	231	#endif
475d92fc WD	232	#ifdef CONFIG_ARM_ERRATA_743622
	233	teq r6, #0x20 @ present in r2p0
	234	teqne r6, #0x21 @ present in r2p1
	235	teqne r6, #0x22 @ present in r2p2
	236	mrceq p15, 0, r10, c15, c0, 1 @ read diagnostic register
	237	orreq r10, r10, #1 << 6 @ set bit #6
	238	mcreq p15, 0, r10, c15, c0, 1 @ write diagnostic register
	239	#endif
ba90c516 DM	240	#if defined(CONFIG_ARM_ERRATA_751472) && defined(CONFIG_SMP)
	241	ALT_SMP(cmp r6, #0x30) @ present prior to r3p0
	242	ALT_UP_B(1f)
9a27c27c WD	243	mrclt p15, 0, r10, c15, c0, 1 @ read diagnostic register
	244	orrlt r10, r10, #1 << 11 @ set bit #11
	245	mcrlt p15, 0, r10, c15, c0, 1 @ write diagnostic register
ba90c516	246	1:
9a27c27c	247	#endif
1946d6ef	248
9f05027c	249	3: mov r10, #0
bbe88886	250	mcr p15, 0, r10, c7, c5, 0 @ I+BTB cache invalidate
bbe88886	251	dsb
2eb8c82b	252	#ifdef CONFIG_MMU
bbe88886	253	mcr p15, 0, r10, c8, c7, 0 @ invalidate I + D TLBs
8d2cd3a3	254	v7_ttb_setup r10, r4, r8, r5 @ TTBCR, TTBRx setup
f6b0fa02 RK	255	ldr r5, =PRRR @ PRRR
f6b0fa02 RK	256	ldr r6, =NMRR @ NMRR
3f69c0c1 RK	257	mcr p15, 0, r5, c10, c2, 0 @ write PRRR
3f69c0c1 RK	258	mcr p15, 0, r6, c10, c2, 1 @ write NMRR
bdaaaec3	259	#endif
2eb8c82b CM	260	adr r5, v7_crval
2eb8c82b CM	261	ldmia r5, {r5, r6}
26584853 CM	262	#ifdef CONFIG_CPU_ENDIAN_BE8
26584853 CM	263	orr r6, r6, #1 << 25 @ big-endian page tables
64d2dc38 LL	264	#endif
	265	#ifdef CONFIG_SWP_EMULATE
	266	orr r5, r5, #(1 << 10) @ set SW bit in "clear"
	267	bic r6, r6, #(1 << 10) @ clear it in "mmuset"
26584853	268	#endif
2eb8c82b CM	269	mrc p15, 0, r0, c1, c0, 0 @ read control register
	270	bic r0, r0, r5 @ clear bits them
	271	orr r0, r0, r6 @ set them
347c8b70	272	THUMB( orr r0, r0, #1 << 30 ) @ Thumb exceptions
bbe88886	273	mov pc, lr @ return to head.S:__ret
93ed3970	274	ENDPROC(__v7_setup)
bbe88886	275
8d2cd3a3	276	.align 2
bbe88886 CM	277	__v7_setup_stack:
	278	.space 4 * 11 @ 11 registers
	279
5085f3ff RK	280	__INITDATA
5085f3ff RK	281
78a8f3c3 DM	282	@ define struct processor (see <asm/proc-fns.h> and proc-macros.S)
78a8f3c3 DM	283	define_processor_functions v7, dabort=v7_early_abort, pabort=v7_pabort, suspend=1
bbe88886	284
5085f3ff RK	285	.section ".rodata"
5085f3ff RK	286
78a8f3c3 DM	287	string cpu_arch_name, "armv7"
78a8f3c3 DM	288	string cpu_elf_name, "v7"
bbe88886 CM	289	.align
	290
	291	.section ".proc.info.init", #alloc, #execinstr
	292
dc939cd8 PM	293	/*
	294	* Standard v7 proc info content
	295	*/
	296	.macro __v7_proc initfunc, mm_mmuflags = 0, io_mmuflags = 0, hwcaps = 0
	297	ALT_SMP(.long PMD_TYPE_SECT \| PMD_SECT_AP_WRITE \| PMD_SECT_AP_READ \| \
1b6ba46b	298	PMD_SECT_AF \| PMD_FLAGS_SMP \| \mm_mmuflags)
dc939cd8	299	ALT_UP(.long PMD_TYPE_SECT \| PMD_SECT_AP_WRITE \| PMD_SECT_AP_READ \| \
1b6ba46b CM	300	PMD_SECT_AF \| PMD_FLAGS_UP \| \mm_mmuflags)
	301	.long PMD_TYPE_SECT \| PMD_SECT_AP_WRITE \| \
	302	PMD_SECT_AP_READ \| PMD_SECT_AF \| \io_mmuflags
dc939cd8	303	W(b) \initfunc
14eff181 DW	304	.long cpu_arch_name
14eff181 DW	305	.long cpu_elf_name
dc939cd8 PM	306	.long HWCAP_SWP \| HWCAP_HALF \| HWCAP_THUMB \| HWCAP_FAST_MULT \| \
dc939cd8 PM	307	HWCAP_EDSP \| HWCAP_TLS \| \hwcaps
14eff181 DW	308	.long cpu_v7_name
	309	.long v7_processor_functions
	310	.long v7wbi_tlb_fns
	311	.long v6_user_fns
	312	.long v7_cache_fns
dc939cd8 PM	313	.endm
dc939cd8 PM	314
1b6ba46b	315	#ifndef CONFIG_ARM_LPAE
15eb169b PM	316	/*
	317	* ARM Ltd. Cortex A5 processor.
	318	*/
	319	.type __v7_ca5mp_proc_info, #object
	320	__v7_ca5mp_proc_info:
	321	.long 0x410fc050
	322	.long 0xff0ffff0
	323	__v7_proc __v7_ca5mp_setup
	324	.size __v7_ca5mp_proc_info, . - __v7_ca5mp_proc_info
	325
dc939cd8 PM	326	/*
	327	* ARM Ltd. Cortex A9 processor.
	328	*/
	329	.type __v7_ca9mp_proc_info, #object
	330	__v7_ca9mp_proc_info:
	331	.long 0x410fc090
	332	.long 0xff0ffff0
	333	__v7_proc __v7_ca9mp_setup
14eff181	334	.size __v7_ca9mp_proc_info, . - __v7_ca9mp_proc_info
1b6ba46b	335	#endif /* CONFIG_ARM_LPAE */
14eff181	336
868dbf90 WD	337	/*
	338	* ARM Ltd. Cortex A7 processor.
	339	*/
	340	.type __v7_ca7mp_proc_info, #object
	341	__v7_ca7mp_proc_info:
	342	.long 0x410fc070
	343	.long 0xff0ffff0
	344	__v7_proc __v7_ca7mp_setup, hwcaps = HWCAP_IDIV
	345	.size __v7_ca7mp_proc_info, . - __v7_ca7mp_proc_info
	346
7665d9d2 WD	347	/*
	348	* ARM Ltd. Cortex A15 processor.
	349	*/
	350	.type __v7_ca15mp_proc_info, #object
	351	__v7_ca15mp_proc_info:
	352	.long 0x410fc0f0
	353	.long 0xff0ffff0
	354	__v7_proc __v7_ca15mp_setup, hwcaps = HWCAP_IDIV
	355	.size __v7_ca15mp_proc_info, . - __v7_ca15mp_proc_info
	356
bbe88886 CM	357	/*
	358	* Match any ARMv7 processor core.
	359	*/
	360	.type __v7_proc_info, #object
	361	__v7_proc_info:
	362	.long 0x000f0000 @ Required ID value
	363	.long 0x000f0000 @ Mask for ID
dc939cd8	364	__v7_proc __v7_setup
bbe88886	365	.size __v7_proc_info, . - __v7_proc_info