[linux-2.6-block.git] / arch / arm / mm / proc-v7-2level.S

/*
 * arch/arm/mm/proc-v7-2level.S
 *
 * Copyright (C) 2001 Deep Blue Solutions Ltd.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#define TTB_S		(1 << 1)
#define TTB_RGN_NC	(0 << 3)
#define TTB_RGN_OC_WBWA	(1 << 3)
#define TTB_RGN_OC_WT	(2 << 3)
#define TTB_RGN_OC_WB	(3 << 3)
#define TTB_NOS		(1 << 5)
#define TTB_IRGN_NC	((0 << 0) | (0 << 6))
#define TTB_IRGN_WBWA	((0 << 0) | (1 << 6))
#define TTB_IRGN_WT	((1 << 0) | (0 << 6))
#define TTB_IRGN_WB	((1 << 0) | (1 << 6))

/* PTWs cacheable, inner WB not shareable, outer WB not shareable */
#define TTB_FLAGS_UP	TTB_IRGN_WB|TTB_RGN_OC_WB
#define PMD_FLAGS_UP	PMD_SECT_WB

/* PTWs cacheable, inner WBWA shareable, outer WBWA not shareable */
#define TTB_FLAGS_SMP	TTB_IRGN_WBWA|TTB_S|TTB_NOS|TTB_RGN_OC_WBWA
#define PMD_FLAGS_SMP	PMD_SECT_WBWA|PMD_SECT_S

/*
 *	cpu_v7_switch_mm(pgd_phys, tsk)
 *
 *	Set the translation table base pointer to be pgd_phys
 *
 *	- pgd_phys - physical address of new TTB
 *
 *	It is assumed that:
 *	- we are not using split page tables
 *
 *	Note that we always need to flush BTAC/BTB if IBE is set
 *	even on Cortex-A8 revisions not affected by 430973.
 *	If IBE is not set, the flush BTAC/BTB won't do anything.
 */
ENTRY(cpu_ca8_switch_mm)
#ifdef CONFIG_MMU
	mov	r2, #0
	mcr	p15, 0, r2, c7, c5, 6		@ flush BTAC/BTB
#endif
ENTRY(cpu_v7_switch_mm)
#ifdef CONFIG_MMU
	mmid	r1, r1				@ get mm->context.id
	ALT_SMP(orr	r0, r0, #TTB_FLAGS_SMP)
	ALT_UP(orr	r0, r0, #TTB_FLAGS_UP)
#ifdef CONFIG_PID_IN_CONTEXTIDR
	mrc	p15, 0, r2, c13, c0, 1		@ read current context ID
	lsr	r2, r2, #8			@ extract the PID
	bfi	r1, r2, #8, #24			@ insert into new context ID
#endif
#ifdef CONFIG_ARM_ERRATA_754322
	dsb
#endif
	mcr	p15, 0, r1, c13, c0, 1		@ set context ID
	isb
	mcr	p15, 0, r0, c2, c0, 0		@ set TTB 0
	isb
#endif
	bx	lr
ENDPROC(cpu_v7_switch_mm)
ENDPROC(cpu_ca8_switch_mm)

/*
 *	cpu_v7_set_pte_ext(ptep, pte)
 *
 *	Set a level 2 translation table entry.
 *
 *	- ptep  - pointer to level 2 translation table entry
 *		  (hardware version is stored at +2048 bytes)
 *	- pte   - PTE value to store
 *	- ext	- value for extended PTE bits
 */
ENTRY(cpu_v7_set_pte_ext)
#ifdef CONFIG_MMU
	str	r1, [r0]			@ linux version

	bic	r3, r1, #0x000003f0
	bic	r3, r3, #PTE_TYPE_MASK
	orr	r3, r3, r2
	orr	r3, r3, #PTE_EXT_AP0 | 2

	tst	r1, #1 << 4
	orrne	r3, r3, #PTE_EXT_TEX(1)

	eor	r1, r1, #L_PTE_DIRTY
	tst	r1, #L_PTE_RDONLY | L_PTE_DIRTY
	orrne	r3, r3, #PTE_EXT_APX

	tst	r1, #L_PTE_USER
	orrne	r3, r3, #PTE_EXT_AP1

	tst	r1, #L_PTE_XN
	orrne	r3, r3, #PTE_EXT_XN

	tst	r1, #L_PTE_YOUNG
	tstne	r1, #L_PTE_VALID
	eorne	r1, r1, #L_PTE_NONE
	tstne	r1, #L_PTE_NONE
	moveq	r3, #0

 ARM(	str	r3, [r0, #2048]! )
 THUMB(	add	r0, r0, #2048 )
 THUMB(	str	r3, [r0] )
	ALT_SMP(W(nop))
	ALT_UP (mcr	p15, 0, r0, c7, c10, 1)		@ flush_pte
#endif
	bx	lr
ENDPROC(cpu_v7_set_pte_ext)

	/*
	 * Memory region attributes with SCTLR.TRE=1
	 *
	 *   n = TEX[0],C,B
	 *   TR = PRRR[2n+1:2n]		- memory type
	 *   IR = NMRR[2n+1:2n]		- inner cacheable property
	 *   OR = NMRR[2n+17:2n+16]	- outer cacheable property
	 *
	 *			n	TR	IR	OR
	 *   UNCACHED		000	00
	 *   BUFFERABLE		001	10	00	00
	 *   WRITETHROUGH	010	10	10	10
	 *   WRITEBACK		011	10	11	11
	 *   reserved		110
	 *   WRITEALLOC		111	10	01	01
	 *   DEV_SHARED		100	01
	 *   DEV_NONSHARED	100	01
	 *   DEV_WC		001	10
	 *   DEV_CACHED		011	10
	 *
	 * Other attributes:
	 *
	 *   DS0 = PRRR[16] = 0		- device shareable property
	 *   DS1 = PRRR[17] = 1		- device shareable property
	 *   NS0 = PRRR[18] = 0		- normal shareable property
	 *   NS1 = PRRR[19] = 1		- normal shareable property
	 *   NOS = PRRR[24+n] = 1	- not outer shareable
	 */
.equ	PRRR,	0xff0a81a8
.equ	NMRR,	0x40e040e0

	/*
	 * Macro for setting up the TTBRx and TTBCR registers.
	 * - \ttb0 and \ttb1 updated with the corresponding flags.
	 */
	.macro	v7_ttb_setup, zero, ttbr0l, ttbr0h, ttbr1, tmp
	mcr	p15, 0, \zero, c2, c0, 2	@ TTB control register
	ALT_SMP(orr	\ttbr0l, \ttbr0l, #TTB_FLAGS_SMP)
	ALT_UP(orr	\ttbr0l, \ttbr0l, #TTB_FLAGS_UP)
	ALT_SMP(orr	\ttbr1, \ttbr1, #TTB_FLAGS_SMP)
	ALT_UP(orr	\ttbr1, \ttbr1, #TTB_FLAGS_UP)
	mcr	p15, 0, \ttbr1, c2, c0, 1	@ load TTB1
	.endm

	/*   AT
	 *  TFR   EV X F   I D LR    S
	 * .EEE ..EE PUI. .T.T 4RVI ZWRS BLDP WCAM
	 * rxxx rrxx xxx0 0101 xxxx xxxx x111 xxxx < forced
	 *   01    0 110       0011 1100 .111 1101 < we want
	 */
	.align	2
	.type	v7_crval, #object
v7_crval:
	crval	clear=0x2120c302, mmuset=0x10c03c7d, ucset=0x00c01c7c
Commit	Line	Data
8d2cd3a3 CM	1	/*
	2	* arch/arm/mm/proc-v7-2level.S
	3	*
	4	* Copyright (C) 2001 Deep Blue Solutions Ltd.
	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License version 2 as
	8	* published by the Free Software Foundation.
	9	*/
	10
	11	#define TTB_S (1 << 1)
	12	#define TTB_RGN_NC (0 << 3)
	13	#define TTB_RGN_OC_WBWA (1 << 3)
	14	#define TTB_RGN_OC_WT (2 << 3)
	15	#define TTB_RGN_OC_WB (3 << 3)
	16	#define TTB_NOS (1 << 5)
	17	#define TTB_IRGN_NC ((0 << 0) \| (0 << 6))
	18	#define TTB_IRGN_WBWA ((0 << 0) \| (1 << 6))
	19	#define TTB_IRGN_WT ((1 << 0) \| (0 << 6))
	20	#define TTB_IRGN_WB ((1 << 0) \| (1 << 6))
	21
	22	/* PTWs cacheable, inner WB not shareable, outer WB not shareable */
	23	#define TTB_FLAGS_UP TTB_IRGN_WB\|TTB_RGN_OC_WB
	24	#define PMD_FLAGS_UP PMD_SECT_WB
	25
	26	/* PTWs cacheable, inner WBWA shareable, outer WBWA not shareable */
	27	#define TTB_FLAGS_SMP TTB_IRGN_WBWA\|TTB_S\|TTB_NOS\|TTB_RGN_OC_WBWA
	28	#define PMD_FLAGS_SMP PMD_SECT_WBWA\|PMD_SECT_S
	29
	30	/*
	31	* cpu_v7_switch_mm(pgd_phys, tsk)
	32	*
	33	* Set the translation table base pointer to be pgd_phys
	34	*
	35	* - pgd_phys - physical address of new TTB
	36	*
	37	* It is assumed that:
	38	* - we are not using split page tables
e748994f TL	39	*
	40	* Note that we always need to flush BTAC/BTB if IBE is set
	41	* even on Cortex-A8 revisions not affected by 430973.
	42	* If IBE is not set, the flush BTAC/BTB won't do anything.
8d2cd3a3	43	*/
a6d74678	44	ENTRY(cpu_ca8_switch_mm)
8d2cd3a3 CM	45	#ifdef CONFIG_MMU
8d2cd3a3 CM	46	mov r2, #0
8d2cd3a3 CM	47	mcr p15, 0, r2, c7, c5, 6 @ flush BTAC/BTB
8d2cd3a3 CM	48	#endif
a6d74678 RK	49	ENTRY(cpu_v7_switch_mm)
	50	#ifdef CONFIG_MMU
	51	mmid r1, r1 @ get mm->context.id
	52	ALT_SMP(orr r0, r0, #TTB_FLAGS_SMP)
	53	ALT_UP(orr r0, r0, #TTB_FLAGS_UP)
575320d6 WD	54	#ifdef CONFIG_PID_IN_CONTEXTIDR
	55	mrc p15, 0, r2, c13, c0, 1 @ read current context ID
	56	lsr r2, r2, #8 @ extract the PID
	57	bfi r1, r2, #8, #24 @ insert into new context ID
	58	#endif
8d2cd3a3 CM	59	#ifdef CONFIG_ARM_ERRATA_754322
	60	dsb
	61	#endif
	62	mcr p15, 0, r1, c13, c0, 1 @ set context ID
	63	isb
3c5f7e7b WD	64	mcr p15, 0, r0, c2, c0, 0 @ set TTB 0
3c5f7e7b WD	65	isb
8d2cd3a3	66	#endif
6ebbf2ce	67	bx lr
8d2cd3a3	68	ENDPROC(cpu_v7_switch_mm)
a6d74678	69	ENDPROC(cpu_ca8_switch_mm)
8d2cd3a3 CM	70
	71	/*
	72	* cpu_v7_set_pte_ext(ptep, pte)
	73	*
	74	* Set a level 2 translation table entry.
	75	*
	76	* - ptep - pointer to level 2 translation table entry
	77	* (hardware version is stored at +2048 bytes)
	78	* - pte - PTE value to store
	79	* - ext - value for extended PTE bits
	80	*/
	81	ENTRY(cpu_v7_set_pte_ext)
	82	#ifdef CONFIG_MMU
	83	str r1, [r0] @ linux version
	84
	85	bic r3, r1, #0x000003f0
	86	bic r3, r3, #PTE_TYPE_MASK
	87	orr r3, r3, r2
	88	orr r3, r3, #PTE_EXT_AP0 \| 2
	89
	90	tst r1, #1 << 4
	91	orrne r3, r3, #PTE_EXT_TEX(1)
	92
	93	eor r1, r1, #L_PTE_DIRTY
	94	tst r1, #L_PTE_RDONLY \| L_PTE_DIRTY
	95	orrne r3, r3, #PTE_EXT_APX
	96
	97	tst r1, #L_PTE_USER
	98	orrne r3, r3, #PTE_EXT_AP1
8d2cd3a3 CM	99
	100	tst r1, #L_PTE_XN
	101	orrne r3, r3, #PTE_EXT_XN
	102
	103	tst r1, #L_PTE_YOUNG
dbf62d50	104	tstne r1, #L_PTE_VALID
26ffd0d4 WD	105	eorne r1, r1, #L_PTE_NONE
26ffd0d4 WD	106	tstne r1, #L_PTE_NONE
8d2cd3a3 CM	107	moveq r3, #0
	108
	109	ARM( str r3, [r0, #2048]! )
	110	THUMB( add r0, r0, #2048 )
	111	THUMB( str r3, [r0] )
bf3f0f33	112	ALT_SMP(W(nop))
ae8a8b95	113	ALT_UP (mcr p15, 0, r0, c7, c10, 1) @ flush_pte
8d2cd3a3	114	#endif
6ebbf2ce	115	bx lr
8d2cd3a3 CM	116	ENDPROC(cpu_v7_set_pte_ext)
	117
	118	/*
	119	* Memory region attributes with SCTLR.TRE=1
	120	*
	121	* n = TEX[0],C,B
	122	* TR = PRRR[2n+1:2n] - memory type
	123	* IR = NMRR[2n+1:2n] - inner cacheable property
	124	* OR = NMRR[2n+17:2n+16] - outer cacheable property
	125	*
	126	* n TR IR OR
	127	* UNCACHED 000 00
	128	* BUFFERABLE 001 10 00 00
	129	* WRITETHROUGH 010 10 10 10
	130	* WRITEBACK 011 10 11 11
	131	* reserved 110
	132	* WRITEALLOC 111 10 01 01
	133	* DEV_SHARED 100 01
	134	* DEV_NONSHARED 100 01
	135	* DEV_WC 001 10
	136	* DEV_CACHED 011 10
	137	*
	138	* Other attributes:
	139	*
	140	* DS0 = PRRR[16] = 0 - device shareable property
	141	* DS1 = PRRR[17] = 1 - device shareable property
	142	* NS0 = PRRR[18] = 0 - normal shareable property
	143	* NS1 = PRRR[19] = 1 - normal shareable property
	144	* NOS = PRRR[24+n] = 1 - not outer shareable
	145	*/
	146	.equ PRRR, 0xff0a81a8
	147	.equ NMRR, 0x40e040e0
	148
	149	/*
	150	* Macro for setting up the TTBRx and TTBCR registers.
	151	* - \ttb0 and \ttb1 updated with the corresponding flags.
	152	*/
b2c3e38a	153	.macro v7_ttb_setup, zero, ttbr0l, ttbr0h, ttbr1, tmp
8d2cd3a3	154	mcr p15, 0, \zero, c2, c0, 2 @ TTB control register
b2c3e38a RK	155	ALT_SMP(orr \ttbr0l, \ttbr0l, #TTB_FLAGS_SMP)
b2c3e38a RK	156	ALT_UP(orr \ttbr0l, \ttbr0l, #TTB_FLAGS_UP)
8d2cd3a3 CM	157	ALT_SMP(orr \ttbr1, \ttbr1, #TTB_FLAGS_SMP)
	158	ALT_UP(orr \ttbr1, \ttbr1, #TTB_FLAGS_UP)
	159	mcr p15, 0, \ttbr1, c2, c0, 1 @ load TTB1
	160	.endm
	161
8d2cd3a3 CM	162	/* AT
	163	* TFR EV X F I D LR S
	164	* .EEE ..EE PUI. .T.T 4RVI ZWRS BLDP WCAM
	165	* rxxx rrxx xxx0 0101 xxxx xxxx x111 xxxx < forced
0cbbbad6	166	* 01 0 110 0011 1100 .111 1101 < we want
8d2cd3a3 CM	167	*/
	168	.align 2
	169	.type v7_crval, #object
	170	v7_crval:
0cbbbad6	171	crval clear=0x2120c302, mmuset=0x10c03c7d, ucset=0x00c01c7c