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1 | /* |
2 | * linux/arch/arm/mm/proc-v6.S | |
3 | * | |
4 | * Copyright (C) 2001 Deep Blue Solutions Ltd. | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License version 2 as | |
8 | * published by the Free Software Foundation. | |
9 | * | |
10 | * This is the "shell" of the ARMv6 processor support. | |
11 | */ | |
12 | #include <linux/linkage.h> | |
13 | #include <asm/assembler.h> | |
e6ae744d | 14 | #include <asm/asm-offsets.h> |
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15 | #include <asm/procinfo.h> |
16 | #include <asm/pgtable.h> | |
17 | ||
18 | #include "proc-macros.S" | |
19 | ||
20 | #define D_CACHE_LINE_SIZE 32 | |
21 | ||
22 | .macro cpsie, flags | |
23 | .ifc \flags, f | |
24 | .long 0xf1080040 | |
25 | .exitm | |
26 | .endif | |
27 | .ifc \flags, i | |
28 | .long 0xf1080080 | |
29 | .exitm | |
30 | .endif | |
31 | .ifc \flags, if | |
32 | .long 0xf10800c0 | |
33 | .exitm | |
34 | .endif | |
35 | .err | |
36 | .endm | |
37 | ||
38 | .macro cpsid, flags | |
39 | .ifc \flags, f | |
40 | .long 0xf10c0040 | |
41 | .exitm | |
42 | .endif | |
43 | .ifc \flags, i | |
44 | .long 0xf10c0080 | |
45 | .exitm | |
46 | .endif | |
47 | .ifc \flags, if | |
48 | .long 0xf10c00c0 | |
49 | .exitm | |
50 | .endif | |
51 | .err | |
52 | .endm | |
53 | ||
54 | ENTRY(cpu_v6_proc_init) | |
55 | mov pc, lr | |
56 | ||
57 | ENTRY(cpu_v6_proc_fin) | |
67c5587a TL |
58 | stmfd sp!, {lr} |
59 | cpsid if @ disable interrupts | |
60 | bl v6_flush_kern_cache_all | |
61 | mrc p15, 0, r0, c1, c0, 0 @ ctrl register | |
62 | bic r0, r0, #0x1000 @ ...i............ | |
63 | bic r0, r0, #0x0006 @ .............ca. | |
64 | mcr p15, 0, r0, c1, c0, 0 @ disable caches | |
65 | ldmfd sp!, {pc} | |
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66 | |
67 | /* | |
68 | * cpu_v6_reset(loc) | |
69 | * | |
70 | * Perform a soft reset of the system. Put the CPU into the | |
71 | * same state as it would be if it had been reset, and branch | |
72 | * to what would be the reset vector. | |
73 | * | |
74 | * - loc - location to jump to for soft reset | |
75 | * | |
76 | * It is assumed that: | |
77 | */ | |
78 | .align 5 | |
79 | ENTRY(cpu_v6_reset) | |
80 | mov pc, r0 | |
81 | ||
82 | /* | |
83 | * cpu_v6_do_idle() | |
84 | * | |
85 | * Idle the processor (eg, wait for interrupt). | |
86 | * | |
87 | * IRQs are already disabled. | |
88 | */ | |
89 | ENTRY(cpu_v6_do_idle) | |
90 | mcr p15, 0, r1, c7, c0, 4 @ wait for interrupt | |
91 | mov pc, lr | |
92 | ||
93 | ENTRY(cpu_v6_dcache_clean_area) | |
94 | #ifndef TLB_CAN_READ_FROM_L1_CACHE | |
95 | 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry | |
96 | add r0, r0, #D_CACHE_LINE_SIZE | |
97 | subs r1, r1, #D_CACHE_LINE_SIZE | |
98 | bhi 1b | |
99 | #endif | |
100 | mov pc, lr | |
101 | ||
102 | /* | |
103 | * cpu_arm926_switch_mm(pgd_phys, tsk) | |
104 | * | |
105 | * Set the translation table base pointer to be pgd_phys | |
106 | * | |
107 | * - pgd_phys - physical address of new TTB | |
108 | * | |
109 | * It is assumed that: | |
110 | * - we are not using split page tables | |
111 | */ | |
112 | ENTRY(cpu_v6_switch_mm) | |
113 | mov r2, #0 | |
114 | ldr r1, [r1, #MM_CONTEXT_ID] @ get mm->context.id | |
cd03adb0 RK |
115 | #ifdef CONFIG_SMP |
116 | orr r0, r0, #2 @ set shared pgtable | |
117 | #endif | |
d93742f5 | 118 | mcr p15, 0, r2, c7, c5, 6 @ flush BTAC/BTB |
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119 | mcr p15, 0, r2, c7, c10, 4 @ drain write buffer |
120 | mcr p15, 0, r0, c2, c0, 0 @ set TTB 0 | |
121 | mcr p15, 0, r1, c13, c0, 1 @ set context ID | |
122 | mov pc, lr | |
123 | ||
1da177e4 LT |
124 | /* |
125 | * cpu_v6_set_pte(ptep, pte) | |
126 | * | |
127 | * Set a level 2 translation table entry. | |
128 | * | |
129 | * - ptep - pointer to level 2 translation table entry | |
130 | * (hardware version is stored at -1024 bytes) | |
131 | * - pte - PTE value to store | |
132 | * | |
133 | * Permissions: | |
134 | * YUWD APX AP1 AP0 SVC User | |
135 | * 0xxx 0 0 0 no acc no acc | |
136 | * 100x 1 0 1 r/o no acc | |
137 | * 10x0 1 0 1 r/o no acc | |
138 | * 1011 0 0 1 r/w no acc | |
79042f08 CM |
139 | * 110x 0 1 0 r/w r/o |
140 | * 11x0 0 1 0 r/w r/o | |
1da177e4 LT |
141 | * 1111 0 1 1 r/w r/w |
142 | */ | |
143 | ENTRY(cpu_v6_set_pte) | |
144 | str r1, [r0], #-2048 @ linux version | |
145 | ||
cd03adb0 | 146 | bic r2, r1, #0x000003f0 |
1da177e4 | 147 | bic r2, r2, #0x00000003 |
1b9749e7 | 148 | orr r2, r2, #PTE_EXT_AP0 | 2 |
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149 | |
150 | tst r1, #L_PTE_WRITE | |
151 | tstne r1, #L_PTE_DIRTY | |
1b9749e7 | 152 | orreq r2, r2, #PTE_EXT_APX |
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153 | |
154 | tst r1, #L_PTE_USER | |
6626a707 | 155 | orrne r2, r2, #PTE_EXT_AP1 |
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156 | tstne r2, #PTE_EXT_APX |
157 | bicne r2, r2, #PTE_EXT_APX | PTE_EXT_AP0 | |
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158 | |
159 | tst r1, #L_PTE_YOUNG | |
1b9749e7 | 160 | biceq r2, r2, #PTE_EXT_APX | PTE_EXT_AP_MASK |
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161 | |
162 | @ tst r1, #L_PTE_EXEC | |
1b9749e7 | 163 | @ orreq r2, r2, #PTE_EXT_XN |
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164 | |
165 | tst r1, #L_PTE_PRESENT | |
166 | moveq r2, #0 | |
167 | ||
168 | str r2, [r0] | |
169 | mcr p15, 0, r0, c7, c10, 1 @ flush_pte | |
170 | mov pc, lr | |
171 | ||
172 | ||
173 | ||
174 | ||
175 | cpu_v6_name: | |
176 | .asciz "Some Random V6 Processor" | |
177 | .align | |
178 | ||
179 | .section ".text.init", #alloc, #execinstr | |
180 | ||
181 | /* | |
182 | * __v6_setup | |
183 | * | |
184 | * Initialise TLB, Caches, and MMU state ready to switch the MMU | |
185 | * on. Return in r0 the new CP15 C1 control register setting. | |
186 | * | |
187 | * We automatically detect if we have a Harvard cache, and use the | |
188 | * Harvard cache control instructions insead of the unified cache | |
189 | * control instructions. | |
190 | * | |
191 | * This should be able to cover all ARMv6 cores. | |
192 | * | |
193 | * It is assumed that: | |
194 | * - cache type register is implemented | |
195 | */ | |
196 | __v6_setup: | |
197 | mov r0, #0 | |
198 | mcr p15, 0, r0, c7, c14, 0 @ clean+invalidate D cache | |
199 | mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache | |
200 | mcr p15, 0, r0, c7, c15, 0 @ clean+invalidate cache | |
201 | mcr p15, 0, r0, c7, c10, 4 @ drain write buffer | |
202 | mcr p15, 0, r0, c8, c7, 0 @ invalidate I + D TLBs | |
203 | mcr p15, 0, r0, c2, c0, 2 @ TTB control register | |
cd03adb0 RK |
204 | #ifdef CONFIG_SMP |
205 | orr r4, r4, #2 @ set shared pgtable | |
206 | #endif | |
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207 | mcr p15, 0, r4, c2, c0, 1 @ load TTB1 |
208 | #ifdef CONFIG_VFP | |
209 | mrc p15, 0, r0, c1, c0, 2 | |
d1d890ed | 210 | orr r0, r0, #(0xf << 20) |
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211 | mcr p15, 0, r0, c1, c0, 2 @ Enable full access to VFP |
212 | #endif | |
213 | mrc p15, 0, r0, c1, c0, 0 @ read control register | |
214 | ldr r5, v6_cr1_clear @ get mask for bits to clear | |
215 | bic r0, r0, r5 @ clear bits them | |
216 | ldr r5, v6_cr1_set @ get mask for bits to set | |
217 | orr r0, r0, r5 @ set them | |
218 | mov pc, lr @ return to head.S:__ret | |
219 | ||
220 | /* | |
221 | * V X F I D LR | |
222 | * .... ...E PUI. .T.T 4RVI ZFRS BLDP WCAM | |
223 | * rrrr rrrx xxx0 0101 xxxx xxxx x111 xxxx < forced | |
224 | * 0 110 0011 1.00 .111 1101 < we want | |
225 | */ | |
226 | .type v6_cr1_clear, #object | |
227 | .type v6_cr1_set, #object | |
228 | v6_cr1_clear: | |
229 | .word 0x01e0fb7f | |
230 | v6_cr1_set: | |
231 | .word 0x00c0387d | |
232 | ||
233 | .type v6_processor_functions, #object | |
234 | ENTRY(v6_processor_functions) | |
235 | .word v6_early_abort | |
236 | .word cpu_v6_proc_init | |
237 | .word cpu_v6_proc_fin | |
238 | .word cpu_v6_reset | |
239 | .word cpu_v6_do_idle | |
240 | .word cpu_v6_dcache_clean_area | |
241 | .word cpu_v6_switch_mm | |
242 | .word cpu_v6_set_pte | |
243 | .size v6_processor_functions, . - v6_processor_functions | |
244 | ||
245 | .type cpu_arch_name, #object | |
246 | cpu_arch_name: | |
247 | .asciz "armv6" | |
248 | .size cpu_arch_name, . - cpu_arch_name | |
249 | ||
250 | .type cpu_elf_name, #object | |
251 | cpu_elf_name: | |
252 | .asciz "v6" | |
253 | .size cpu_elf_name, . - cpu_elf_name | |
254 | .align | |
255 | ||
02b7dd12 | 256 | .section ".proc.info.init", #alloc, #execinstr |
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257 | |
258 | /* | |
259 | * Match any ARMv6 processor core. | |
260 | */ | |
261 | .type __v6_proc_info, #object | |
262 | __v6_proc_info: | |
263 | .long 0x0007b000 | |
264 | .long 0x0007f000 | |
265 | .long PMD_TYPE_SECT | \ | |
266 | PMD_SECT_BUFFERABLE | \ | |
267 | PMD_SECT_CACHEABLE | \ | |
268 | PMD_SECT_AP_WRITE | \ | |
269 | PMD_SECT_AP_READ | |
270 | b __v6_setup | |
271 | .long cpu_arch_name | |
272 | .long cpu_elf_name | |
273 | .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_VFP|HWCAP_EDSP|HWCAP_JAVA | |
274 | .long cpu_v6_name | |
275 | .long v6_processor_functions | |
276 | .long v6wbi_tlb_fns | |
277 | .long v6_user_fns | |
278 | .long v6_cache_fns | |
279 | .size __v6_proc_info, . - __v6_proc_info |