Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * linux/arch/arm/mm/proc-v6.S | |
3 | * | |
4 | * Copyright (C) 2001 Deep Blue Solutions Ltd. | |
d090ddda | 5 | * Modified by Catalin Marinas for noMMU support |
1da177e4 LT |
6 | * |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License version 2 as | |
9 | * published by the Free Software Foundation. | |
10 | * | |
11 | * This is the "shell" of the ARMv6 processor support. | |
12 | */ | |
13 | #include <linux/linkage.h> | |
14 | #include <asm/assembler.h> | |
e6ae744d | 15 | #include <asm/asm-offsets.h> |
5ec9407d | 16 | #include <asm/hwcap.h> |
74945c86 | 17 | #include <asm/pgtable-hwdef.h> |
1da177e4 LT |
18 | #include <asm/pgtable.h> |
19 | ||
20 | #include "proc-macros.S" | |
21 | ||
22 | #define D_CACHE_LINE_SIZE 32 | |
23 | ||
3747b36e RK |
24 | #define TTB_C (1 << 0) |
25 | #define TTB_S (1 << 1) | |
26 | #define TTB_IMP (1 << 2) | |
27 | #define TTB_RGN_NC (0 << 3) | |
28 | #define TTB_RGN_WBWA (1 << 3) | |
29 | #define TTB_RGN_WT (2 << 3) | |
30 | #define TTB_RGN_WB (3 << 3) | |
31 | ||
f2131d34 RK |
32 | #ifndef CONFIG_SMP |
33 | #define TTB_FLAGS TTB_RGN_WBWA | |
34 | #else | |
35 | #define TTB_FLAGS TTB_RGN_WBWA|TTB_S | |
36 | #endif | |
37 | ||
1da177e4 LT |
38 | ENTRY(cpu_v6_proc_init) |
39 | mov pc, lr | |
40 | ||
41 | ENTRY(cpu_v6_proc_fin) | |
67c5587a TL |
42 | stmfd sp!, {lr} |
43 | cpsid if @ disable interrupts | |
44 | bl v6_flush_kern_cache_all | |
45 | mrc p15, 0, r0, c1, c0, 0 @ ctrl register | |
46 | bic r0, r0, #0x1000 @ ...i............ | |
47 | bic r0, r0, #0x0006 @ .............ca. | |
48 | mcr p15, 0, r0, c1, c0, 0 @ disable caches | |
49 | ldmfd sp!, {pc} | |
1da177e4 LT |
50 | |
51 | /* | |
52 | * cpu_v6_reset(loc) | |
53 | * | |
54 | * Perform a soft reset of the system. Put the CPU into the | |
55 | * same state as it would be if it had been reset, and branch | |
56 | * to what would be the reset vector. | |
57 | * | |
58 | * - loc - location to jump to for soft reset | |
59 | * | |
60 | * It is assumed that: | |
61 | */ | |
62 | .align 5 | |
63 | ENTRY(cpu_v6_reset) | |
64 | mov pc, r0 | |
65 | ||
66 | /* | |
67 | * cpu_v6_do_idle() | |
68 | * | |
69 | * Idle the processor (eg, wait for interrupt). | |
70 | * | |
71 | * IRQs are already disabled. | |
72 | */ | |
73 | ENTRY(cpu_v6_do_idle) | |
8553cb67 CM |
74 | mov r1, #0 |
75 | mcr p15, 0, r1, c7, c10, 4 @ DWB - WFI may enter a low-power mode | |
1da177e4 LT |
76 | mcr p15, 0, r1, c7, c0, 4 @ wait for interrupt |
77 | mov pc, lr | |
78 | ||
79 | ENTRY(cpu_v6_dcache_clean_area) | |
80 | #ifndef TLB_CAN_READ_FROM_L1_CACHE | |
81 | 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry | |
82 | add r0, r0, #D_CACHE_LINE_SIZE | |
83 | subs r1, r1, #D_CACHE_LINE_SIZE | |
84 | bhi 1b | |
85 | #endif | |
86 | mov pc, lr | |
87 | ||
88 | /* | |
89 | * cpu_arm926_switch_mm(pgd_phys, tsk) | |
90 | * | |
91 | * Set the translation table base pointer to be pgd_phys | |
92 | * | |
93 | * - pgd_phys - physical address of new TTB | |
94 | * | |
95 | * It is assumed that: | |
96 | * - we are not using split page tables | |
97 | */ | |
98 | ENTRY(cpu_v6_switch_mm) | |
d090ddda | 99 | #ifdef CONFIG_MMU |
1da177e4 LT |
100 | mov r2, #0 |
101 | ldr r1, [r1, #MM_CONTEXT_ID] @ get mm->context.id | |
f2131d34 | 102 | orr r0, r0, #TTB_FLAGS |
d93742f5 | 103 | mcr p15, 0, r2, c7, c5, 6 @ flush BTAC/BTB |
1da177e4 LT |
104 | mcr p15, 0, r2, c7, c10, 4 @ drain write buffer |
105 | mcr p15, 0, r0, c2, c0, 0 @ set TTB 0 | |
106 | mcr p15, 0, r1, c13, c0, 1 @ set context ID | |
d090ddda | 107 | #endif |
1da177e4 LT |
108 | mov pc, lr |
109 | ||
1da177e4 | 110 | /* |
ad1ae2fe | 111 | * cpu_v6_set_pte_ext(ptep, pte, ext) |
1da177e4 LT |
112 | * |
113 | * Set a level 2 translation table entry. | |
114 | * | |
115 | * - ptep - pointer to level 2 translation table entry | |
116 | * (hardware version is stored at -1024 bytes) | |
117 | * - pte - PTE value to store | |
ad1ae2fe | 118 | * - ext - value for extended PTE bits |
1da177e4 | 119 | */ |
639b0ae7 RK |
120 | armv6_mt_table cpu_v6 |
121 | ||
ad1ae2fe | 122 | ENTRY(cpu_v6_set_pte_ext) |
d090ddda | 123 | #ifdef CONFIG_MMU |
639b0ae7 | 124 | armv6_set_pte_ext cpu_v6 |
d090ddda | 125 | #endif |
1da177e4 LT |
126 | mov pc, lr |
127 | ||
128 | ||
129 | ||
130 | ||
131 | cpu_v6_name: | |
94b1e96d | 132 | .asciz "ARMv6-compatible processor" |
1da177e4 LT |
133 | .align |
134 | ||
135 | .section ".text.init", #alloc, #execinstr | |
136 | ||
137 | /* | |
138 | * __v6_setup | |
139 | * | |
140 | * Initialise TLB, Caches, and MMU state ready to switch the MMU | |
141 | * on. Return in r0 the new CP15 C1 control register setting. | |
142 | * | |
143 | * We automatically detect if we have a Harvard cache, and use the | |
144 | * Harvard cache control instructions insead of the unified cache | |
145 | * control instructions. | |
146 | * | |
147 | * This should be able to cover all ARMv6 cores. | |
148 | * | |
149 | * It is assumed that: | |
150 | * - cache type register is implemented | |
151 | */ | |
152 | __v6_setup: | |
862184fe | 153 | #ifdef CONFIG_SMP |
862184fe RK |
154 | mrc p15, 0, r0, c1, c0, 1 @ Enable SMP/nAMP mode |
155 | orr r0, r0, #0x20 | |
156 | mcr p15, 0, r0, c1, c0, 1 | |
862184fe RK |
157 | #endif |
158 | ||
1da177e4 LT |
159 | mov r0, #0 |
160 | mcr p15, 0, r0, c7, c14, 0 @ clean+invalidate D cache | |
161 | mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache | |
162 | mcr p15, 0, r0, c7, c15, 0 @ clean+invalidate cache | |
163 | mcr p15, 0, r0, c7, c10, 4 @ drain write buffer | |
d090ddda | 164 | #ifdef CONFIG_MMU |
1da177e4 LT |
165 | mcr p15, 0, r0, c8, c7, 0 @ invalidate I + D TLBs |
166 | mcr p15, 0, r0, c2, c0, 2 @ TTB control register | |
f2131d34 | 167 | orr r4, r4, #TTB_FLAGS |
1da177e4 | 168 | mcr p15, 0, r4, c2, c0, 1 @ load TTB1 |
d090ddda | 169 | #endif /* CONFIG_MMU */ |
22b19086 RK |
170 | adr r5, v6_crval |
171 | ldmia r5, {r5, r6} | |
1da177e4 | 172 | mrc p15, 0, r0, c1, c0, 0 @ read control register |
1da177e4 | 173 | bic r0, r0, r5 @ clear bits them |
22b19086 | 174 | orr r0, r0, r6 @ set them |
1da177e4 LT |
175 | mov pc, lr @ return to head.S:__ret |
176 | ||
177 | /* | |
178 | * V X F I D LR | |
179 | * .... ...E PUI. .T.T 4RVI ZFRS BLDP WCAM | |
180 | * rrrr rrrx xxx0 0101 xxxx xxxx x111 xxxx < forced | |
181 | * 0 110 0011 1.00 .111 1101 < we want | |
182 | */ | |
22b19086 RK |
183 | .type v6_crval, #object |
184 | v6_crval: | |
185 | crval clear=0x01e0fb7f, mmuset=0x00c0387d, ucset=0x00c0187c | |
1da177e4 LT |
186 | |
187 | .type v6_processor_functions, #object | |
188 | ENTRY(v6_processor_functions) | |
189 | .word v6_early_abort | |
4a1fd556 | 190 | .word pabort_noifar |
1da177e4 LT |
191 | .word cpu_v6_proc_init |
192 | .word cpu_v6_proc_fin | |
193 | .word cpu_v6_reset | |
194 | .word cpu_v6_do_idle | |
195 | .word cpu_v6_dcache_clean_area | |
196 | .word cpu_v6_switch_mm | |
ad1ae2fe | 197 | .word cpu_v6_set_pte_ext |
1da177e4 LT |
198 | .size v6_processor_functions, . - v6_processor_functions |
199 | ||
200 | .type cpu_arch_name, #object | |
201 | cpu_arch_name: | |
202 | .asciz "armv6" | |
203 | .size cpu_arch_name, . - cpu_arch_name | |
204 | ||
205 | .type cpu_elf_name, #object | |
206 | cpu_elf_name: | |
207 | .asciz "v6" | |
208 | .size cpu_elf_name, . - cpu_elf_name | |
209 | .align | |
210 | ||
02b7dd12 | 211 | .section ".proc.info.init", #alloc, #execinstr |
1da177e4 LT |
212 | |
213 | /* | |
214 | * Match any ARMv6 processor core. | |
215 | */ | |
216 | .type __v6_proc_info, #object | |
217 | __v6_proc_info: | |
218 | .long 0x0007b000 | |
219 | .long 0x0007f000 | |
220 | .long PMD_TYPE_SECT | \ | |
221 | PMD_SECT_BUFFERABLE | \ | |
222 | PMD_SECT_CACHEABLE | \ | |
223 | PMD_SECT_AP_WRITE | \ | |
224 | PMD_SECT_AP_READ | |
8799ee9f RK |
225 | .long PMD_TYPE_SECT | \ |
226 | PMD_SECT_XN | \ | |
227 | PMD_SECT_AP_WRITE | \ | |
228 | PMD_SECT_AP_READ | |
1da177e4 LT |
229 | b __v6_setup |
230 | .long cpu_arch_name | |
231 | .long cpu_elf_name | |
efe90d27 | 232 | .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP|HWCAP_JAVA |
1da177e4 LT |
233 | .long cpu_v6_name |
234 | .long v6_processor_functions | |
235 | .long v6wbi_tlb_fns | |
236 | .long v6_user_fns | |
237 | .long v6_cache_fns | |
238 | .size __v6_proc_info, . - __v6_proc_info |