[linux-2.6-block.git] / arch / arm / mm / proc-v6.S

/*
 *  linux/arch/arm/mm/proc-v6.S
 *
 *  Copyright (C) 2001 Deep Blue Solutions Ltd.
 *  Modified by Catalin Marinas for noMMU support
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 *  This is the "shell" of the ARMv6 processor support.
 */
#include <linux/init.h>
#include <linux/linkage.h>
#include <asm/assembler.h>
#include <asm/asm-offsets.h>
#include <asm/hwcap.h>
#include <asm/pgtable-hwdef.h>
#include <asm/pgtable.h>

#include "proc-macros.S"

#define D_CACHE_LINE_SIZE	32

#define TTB_C		(1 << 0)
#define TTB_S		(1 << 1)
#define TTB_IMP		(1 << 2)
#define TTB_RGN_NC	(0 << 3)
#define TTB_RGN_WBWA	(1 << 3)
#define TTB_RGN_WT	(2 << 3)
#define TTB_RGN_WB	(3 << 3)

#ifndef CONFIG_SMP
#define TTB_FLAGS	TTB_RGN_WBWA
#define PMD_FLAGS	PMD_SECT_WB
#else
#define TTB_FLAGS	TTB_RGN_WBWA|TTB_S
#define PMD_FLAGS	PMD_SECT_WBWA|PMD_SECT_S
#endif

ENTRY(cpu_v6_proc_init)
	mov	pc, lr

ENTRY(cpu_v6_proc_fin)
	mrc	p15, 0, r0, c1, c0, 0		@ ctrl register
	bic	r0, r0, #0x1000			@ ...i............
	bic	r0, r0, #0x0006			@ .............ca.
	mcr	p15, 0, r0, c1, c0, 0		@ disable caches
	mov	pc, lr

/*
 *	cpu_v6_reset(loc)
 *
 *	Perform a soft reset of the system.  Put the CPU into the
 *	same state as it would be if it had been reset, and branch
 *	to what would be the reset vector.
 *
 *	- loc   - location to jump to for soft reset
 */
	.align	5
ENTRY(cpu_v6_reset)
	mov	pc, r0

/*
 *	cpu_v6_do_idle()
 *
 *	Idle the processor (eg, wait for interrupt).
 *
 *	IRQs are already disabled.
 */
ENTRY(cpu_v6_do_idle)
	mov	r1, #0
	mcr	p15, 0, r1, c7, c10, 4		@ DWB - WFI may enter a low-power mode
	mcr	p15, 0, r1, c7, c0, 4		@ wait for interrupt
	mov	pc, lr

ENTRY(cpu_v6_dcache_clean_area)
#ifndef TLB_CAN_READ_FROM_L1_CACHE
1:	mcr	p15, 0, r0, c7, c10, 1		@ clean D entry
	add	r0, r0, #D_CACHE_LINE_SIZE
	subs	r1, r1, #D_CACHE_LINE_SIZE
	bhi	1b
#endif
	mov	pc, lr

/*
 *	cpu_arm926_switch_mm(pgd_phys, tsk)
 *
 *	Set the translation table base pointer to be pgd_phys
 *
 *	- pgd_phys - physical address of new TTB
 *
 *	It is assumed that:
 *	- we are not using split page tables
 */
ENTRY(cpu_v6_switch_mm)
#ifdef CONFIG_MMU
	mov	r2, #0
	ldr	r1, [r1, #MM_CONTEXT_ID]	@ get mm->context.id
	orr	r0, r0, #TTB_FLAGS
	mcr	p15, 0, r2, c7, c5, 6		@ flush BTAC/BTB
	mcr	p15, 0, r2, c7, c10, 4		@ drain write buffer
	mcr	p15, 0, r0, c2, c0, 0		@ set TTB 0
	mcr	p15, 0, r1, c13, c0, 1		@ set context ID
#endif
	mov	pc, lr

/*
 *	cpu_v6_set_pte_ext(ptep, pte, ext)
 *
 *	Set a level 2 translation table entry.
 *
 *	- ptep  - pointer to level 2 translation table entry
 *		  (hardware version is stored at -1024 bytes)
 *	- pte   - PTE value to store
 *	- ext	- value for extended PTE bits
 */
	armv6_mt_table cpu_v6

ENTRY(cpu_v6_set_pte_ext)
#ifdef CONFIG_MMU
	armv6_set_pte_ext cpu_v6
#endif
	mov	pc, lr


	.type	cpu_v6_name, #object
cpu_v6_name:
	.asciz	"ARMv6-compatible processor"
	.size	cpu_v6_name, . - cpu_v6_name

	.type	cpu_pj4_name, #object
cpu_pj4_name:
	.asciz	"Marvell PJ4 processor"
	.size	cpu_pj4_name, . - cpu_pj4_name

	.align

	__INIT

/*
 *	__v6_setup
 *
 *	Initialise TLB, Caches, and MMU state ready to switch the MMU
 *	on.  Return in r0 the new CP15 C1 control register setting.
 *
 *	We automatically detect if we have a Harvard cache, and use the
 *	Harvard cache control instructions insead of the unified cache
 *	control instructions.
 *
 *	This should be able to cover all ARMv6 cores.
 *
 *	It is assumed that:
 *	- cache type register is implemented
 */
__v6_setup:
#ifdef CONFIG_SMP
	mrc	p15, 0, r0, c1, c0, 1		@ Enable SMP/nAMP mode
	orr	r0, r0, #0x20
	mcr	p15, 0, r0, c1, c0, 1
#endif

	mov	r0, #0
	mcr	p15, 0, r0, c7, c14, 0		@ clean+invalidate D cache
	mcr	p15, 0, r0, c7, c5, 0		@ invalidate I cache
	mcr	p15, 0, r0, c7, c15, 0		@ clean+invalidate cache
	mcr	p15, 0, r0, c7, c10, 4		@ drain write buffer
#ifdef CONFIG_MMU
	mcr	p15, 0, r0, c8, c7, 0		@ invalidate I + D TLBs
	mcr	p15, 0, r0, c2, c0, 2		@ TTB control register
	orr	r4, r4, #TTB_FLAGS
	mcr	p15, 0, r4, c2, c0, 1		@ load TTB1
#endif /* CONFIG_MMU */
	adr	r5, v6_crval
	ldmia	r5, {r5, r6}
#ifdef CONFIG_CPU_ENDIAN_BE8
	orr	r6, r6, #1 << 25		@ big-endian page tables
#endif
	mrc	p15, 0, r0, c1, c0, 0		@ read control register
	bic	r0, r0, r5			@ clear bits them
	orr	r0, r0, r6			@ set them
	mov	pc, lr				@ return to head.S:__ret

	/*
	 *         V X F   I D LR
	 * .... ...E PUI. .T.T 4RVI ZFRS BLDP WCAM
	 * rrrr rrrx xxx0 0101 xxxx xxxx x111 xxxx < forced
	 *         0 110       0011 1.00 .111 1101 < we want
	 */
	.type	v6_crval, #object
v6_crval:
	crval	clear=0x01e0fb7f, mmuset=0x00c0387d, ucset=0x00c0187c

	.type	v6_processor_functions, #object
ENTRY(v6_processor_functions)
	.word	v6_early_abort
	.word	v6_pabort
	.word	cpu_v6_proc_init
	.word	cpu_v6_proc_fin
	.word	cpu_v6_reset
	.word	cpu_v6_do_idle
	.word	cpu_v6_dcache_clean_area
	.word	cpu_v6_switch_mm
	.word	cpu_v6_set_pte_ext
	.size	v6_processor_functions, . - v6_processor_functions

	.type	cpu_arch_name, #object
cpu_arch_name:
	.asciz	"armv6"
	.size	cpu_arch_name, . - cpu_arch_name

	.type	cpu_elf_name, #object
cpu_elf_name:
	.asciz	"v6"
	.size	cpu_elf_name, . - cpu_elf_name
	.align

	.section ".proc.info.init", #alloc, #execinstr

	/*
	 * Match any ARMv6 processor core.
	 */
	.type	__v6_proc_info, #object
__v6_proc_info:
	.long	0x0007b000
	.long	0x0007f000
	.long   PMD_TYPE_SECT | \
		PMD_SECT_AP_WRITE | \
		PMD_SECT_AP_READ | \
		PMD_FLAGS
	.long   PMD_TYPE_SECT | \
		PMD_SECT_XN | \
		PMD_SECT_AP_WRITE | \
		PMD_SECT_AP_READ
	b	__v6_setup
	.long	cpu_arch_name
	.long	cpu_elf_name
	/* See also feat_v6_fixup() for HWCAP_TLS */
	.long	HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP|HWCAP_JAVA|HWCAP_TLS
	.long	cpu_v6_name
	.long	v6_processor_functions
	.long	v6wbi_tlb_fns
	.long	v6_user_fns
	.long	v6_cache_fns
	.size	__v6_proc_info, . - __v6_proc_info

	.type	__pj4_v6_proc_info, #object
__pj4_v6_proc_info:
	.long	0x560f5810
	.long	0xff0ffff0
	.long   PMD_TYPE_SECT | \
		PMD_SECT_AP_WRITE | \
		PMD_SECT_AP_READ | \
		PMD_FLAGS
	.long   PMD_TYPE_SECT | \
		PMD_SECT_XN | \
		PMD_SECT_AP_WRITE | \
		PMD_SECT_AP_READ
	b	__v6_setup
	.long	cpu_arch_name
	.long	cpu_elf_name
	.long	HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP|HWCAP_TLS
	.long	cpu_pj4_name
	.long	v6_processor_functions
	.long	v6wbi_tlb_fns
	.long	v6_user_fns
	.long	v6_cache_fns
	.size	__pj4_v6_proc_info, . - __pj4_v6_proc_info
Commit	Line	Data
1da177e4 LT	1	/*
	2	* linux/arch/arm/mm/proc-v6.S
	3	*
	4	* Copyright (C) 2001 Deep Blue Solutions Ltd.
d090ddda	5	* Modified by Catalin Marinas for noMMU support
1da177e4 LT	6	*
	7	* This program is free software; you can redistribute it and/or modify
	8	* it under the terms of the GNU General Public License version 2 as
	9	* published by the Free Software Foundation.
	10	*
	11	* This is the "shell" of the ARMv6 processor support.
	12	*/
991da17e	13	#include <linux/init.h>
1da177e4 LT	14	#include <linux/linkage.h>
1da177e4 LT	15	#include <asm/assembler.h>
e6ae744d	16	#include <asm/asm-offsets.h>
5ec9407d	17	#include <asm/hwcap.h>
74945c86	18	#include <asm/pgtable-hwdef.h>
1da177e4 LT	19	#include <asm/pgtable.h>
	20
	21	#include "proc-macros.S"
	22
	23	#define D_CACHE_LINE_SIZE 32
	24
3747b36e RK	25	#define TTB_C (1 << 0)
	26	#define TTB_S (1 << 1)
	27	#define TTB_IMP (1 << 2)
	28	#define TTB_RGN_NC (0 << 3)
	29	#define TTB_RGN_WBWA (1 << 3)
	30	#define TTB_RGN_WT (2 << 3)
	31	#define TTB_RGN_WB (3 << 3)
	32
f2131d34 RK	33	#ifndef CONFIG_SMP
f2131d34 RK	34	#define TTB_FLAGS TTB_RGN_WBWA
4b46d641	35	#define PMD_FLAGS PMD_SECT_WB
f2131d34 RK	36	#else
f2131d34 RK	37	#define TTB_FLAGS TTB_RGN_WBWA\|TTB_S
4b46d641	38	#define PMD_FLAGS PMD_SECT_WBWA\|PMD_SECT_S
f2131d34 RK	39	#endif
f2131d34 RK	40
1da177e4 LT	41	ENTRY(cpu_v6_proc_init)
	42	mov pc, lr
	43
	44	ENTRY(cpu_v6_proc_fin)
67c5587a TL	45	mrc p15, 0, r0, c1, c0, 0 @ ctrl register
	46	bic r0, r0, #0x1000 @ ...i............
	47	bic r0, r0, #0x0006 @ .............ca.
	48	mcr p15, 0, r0, c1, c0, 0 @ disable caches
9ca03a21	49	mov pc, lr
1da177e4 LT	50
	51	/*
	52	* cpu_v6_reset(loc)
	53	*
	54	* Perform a soft reset of the system. Put the CPU into the
	55	* same state as it would be if it had been reset, and branch
	56	* to what would be the reset vector.
	57	*
	58	* - loc - location to jump to for soft reset
1da177e4 LT	59	*/
	60	.align 5
	61	ENTRY(cpu_v6_reset)
	62	mov pc, r0
	63
	64	/*
	65	* cpu_v6_do_idle()
	66	*
	67	* Idle the processor (eg, wait for interrupt).
	68	*
	69	* IRQs are already disabled.
	70	*/
	71	ENTRY(cpu_v6_do_idle)
8553cb67 CM	72	mov r1, #0
8553cb67 CM	73	mcr p15, 0, r1, c7, c10, 4 @ DWB - WFI may enter a low-power mode
1da177e4 LT	74	mcr p15, 0, r1, c7, c0, 4 @ wait for interrupt
	75	mov pc, lr
	76
	77	ENTRY(cpu_v6_dcache_clean_area)
	78	#ifndef TLB_CAN_READ_FROM_L1_CACHE
	79	1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
	80	add r0, r0, #D_CACHE_LINE_SIZE
	81	subs r1, r1, #D_CACHE_LINE_SIZE
	82	bhi 1b
	83	#endif
	84	mov pc, lr
	85
	86	/*
	87	* cpu_arm926_switch_mm(pgd_phys, tsk)
	88	*
	89	* Set the translation table base pointer to be pgd_phys
	90	*
	91	* - pgd_phys - physical address of new TTB
	92	*
	93	* It is assumed that:
	94	* - we are not using split page tables
	95	*/
	96	ENTRY(cpu_v6_switch_mm)
d090ddda	97	#ifdef CONFIG_MMU
1da177e4 LT	98	mov r2, #0
1da177e4 LT	99	ldr r1, [r1, #MM_CONTEXT_ID] @ get mm->context.id
f2131d34	100	orr r0, r0, #TTB_FLAGS
d93742f5	101	mcr p15, 0, r2, c7, c5, 6 @ flush BTAC/BTB
1da177e4 LT	102	mcr p15, 0, r2, c7, c10, 4 @ drain write buffer
	103	mcr p15, 0, r0, c2, c0, 0 @ set TTB 0
	104	mcr p15, 0, r1, c13, c0, 1 @ set context ID
d090ddda	105	#endif
1da177e4 LT	106	mov pc, lr
1da177e4 LT	107
1da177e4	108	/*
ad1ae2fe	109	* cpu_v6_set_pte_ext(ptep, pte, ext)
1da177e4 LT	110	*
	111	* Set a level 2 translation table entry.
	112	*
	113	* - ptep - pointer to level 2 translation table entry
	114	* (hardware version is stored at -1024 bytes)
	115	* - pte - PTE value to store
ad1ae2fe	116	* - ext - value for extended PTE bits
1da177e4	117	*/
639b0ae7 RK	118	armv6_mt_table cpu_v6
639b0ae7 RK	119
ad1ae2fe	120	ENTRY(cpu_v6_set_pte_ext)
d090ddda	121	#ifdef CONFIG_MMU
639b0ae7	122	armv6_set_pte_ext cpu_v6
d090ddda	123	#endif
1da177e4 LT	124	mov pc, lr
	125
	126
	127
edabd38e	128	.type cpu_v6_name, #object
1da177e4	129	cpu_v6_name:
94b1e96d	130	.asciz "ARMv6-compatible processor"
edabd38e SB	131	.size cpu_v6_name, . - cpu_v6_name
	132
	133	.type cpu_pj4_name, #object
	134	cpu_pj4_name:
	135	.asciz "Marvell PJ4 processor"
	136	.size cpu_pj4_name, . - cpu_pj4_name
	137
1da177e4 LT	138	.align
1da177e4 LT	139
991da17e	140	__INIT
1da177e4 LT	141
	142	/*
	143	* __v6_setup
	144	*
	145	* Initialise TLB, Caches, and MMU state ready to switch the MMU
	146	* on. Return in r0 the new CP15 C1 control register setting.
	147	*
	148	* We automatically detect if we have a Harvard cache, and use the
	149	* Harvard cache control instructions insead of the unified cache
	150	* control instructions.
	151	*
	152	* This should be able to cover all ARMv6 cores.
	153	*
	154	* It is assumed that:
	155	* - cache type register is implemented
	156	*/
	157	__v6_setup:
862184fe	158	#ifdef CONFIG_SMP
862184fe RK	159	mrc p15, 0, r0, c1, c0, 1 @ Enable SMP/nAMP mode
	160	orr r0, r0, #0x20
	161	mcr p15, 0, r0, c1, c0, 1
862184fe RK	162	#endif
862184fe RK	163
1da177e4 LT	164	mov r0, #0
	165	mcr p15, 0, r0, c7, c14, 0 @ clean+invalidate D cache
	166	mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
	167	mcr p15, 0, r0, c7, c15, 0 @ clean+invalidate cache
	168	mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
d090ddda	169	#ifdef CONFIG_MMU
1da177e4 LT	170	mcr p15, 0, r0, c8, c7, 0 @ invalidate I + D TLBs
1da177e4 LT	171	mcr p15, 0, r0, c2, c0, 2 @ TTB control register
f2131d34	172	orr r4, r4, #TTB_FLAGS
1da177e4	173	mcr p15, 0, r4, c2, c0, 1 @ load TTB1
d090ddda	174	#endif /* CONFIG_MMU */
22b19086 RK	175	adr r5, v6_crval
22b19086 RK	176	ldmia r5, {r5, r6}
26584853 CM	177	#ifdef CONFIG_CPU_ENDIAN_BE8
	178	orr r6, r6, #1 << 25 @ big-endian page tables
	179	#endif
1da177e4	180	mrc p15, 0, r0, c1, c0, 0 @ read control register
1da177e4	181	bic r0, r0, r5 @ clear bits them
22b19086	182	orr r0, r0, r6 @ set them
1da177e4 LT	183	mov pc, lr @ return to head.S:__ret
	184
	185	/*
	186	* V X F I D LR
	187	* .... ...E PUI. .T.T 4RVI ZFRS BLDP WCAM
	188	* rrrr rrrx xxx0 0101 xxxx xxxx x111 xxxx < forced
	189	* 0 110 0011 1.00 .111 1101 < we want
	190	*/
22b19086 RK	191	.type v6_crval, #object
	192	v6_crval:
	193	crval clear=0x01e0fb7f, mmuset=0x00c0387d, ucset=0x00c0187c
1da177e4 LT	194
	195	.type v6_processor_functions, #object
	196	ENTRY(v6_processor_functions)
	197	.word v6_early_abort
4fb28474	198	.word v6_pabort
1da177e4 LT	199	.word cpu_v6_proc_init
	200	.word cpu_v6_proc_fin
	201	.word cpu_v6_reset
	202	.word cpu_v6_do_idle
	203	.word cpu_v6_dcache_clean_area
	204	.word cpu_v6_switch_mm
ad1ae2fe	205	.word cpu_v6_set_pte_ext
1da177e4 LT	206	.size v6_processor_functions, . - v6_processor_functions
	207
	208	.type cpu_arch_name, #object
	209	cpu_arch_name:
	210	.asciz "armv6"
	211	.size cpu_arch_name, . - cpu_arch_name
	212
	213	.type cpu_elf_name, #object
	214	cpu_elf_name:
	215	.asciz "v6"
	216	.size cpu_elf_name, . - cpu_elf_name
	217	.align
	218
02b7dd12	219	.section ".proc.info.init", #alloc, #execinstr
1da177e4 LT	220
	221	/*
	222	* Match any ARMv6 processor core.
	223	*/
	224	.type __v6_proc_info, #object
	225	__v6_proc_info:
	226	.long 0x0007b000
	227	.long 0x0007f000
	228	.long PMD_TYPE_SECT \| \
1da177e4	229	PMD_SECT_AP_WRITE \| \
4b46d641 RK	230	PMD_SECT_AP_READ \| \
4b46d641 RK	231	PMD_FLAGS
8799ee9f RK	232	.long PMD_TYPE_SECT \| \
	233	PMD_SECT_XN \| \
	234	PMD_SECT_AP_WRITE \| \
	235	PMD_SECT_AP_READ
1da177e4 LT	236	b __v6_setup
	237	.long cpu_arch_name
	238	.long cpu_elf_name
f159f4ed TL	239	/* See also feat_v6_fixup() for HWCAP_TLS */
f159f4ed TL	240	.long HWCAP_SWP\|HWCAP_HALF\|HWCAP_THUMB\|HWCAP_FAST_MULT\|HWCAP_EDSP\|HWCAP_JAVA\|HWCAP_TLS
1da177e4 LT	241	.long cpu_v6_name
	242	.long v6_processor_functions
	243	.long v6wbi_tlb_fns
	244	.long v6_user_fns
	245	.long v6_cache_fns
	246	.size __v6_proc_info, . - __v6_proc_info
edabd38e SB	247
	248	.type __pj4_v6_proc_info, #object
	249	__pj4_v6_proc_info:
	250	.long 0x560f5810
	251	.long 0xff0ffff0
	252	.long PMD_TYPE_SECT \| \
edabd38e	253	PMD_SECT_AP_WRITE \| \
f0e5d2c9 SB	254	PMD_SECT_AP_READ \| \
f0e5d2c9 SB	255	PMD_FLAGS
edabd38e SB	256	.long PMD_TYPE_SECT \| \
	257	PMD_SECT_XN \| \
	258	PMD_SECT_AP_WRITE \| \
	259	PMD_SECT_AP_READ
	260	b __v6_setup
	261	.long cpu_arch_name
	262	.long cpu_elf_name
f159f4ed	263	.long HWCAP_SWP\|HWCAP_HALF\|HWCAP_THUMB\|HWCAP_FAST_MULT\|HWCAP_EDSP\|HWCAP_TLS
edabd38e SB	264	.long cpu_pj4_name
	265	.long v6_processor_functions
	266	.long v6wbi_tlb_fns
	267	.long v6_user_fns
	268	.long v6_cache_fns
	269	.size __pj4_v6_proc_info, . - __pj4_v6_proc_info